AMD Advanced Micro Devices AM29DL400BT-90FI, AM29DL400BT-90FEB, AM29DL400BT-90FE, AM29DL400BT-90FCB, AM29DL400BT-90FC Datasheet
...
Publication# 21606 Rev: C Amendment/0
Issue Date: May 1998
PRELIMINARY
Am29DL400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
■
Simultaneous Read/Write operations
Ñ Host system can program or erase in one bank,
then immediately and simultaneously read from
the other bank
Ñ Zero latency between read and write operations
Ñ Read-while-erase
Ñ Read-while-program
■
Single power supply operation
Ñ 2.7 to 3.6 volt read and write operations for
battery-powered applications
■
Manufactured on 0.35 µm process technology
High performance
■
Ñ Access times as fast as 70 ns
■
Low current consumption (typical values
at 5 MHz)
Ñ 7 mA active read current
Ñ 21 mA active read-while-program or read-while-
erase current
Ñ 17 mA active program-while-erase-suspended
current
Ñ 200 nA in standby mode
Ñ 200 nA in automatic sleep mode
Ñ Standard t
to transition from automatic sleep mode to
active mode
■
Flexible sector architecture
Ñ Two 16 Kword, two 8 Kword, four 4 Kword, and
six 32 Kword sectors in word mode
Ñ Two 32 Kbyte, two 16 Kbyte, four 8 Kbyte, and
six 64 Kbyte sectors in byte mode
Ñ Any combination of sectors can be erased
Ñ Supports full chip erase
■
Unlock Bypass Program Command
Ñ Reduces overall programming time when
issuing multiple program command sequences
chip enable access time applies
CE
■
Sector protection
Ñ Hardware method of locking a sector to prevent
any program or erase operation within that
sector
Ñ Sectors can be locked in-system or via
programming equipment
Ñ Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■
Top or bottom boot block conÞgurations
available
■
Embedded Algorithms
Ñ Embedded Erase algorithm automatically
pre-programs and erases sectors or entire chip
Ñ Embedded Program algorithm automatically
programs and veriÞes data at speciÞed address
■
Minimum 1 million program/erase cycles
guaranteed per sector
■
Package options
Ñ 44-pin SO
Ñ 48-pin TSOP
■
Compatible with JEDEC standards
Ñ Pinout and software compatible with
single-power-supply ßash standard
Ñ Superior inadvertent write protection
■
Data# Polling and Toggle Bits
Ñ Provides a software method of detecting
program or erase cycle completion
■
Ready/Busy# output (RY/BY#)
Ñ Hardware method for detecting program or
erase cycle completion
■
Erase Suspend/Erase Resume
Ñ Suspends or resumes erasing sectors to allow
reading and programming in other sectors
Ñ No need to suspend if sector is in the other bank
■
Hardware reset pin (RESET#)
Ñ Hardware method of resetting the device to
reading array data
PRELIMINARY
GENERAL DESCRIPTION
The Am29DL400B is an 4 Mbit, 3.0 volt-only ßash
memory device, organized as 262,144 words or
524,288 bytes. The device is offered in 44-pin SO and
48-pin TSOP packages. The word-wide (x16) data appears on DQ0ÐDQ15; the byte-wide (x8) data appears
on DQ0ÐDQ7. This device requires only a single 3.0
volt V
operations. A standard EPROM programmer can also
be used to program and erase the device.
The standard device offers access times of 70, 80, 90,
and 120 ns, allowing high-speed microprocessors to
operate without wait states. Standard control pinsÑ
chip enable (CE#), write enable (WE#), and output enable (OE#)Ñcontrol read and write operations, and
avoid bus contention issues.
The device requires only a
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
supply to perform read, program, and erase
CC
single 3.0 volt power sup-
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides si-
multaneous operation by dividing the memory space
into two banks. Bank 1 contains boot/parameter sectors, and Bank 2 consists of larger, code sectors of uniform size. The device can improve overall system
performance by allowing a host system to program or
erase in one bank, then immediately and simultaneously read from the other bank, with zero latency . This
releases the system from waiting for the completion of
program or erase operations.
Am29DL400B Features
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard . Commands are written to the command
register using standard microprocessor write timings.
Register contents serve as input to an internal state
machine that controls the erase and programming
circuitry. Write cycles also internally latch addresses
and data needed for the programming and erase
operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithmÑan internal algorithm that auto-
matically times the program pulse widths and veriÞes
proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the
algorithmÑan internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
veriÞes proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
been completed, the device automatically returns to
reading array data.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector within that bank that is
not selected for erasure. True background erase can
thus be achieved. There is no need to suspend the
erase operation if the read data is in the other bank.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device to reading array data, enabling the system microprocessor to read the boot-up Þrmware from
the Flash memory.
The device offers two power-saving features. When addresses have been stable for a speciÞed amount of
time, the device enters the automatic sleep mode .
The system can also place the device into the standby
mode . Power consumption is greatly reduced in both
these modes.
AMDÕs Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The
device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are
programmed one byte or word at a time using hot electron injection.
status bits . After a program or erase cycle has
detector that automatically inhibits write opera-
CC
Embedded Erase
2 Am29DL400B
PRODUCT SELECTOR GUIDE
PRELIMINARY
Family Part Number
Speed Options (Full Voltage Range: V
= 2.7 Ð 3.6 V)
CC
-70 -80 -90 -120
Am29DL400B
Max Access Time (ns) 70 80 90 120
CE# Access (ns) 70 80 90 120
OE# Access (ns) 30 30 35 50
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
V
CC
V
SS
A0–A17
A0–A17
RESET#
WE#
CE#
BYTE#
DQ0–DQ15
RY/BY#
A0–A17A0–A17
STATE
CONTROL
&
COMMAND
REGISTER
Upper Bank Address
Upper Bank
Y-Decoder
X-Decoder
Status
Control
X-Decoder
OE# BYTE#
Latches and Control Logic
DQ0–DQ15
A0–A17
Lower Bank Address
Lower Bank
Y-Decoder
Latches and
Control Logic
OE# BYTE#
DQ0–DQ15 DQ0–DQ15
21606C-1
Am29DL400B 3
CONNECTION DIAGRAMS
PRELIMINARY
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Reverse TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
21606C-2
4 Am29DL400B
CONNECTION DIAGRAMS
PRELIMINARY
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
SO
44
RESET#
43
WE#
42
A8
41
A9
40
A10
39
A11
38
A12
37
A13
36
A14
35
A15
34
A16
33
BYTE#
32
V
DQ15/A-1
31
DQ7
30
DQ14
29
DQ6
28
DQ13
27
DQ5
26
DQ12
25
DQ4
24
V
23
SS
CC
21606C-3
Am29DL400B 5
21606C-4
18
16 or 8
DQ0ÐDQ15
(A-1)
A0ÐA17
CE#
OE#
WE#
RESET#
BYTE# RY/BY#
PRELIMINARY
PIN DESCRIPTION
A0-A17 = 18 Addresses
DQ0-DQ14 = 15 Data Inputs/Outputs
DQ15/A-1 = DQ15 (Data Input/Output, word mode),
A-1 (LSB Address Input, byte mode)
CE# = Chip Enable
OE# = Output Enable
WE# = Write Enable
BYTE# = Selects 8-bit or 16-bit mode
RESET# = Hardware Reset Pin, Active Low
RY/BY# = Ready/Busy Output
= 3.0 volt-only single power supply
V
CC
V
SS
NC = Pin Not Connected Internally
(see Product Selector Guide for speed
options and voltage supply tolerances)
= Device Ground
LOGIC SYMBOL
6 Am29DL400B
PRELIMINARY
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
AM29DL400B -70
T
E
C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C = Commercial (0¡C to +70¡C)
I = Industrial (Ð40¡C to +85¡C)
E = Extended (Ð55¡C to +125¡C)
PACKAGE TYPE
E = 40-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 040)
F = 40-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR040)
S = 44-Pin Small Outline Package (SO 044)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
AM29DL400BT-70
AM29DL400BB-70
AM29DL400BT-80
AM29DL400BB-80
AM29DL400BT-90
AM29DL400BB-90
AM29DL400BT-120
AM29DL400BB-120
DEVICE NUMBER/DESCRIPTION
Am29DL400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
Valid Combinations
EC, EI, FC, FI,
EC, EI, EE,
FC, FI, FE,
SC, SI, SE
SC, SI
Valid Combinations
Valid Combinations list conÞgurations planned to be supported in volume for this device. Consult the local AMD sales
ofÞce to conÞrm availability of speciÞc valid combinations to
check on newly released combinations.
Am29DL400B 7
±
±
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the
commands, along with the address and data information needed to execute the command. The contents of
Table 1. Am29DL400B Device Bus Operations
Operation CE# OE# WE# RESET#
Read L L H H A
Write L H L H A
Standby
CC
0.3 V
XX
V
Output Disable L H H H X High-Z High-Z High-Z
Reset X X X L X High-Z High-Z High-Z
Sector Protect (Note 2) L H L V
Sector Unprotect (Note 2) L H L V
Temporary Sector Unprotect X X X V
Legend:
L = Logic Low = V
, H = Logic High = V
IL
, V
= 12.0
IH
ID
Notes:
1. Addresses are A17:A0 in word mode (BYTE# = V
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
V
CC
0.3 V
0.5 V, X = Don’t Care, A
±
), A17:A-1 in byte mode (BYTE# = V
IH
the register serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
DQ8ÐDQ15
Sector Address,
A6 = L, A1 = H,
ID
Sector Address,
A6 = H, A1 = H,
ID
ID
Addresses
(Note 1)
IN
IN
X High-Z High-Z High-Z
A0 = L
A0 = L
A
IN
DQ0Ð
DQ7
D
OUT
D
IN
D
IN
D
IN
D
IN
= Address In, D
IN
IL
BYTE#
= V
IH
D
DQ8ÐDQ14 = High-Z,
OUT
D
IN
DQ15 = A-1
XX
XX
D
IN
= Data In, D
IN
).
BYTE#
= V
IL
High-Z
= Data Out
OUT
Word/Byte ConÞguration
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word conÞguration. If the
BYTE# pin is set at logic Ô1Õ, the device is in word conÞguration, DQ0-15 are active and controlled by CE#
and OE# .
If the BYTE# pin is set at logic Ô0Õ, the device is in byte
conÞguration, and only data I/O pins DQ0ÐDQ7 are active and controlled by CE# and OE#. The data I/O pins
DQ8ÐDQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at V
. The BYTE# pin determines whether the
IH
device outputs array data in words or bytes.
. CE# is the power
IL
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the memory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank
remains enabled for read access until the command
register contents are altered.
See ÒReading Array DataÓ for more information. Refer
to the AC Read-Only Operations table for timing specifications and to Figure 13 for the timing diagram. I
in the DC Characteristics table represents the active
current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
8 Am29DL400B
CC1
PRELIMINARY
±
sectors of memory), the system must drive WE# and
CE# to V
, and OE# to V
IL
.
IH
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to ÒWord/Byte ConÞgurationÓ for more information.
The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock
Bypass mode, only two write cycles are required to program a word or byte, instead of four. The ÒByte/Word
Program Command SequenceÓ section has details on
programming data to the device using both standard and
Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. The device
address space is divided into two banks: Bank 1 contains the boot/parameter sectors, and Bank 2 contains
the larger, code sectors of uniform size. A Òbank addressÓ is the address bits required to uniquely select a
bank. Similarly, a Òsector addressÓ is the address bits
required to uniquely select a sector.
If the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7ÐDQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.
in the DC Characteristics table represents the ac-
I
CC2
tive current specification for the write mode. The AC
Characteristics section contains timing speciÞcation tables and timing diagrams for write operations.
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank of
memory while programming or erasing in the other
bank of memory. An erase operation may also be suspended to read from or program to another location
within the same bank (except the sector being erased).
Figure 19 shows how read and write cycles may be initiated for simultaneous operation with zero latency.
I
CC6
and I
in the DC Characteristics table represent
CC7
the current speciÞcations for read-while-program and
read-while-erase, respectively.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
CC
0.3 V.
(Note that this is a more restricted voltage range than
V
.) If CE# and RESET# are held at V
IH
V
±
0.3 V, the device will be in the standby mode, but
CC
, but not within
IH
the standby current will be greater. The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
ÒRESET#: Hardware Reset PinÓ.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
I
in the DC Characteristics table represents the
CC3
standby current speciÞcation.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for t
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I
CC4
Characteristics table represents the automatic sleep
mode current speciÞcation.
+ 30
ACC
in the DC
Am29DL400B 9
PRELIMINARY
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of tRP,
the device
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at VIL but not within VSS±0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
immediately terminates
SS
). If RESET# is held
CC4
any operation in
±0.3 V, the device
memory, enabling the system to read the boot-up
Þrmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a Ò0Ó (busy) until the
internal reset operation is complete, which requires a
time of t
(during Embedded Algorithms). The
READY
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is Ò1Ó), the reset operation is
completed within a time of t
(not du ring Embed-
READY
ded Algorithms). The system can read data tRH after
the RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance state.
10 Am29DL400B
PRELIMINARY
Table 2. Am29DL400BT Top Boot Sector Architecture
Sector Address
Bank Sector
SA0 0 0 0 X X X 64/32 00000hÐ0FFFFh 00000hÐ07FFFh
SA1 0 0 1 X X X 64/32 10000hÐ1FFFFh 08000hÐ0FFFFh
SA2 0 1 0 X X X 64/32 20000hÐ2FFFFh 10000hÐ17FFFh
Bank 2
SA3 0 1 1 X X X 64/32 30000hÐ3FFFFh 18000hÐ1FFFFh
SA4 1 0 0 X X X 64/32 40000hÐ4FFFFh 20000hÐ27FFFh
SA5 1 0 1 X X X 64/32 50000hÐ5FFFFh 28000hÐ2FFFFh
SA6 11000X 16/8 60000hÐ63FFFh 30000hÐ31FFFh
SA7 1 1 0
SA8 110110 8/4 6C000hÐ6DFFFh 36000hÐ36FFFh
SA9 110111 8/4 6E000hÐ6FFFFh 37000hÐ37FFFh
Bank 1
SA10 111000 8/4 70000hÐ71FFFh 38000hÐ38FFFh
SA11 111001 8/4 72000hÐ73FFFh 39000hÐ39FFFh
SA12 1 1 1
Bank
Address
Sector Size
(Kbytes/
A15 A14 A13 A12A17 A16
01X
10X
01X
10X
Kwords)
32/16 64000hÐ6BFFFh 32000hÐ35FFFh
32/16 74000hÐ7BFFFh 3A000hÐ3DFFFh
(x8)
Address Range
(x16)
Address Range
SA13 11111X 16/8 7C000hÐ7FFFFh 3E000hÐ3FFFFh
Note: The address r ange is A17:A-1 if in b yte mode (BYTE# = VIL). The address range is A17:A0 if in word mode (BYTE# = VIH).
Am29DL400B 11
Bank Sector
SA13 1 1 1 X X X 64/32 70000hÐ7FFFFh 38000hÐ3FFFFh
SA12 1 1 0 X X X 64/32 60000hÐ6FFFFh 30000hÐ37FFFh
Bank
Address
PRELIMINARY
Table 3. Am29DL400BB Bottom Boot Sector Architecture
Sector Address
Sector Size
A15 A14 A13 A12A17 A16
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
Bank 2
Bank 1
Note: The address r ange is A17:A-1 if in b yte mode (BYTE# = VIL). The address range is A17:A0 if in word mode (BYTE# = VIH).
Autoselect Mode
The autoselect mode provides manufacturer and device identiÞcation, and sector protection veriÞcation,
through identiÞer codes output on DQ7ÐDQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin A9.
Address pins A6, A1, and A0 must be as shown in
SA11 1 0 1 X X X 64/32 50000hÐ5FFFFh 28000hÐ2FFFFh
SA10 1 0 0 X X X 64/32 40000hÐ4FFFFh 20000hÐ27FFFh
SA9 0 1 1 X X X 64/32 30000hÐ3FFFFh 18000hÐ1FFFFh
SA8 0 1 0 X X X 64/32 20000hÐ2FFFFh 10000hÐ17FFFh
SA7 00111X 16/8 1C000hÐ1FFFFh 0E000hÐ0FFFFh
SA6 0 0 1
SA5 001001 8/4 12000hÐ13FFFh 09000hÐ09FFFh
SA4 001000 8/4 10000hÐ11FFFh 08000hÐ08FFFh
SA3 000111 8/4 0E000hÐ0FFFFh 07000hÐ07FFFh
SA2 000110 8/4 0C000hÐ0DFFFh 06000hÐ06FFFh
SA1 0 0 0
SA0 00000X 16/8 00000hÐ03FFFh 00000hÐ01FFFh
10X
32/16 14000hÐ1BFFFh 0A000hÐ0DFFFh
01X
10X
32/16 04000hÐ0BFFFh 02000hÐ05FFFh
01X
Table 4. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits (see Tables 2 and 3). Table
4 shows the remaining address bits that are donÕt care.
When all necessary bits have been set as required, the
programming equipment may then read the corresponding identiÞer code on DQ7-DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
does not require VID. Refer to the Autoselect Command
Sequence section for more information.
12 Am29DL400B
PRELIMINARY
START
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = V
ID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
21606C-5
Table 4. Am29DL400B Autoselect Codes (High Voltage Method)
Description Mode CE# OE# WE#
A17
to
A12
A11
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: AMD L L H BA X V
Device ID:
Am29DL400B
(Top Boot Block)
Device ID:
Am29DL400B
(Bottom Boot Block)
Sector Protection VeriÞcation L L H SA X V
Note: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care.
Word L L H
BA X V
Byte L L H X 0C
Word L L H
BA X V
Byte L L H X 0F
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected
sectors. Sector protection/unprotection can be implemented via two methods.
XLXLL X 01h
ID
22h 0C
XLXLH
ID
22h 0F
XLXLH
ID
XLXHL
ID
RESET# pin to VID (11.5 V Ð 12.5 V). During this
mode, formerly protected sectors can be programmed
or erased by selecting the sector addresses. Once V
is removed from the RESET# pin, all the previously
protected sectors are protected again. Figure 1
shows the algorithm, and Figure 23 shows the timing
diagrams, for this feature.
The primary method requires VID on the RESET# pin
only, and can be implemented either in-system or via
programming equipment. Figure 2 shows the algorithms and Figure 24 shows the timing diagram. This
method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must
Þrst be protected prior to the Þrst sector unprotect
write cycle.
X
X
01h
(protected)
00h
(unprotected)
ID
The alternate method intended only for programming
equipment requires VID on address pin A9 and OE#.
This method is compatible with programmer routines
written for earlier 3.0 volt-only AMD ßash devices. Publication number 22145 contains further details; contact
an AMD representative to request a copy.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMDÕs ExpressFlashª Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected or unprotected. See the Autoselect Mode section for details.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system.
The Sector Unprotect mode is activated by setting the
Figure 1. Temporary Sector Unprotect Operation
Am29DL400B 13
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