AMD Advanced Micro Devices Am29BDS323DT11AWKI Datasheet
PRELIMINARY
Am29BDS323D
32 Megabit (2 M x 16-Bit)
CMOS 1.8 Volt-only Simultane ous Read/Write, Burst Mode Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single 1.8 volt read, program and erase (1.7 to
1.9 volt)
■ Multiplexed Data and Address for reduced I/O
count
— A0–A15 multiplexed as D0–D15
— Addresses are latched with A VD# control inputs
while CE# low
■ Simultaneous Read/Write operation
— Data can be continuously read from one bank
while exec uting erase/progr am functions in othe r
bank
— Zero latency between read and write operations
■ Read access times at 40 MHz
— Burst access times of 20 ns @ 30 pF
at industrial temperature range
— Asynchronous random access times
of 110 ns @ 30 pF
— Synchronous random access times
of 120 ns @ 30 pF
■ Burst length
— Continuous linear burst
■ Power dissipation (typical values, 8 bits
switching, C
— Burst Mode Read: 25 mA
— Simu ltan eous Operation: 40 mA
— Program/Erase: 15 mA
— Standby mode: 0.2 µA
■ Sector Architecture
— Eight 4 Kword sectors and sixty-three sectors of
32 Kwords each
— Bank A contains the eight 4 Kword sectors and
fifteen 32 Kword sectors
— Bank B contains forty-eight 32 Kword sectors
= 30 pF)
L
■ Sector Protection
— Software command sector locking
— WP# protects the last two boot sectors
— All sectors locked when V
■ Software command set compatible with JEDEC
42.4 standards
— Backwards compatible with Am29F and Am29LV
families
■ Minimum 1 million erase cycle guarantee
per sector
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Data# Polling and toggle bits
— Provides a software method of detecting
program and erase operation completion
■ Erase Suspend/Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Hardware reset input (RESET#)
— Hardware method to reset the device for reading
array data
■ CMOS compatible inputs, CMOS compatible
outputs
■ Low V
■ Package Option
— 47-ball FBGA
write inhibit
CC
PP
= V
IL
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Refer to AMD’s Website (www.amd.com) for the latest information.
Publication# 23476 Rev: B Amendment/+4
Issue Date: September 4, 2001
PRELIMINARY
GENERAL DESCRIPTION
The Am29BDS323 is a 3 2 Mbit , 1. 8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory de vice,
organized as 2,097,152 words of 16 bits each. This
device uses a single V
gram, and erase the memory array. A 12.0-volt V
of 1.7 to 1.9 V to read, pro-
CC
PP
may be used for faster program performance if desired.
The device can also be programmed i n standard
EPROM programmers.
The Am29BDS323 provides a burst access of 20 ns at
30 pF with initial acc ess time s of 120 ns at 30 p F. The
device operates within the industrial temperature range
of –40°C to +85°C. The device is offered i n the 47 -b all
FBGA package.
Simultaneous Read/Write Ope rations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory
space into two banks. The device can improve overall
system performance b y a llowi ng a hos t s yste m to program or erase in one ba nk, then imme diately and s imultaneously read from the other bank, with zero
latency. This releases the system from waiting for the
completion of program or erase operations.
The device is divided as shown in the following table:
Bank A Sectors Bank B Sectors
Quantity Size Quantity Size
8 4 Kwords
15 32 Kwords
8 Mbits total 24 Mbits total
The device uses Chip Enable (CE#), Write Enable
(WE#), Address Valid (AVD#) and Output Enable
(OE#) to control asynchronous read and write operations. For burst operations, the device additionally
48 32 Kwords
requires Power Savi ng (PS), Rea dy (RDY) , and Clo ck
(CLK). This implementa tion allow s easy interfac e with
minimal glue log ic to a wide range of mic roprocessors/microcontrollers for high performance read operations.
The device offers complete compatibility with the
JEDEC 42.4 single-power-supply Flash command
set standard. Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device sta-
tus bit DQ7 (Data# Polling) and DQ 6/DQ2 (toggle
bits). After a program or erase cycle has been completed, the device automatically re turns to reading
array data.
The sector erase architecture allows memory sectors to be erased and reprogra mmed withou t affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
detector that automatically inhibits write opera-
V
CC
tions during power transitions. The device also offers
three types of data protection at the sector level. The
sector lock/unlock command sequence disabl es or
re-enables both program and erase operations in any
sector. When at V
tors. Finally, when V
, WP# locks the two outermost sec-
IL
is at VIL, all sectors are locked.
PP
The device offers two power-saving features. Whe n
addresses have been sta ble f or a spe cified am ount o f
time, the device enters the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly reduced in both modes.
2 Am29BDS323D
PRELIMINARY
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Simultaneous Op era tio n Circuit Block Diagram. 5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .6
Special Handling Instructions for FBGA Package ....................6
Input/Output Descriptions . . . . . . . . . . . . . . . . . . .7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9
Table 1. Device Bus Operations ......................................................9
Requirements for Asynchronous Read Operation(Non-Burst) 9
Requirements for Synchronous (Burst) Read Operation ..........9
Programmable Wait State ......................................................10
Power Saving Function ...........................................................10
Simultaneous Read/Write Operations with Zero Latency .......10
Writing Commands/Command Sequences ............................10
Accelerated Program Operation ......................................................11
Autoselect Functions .......................................................................11
Automatic Sleep Mode ...........................................................11
RESET#: Hardware Reset Input .............................................11
Output Disable Mode ..............................................................11
Hardware Data Protection ......................................................11
Low VCC Write Inhibit .....................................................................12
Write Pulse “Glitch” Protection ........................................................12
Logical Inhibit ..................................................................................12
Table 2. Sector Address Table ........................................................13
Command Definitions . . . . . . . . . . . . . . . . . . . . . .15
Reading Array Data ................................................................15
Set Wait State Command Sequence ......................................15
Table 3. Third Cycle Address/Data .................................................15
Enable PS (Power Saving) Mode Command Sequence ........15
Sector Lock/Unlock Command Sequence ..............................15
Reset Command .....................................................................15
Autoselect Command Sequence ............................................16
Program Command Sequence ...............................................16
Unlock Bypass Command Sequence ..............................................16
Figure 1. Program Operation .......................................................... 17
Chip Erase Command Sequence ...........................................17
Sector Erase Command Sequence ........................................17
Erase Suspend/Erase Resume Commands ...........................18
Figure 2. Erase Operation............................................................... 19
Command Definitions............................................................. 20
Table 4. Command Definitions .......................................................20
Write Operation Status . . . . . . . . . . . . . . . . . . . . .21
DQ7: Data# Polling .................................................................21
Figure 3. Data# Polling Algorithm ................................................... 21
DQ6: Toggle Bit I ....................................................................22
Figure 4. Toggle Bit Algorithm........................................................ 22
DQ2: Toggle Bit II ...................................................................23
Table 5. DQ6 and DQ2 Indications ................................................ 23
Reading Toggle Bits DQ6/DQ2 ...............................................23
DQ5: Exceeded Timing Limits ................................................23
DQ3: Sector Erase Timer .......................................................24
Table 6. Write Operation Status ..................................................... 24
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 25
Figure 5. Maximum Negative Overshoot Waveform...................... 25
Figure 6. Maximum Positive Overshoot Waveform........................ 25
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 25
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 7. Test Setup....................................................................... 27
Table 7. Test Specifications ........................................................... 27
Figure 8. Input Waveforms and Measurement Levels ................... 27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
Synchronous/Burst Read ........................................................28
Figure 9. Burst Mode Read............................................................ 28
Asynchronous Read ...............................................................29
Figure 10. Asynchronous Mode Read............................................ 29
Figure 11. Reset Timings............................................................... 30
Erase/Program Operations .....................................................31
Figure 12. Program Operation Timings.......................................... 32
Figure 13. Chip/Sector Erase Operations...................................... 33
Figure 14. Accelerated Unlock Bypass Programming Timing........ 34
Figure 15. Data# Polling Timings (During Embedded Algorithm) .. 35
Figure 16. Toggle Bit Timings (During Embedded Algorithm)........ 35
Figure 17. Latency with Boundary Crossing.................................. 36
Figure 18. Initial Access with Power Saving (PS)
Function and Address Boundary Latency...................................... 37
Figure 19. Initial Access with Address Boundary Latency............. 37
Figure 20. Example of Five Wait States Insertion.......................... 38
Figure 21. Back-to-Back Read/Write Cycle Timings...................... 39
Erase and Programming Performance . . . . . . . 40
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 41
FDD047—47-Pin Fine-Pitch Ball Grid Array (FBGA)
7 x 10 mm package ................................................................ 41
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision A (February 15, 2000) ..............................................43
Revision B (June 20, 2000) ....................................................43
Revision B+1 (November 27, 2000) .......................................43
Revision B+2 (November 30, 2000) .......................................43
Revision B+3 (December 21, 2000) .......................................43
Revision B+4 (September 4, 2001) ........................................43
Am29BDS323D 3
PRODUCT SELECTOR GU IDE
PRELIMINARY
Am29BDS323D
Part Number
Max Initial Access Time, ns (t
= 1.7 – 1.9 V
V
CC
Max Burst Access Time, ns (t
Max OE# Access, ns (tOE) 20 Max OE# Access, ns (tOE)35
BLOCK DIAGRAM
V
CC
V
SS
RDY
Buffer
WE#
RESET#
V
PP
CE#
OE#
State
Control
Command
Register
Synchronous/Burst Asynchronous
Speed Option
) 120 Max Access Time, ns (t
IACC
) 20 Max CE# Access, ns (tCE)110
BACC
11A
(40 MHz)
Speed Option 11A
ACC
PS
A/DQ0
RDY
Erase Voltage
Generator
PS Buffer
Input/Output
Buffers
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
)110
–A/DQ15
Data
Latch
V
CC
Timer
Detector
AVD#
CLK
Burst
State
Control
Burst
Address
Counter
A0–A20
A/DQ0–A/DQ15
A16–A20
4 Am29BDS323D
Address Latch
Y-Decoder
X-Decoder
Y-Gating
Cell Matrix
PRELIMINARY
SIMULTANEOUS OPERATION CIRCUIT BLOCK DIAGRAM
V
CC
V
SS
A0–A20
Upper Bank Address
Upper Bank
OE#
Y-Decoder
A0–A20
RESET#
WE#
CE#
ADV#
DQ0–DQ15
16/32#
A0–A20A0–A20
STATE
CONTROL
&
COMMAND
REGISTER
X-Decoder
Status
Control
X-Decoder
Latches and Control Logic
DQ0–DQ15
DQ0–DQ15 DQ0–DQ15
A0–A20
Lower Bank Address
Lower Bank
Y-Decoder
Latches and
Control Logic
Note: A0–A15 are multiplexed wi th DQ0–DQ15.
Am29BDS323D 5
CONNECTION DIAGRAM
PRELIMINARY
47-Ball FBGA
Top View, Balls Facing Down
A1
RDYA2NCA3GNDA4CLKA5V
B1
B2
V
A16B3A20B4AVD#B5PS
CC
C1
C2
A/DQ7C3A/DQ6C4A/DQ13C5A/DQ12C6A/DQ3C7A/DQ2C8A/DQ9C9A/DQ8
GND
D1
A/DQ15D2A/DQ14
D3
D4
GND
A/DQ5D5A/DQ4D6A/DQ11D7A/DQ10
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products
in FBGA packages.
CC
A6
WE#A7V
B6
RESET#
A8
A19A9A17
PP
B7
WP#B8A18B9CE#
D8
D9
V
A/DQ1
CC
A10
NC
B10
GND
C10
OE#
D10
A/DQ0
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be
compromised if the package body is exposed to
temperatures above 150°C for prolonged periods of
time.
6 Am29BDS323D
INPUT/OUTPUT DESCRIPTIONS
A16–A20 = Address Inputs
PRELIMINARY
PS = Power Saving input/output
A/DQ0– = Multiplexed Address/Data input/output
A/DQ15
CE# = Chip Enable Input. Asynchronous
relative to CLK for the Burst mode.
OE# = Output Enable Input. Asynchronous
relative to CLK for the Burst mode.
WE# = Write Enable Input.
V
CC
V
SS
= Device Power Supply (1.7 V–1.9 V).
= Ground
NC = No Connect; not connected internally
RDY = Ready output; indicates the status of
the Burst read. Low = data not valid at
expected time. High = data valid.
CLK = The first rising edge of CLK in
conjunction with AVD# low latches
address input and activates burst
mode operation. After the initial word
is output, subsequent rising edges of
CLK increment the internal address
counter. CLK should remain low
during asynchronous access.
AVD# = Address Valid input. Indicates to
device that the valid address is
present on the address inputs
(address bits A0–A15 are multiplexed,
address bits A16–A20 are address
only).
Low = for asynchronous mode,
indicates valid addr es s; for bu rst
mode, causes starting address to be
latched on rising edge of CLK.
High = device ignores address inputs
During a read operation, PS indicates
whether or not the data on the outputs
are inverted. Low = data not inverted;
High = data inverted
RESET# = Hardware reset input. Low = device
resets and returns to rea ding array
data. RESET# must be low during
device power up.
WP# = Hardware write protect input. Low =
disables writes to SA70 and SA71
V
PP
= At 12 V, accelerates programming;
automatically places device in unlock
bypass mode. At V
, disables
IL
program and erase functions. Should
be at V
for all other conditions.
IH
LOGIC SYMBOL
5
A16–A20
CLK
CE#
OE#
WE#
RESET#
AVD#
A/DQ0–
A/DQ15
PS
RDY
16
Am29BDS323D 7
PRELIMINARY
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Am29BDS323D T 11 A WK I
TEMPERATURE RANGE
I = Industrial (–40
PACKAGE TYPE
WK = 47-Ball Fine-Pitch Grid Array (FBGA)
0.50 mm pitch, 7 x 10 mm package (FDD047)
CLOCK RATE
A=40 MHz
SPEED
See Product Selector Gu id e an d Valid Combination
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
DEVICE NUMBER/DESCRIPTION
Am29BDS323D
32 Megabit (2 M x 16-Bit) CMOS Flash Memory, Simultaneous Read/Write, Burst Mode Flash Memory
1.8 Volt-only Read, Program, and Erase
°C to +85°C)
Valid Combinations
Valid Combination configuration planned to be supported for this
device.
Valid Combinations
Order Number Package Marking
Am29BDS323DT11AWKI N323DT1AVI
8 Am29BDS323D
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, wh ich are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the commands, along with the address a nd data information
needed to execute the command . The conte nts of the
Table 1. Device Bus Operati ons
Operation CE# OE# WE# A16–20 A/DQ0–15 RESET# CLK AVD#
Asynchronous Read L L H Addr In I/O H L
Write L H L Addr In I/O H L
Standby (CE#) H X X HIGH Z HIGH Z H X X
Hardware Reset X X X HIGH Z HIGH Z L X X
Burst Read Operations
Load Starting Burst Address L H H Addr In I/O H
register serve as inputs to the interna l state mach ine.
The state m achine outp uts dictate the functi on of the
device. Table 1 lists the device b us operat ions, the inputs and control level s they require, and the resul ting
output. The following subsections describe ea ch of
these operations in further detail.
Advance Burst to next address with appropriate
Data presented on the Data Bus
Terminate current Burst read cycle H X H HIGH Z HIGH Z H X
Terminate current Burst read cycle via RESET# X X H HIGH Z HIGH Z L X X
Terminate current Burst read cycle and start new
Burst read cycle
Legend: L = Logic 0, H = Logic 1, X = Don’t Care.
Requirements for Asynchronous
Read Operation (Non-Burst)
To read data from the m emor y arra y, the system must
first assert a valid address on A/DQ0–A/DQ15 and
A16–A20, wh ile driving AVD# and CE# to V
should remain at V
for asynchronous read operations. The rising edge of
AVD# latches the address, after which t he sy st em can
drive OE# to V
A/DQ0–A/DQ1 5. Since the m emory arra y is divi ded
into two banks, each bank remains enabled for read
access until the command register contents are
altered.
. Note that CLK must remain low
IH
. The data will appear on
IL
LLHHIGH Z
L H H HIGH Z I/O H
ensures that no sp urious alteration of th e memory
content occurs during the power transition.
Requirements for Synchronous (Burst)
. WE#
IL
Read Operation
The device is capable of continuous, sequential (linear)
burst operation. However, when the device first powers
up, it is enabled for asynchronous read operation. The
device will automatically be enabled for burst mode on
the first rising edge on the CLK input, while AVD# is
held low for one clock cycle. Prior to activating the clock
signal, the system should determine how many wait
states are desired for the ini tial word (t
Burst
Data Out
HH
) of each
IACC
burst session. The system would then write the Set
Address access time (t
stable addresses to valid out put dat a. Th e ch ip ena bl e
access time (t
) is the delay from the stable
CE
addresses and stable CE# to valid data at the outputs.
The output enable access time (t
the falling edge of OE# to valid data at the output.
The internal state machine is set for reading array data
upon device power-up, or af ter a har dware r eset. This
) is equal to the dela y from
ACC
) is the delay from
OE
Wait Count command seq uence (see “Programmable
Wai t St at e ”). The system may optionally activate the
PS mode (see “Power Saving Function”) by writing the
Enable PS Mode comma nd seque nce at thi s time, but
note that the PS mode can only be disabled by a hardware reset. (See “Command Definitions” for further
details).
The initial word is outpu t t
after the rising edge of
IACC
the first CLK cycle. Subsequent words are output t
BACC
Am29BDS323D 9
PRELIMINARY
after the rising edge of each successive clock cycle,
which automatically increments the internal address
counter. Note that the device has a fixed internal
address boundary that occurs every 64 words,
starting at address 00000h. During the time the
device is outputting the 64th word (address 0003Fh,
0007Fh, 000BFh, etc.), a one cycle latency occurs
before data appears for the next address (address
00040h, 00080h, 000C0h, et c.). The RDY ou tput indicates this conditio n to the syste m by pulsin g low. See
Figure 17.
The device will continue to output sequential burst
data, wrapping around to address 00000h after it
reaches the highest addressable memory location,
until the system asserts CE# high, RESET# low, or
A VD# low in conjunction with a new address. See T able
1. The reset co mmand does not t erminate the bu rst
read operation.
If the host system crosses the bank boundary while
reading in burst mo de, an d the devi ce is not prog ramming or erasing, a one cycle latency wi ll occur as
described above. If the host system cr osses the bank
boundary while the d evice i s program ming or er asing,
the device will provide asynchronous read status information. The clock will be ignored. After the host has
completed st atus reads, or the device has completed
the program or era se op eration, the h ost can rest art a
burst operation using a new address and AVD# pulse.
If the clock frequency is less than 6 MHz during a burst
mode operation, additional late ncies will occur. RDY
indicates the length of the latency by pulsing low.
Programmable Wait State
The programmable wait state feature indicates to the
device the number of addi ti onal cloc k c ycle s th at m ust
elapse after AVD# is driven active befor e data will be
available. Upon power up, the device defaults to the
maximum of seven total cyc les. The total number of
wait states is programmable from four to seven cycles.
See Figur e 20.
Power Saving Function
The Power Save function r educes the amount of
switching on th e data output bus by cha nging the
minimum number of bits possible, thereby reducing
power consumption. This fun ction is acti ve on ly durin g
burst mode operations.
The device compares the word previously output to the
system with the new word to be output. If the number of
bits to be switched is 0–8 (less than half the bus width),
the device simply o utputs the new word on the data
bus. If, however, the number of bits that must be
switched is 9 or higher, the data is inverted before being
output on the data bus. This effectively limits the
maximum number of bits that are switched for any
given read cy cle to eight. The device i ndicates to the
system whether or not the data is inverted v ia the PS
(power saving) output. If the word on the data bus is not
inverted, PS = V
inverted, PS = V
; if the word on the data bus is
OL
.
OH
During initial power up the PS function i s disabled. To
enable the PS function, the system must write the
Enable PS command sequence to the flash device (see
the Command Definitions table).
When the PS fu nc tio n is enabled, one ad dit ion al c lo ck
cycle is inserted during the initial and second access of
a burst sequence. See Figure 18. The RDY output indicates this condition to the system.
The device is also capable of receiving inverted data
during program operations. The host system must indicate to the device via the PS in put whether or n ot the
program data are inverted. PS must be driven to V
inverted data, or to V
for non-inverted data.
IL
IH
for
To disable the PS function, the system must hardware
reset the device (drive the RESET# input low).
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be su spended to read from or program to another location
within the same bank (except the sector being
erased). Figu re 21 s hows how read and w rite cycles
may be initiated for simultaneous operation with zero
latency. Refer to the DC Characteristics table for
read-while-program and r ead-while-erase c urrent
specifications.
Writing Commands/Command Sequences
The device has inputs/outputs that accept both address and data information. To write a command or
command sequenc e (which includes programming
data to the device and erasing sectors of memory), the
system must drive CLK, AVD# and CE# to V
OE# to V
and drive CLK, WE# an d CE# to V
when providing an address to the device,
IH
, and OE# to VIH.
IL
when writing commands or data.
The device features an Unlock Bypass mode to facili-
tate faster progr amming. Once a bank enters the
Unlock Bypass mode, only two write cycles are required to program a word, instead of four.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicates the address
space that each sector occupies. The device address
space is divided into two banks: Bank A contains the
boot/parameter sectors, and B ank B contains the
larger, code sectors of uniform size. A “bank address”
is the address bits required to uniquely select a bank.
Similarly, a “sector address” is the address bits required to uniquely select a sector.
, and
IL
10 Am29BDS323D
PRELIMINARY
I
in the DC Characteristics table represents the ac-
CC2
tive current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
addresses are changed. While in sl eep mode, output
data is latc hed and always a vailable to the system .
in the DC Characteristics table represents the
I
CC4
automatic sleep mode current specification.
Accelerated Program Operation
The device offers accelerated p rogram operat ions
through V
. This function is primarily intended to
PP
allow faster manufact uring thr oughp ut at the factory. If
the system asserts V
on this input, the device auto-
ID
matically enters the aforemention ed Unlock B ypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltag e on the input to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unloc k Bypass mo de. Removing
from the VPP input returns the device to normal op-
V
ID
eration. Note th at sect ors mus t be unl ocked usi ng the
Sector Lock/Unlock command sequence prior to raising V
to VID.
PP
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autosel ect cod es fro m the internal register (which is separate from the memory array)
on DQ7–DQ0. Stand ard read cy cle timings apply in
this mode. Refer to the Autoselect Functions and Autoselect Command Sequence sections for more
information.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters th e CMOS s tandby mode when th e
CE# and RESET# inputs are both held at V
The device requires standard access time (t
± 0.2 V.
CC
CE
) for
read access when the device is in either of these
standby modes, before it is ready to read data.
If the device is deselecte d during erasur e or programming, the device draws active current until the
operation is completed.
in the DC Characteristics table represents the
I
CC3
standby current specif ic ati on.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automati cally enables
this mode when addresses remain stabl e for t
60 ns. The automa tic sleep mode is indepe ndent of
the CE#, WE#, and OE# contro l sign als. St andard ad dress access timi ngs provide new data when
ACC
+
RESET#: Hardware Reset Input
The RESET# input pro vides a h ardwa re met hod of r esetting the device to reading array data. When
RESET# is driven low for at least a period of t
RP
, the
device immediately terminates any operation in
progress, tristates al l outputs, and ignores all
read/write commands for the duration of the RESET#
pulse. The device al so resets the i nternal state machine to reading arra y data. The o peration that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
held at V
but not within VSS±0.2 V, the standby cur-
IL
±0.2 V, the device
SS
). If RESET# is
CC4
rent will be greater.
RESET# may be tied to the system reset circuitry. A
system reset would thus a lso res et the Flash m emory,
enabling the system to read the boot-up firmware from
the Flash memory. Note that RESET# must be asserted low during device power-up for proper
operation.
If RESET# is asserted during a program or erase operation, the device requires a time of t
READY
(during
Embedded Algorithms) before the device is ready to
read data again. If RESET# is asserted when a program or erase operation is not executing, the reset
operation is completed within a time of t
READY
(not
during Embedded Algorithms). The system can read
data t
after RESET# returns to VIH.
RH
Refer to the AC Characteristics tables for RESET# parameters and to Figure 11 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device
is disabled. The ou tputs are placed in the high
impedance state.
Hardware Data Protection
The command sequence r equ irement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes ( refer to Table 4 for command definitions).
The device offers three types of data protection at the
sector level:
■ The sector lock/unlock command sequence dis-
ables or re-enables both program and erase operations in any sector.
Am29BDS323D 11
PRELIMINARY
■ When WP# is at V
the two outermost sec tors a r e
IL,
locked.
■ When V
is at VIL, all sectors are locked.
PP
The following hardware data pr ot ec tio n measur es prevent accidental erasure or programming, which might
otherwise be cau sed by sp urious sy stem level s ignals
during V
power-up and power-down trans itions, or
CC
from system noise.
Low V
When V
cept any write cycles. This protects data during V
Write Inhibit
CC
is less than V
CC
, the device does not ac-
LKO
CC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to reading array data. Subse-
quent writes are ignored until V
. The system must provide the proper signals to
V
LKO
is greater than
CC
the control inputs to pr event unintent ional wri tes when
is greater than V
V
CC
LKO
.
Write Pulse “Glitch” Prote ct i o n
Noise pulses of less than 5 ns (typic al) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
, CE# = VIH or WE# = VIH. To initiate a write cycle,
IL
CE# and WE# must be a logical zero while O E# is a
logical one.
12 Am29BDS323D
Bank B
PRELIMINARY
Table 2. Sector Address Table
Sector Sector Size (x16) Address Range
SA0 32 Kwords 00000h—07FFFh
SA1 32 Kwords 08000h—0FFFFh
SA2 32 Kwords 10000h—17FFFh
SA3 32 Kwords 18000h—1FFFFh
SA4 32 Kwords 20000h—27FFFh
SA5 32 Kwords 28000h—2FFFFh
SA6 32 Kwords 30000h—37FFFh
SA7 32 Kwords 38000h—3FFFFh
SA8 32 Kwords 40000h—47FFFh
SA9 32 Kwords 48000h—4FFFFh
SA10 32 Kwords 50000h—57FFFh
SA11 32 Kwords 58000h—5FFFFh
SA12 32 Kwords 60000h—67FFFh
SA13 32 Kwords 68000h—6FFFFh
SA14 32 Kwords 70000h—77FFFh
SA15 32 Kwords 78000h—7FFFFh
SA16 32 Kwords 80000h—87FFFh
SA17 32 Kwords 88000h—8FFFFh
SA18 32 Kwords 90000h—97FFFh
SA19 32 Kwords 98000h—9FFFFh
SA20 32 Kwords A0000h—A7FFFh
SA21 32 Kwords A8000h—AFFFFh
SA22 32 Kwords B0000h—B7FFFh
SA23 32 Kwords B8000h—BFFFFh
SA24 32 Kwords C0000h—C7FFFh
SA25 32 Kwords C8000h—CFFFFh
SA26 32 Kwords D0000h—D7FFFh
SA27 32 Kwords D8000h—DFFFFh
SA28 32 Kwords E0000h—E7FFFh
SA29 32 Kwords E8000h—EFFFFh
SA30 32 Kwords F0000h—F7FFFh
SA31 32 Kwords F8000h—FFFFFh
SA32 32 Kwords 100000h—107FFFh
SA33 32 Kwords 108000h—10FFFFh
SA34 32 Kwords 110000h—117FFFh
SA35 32 Kwords 118000h—11FFFFh
SA36 32 Kwords 120000h—127FFFh
SA37 32 Kwords 128000h—12FFFFh
Am29BDS323D 13
Bank B
Bank A
PRELIMINARY
Table 2. Sector Address Table (Continued)
Sector Sector Size (x16) Address Range
SA38 32 Kwords 130000h—137FFFh
SA39 32 Kwords 138000h—13FFFFh
SA40 32 Kwords 140000h—147FFFh
SA41 32 Kwords 148000h—14FFFFh
SA42 32 Kwords 150000h—157FFFh
SA43 32 Kwords 158000h—15FFFFh
SA44 32 Kwords 160000h—167FFFh
SA45 32 Kwords 168000h—16FFFFh
SA46 32 Kwords 170000h—177FFFh
SA47 32 Kwords 178000h—17FFFFh
SA48 32 Kwords 180000h—187FFFh
SA49 32 Kwords 188000h—18FFFFh
SA50 32 Kwords 190000h—197FFFh
SA51 32 Kwords 198000h—19FFFFh
SA52 32 Kwords 1A0000h—1A7FFFh
SA53 32 Kwords 1A8000h—1AFFFFh
SA54 32 Kwords 1B0000h—1B7FFFh
SA55 32 Kwords 1B8000h—1BFFFFh
SA56 32 Kwords 1C0000h—1C7FFFh
SA57 32 Kwords 1C8000h—1CFFFFh
SA58 32 Kwords 1D0000h—1D7FFFh
SA59 32 Kwords 1D8000h—1DFFFFh
SA60 32 Kwords 1E0000h—1E7FFFh
SA61 32 Kwords 1E8000h—1EFFFFh
SA62 32 Kwords 1F0000h—1F7FFFh
SA64 4 Kwords 1F8000h—1F8FFFh
SA65 4 Kwords 1F9000h—1F9FFFh
SA66 4 Kwords 1FA000h—1FAFFFh
SA67 4 Kwords 1FB000h—1FBFFFh
SA68 4 Kwords 1FC000h—1FCFFFh
SA69 4 Kwords 1FD000h—1FDFFFh
SA70 4 Kwords 1FE000h—1FEFFFh
SA71 4 Kwords 1FF000h—1FFFFFh
14 Am29BDS323D
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