AMD Advanced Micro Devices AM28F512-90PIB, AM28F512-90PI, AM28F512-90PEB, AM28F512-90FI, AM28F512-90FE Datasheet

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FINAL

Am28F512

512 Kilobi t ( 64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory

DISTINCTIVE CHARACTERISTICS

■

High performance

— 70 ns maximum access time

■

CMOS Low power consumption

— 30 mA max imum act ive current — 100 µA maximum standby current — No data retention power consumption

■

Compatible with JEDEC-standard byte-wide 32-Pin EPROM pino uts

— 32-pin PDIP — 32-pin PLCC — 32-pin TSOP

■

10,000 write/erase cycles minimum

■

Write and erase voltage 12.0 V ±5%

■

Latch-up protected to 100 mA from -1 V to V

Flasherase Electrical Bulk Chip-Erase

— One second typical chip-erase

Flashrite Programming

— 10 µs typical byte-program — One second typical chip program

Command regist er architecture for microprocessor/microcontroller compatible write interface

On-chi p add r es s and dat a latches Advanced CMOS flash memory technology

— Low cost single transistor memory cell

Aut o matic write/eras e pulse sto p timer

+1 V

GENERAL DESCRIPTION

The Am2 8F512 is a 512 K bi t Flash me mory or ganized as 64 Kbytes of 8 bits each. AMD’s Flash memories offer the most cost-effective and reliable read/ write non-volatile random access memory. The Am28F51 2 is packaged in 32-pin PDIP, P LCC, and TSOP versio ns. It is designed to b e reprogrammed and erased in-system or in standard EPROM programmers. The Am28F 512 is erased when sh ipped from the factory.

The standard Am28F512 offers access times as fast as 70 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the Am28F512 has separate chip enable (CE#) and output enable (OE#) controls.

AMD’s Flash memories augment EPROM funct ionality with i n-circuit elec trical e rasure and programming. The Am28F512 uses a command register to manage this functionality, while maintaining a standard JEDEC Flash Standard 32-pin pinout. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming.

AMD’s Flash technology reliably stores memory contents even after 10,000 erase and program cycles. The AMD cell is designed to optimize the erase and pro-

gra mmin g m ec han i sms . I n ad di t io n, th e c o mbin a tio n of advanced t unnel oxide pr ocessi ng and low in ternal electric fields for erase and programming operations produces reliable cycling. The Am28F 512 uses a

12.0 V± 5% VPP high voltage input to per form the Flashera se and Flashrit e algorithms.

The highest degree of latch-up protection is achieved with AMD’s prop r ietary non -e pi pr oc e ss. Lat ch- up pro tection is provided for stresses up to 100 mA on address and data pins from -1 V to VCC +1 V.

The Am28F512 is byte programmable using 10 ms programmin g pul ses in acco rdance with A MD’s Flas hrit e programming algorithm. The typical room temperature programming time of the Am28F 512 is one s econd. The en tire chip is b ul k er as ed u sing 10 m s era se puls es according to AMD’s Flasherase algorithm. Typical erasure at room temperature is accomplished in less than one second. The wi ndowed package and the 15-20 minutes required for EPROM erasure usi ng ultra-vio let light are eliminated.

Commands are wr itten to the command register using standard microprocessor write timings. Register contents serve as inputs to an internal state-machine which controls the erase and programming circuitry. During

Publication# Issu e Date:

Rev: GAmendment/

11561

January 1998

write cycles, the command register internally latches address and data needed for the pro gramming and erase operations. For system design simplification, the Am28F512 is designed to s uppor t either W E# or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the rising edge of WE# or CE# whichever occurs first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal.

BLOCK DIAGRAM

Erase

Voltage

Switch

AMD’s Flash technology combines years of EPROM and EEPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. Th e Am28F512 electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.

DQ0–DQ7

Input/Output

Buffers

WE#

CE#

OE#

Low V

Detector

A0–A15

State

Control

Command

Program/Erase

Pulse Timer

Program

Voltage

Switch

To Array

Address

Latch

Chip Enable

Output Enable

Logic

Y-Decoder

X-Decoder

Data

Latch

Y-Gating

524,288

Bit

Cell Matrix

11561G-1

PRODUCT SELECTOR GUIDE

Family Part Number Speed Options (V Max Access Time (ns) 70 90 120 150 200 CE# (E#) Access (ns) 70 90 120 150 200 OE# (G#) Access (ns) 35 35 50 55 55

= 5.0 V ± 10%)

-70 -90 -120 -150 -200

2 Am28F512

Am28F512

CONNECTION DIAGRAMS

NC A15 A12

A7 A6 A5 A4 A3 A2 A1

A0 DQ0 DQ1 DQ2

1 2 3 4 5

6 7

8 9 10 11 12

13 14 15 16

PDIP

32 31 30 29 28

27 26

25 24 23 22 21

20 19

18 17

WE# (W#) NC A14

A13 A8 A9 A11

OE# (G#) A10 CE# (E#) DQ7 DQ6 DQ5 DQ4

DQ3

11561G-2

A7 A6 A5

A4 A3 A2 A1 A0

DQ0

5 6

8 9 10

11 12 13

A12

DQ1

A15

DQ2

PLCC

VCCWE# (W#)

31 30

19 2016

DQ4

DQ3

DQ5

29 28 27

26 25 24 23 22 21

DQ6

A14 A13

A9 A11 OE# (G#)

A10 CE# (E#) DQ7

11561G-3

Note:

Pin 1 is marked for orientation.

Am28F512 3

CONNECTION DIAGRAMS (contin ued)

A11

A13 A14

WE#

NC A15 A12

OE#

A10

CE#

D7 D6 D5 D4 D3

D2 D1 D0 A0 A1 A2 A3

A9 A8

A7 A6 A5 A4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

32-Pin — Standard Pinout

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

OE# A10 CE# D7 D6 D5 D4 D3 V

D2 D1 D0 A0 A1 A2 A3

A11 A9 A8 A13 A14 NC WE# V

NC A15 A12 A7 A6 A5 A4

LOGIC SYMBOL

32-Pin — Reverse Pinout

A0–A15

CE# (E#) OE# (G#)

WE# (W#)

11561G-4

DQ0–DQ7

11561G-5

4 Am28F512

ORDERIN G IN FOR MATION Standard Products

AMD standard products are available in several packages and operating ranges. The order number (V alid Combination) is formed by a combination of:

AM28F512 -70 J C

DEVICE NUMBER/DESCRIPTION

Am28F512 512 Kilobit (64 K x 8-Bit) CMOS Flash Memory

OPTIONAL PROCESSING

Blank = Standard Processing B = Burn-In

Contact an AMD representative for more information.

TEMPERATURE RANGE

C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C)

PACKAGE TYPE

P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

AM28F256-70 AM28F256-90 AM28F256-120 AM28F256-150 AM28F256-200

Valid Combinations

PC, PI, PE,

EC, EI, EE,

JC, JI, JE,

FC, FI, FE

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Am28F512 5

PIN DESCRIPTION A0–A15

Address In puts for memor y lo cations. Inte rnal la tches hold addresses during write cycles.

CE# (E#)

Chip Enable active low input activates the chip’s control logic and input buffers. Chip Enable high will deselect the device and operates the chip in stand-by mode.

DQ0–DQ7

Data Inputs during memory write cycles. Internal latches hold data during write cycles. Data Outputs during memory read cycles.

No Conn ect- corre spond ing pin i s no t conn ec ted in ternally to the die.

OE# (G#)

Output Enable active low input gates the outputs of the device through the data buffers during memory read cycles. Output Enable is high during command sequencing and program/erase operations.

Po w er supp ly for de vi ce oper at ion . (5.0 V ± 5% or 10%)

Program voltage i nput. VPP must be at hi g h vol ta ge in order to write to the command register. The command register controls all functions required to alter the memory array contents. Memory contents cannot be altered when VPP ≤ V

Ground

+2 V.

WE# (W#)

Write Enable active low input controls the write function of the command register to the memory array. The target address is latched on the falling edge of the Write Enable pulse and the appropriate data is latched on the rising edge of the pulse. Write Enable high inhibits writing to the device.

6 Am28F512

BASIC PRINCIPLES

The device uses 100% TTL-level control inputs to manage th e command register. Erase and rep rogramming opera tions use a fixed 12.0 V ± 5% high voltage input.

Read Only Memory

Without high VPP voltage, the device functions as a read only memory and operates like a standard EPROM. Th e control inpu ts still ma nage traditi onal read, standby, output disable, and Auto select modes.

Command Register

The command register is enabled only when high voltage is applied to the VPP pin. The erase and reprogramming operations are only accessed via the register. In addition, two-cycle commands are required for erase and reprogramming op erations. The traditional read, standby, output disable, and Auto select modes are available via the register.

The device’s com mand regi ster is wr itt en us ing standard microprocessor write timings. The register controls an internal state machine that manages all device operations. For system design simplification, the device is designed to suppor t either WE# or CE# controlled writes. Durin g a system write cy cle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the rising edge of WE# or CE# whichever occur first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal.

Overview of Erase/Program Operations

Flasherase™ Sequence

A multiple step command sequence is required to erase the Flash device (a two-cycle Erase command and repeated one cycle verify commands).

Note: The Flash memory array must be completely programmed to 0’s prior to erasure. Refer to the Flashrite™ Programming Algorithm.

1. Erase S etup: Write the Setup Erase command to the command register.

2. Erase: Wr it e the Erase com mand (sam e as Setu p Erase command) to the command register again. The seco nd comm an d i n it iat es t he er a s e o per at i o n. The system software routines must now time-out the erase pulse width (10 ms) prior to issuing the Erase-ver ify command. An integrate d stop time r prevents any possibility of overerasure.

3. Erase-Verify: Write the Erase-verify command to the command register. This command terminates the erase operation. After the erase operation, each byte of the array must be verified. Address in-

formation must be supplied with the Erase-verify command. This command verifies the margin and outputs t he add re ssed b y te in o rde r to co mpar e th e array data with FFh data (Byte erased). After successful data verification the Erase-verify command is written again with new address information. Each byte of the array is sequentially verified in this manner.

If data of the addressed loca tion is not verified, the Erase sequence is repe ated until the entire array is successfully verified or the sequence is repea ted 1000 times.

Flashrite Programming Sequence

A three step command sequence (a two-cycle Program command and one cycle Verify command ) is required to pr og r am a byte of t h e Fla sh arr ay. Refe r to th e Fl as hrite Algorit h m.

1. Program Setup: Write the Setup Program com- mand to the command regist er.

2. Pr ogram: Write the Program command to the com- mand register with the appropriate Address and Data. The system software routines must now timeout the program pulse width (10 µs) prior to issuing the Program-verify command. An integrated stop timer prevents any possibility of overprogramming.

3. Program-Verify: Write the Program-verify com- mand t o th e com ma nd register. Thi s command ter minates the programming op eration. In additio n, this command verifies the margin and outputs the byte just programmed in order to compare the array data with the original data programmed. After successful d ata ver ification, the programm ing sequence is initiated again for the next byte address to be programmed.

If data is n ot verified succes sfully, the Pr ogram sequence is repeated until a successful comparison is verified or the sequence is repeated 25 times.

Data Protection

The device is designed to offer protection aga inst acci dental erasure or programming ca used by spurious system level signals that may exist during power transitions . The d evice po wers up in it s r ea d onl y st at e . A ls o, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences.

The device al so i ncor pora tes s everal feat ures t o pre vent inadvertent write cycles resulting fromVCC powerup and power-down transitions or system noise.

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up and power-d own, the d evice locks out wr ite cycl es for

Am28F512 7

VCC < V voltages) . Wh en VCC < V

(see DC Characteristics section for

LKO

, the comm an d r eg i ster i s

LKO

disabled, all internal program/erase circuits are disabled , an d th e d evice resets to the r ea d m od e. Th e device ignores all writes until VCC > V

. The user

LKO

must ensure that the control pins are in the correct logic state wh en VCC > V

to prevent uninitentional writes.

LKO

Write Pulse “Glitch” Protection

Noise pul se s of less than 10 ns (typical) on OE#, CE# or WE# will not initiate a write cycle.

FUNCTIONAL DESCRIPTION Description of User Modes

Table 1. Am28F512 User Bus Operations (Notes 7 and 8)

Operation CE# (E#)OE# (G#)WE# (W#)

Read-Only

Read V Standby V Output Disable V Auto-select Manufacturer

Code (Note 2)

Logical Inhibit

Writing is inhibited by holding an y one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle CE# a nd WE# must be a logical zero while OE# is a logical one.

Power- U p Wr ite Inhibi t

Power-up of the device with W E# = CE# = VIL and OE# = VIH will not accept commands on the r ising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.

(Note 1) A0 A9 I/O

XXV

PPL

A0 A9 D

OUT

X X HIGH Z X X HIGH Z

(Note 3)

CODE

(01H)

(Note 3)

Read/Write

Auto-select Device Code (Note 2)

Read V

Standby (Note 5) V Output Disable V

Write V

XXV

PPL

PPH

A0 A9

X X HIGH Z X X HIGH Z

A0 A9

Legend:

X = Don’t care, where Don’t Care is either V

levels of V

. 0 V < An < V

PPH

+ 2 V, (normal TTL or CMOS input levels, where n = 0 or 9).

levels. V

PPL

= V

< V

+ 2 V. See DC Characteristics for voltage

or V

Notes:

1. V

may be grounded, connected with a resistor to ground, or < VCC +2.0 V. V

PPL

for the device. Refer to the DC characteristics. When V

= V

, memory contents can be read but not written or erased.

PPL

is the programming voltage specified

PPH

2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2.

3. 11.5 < V

4. Read operation with V

5. With V

6. Refer to Table 3 for valid D

7. All inputs are Don’t Care unless otherwise stated, where Don’t Care is either V

< 13.0 V. Minimum V

= V

at high voltage, the standby current is ICC + I

rise time and fall time (between 0 and VID voltages) is 500 ns.

may access array data or the Auto select codes.

PPH

during a write operation.

(standby).

or V

levels. In the Auto select mode all

addresses except A9 and A0 must be held at VIL.

8. If V

≤ 1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 Volts. Also, the Am28F512 has a V

rise time and fall time specification of 500 ns minimum.

CODE

(25H) D

OUT

(Note 4)

(Note 6)

8 Am28F512

READ ONLY MODE

When VPP is less than V is inactive. The device can either read array or autoselect data, or be standby mode.

+ 2 V, the comm and regis ter

Read

The device f unc t ion s as a r ea d o nly m em ory wh en V < V

+ 2 V . The de v ice ha s tw o con tro l fu ncti ons . Bo th

must be satisfied in order to output data. CE# controls power to the d evice. This pin sh ould be used for specific device sele ctio n. OE# c ontro ls the device ou tputs and shou ld be used to gate data to the output pin s if a device is selected.

Address access time t

is equal to the delay from

ACC

stable addresses to valid ou tput data. Th e ch i p en able access time tCE is the delay from stable addresses and stable CE# to valid data at the output pins. The output enable access time is the delay from the falling edge of OE# to valid data at the output pins (assuming the addresses have been stable at least t

ACC–tOE

Standby Mode

The device has two standby modes. The CMOS standby mode (CE# input held at V sumes less t han 100 µA o f c urr ent . TTL s ta ndb y mode (CE# is held at VIH) reduces the current requirements to less than 1mA. When in the standby mode the outputs are in a h igh imp eda nce s ta te , i nde pend ent of th e OE# input.

If the device is deselected during eras ure, programming, or p rogram/erase verificati on, the device will draw active current until the operation is terminated.

0.5 V), con-

Output Dis a ble

Output from the device is disabled when OE# is at a logic high level. When disabled, output pins are in a high impedance state.

Auto Select

Flash memories can be programmed in-system or in a standard PROM programmer. The device may be soldered to the circuit board upon receipt of shipment and programmed in-system. Alternatively, the device may initially be programmed in a PROM programmer pr ior to soldering the device to the board.

The Auto select mode allows the reading out of a binary code from the device that will identify its manufacturer and type. T his mode is i ntended for the pu rpose of automatically matching the device to be programmed with its corresp onding programming algorithm. This mode is functional over the entire temperature range of the device.

Programming In A PROM Programmer

To activate thi s mode, the programmin g equipm ent must force VID (11.5 V to 13.0 V ) on addre ss A9 . Two identi fie r b yte s ma y th en be seq uence d fr om th e de vi ce outpu ts b y t oggli ng addr ess A0 from VIL to VIH. All other address lines must be held at VIL, and VPP must be less than or equal to VCC + 2.0 V while using this Auto select mode. Byte 0 (A0 = VIL) repr esen ts th e man uf acturer code and byte 1 (A0 = VIH) the device identifier code. For the device these two bytes are given in Table 2 below. All identifiers for manufacturer and device codes will exhibit odd parity with the MSB (DQ7) defined as the parity bit.

Table 2. Am28F512 Auto Select Code

Type A0 Code (HEX)

Manufacturer Code V Device Code V

01 25

Am28F512 9

ERASE, PROGRAM, AND READ MODE

When VPP is equal to 12.0 V ± 5%, the command register is active. All fu nctions ar e available. Tha t is, the device can program, erase, read array or autoselect data, or be standby mode.

Write Operations

High voltage must be applied to the VPP pin in order to activate the command register. Data written to the register serves as input to the internal state machine. The output of the state machine determines the operational function of the device.

Refer to AC Writ e Chara cteris tics and th e Erase/ Programming Waveforms for specific timing parameters.

Command Definitions

The contents of the command register default to 00h (Read Mode) in the absence of high voltage applied to the VPP pin. The device opera tes as a rea d only mem ory. High voltage on the VPP pin enables the co mma nd regist e r. Device op er a t ion s ar e s e lec t e d by writin g s p ecific data codes into the command register. Table 3 defines thes e re gist e r com m and s.

The command register does not occupy an addressable memory location. The register is a latch that stores the command, along with the address and data information needed to execute the command. The register is written by bringing WE# and CE# to VIL, while OE# is at VIH. Addresses are latched on the falling edge of WE#, while data is latched on the rising edge of the WE# pulse. Standard microprocessor write timings are used.

The device requires the OE# pin to be VIH for write operations. This condition eliminates the possibility for bus contention during programming operations. In order to write, OE# must be VIH, and CE# and WE# must be VIL. If any pin is not in the correct state a write command will not be executed.

Read Command

Memor y conte nts can be acces sed via th e read com mand when VPP is high. To read from the device, write 00h into the command register. Standard microprocessor read cycles access data from the memory. The device will remain in the read mode until the command register contents are altered.

The comma nd register defaults to 00h (r ead mode) upon VPP power -up . The 00h (Re ad Mode ) regis ter default helps ensure that inadvertent alteration of the memory contents does not occur during the VPP power transition. Refer to the AC Read Characteristics and Waveform s for the spec ifi c timi n g para m ete rs.

Table 3. Am28F512 Command Definitions

First Bus Cycle Second Bus Cycle

Operation

Command (Note 4)

Read Memory Write X 00H/FFh Read RA RD Read Auto select Write X 80h or 90h Read 00h/01h 01h/25h

(Note 1)

Address

(Note 2)

Data

(Note 3)

Operation

(Note 1)

Address

(Note 2)

Data

(Note 3)

Erase Set-up/Erase Write Write X 20h Write X 20h Erase-Verify Write EA A0h Read X EVD Program Set-up/ Program Write X 40h Write PA PD Program-Verify Write X C0h Read X PVD Reset Write X FFh Write X FFh

Notes:

1. Bus operations are defined in Table 1.

2. RA = Address of the memory location to be read. EA = Address of the memory location to be read during erase-verify. PA = Address of the memory location to be programmed. X = Don’t care. Addresses are latched on the falling edge of the WE

3. RD = Data read from location RA during read operation. EVD = Data read from location EA during erase-verify. PD = Data to be programmed at location PA. Data latched on the rising edge of WE PVD = Data read from location PA during program-verify. PA is latched on the Program command.

4. Refer to the appropriate section for algorithms and timing diagrams.

pulse.

10 Am28F512

FLASHERASE ERASE SEQUENCE Erase Setup

Erase Setup is the first of a two-cycle erase command. It is a com mand -only ope ration th at stag es the device for bulk chip erase. T he array cont ent s are no t altere d with t his co mma nd . 20 h is wri tte n t o t h e com ma nd re gister in order to perform the Erase Setup operation.

Erase

The seco nd two-cycle e rase comman d initiates th e bulk erase operation. You must write the Erase command (20h) again to the register. The erase operation begins with the rising edge of the WE# pulse. The erase operation mu st be ter minated by writin g a new command (Erase-verify) to the register .

This two ste p seq uenc e o f the Set up an d E rase c ommands h elps to ensure th at memo ry c ontents are not accidentally eras ed . Al so, chi p e rasu re ca n only occ u r when hig h vo ltag e is appl ied to the VPP pin an d al l c o ntrol pins are in their proper state. In absence of this high voltage, me mor y contents c annot be altere d. Refer to AC Erase Characteristics and Waveforms for specific timing parame ters.

Note: The Flash memory device must be fully programmed to 00h data prior to erasure. This equalizes the charge on all memory cells ensuring reliable era sure.

Erase-V erify Command

The erase op eration erases all bytes of the array in pa ral lel. After the e ras e op era ti on , all byte s mu s t b e sequentially verified. The Erase-verify operation is initi-

ated b y w ri tin g A 0 h to t he reg i s ter. The byte ad dr es s to be verified must be supplied with the command. Addresses are latc hed on the falling edge of the WE # pulse or CE# pulse, whichever occurs later. The rising edge of the WE# pulse terminates the erase operation.

Margin Verify

During the Erase-verify operation, the device applies an internally generated margin voltage to the addressed byte. Reading FFh from the addressed byte indicates that all bits in the byte are properly erased.

Verify Next Address

You must write the Erase-verify command with the appropriate address to the register prior to verification of each address. Each new address is latched on the falling edge of WE# or CE# pulse, whichever occurs later. The process co ntinues for each byte in the memor y array until a byte does not return FFh data or all the bytes in the array are accessed and verified.

If an address is not verified to FFh data, the entire chip is erased again (refer to Erase Setup/Erase). Erase verifica tion then resumes at the ad dress tha t failed to verify. Erase is complete when all bytes in the array have been verified. The device is now ready to be programmed. At this point, the verification operation is terminated by writing a valid command (e.g. Program Setup) to the command register. Figure 1 and Table 4, the Flasherase electrical erase algorithm, illustrate how commands and bus operations are combined to perform electrical erasure. Refer to AC Erase Characteristics and Waveforms for specific timing parameters.

Am28F512 11

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