AMD Am28F256A Service Manual

FINAL

Am28F256A

256 Kilobit (32 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms

DISTINCTIVE CHARACTERISTICS

■ High performance

— Access times as fast as 70 ns

■ CMOS low power consumption

— 30 mA maximum active current — 100 µA maximum standby current — No data retention power consumption

■ Compatible with JEDEC-standard byte-wide

32-Pin EPROM pinouts

— 32-pin PDIP — 32-pin PLCC — 32-pin TSOP

■ 100,000 write/erase cycles minimum

■ Write and erase voltage 12.0 V ±5%

■ Latch-up protected to 100 mA from –1 V to

+1 V

■ Embedded Erase Electrical Bulk Chip-Erase

— 1.5 seconds typical chip-erase including

pre-programming

■ Embedded Program

— 14 µs typical byte-program including time-out — 0.5 second typical chip program

■ Command register architecture fo r

microprocessor/microcontroller compatible write interface

■ On-chip address and data latches

■ Advanced CMOS flash memory technology

— Low cost single transistor memory cell

■ Embedded

self-timed write/erase operations

algorithms fo r completely

GENERAL DESCRIPTION

The Am28F256A is a 256 K Flash memory organized as 32 Kbytes of 8 bits each. AMD’s Flash memories offer the most cost-effective and reliable read/write non- volatile rand om access memory . The Am28F256A is packaged in 32-pin PDIP, PLCC, and TSOP versions . It is designed to be reprogrammed and erased in-system or in standard EPROM programmers. The Am28F256A is erased when shipped from the factory.

The standard Am28F256A offers access times as fast as 70 ns, allowing operation of high-spee d microprocessors without wait states. To eliminate bus contention, the Am28F256A has separate chip enable (CE#) and output enable (OE#) controls.

AMD’s Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The Am28F256A uses a command register to manage this functionality, while maintaining a standard JEDEC Flash Standard 32-pin pinout. The command registe r allows for 100% TTL level control inputs and fixed power supply levels during erase and programming.

AMD’s Flash technology reliably stores me mory contents even after 100,000 erase and program cycles. The AMD cell is designed to optimize the erase and

programming mechanisms. In addition, the combination of advanced tunnel o xide processing and l ow internal electric fields for erase and programming operations produces reliable cycling. The Am28F256A uses a 12.0V ± 5% V the erase

The highest degree of latch-up protection is achieved with AMD’s proprietary non-epi process. Latch-up protection is provided for stresses up to 100 milliamps on address and data pins from –1 V to V

and programming functions.

high voltage i nput to perfor m

+1 V.

Embedded Program

The Am28F256A is byte programmable using the Embedded Program ming algorithm. The Em bedded Programming algorithm does not require the system to time-out or verify the data programmed. The typical room temperature programming time of the Am28F256A is one half second.

Embedded Erase

The entire chip is bulk erased using the Embedded Erase algorithm. The Embedded automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are

Erase algorithm

Publication# 18879 Rev: C Amendment/+2 Issue Date: May 1998

controlled internal to the device. Typical erasure at room temperature is acco mplished in 1 .5 seconds, including preprogramming.

Comparing Embedded Algorithms with Flasherase and Flashrite Algorithms

AMD’s Am28F256A is entirely pin and software compatible with AMD’s Am28F020A, Am28F256A and Am28F512A Flash memories.

Embedded Programming Algorithm vs. Flashrite Programming Algorithm

Embedded Erase Algorithm vs. Flasherase Erase Algorithm

Am28F256A with

Embedded Algorithms

AMD’s Embedded Programming algorithm requires the user to only write a program set-up command and a program command (program data and address). The device automatically times the programming pulse width, verifies the programming, and counts the number of sequences. A status bit, Data the programming operation status.

AMD’s Embedded Erase algorithm requires the user to only write an erase setup command and erase command. The device automatically pre-programs and verifies the entire array. The device then automatically times the erase pulse width, verifies the erase operation, and counts the number of sequences. A status bit, Data erase operation status.

# Polling, provides the user with

# Polling, provides the user with the

Am28F256 using AMD Flashrite

and Flasherase Algorith ms

The Flashrite Programming algorithm requires the user to write a program set-up command, a program command, (program data and address), and a program verify command, followed by a read and compare operation. The user is required to time the programming pulse width in order to issue the program verify command. An integrated stop timer prevents any possibility of overprogramming.

Upon completion of this sequence, the data is read back from the device and compared by the user with the data intended to be written; if there is not a match, the sequence is repeated until there is a match or the sequence has been repeated 25 times.

The Flasherase Erase algorithm requires the device to be completely programmed prior to executing an erase command.

To invoke the erase operation, the user writes an erase set-up command, an erase command, and an erase verify command. The user is required to time the erase pulse width in order to issue the erase verify command. An integrated stop timer prevents any possibility of overerasure.

Upon completion of this sequence, the data is read back from the device and compared by the user with erased data. If there is not a match, the sequence is repeated until there is a match or the sequence has been repeated 1,000 times.

Commands are written to the command register using standard microprocessor write timings. Register contents serve as inputs to an internal state-machine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. For system design simplification, the Am28F256A is designed to support either WE# or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the rising

the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal.

AMD’s Flash technology combines years of EPROM and EEPROM experience to produce the highest lev els of quality, reliability, and cost effectiveness. The Am28F256A electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.

edge of WE# or CE# whichever occurs first. To simplify

2 Am28F256A

BLOCK DIAGRAM

Erase

Voltage

Switch

DQ0–DQ7

Input/Output

Buffers

WE#

CE# OE#

Low V Detector

A0–A14

State

Control

Command

Embedded Algorithms

Program/Erase

Pulse Timer

Program

Voltage

Switch

To Array

Address

Latch

Chip Enable

Output Enable

Logic

Y-Decoder

X-Decoder

Data

Latch

Y-Gating

262,144

Bit

Cell Matrix

18879C-1

PRODUCT SELECTOR GUIDE

Family Part Number Am28F256A Speed Options (V Max Access Time (ns) 70 90 120 150 200

# (E#) Access (ns) 70 90 120 150 200

# (G#) Access (ns) 35 35 50 55 55

= 5.0 V ±10%) -70 -90 -120 -150 -200

Am28F256A 3

CONNECTION DIAGRAMS

PDIP

PLCC

NC NC

A12

DQ0 DQ1 DQ2

A7 A6 A5

A4 A3 A2

A1 A0

1 2 3 4 5

6 7

8 9 10 11 12

13 14 15 16

32 31 30 29 28

27 26

25 24 23 22

21 20

19 18 17

Note: Pin 1 is marked for orientation.

WE# (W#) NC A14

A13 A8 A9 A11

(G#)

OE# A10 CE# (E#)

DQ7 DQ6

DQ5 DQ4

DQ3

18879C-2

A7 A6 A5

A4 A3 A2 A1 A0

DQ0

5 6

8 9 10

11 12 13

A12

DQ1

DQ2

DQ3

WE# (W#)

31 30

19 2016

DQ4

DQ5

29 28 27

26 25 24 23 22 21

DQ6

A14 A13

A9 A11 OE# (G#)

A10 CE# (E#) DQ7

18879B-3

4 Am28F256A

CONNECTION DIAGRAMS (continued)

A11

A13 A14

A12

OE#

A10

CE#

D7 D6 D5 D4 D3

D2 D1 D0

A0 A1 A2 A3

A9 A8

NC NC

A7 A6 A5 A4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

32-Pin — Standard Pinout

32-Pin — Reverse Pinout

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

OE# A10 CE# D7 D6 D5 D4 D3 V

D2 D1 D0 A0 A1 A2 A3

A11 A9 A8 A13 A14 NC WE# V

NC NC A12 A7 A6 A5 A4

18879C-4

LOGIC SYMBOL

A0–A14

CE# (E#) OE# (G#)

WE# (W#)

DQ0–DQ7

18879C-5

Am28F256A 5

ORDERING INFORMATION Standard Products

AM28F256A -70 J C

DEVICE NUMBER/DES CR IPT IO N

Am28F256A 256 Kilobit (32 K x 8-Bit) CMOS Flash Memory with Embedded Algorithms

OPTIONAL PROCESSING

Blank = Standard Pro ces sin g B = Burn-In

Contact an AMD representative for more information.

TEMPERATURE RANGE

C=Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C)

PACKAGE TYPE

P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

AM28F256A-70 AM28F256A-90 AM28F256A-120 AM28F256A-150 AM28F256A-200

Valid Combinations

PC, PI, PE,

EC, EI, EE,

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

JC, JI, JE,

FC, FI, FE

6 Am28F256A

PIN DESCRIPTION

A0–A14

Address Inputs for memory locations. Internal latches hold addresses during write cycles.

CE# (E#)

Chip Enable active lo w input activates the chip’ s control logic and input buffers. Chip Enable high will deselect the device and operates the chip in stand-by mode.

DQ0-DQ7

Data Inputs during memory write cycles. Internal latches hold data during write cycles. Data Outputs during memory read cycles.

No Connect-corresponding pin is not connected internally to the die.

OE# (G#)

Output Enable active low input gates the outputs of the device through the data buffers during memory read cycles. Output Enable is high during command sequencing and program/erase operations.

Pow er supply f or de vice operat ion. (5.0 V ± 5% or 10%)

Program voltage input. VPP must be at high voltage in order to write to the command register. The command register controls all functions required to alt er the memory array contents. Memory contents cannot be a ltered when V

Ground.

≤ V

+2 V.

WE# (W)

Write Enable active low input controls the write function of the command register to the memory array . The target address is latche d on the falling edge of the Write Enable pulse and the appropriate data is latched on the rising edge of the pulse. Write Enable high inhibits wr iting to the device.

Am28F256A 7

BASIC PRINCIPLES

This section contains descriptions about the device read, erase, and program operations, and write operation status of the Am29FxxxA, 12.0 volt f amily of Flash devices. References to some tables or figures may be

given in generic form, such as “Command Definitions table”, rather than “ Table 1”. Refer to the corresponding data sheet for the actual table or figure.

The Am28FxxxA family uses 100% TTL-level control inputs to manage the comman d register. Erase and reprogramming operations use a fixed 12.0 V ± 5% high voltage input.

Read Only Memory

Without high VPP voltage, the device functions as a read only memory and operates like a standard EPROM. The control inputs still manage traditional read, standby, out put disable, and Auto select modes.

Command Register

The command register is enabled only when high voltage is applied to the V gramming operations are only accessed via the register. In addit i on, two-cycle commands are required for erase and reprogramming operations. The traditional read, standby, output disable, and Auto select modes are available via the register.

The device’s command register is written using standard microprocessor write timings. The register controls an intern al state machi ne that manag es all device operations. For system design simplification, the device is designed to support either WE# or CE # controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# o r CE# whichever occurs last . Data is latched on the rising edge of WE# or CE# whichever occur first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal.

pin. The erase and repro-

OVERVIEW OF ERASE/PROGRAM OPERATIONS

Embedded

AMD now makes erasure extremely simple and reliable. The Embedded Erase algorithm requires the user to only write an erase setup command and erase command. The device will automatica lly pre-program and verify the entire array. The device automatically times the erase pulse width, provides the erase verify and counts the number of sequences. A status bit, Data# Polling, provides feedback to the user as to the status of the erase operation.

Erase Algorithm

Embedded Programming Algorithm

AMD now makes programming extremely simple and reliable. The Embedded Programming algorithm requires the user to only write a program setup command and a program command. The device automatically times the programming pulse width, provides the program verify and counts the number of sequences. A status bit, Data# Polling, provides feedback to the user as to the status of the programming operation.

DATA PROTECTION

The device is designed to offer protection against accidental erasur e or programming ca used by spurious system level signals that ma y e xist during power t ransitions. The device po wers up in its read only state . Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences.

The device also incor porates several features to prevent inadvertent wr ite cycles resulting from V power-up and power-down trans itions or system noise.

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up and power-down, the device locks out write cycles for

< V

ages). When V abled, all internal program/erase circuits are disabled, and the device resets to the read mode. The dev ic e ignores all writes until V that the control pins are in the correct logic state when

> V

(see DC characteristics section for volt-

LKO

< V

to prevent unintentional writes.

, the command register is dis-

LKO

> V

. The user must ensure

LKO

Write Pulse “Glitch” Protection

Noise pulses of less than 10 ns (typical) on OE#, CE# or WE# will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE# = VIL, CE# =V and WE# must be a logical zero while OE# is a logical one.

or WE# = VIH. To initiate a write cycle CE#

Power-Up Write Inhibit

Power-up of the device with WE# = CE# = VIL and OE# = V edge of WE#. The internal state machine is automatically reset to the read mode on power-up.

will not accept commands on the rising

8 Am28F256A

FUNCTIONAL DESCRIPTION Description Of User Modes

Table 1. Am28F256A Device Bus Operations (Notes 7 and 8)

Read-Only

Read/Write

CE#

Operation

(E#)

Read V Standby V Output Disable V Auto-select Manufacturer

Code (Note 2) Auto-select Device

Code (Note 2) Read V

Standby (Note 5) V Output Disable V Write V

OE# (G#)

V V

WE# (W#)

XXV

(Note 1) A0 A9 I/O

PPL

PPH

A0 A 9 D

X X HIGH Z X X HIGH Z

(Note 3)

A0 A9

X X HIGH Z X X HIGH Z

A0 A9

Legend:

X = Don’t care, where Don’t Care is either V

of V

. 0 V < An < VCC + 2 V, (normal TTL or CMOS input levels, where n = 0 or 9).

PPH

or VIH levels. V

= VPP < VCC + 2 V. See DC Characteristics for voltage levels

PPL

Notes:

1. V

may be grounded, connected with a resistor to ground, or < VCC + 2.0 V . V

PPL

the device. Refer to the DC characteristics. When V

= V

, memory contents can be read but not written or erased.

PPL

is the programming voltage specified for

PPH

2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2.

3. 11.5 < V

4. Read operation with V

5. With V

6. Refer to Table 3 for valid D

7. All inputs are Don’t Care unless otherwise stated, where Don’t Care is either V addresses except A

8. If V

< 13.0 V. Minimum VID rise time and fall time (between 0 and VID voltages) is 500 ns.

= V

at high voltage, the standby current is ICC + IPP (standby).

and A0 must be held at VIL.

≤

1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the Am28F256 has a VPP

may access array data or the Auto select codes.

PPH

during a write operation.

or VIH levels. In the Auto select mode all

rise time and fall time specification of 500 ns minimum.

OUT

CODE

(01h)

CODE

(2Fh) D

OUT

(Note 4)

(Note 6)

Am28F256A 9

READ-ONLY MODE

When VPP is less than V is inactive. The device can either read array or autoselect data, or be standby mode.

+ 2 V , the command register

Read

The device functions as a read only memory when V < V

+ 2 V. The de vice has two control functi ons. Both

must be satisfied in order to output data. CE# controls power to the device. This pin should be used for specific device selection. OE# controls the device outputs and should be used to gate data to the output pins if a device is selected.

Address access time t

is equal to the delay from

ACC

stable addresses to valid output data. The chip enable access time t

is the delay from st able addres ses and

stable CE# to valid data at the output pins. The output enable access time is the delay from the f alling edge of OE# to valid data at the output pins (assuming the addresses have been stable at least t

ACC

- tOE).

Standby Mode

The device has two standby modes. The CMOS standby mode (CE# input held at V

sumes less than 100 µA of current. TTL standby mode (CE# is held at V

) reduces the current requirements

to less than 1 mA. When in the standby mode the outputs are in a high impedance state, independent of the OE# input.

If the device is deselected during erasure, programming, or program/erase verification, the device will draw activ e current until the operation is terminated.

± 0.5 V), con-

Output Disable

Output from the device is disabled whe n OE# is at a logic high level. When disabled, output pins are in a high impedance state.

Auto Select

Flash memories can be programmed in-system or in a standard PROM programmer. The device may be soldered to the circuit board upon receipt of shipment and programmed in-system. Alternatively, the device may initially be programmed in a PROM programmer prior to soldering the device to the board.

The Auto select mode allows the reading out of a binary code from the device that will identify its manufacturer and type. This mode is intended for the purpos e of autom atically matching the device to be programmed with its corresponding p rogramming algorithm . This mode is functional over the entire temperature range of the device.

Programming In A PROM Programmer

To activate this mode, the programming equipment must force V identifier bytes ma y then be sequenced from the device outputs by toggling address A0 f rom V address lines must be held at V less than or equal to V select mode. Byte 0 (A0 = V turer code and byte 1 (A0 = V code. For t he device t he two b ytes are given in the table 2 of the device data sheet. All identifiers for manufacturer and device codes will exhibit odd parity with the MSB (DQ7) defined as the parity bit.

(11.5 V to 13.0 V) on address A9. Two

to VIH. All other

, and VPP must be

+ 2.0 V while using this Auto

) represents the manufac-

) the device identifier

Table 2. Am28F256A Auto Select Code

Type A0

Manufacturer Code V Device Code V

10 Am28F256A

Code

(HEX)

01 2F

ERASE, PROGRAM, AND READ MODE

When VPP is equal to 12.0 V ± 5%, the command reg-

ister is active. All functions are available. That is, the device can program, erase, read array or autoselect data, or be standby mode.

Write Operations

High voltage must be applied to the VPP pin in order to activate the command register. Data written to the register serves as input to the internal state machine. The output of the state machine determines the operational function of the device.

The command register does not occupy an addressable memory location. The register is a latch that stores the command, along with the address and data information needed to execute the command. The register is written by bringing WE# and CE# to V is at V

. Addresses are latched on the falling edge of

WE#, while data is latched on the rising edge of the WE# pulse. Standard microprocessor write timings are used.

The device requires the OE# pin to be V erations. This condition eliminates the possi bility for bus contention during programming operations. In order to write, OE# must be V must be V

. If any pin is not in the correct state a write

, and CE# and WE#

command will not be executed.

, while OE#

for write op-

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

Command Definitions

The contents of the command register default to 00h (Read Mode) in the abs ence of hi gh v oltage applie d to the V memory. High voltage on the V

pin. The device operates as a read only

pin enables the

command register. Device operations are selected by writing specific data codes i nto the command regi ster. Tabl e 3 in the de vice data sheet def ines these regis ter commands.

Read Command

Memory contents can be accessed via the read command when V 00h into the command register. Standard microprocessor read cycles access data from the memory. The device will remain in the read mode until the command register contents are altered.

The command register defaults to 00h (read mode) upon V

fault helps ensure that inadvertent alteration of the memory contents does not occur during the V transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.

is high. To read from the device, write

power-up. The 00h (Read Mode) register de-

power

Table 3. Am28F256A Command Definitions

First Bus Cycle Second Bus Cycle

Operation

Command

Read Memory (Note 4) Write X 00h/FFh Read RA RD Read Auto select Write X 80h or 90h Read 00h/01h 01h/2Fh Embedded Erase Set-up/

Embedded Erase Embedded Program Set-up/

Embedded Program Reset (Note 4) Write X 00h/FFh Write X 00h/FFh

Notes:

1. Bus operations are defined in Table 1.

2. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE

X = Don’t care.

3. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data latched on the rising edge of WE

4. Please reference Reset Command section.

(Note 1)

Write X 30h Write X 30h

Write X 10h or 50h Write PA PD

Address

(Note 2)

pulse.

Data

(Note 3)

Operation

(Note 1)

Address

(Note 2)

Data

(Note 3)

Am28F256A 11

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