AMD Advanced Micro Devices AM28F256-90JEB, AM28F256-90JE, AM28F256-90JCB, AM28F256-90JC, AM28F256-90FIB Datasheet

FINAL

Am28F256

256 Kilobit (32 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory

DISTINCTIVE CHARACTERISTICS

High performance

■

— 70 ns maximum access time

CMOS Low power consumption

■

— 30 mA maximum active current
— 100 µA maximum standby current
— No data retention power consumption

Compatible with JEDEC-standard byte-wide

■

32-Pin EPROM pinouts

— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP

10,000 write/erase cycles minimum

■

Write and erase voltage 12.0 V ±5%

■

■

■

■

■

■

■

■

Latch-up protected to 100 mA
from –1 V to V

Flasherase

+1 V

CC

Electrical Bulk Chip-Erase

— One second typical chip-erase

Flashrite Programming

— 10 µs typical byte-program
— 0.5 second typical chip program

Command register architecture for
microprocessor/microcontroller compatible
write interface

On-chip address and data latches
Advanced CMOS flash memory technology

— Low cost single transistor memory cell

Automatic write/erase pulse stop timer

GENERAL DESCRIPTION

The Am28F256 is a 256 K Flash memory organized as
32 Kbytes of 8 bits each. AMD’s Flash memories offer
the most cost-effective and reliable read/write non­volatile random access memory. T he Am28F256 is
packaged in 32- pin PDIP, PLCC, and TSOP versions. It
is designed to be repr ogram med and erased in- system
or in standard EPROM programmers. The Am28F256
is erased when shipped from the factory.

The standard Am28F256 offers acc ess times as f ast as
70 ns, allowing operation of high-speed microproces­sors without wait states. To eliminate bus contention ,

#

the Am28F256 has separate chip enable (CE
output enable (OE

#

) controls.

AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F256 uses a comman d register to manage t his
functiona lity, wh ile maintaini ng a standard J EDEC
Flash Standard 32-pin pinout. The comma nd register
allows for 100% TTL level control inputs and f ixed
power supply levels during erase and programming.

AMD’s Flash technology reliably sto res memory
contents even after 10,000 erase and program cycles.

) and

The AMD cell is de signed to optimize t he erase an d
programming m echanisms. In a ddition, th e combina­tion of advanc ed tunnel oxide processin g and low
internal electric fields for erase and programming
operations produces r eliable cycling. The Am28 F256
uses a 12.0 V±5% V
the Flasherase

and Flashrite algorithms.

high voltage input to pe rform

PP

The highest degree of latch-up protection is achieved
with AMD’s proprietary non-epi process. Latch-up
protection is provided for stresses up to 100 milliamps
on address and data pins from –1 V to V

CC

+1 V.

The Am28F256 is by te programmable using 10 µs
programming pulses in accordance with AMD’s
Flashrite programming algorithm. The typical room
temperature programming time of the Am28F256 is a
half a second. The entire chip is bulk erased using
10 ms erase pulses accordi ng to AMD’s Fla sheras e
alrogithm. Typical erasure at room temperature is
accomplished in less than one second. The windowed
package and the 15-20 minute s required for EPROM
erasure using ultra-violet light are eliminated.

Publicatio n#
Issue Date:

Rev: GAmendm ent/

11560

January 1998

+2

Commands are written to the command register using
standard microprocessor write timings. Register con­tents se rve as inp uts to an internal state-machi ne which
controls the erase and programming circ uitry. During
write cycles, the command register internally latches ad­dress and data needed for the programming and erase
operations. For system design simplification, the

#

Am28F256 is designed to support either WE

or CE

controlled writes. Dur ing a system write cycle, ad-

#

dresses are latched on the falling edge of WE

or CE

whiche v er o ccur s las t. Data is latc hed on the rising edge

#

or CE# whichev er occurs first . To simplify the fo l-

of WE

BLOCK DIAGRAM

V

CC

V

SS

V

PP

Erase

Voltage

Switch

#

lowi ng discu ssion, the WE

pin is used as the write cycle

control pin throughout the rest of this text. All setup and

#

hold times are with respect to the WE

signal.

AMD’s Flash technology combines years of EPROM
and EEPROM ex perience to produce the highest le vels
of quality, reliability, and cost effectiveness. The
Am28F2 56 electri cally eras es all bits simultane ously

#

using Fowler-N ordheim tunneling. The bytes are
programmed one byte at a time using the EP ROM

#

programming mechanism of hot electron injection.

DQ0–DQ7

Input/Output

Buffers

To Array

Address

Latch

Chip Enable

Output Enable

Logic

Y-Decoder

X-Decoder

Data

Latch

Y-Gating

262,144

Bit

Cell Matrix

11560F-1

WE#

CE#

OE#

Low V

Detector

A0–A14

CC

State

Control

Command

Register

Program

Voltage

Switch

Program/Erase

Pulse Timer

PRODUCT SELECTOR GUIDE

Family Part Number
Speed Options (V
Max Access Time (ns) 70 90 120 150 200
CE# (E#) Access (ns) 70 90 120 150 200
OE# (G#) Access (ns) 35 35 50 55 55

= 5.0 V ± 10%)

CC

-70 -90 -120 -150 -200

Am28F256

2 Am28F256

CONNECTION DIAGRAMS

V

PP

NC
NC

A12

A7
A6

A5
A4

A3
A2

A1

A0
DQ0
DQ1

DQ2

V

SS

1
2
3

4
5

6
7

8
9

10
11

12
13

14
15
16

PDIP

32
31
30
29
28

27
26

25
24
23
22
21

20
19

18
17

V

CC

WE# (W#)
NC
A14

A13
A8
A9
A11
OE# (G#)
A10

CE# (E#)

DQ7
DQ6

DQ5
DQ4

DQ3

11560F-2

A7
A6
A5

A4
A3
A2
A1
A0

DQ0

5
6

7

8
9
10

11
12
13

14

A12

4

15

DQ1

PLCC

NC

3

2

DQ2

V

NC

17

SS

V

1

DQ3

PP

VCCWE# (W#)

31 30

32

19 2016

18

DQ5

DQ4

NC

29
28
27

26
25
24
23
22
21

DQ6

A14
A13

A8

A9
A11
OE# (G#)

A10
CE# (E#)
DQ7

11560F-3

Note: Pin 1 is marked for orientation.

Am28F256 3

CONNECTION DIAGRAMS (continued)

A11

A9

A8
A13
A14

NC

WE#

V

CC

V

PP

NC
NC

A12

A7

A6

A5

A4

OE#

A10

CE#

D7
D6
D5
D4
D3

V

SS

D2
D1
D0
A0
A1
A2
A3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32-Pin TSOP—Sta ndard Pinout

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

OE#
A10
CE#
D7
D6
D5
D4
D3
V

SS

D2
D1
D0
A0
A1
A2
A3

A11
A9
A8
A13
A14
NC
WE#
V

CC

V

PP

NC
NC
A12
A7
A6
A5
A4

LOGIC SYMBOL

32-Pin TSOP—Reverse Pinout

15

A0–A14

DQ0

–DQ7

CE# (E#)
OE# (G#)

WE# (W#)

11560F-5

11560G-4

8

4 Am28F256

ORDERING INFORMATION
Standard Products

AMD standard products are avai lable in sev eral pac kages and opera ting ranges . The order number (V alid Combinat ion) is formed
by a combination of:

AM28F256 -70 J C

DEVICE NUMBER/DESCRIPTION

Am28F256
256 Kilobit (32 K x 8-Bit) CMOS Flash Memory

B

OPTIONAL PROCESSING

Blank = Standard Processing
B=Burn-In

Contact an AMD representative for more information.

TEMP ERATURE RANGE

C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)

PACKA GE TYPE

P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

AM28F256-70
AM28F256-90
AM28F256-120
AM28F256-150
AM28F256-200

Valid Combinations

PC, PI, PE,

JC, JI, JE,

EC, EI, EE,

FC, FI, FE

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

Am28F256 5

PIN DESCRIPTION
A0–A14

A

ddress Inputs for memory locations. Internal latches

hold addresses during write cycles.

CE# (E#)

Chip Enable activ e low i nput activates the chip’ s control
logic and input buffers. Chip Enable high will deselect
the device and operates the chip in stand-by mode.

DQ0–DQ7

Data Inputs during memory write cycles. Internal
latches hold data during write cycles. Data Outputs
during memory read cycles.

NC

No Connect-correspond ing pin is not connecte d
internally to the die.

#

#

OE

Output Enable active lo w input gates the outputs of the
device through the data buffers during memory
read cy cles. O utput E nable i s high duri ng com mand
sequencing and program/erase operations.

(G

)

V

CC

Po wer supply f or de vice operation. (5.0 V ± 5% or 10%)

V

PP

Program voltage input. VPP must be at high voltage in
order to write to the command register. The command
register co ntrols all fun ctions requ ired to alter the
memor y array contents. Memor y cont ents canno t be

≤ V

altered when V

V

SS

Ground

PP

CC

+2 V.

WE# (W#)

Write Enable active l ow input controls the write function
of the command register to the memory array. The
target address is latched on the falling edge of the
Write Enable pulse and the appropriate data is latched
on the rising edge of the pulse. Write Enable high
inhibits writing to the device.

6 Am28F256

BASIC PRINCIPLES

The device use s 100% TTL-l evel control inputs to
manage the command register. Erase and repro­gramming operations use a fixed 12.0 V ± 5% high
voltage input.

Read Only Memory

Without high VPP voltage, the device functions as a
read only memor y and operate s like a stand ard
EPROM. The control inputs still manage traditional
read, standby, output disable, and Auto select modes.

Command Register

The command register is enabled only when high volt­age is applied to the V
gramming operat ions are only acce ssed via the
register. In addition, two-cycle commands are required
for erase and reprogramming operations. The tradi­tional read, standby, output disable, and Auto select
modes are available via the register.

The device’s command register is writ ten using stan­dard microp rocessor w rite timin gs. The re gister con­trols an internal state machine that manages all device
operations. For syst em desig n simplificat ion, the de ­vice is designed to support either WE# or CE# con­trolled writes. During a system write cycle, addresses
are latched on the falling edge of WE# or CE# which­ever occurs last. Data is latched on the rising edge of
WE# or CE# whichever occur first. To simplify the fol­lowing discussion, the WE# pin is used as the write
cycle control pin throughout the rest of this text. All
setup and hold times are with respect to the WE# sig­nal.

pin. The erase and repro-

PP

Overview of Er as e/Progr am Ope ra ti on s

Flasherase™ Sequence

A multiple step command seq uence is require d to
erase the Flash device (a two-cyc le Erase command
and repeated one cycle verify commands).

Note: The Flash memory array must be completely
programmed to 0’s prior to erasure. Refer to the
Flashrite™ Programming Algorithm.

1. Erase Setup: Write the Setup Erase command to
the command register.

2. Erase: Write the Erase command (same as Setup
Erase comman d) to t he comman d register again.
The second command initiates the er ase operation.
The system software routine s must now time-ou t
the erase pulse wid th (10 ms) prior t o issuing the
Erase-verify command. An integrated stop timer
prevents any possibility of overerasure.

3. Erase-Verify: Wr ite the Erase-verify command to
the command register. This command terminates
the erase ope ration. After the erase op eration,
each byte of the array must be verified. Address in-

formation must be supplied with the Erase-verify
command. This command verifies the mar gin and
outputs the addressed byte in order to compare the
array data with FFh data (Byte erased).
After successful data verification the Erase-verify
command is written again with new address infor­mation. Each byte of t he a rray is sequentially veri­fied in this manner.

If data of the addressed location is not verified, the
Erase sequence is repeated until the entire array is
successfully verified or the sequence is repeated
1000 times.

Flashrite

A three step command sequence (a two- cycle Progr am
command and one cycle Verify command) is required
to program a byte of the Flash arra y. Refer to the Flash­rite

1. Program Setup: Write the Setup Program com-

2. Program: Write the Program command to the com-

3. Program-Verify: Write the Program-verify com-

If data is not verified successfully, the Program se­quence is repeat ed until a success ful comp arison is
verified or the sequence is repeated 25 times.

Programming Sequence

Algorithm.

mand to the command register.

mand register with the appropriate Address and
Data. The system software routines m ust no w time­out the program pulse width (10 µs) prior to issuing
the Progr am-verify co mmand. An in tegrated sto p
timer prevents any possibility of overprogramming.

mand to the command register. This command ter­minates the programming operation. In addition,
this command verifies the margin and ou tputs the
byte just progr ammed in or der to compare the arr a y
data with the original data programmed. After suc­cessful data verification, the programming se­quence is initiated again f or the ne xt b yte address to
be programmed.

Data Protection

The device is designed to off er protection against acci­dental erasure or programming caused by spurious
system lev el signals that ma y exist during power transi­tions. The de vic e power s up i n its read only s tate. A lso,
with its co ntrol reg ister ar chitectu re, alteration of the
memory contents only occurs after successful comple­tion of specific command sequences.

The device also incorporates several features to pre­vent inadv ertent write cycles resulting fromV
up and power-down transitions or system noise.

power-

CC

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up
and power-down, the device locks out write cycles for

Am28F256 7

VCC < V
voltages). When V

(see DC C haracteristics section for

LKO

CC

< V

, the command register is

LKO

disabled, al l internal pro gram/erase circuits are
disabled, and the device resets to the read mode. The
device ignores all writes until V

CC

> V

. The user

LKO

must ensure that the control pins are in the correct logic
state when V

CC

> V

to prev ent uni nitentional writes.

LKO

Write Pulse “Glitch” Protection

Noise pulses of less than 10 ns (typical) on OE#, CE#
or WE# will not initiate a write cycle.

FUNCTIONAL DESCRIPTION
Description Of User Modes

Table 1. Am28F256 Device Bus Operations (Notes 7 and 8)

Logical Inhibit

Writing i s inhibi ted by holding any one of OE# = VIL, CE#

or WE# = VIH. To initiate a write cycle CE# and

= V

IH

WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE# = CE# = VIL and
OE# = V
edge of WE # . The in te rn al st at e ma chine is a ut oma t­ically reset to the read mode on power-up.

will not accept commands on the rising

IH

Read-Only

Read/Write

CE

Operation

(E#)

Read V
Standby V
Output Disable V
Auto-select Manufacturer

Code (Note 2)
Auto-select Device

Code (Note 2)
Read V

Standby (Note 5) V
Output Disable V
Write V

#

IL

IH

IL

V

IL

V

IL

IL

IH

IL

IL

#

OE
(G#)

V

IL

XXV

V

IH

V

IL

V

IL

V

IL

XXV

V

IH

V

IH

#

WE
(W#)

XV

V

IH

V

IH

V

IH

V

IH

V

IH

V

IL

V

PP

(Note 1) A0 A9 I/O

PPL

PPL

V

PPL

V

PPL

V

PPL

V

PPH

PPH

V

PPH

V

PPH

A0 A9 D

XXHIGH Z
XXHIGH Z

V

V

IL

V

IH

ID

(Note 3)

V

ID

(Note 3)

A0 A9

XXHIGH Z
XXHIGH Z

A0 A9

Legend:

X = Don’t care, where Don’t Care is either V

of V

. 0 V < An < VCC + 2 V, (normal TTL or CMOS input levels, where n = 0 or 9).

PPH

or VIH levels. V

IL

= VPP < VCC + 2 V. See DC Characteristics for voltage levels

PPL

Notes:

1. V

may be grounded, connected with a resi stor to ground, or < VCC + 2.0 V. V

PPL

the device. Refer to the DC characteristics. When V

PP

= V

, memory contents can be read but not written or erased.

PPL

is the programming v oltage specified f or

PPH

2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2.

3. 11.5 < V

4. Read operation with V

5. With V

6. Refer to Table 3 for vali d D

7. All inputs are Don’t Care unless otherwise stated, where Don’t Care is either V
addresses except A

8. If V

< 13.0 V. Minimum VID rise time and fall time (between 0 and VID voltages) is 500 ns.

ID

= V

at high voltage, the standby current is ICC + IPP (standby).

PP

≤

1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the Am 28F256 has a VPP

CC

PP

and A0 must be held at VIL.

9

may access array data or the Auto select codes.

PPH

during a write operation.

IN

or VIH levels. In the Auto select mode all

IL

rise time and fall time specification of 500 ns minimum.

OUT

CODE

(01h)

CODE

(A1h)
D

OUT

(Note 4)

D

IN

(Note 6)

8 Am28F256

READ ONLY MODE

When VPP is less than V
is inactive. The device can either read array or autose­lect data, or be standby mode.

+ 2 V, the command regist er

CC

Read

The devic e functi ons as a read only memory when V
< V

+ 2 V. The device has two control functions. Both

CC

must be satisfied in order to output data. CE# controls
power to the device. This pin should be used for spe­cific device selection. OE# controls the device outputs
and should be used to gate data to the output pins if a
device is selected.

Address acce ss time t

is equal to the de lay from

ACC

stable addresses to valid output data. The chip enable
access time t

is the delay from stable addresses and

CE

stable CE# to valid data at the output pins. The output
enable access time is the del a y from the falling edge of
OE# to valid data at the output pins (assuming the ad­dresses have been stable at least t

ACC–tOE

).

PP

Standby Mode

The device has two standby mo des. The CMOS
standby mode (CE # inp ut held a t V
sumes less than 100 µA of current. TTL standby mode
(CE# is held at V

) reduces the current requirements

IH

to less than 1mA. When in the sta ndby mode the out­puts are in a high impedance state, independent of the
OE# input.

If the d evice is de select ed dur ing er asure, pr ogram­ming, or program/erase verification, the device will
draw active current until the operation is terminated.

CC

±

0.5 V), con-

Output Disable

Output from th e device is disabled when OE# is at a
logic high level. When disa bled, output pins are in a
high impedance state.

Auto Select

Flash memories can be programmed in-system or in a
standard PROM programmer. The device may be sol­dered to the circuit board upon recei pt of shipment and
programmed in-system. Alternatively, the device may
initially be programmed in a PROM programmer prior
to soldering the device to the board.

The Auto select mode allows the reading out of a binary
code from the device that will identify its manufacturer
and type. This mode is intended for the purpose
of automatically matching the device to be pro­grammed with its corresponding programming algo­rithm. Th is mode is functional over the entire
temperature range of the device.

Programming In A PROM Programmer

To activate this mode, the programming equipment
must force V
identifier bytes may then be sequenced from the de vice
outputs by toggling addr ess A
address lin es must be held at V
less than or equal to V
select mode. Byte 0 (A0 = V
turer code and byte 1 (A0 = V
code. For the de vi ce these tw o by tes are giv en in Table
2 below. All identifiers for manufacturer and device
codes will exhibit odd parit y with the MSB (D Q7) de­fined as the parity bit.

(11.5 V to 13.0 V) on address A9. Two

ID

from VIL to VIH. All other

0

, and VPP must be

+ 2.0 V while using this Auto

CC

IL

) represents the manuf ac-

IL

) the device identifier

IH

Ta ble 2. Am28F256 Auto Select Code

Type A0

Manufactur er Code V
Device Code V

Am28F256 9

Code
(HEX)

IL

IH

01
A1

ERASE, PROGRAM, AND READ MODE

When VPP is equal to 12.0 V ± 5%, the command reg­ister is active. All functions are available. That is, the
device can program, erase, rea d array or a utoselec t
data, or be standby mode.

Write Operations

High voltage must be applied to the VPP pin in order to
activate the command register. Data written to the reg­ister serves as input to the internal state machine. The
output of the state machine determines the operational
function of the device.

Refer to AC Write Character istics and the Erase/Pro­gramming Waveforms for specific timing parameters.

Command Definitions

The contents of th e command register default to 00 h
(Read Mode) in the absence of high voltage applied to
the V
ory. High voltage on the V
register . D e vic e operations are selected by writing spe­cific data codes into the command register. Table 3 de­fines these register commands.

pin. The device operates as a read only mem-

PP

pin enables the command

PP

The co mma nd r eg is ter does not occupy an addressable
memory location. The register is a latch that stores the
comman d, al on g wi th th e addr e ss and da ta in form at io n
needed to execute the command. The register is written
by bringing WE# and CE# to V

, while OE# is at VIH.

IL

Addres ses ar e latc hed on th e fa lli ng edge of WE#, while
data is latch ed on the ri sing edge of the WE# pulse.
Standard microprocessor write timings are used.

The device requires the OE# pin to be V

for write op-

IH

erations. This condition eliminates the possibility for
bus contentio n during programmi ng operations. I n
order to write, OE# must be V
must be V

. If any pin is not in the correct state a write

IL

, and CE# and WE#

IH

command will not be executed.

Read Command

Memory contents can be accessed via the read com­mand when V
00h into the command register . Standard micr oproces­sor read cycles access data from the memory. The de­vice will remain in th e read mode until t he command
register contents are altered.

The command register defaults to 00h (read mode)
upon V

PP

fault helps ensure that inadvertent alteration of the
memory contents does not occur during the V
transition. Refer to the AC Read Characteristics and
Waveforms for the specific timing parameters.

is high. To read from the device, write

PP

power-up . The 00h (Read Mode) register de-

PP

Ta ble 3. Am28F256 Command Definitions

First Bus Cycle Second Bus Cycle

Operation

Command (Note 4)

Read Memory Write X 00h/FFh Read RA RD
Read Auto select Write X 80h or 90h Read 00h/01h 01h/A1h
Erase Set-up/Erase Write Write X 20h Write X 20h

(Note 1)

Address

(Note 2)

Data

(Note 3)

Operation

(Note 1)

Address

(Note 2)

Data

(Note 3)

power

Erase-Verify Write EA A0h Read X EVD
Program Setup/Program Write X 40h Write PA PD
Program-Verify Write X C0h Read X PVD
Reset Write X FFh Write X FFh

Notes:

1. Bus operations are defined in Table 1.

2. RA = Address of the memory location to be read.
EA = Address of the memory location to be read during erase-verify.
PA = Address of the memory location to be programmed.
X = Don ’t care.
Addresses are latched on the falling edge of the WE# pulse.

3. RD = Data read from location RA during read operation.
EVD = Data read from location EA during erase-verify.
PD = Data to be programmed at location PA. Data latched on the rising edge of WE#.
PVD = Data read from location PA during program-verify. PA is latched on the Program command.

4. Refer to the appropriate section for algorithms and timing diagrams.

10 Am28F256

FLASHERASE ERASE SEQUENCE
Erase Setup

Erase Setup is the first of a two-cycle erase command.
It is a command-only operation that stages the device
for bulk chip erase. The array contents are not altered
with this command. 20h is written to the command reg­ister in order to perform the Erase Setup operation.

Erase

The second two-cycle erase command initiates the
bulk erase operation. You must write the Erase com­mand (20h) again to the register. The erase operation
begins with the rising edge of the WE# pulse. The
erase operation must be termina ted by writing a new
command (Erase-verify) to the register.

This two step sequence of the Setup and Erase com­mands helps to ensure that memory contents are not
accidentally erased. Also, chip erasure can only occur
when high vol tage is applied to the V
trol pins are in their proper state . In absence of this high
voltage, memory contents cannot be altered. Refer to
AC Erase Characteristics and Waveforms for specific
timing parameters.

pin and all con-

PP

Note: The Flash memory device must be fully
programmed to 00h data prior to erasure. This
equalizes the charge on all memory cells ensuring
reliable erasure.

Erase-Verify Command

The erase operation erases all bytes of the array
in parallel. After the erase operation, all bytes must be
sequentially verified. The E rase- verify operation is initi -

ated by writing A0h to the register . The byte address to
be verified mus t be supp lied with t he comman d. Ad­dresses are latched on the falling edge of the WE#
pulse or CE# pulse, whichever occurs later. The rising
edge of the WE# pulse terminates the erase operation.

Margin Verify

During the Erase-verify operation, the device applies
an internally generated margin voltage to the
addressed byte. Reading FFh from the addressed byte
indicates that all bits in the byte are properly erased.

Verify Next Address

You must write the Erase-verify command with the ap­propriate address to the register prior to verification of
each address. Each new address is latched on the fall­ing edge of WE# or CE# pulse, whichev er occurs later.
The process continues for each byte in the memory
array until a byte does n ot retur n FFh dat a or all the
bytes in the array are accessed and verified.

If an address is not verified to FFh data, the entire chip
is erased again (refer to Erase Setup/Erase). Erase
verification then resumes at the address that failed to
verify. Erase is complet e when all bytes in the array
have been verified. The device is now ready to be pro­grammed. At this point, the v erific ation operation is ter­minated by writing a valid command (e.g. Program
Setup) to the command register. Figure 1 and Table 4,
the Flasherase
commands and bus operations are com bined to per­form electrical erasure . Refer to AC Er ase Char acteris­tics and Waveforms for specific timing parameters.

electrical erase algorithm, illustr ate how

Am28F256 11

Start

Yes

Data = 00h

No

Program All Bytes to 00h

Apply V

PPH

Address = 00h

PLSCNT = 0

Write Erase Setup Command

Write Erase Command

Time out 10 ms

Write Erase Verify

Time out 6 µs

Read Data from Device

No

PLSCNT =

Apply V

Erase Error

No

1000

Increment

PLSCNT

Yes

PPL

Data = FFh

Yes

Last Address

Yes

Write Reset Command

Apply V

PPL

Erasure Completed

Figure 1. Flasherase Electrical Erase Algorithm

No

Increment Address

11559G-6

12 Am28F256

FLASHERASE ELECTRICAL ERASE ALGORITHM

This Flash memory device erases the entire array in
parallel. The erase time depends on V

, temperature,

PP

and number of erase/program cycles on the device. In
general, reprogramming time increases as the number
of erase/program cycles increases.

The Flasherase electrical erase algorithm employs an
interactive closed loop flow to simultaneously erase all
bits in the array. Erasure begins with a read of the mem­ory contents. The device is erased when shipped from
the factory. Reading FFh data from th e device would
immediately be follo wed by ex ecuting the Flashrite pro­gramming algorithm with the appropriate data pattern.

Should the dev ice be currentl y programmed, data other
than FF h will be r eturned from addre ss locatio ns.
Follow the Flasherase algorithm. Uniform and reliable
erasure is ensured by first programming all bits in the
device to their charged state (Data = 00 h). This is
accomplished us ing the Flashr ite Programming

Table 4. Flasherase Electrical Erase Algorithm

Bus Operations Command Comments

algorithm. Erasure then continues with an initial erase
operation. Erase verification (Data = FFh) begins at
address 0000h and continues through the array to the
last address, or until data other than FFh is
encountered. If a byte fails to verify, the device is
erased again. With each erase operation, an
increasing number of bytes verify to the erased state.
Typically, devices are erased in less than 10 0 pulses
(one second). Erase efficiency may be improved by
storing the address of the last byte that fails to verify in
a register. Following the next erase operation,
verification may start at the stored address location. A
total of 1000 erase pulses are allowed per reprogram
cycle, which cor responds to approximately 10 seconds
of cumulativ e erase time. The entire sequence of er ase
and byte verification is performed with high voltage
applied to the V

pin. Figure 1 illustrates the electrical

PP

erase algorithm.

Entire memory must = 00h before erasure (Note 3)

Note: Use Flashrite
programming.

programming algorithm (Figure 3) for

Wait for V

Standby

Write

Standby Duration of Erase Operation (t

Write Erase-Verify (Note 2)

Standby Write Recovery Time before Read = 6 µs
Read Read byte to verify erasure

Standby

Write Reset Data = FFh, reset the register for read operations
Standby Wait for V

Notes:

1. See AC and DC Characteristics for values of V
switchable. When V

2. Erase V erify is perf ormed only after chip er asure. A final read compare ma y be performed (op tional) after the reg ister is written
with the read command.

3. The erase algorithm Must Be Followed to ensure proper and reliable operation of the device.

Erase Setup Data = 20h
Erase Data = 20h

parameters. The V

is switched, V

PP

PPL

PP

may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V.

Initialize:
Addresses
PLSCNT (Pulse count)

Address = Byte to Verify
Data = A0h
Stops Erase Operation

Compare output to FFh
Increment pulse count

Ramp to V

PP

Ramp to V

PP

power supply can be hard-wired to the device or

PP

PPH

PPL

(Note 1)

WHWH2

(Note 1)

)

Am28F256 13

Section

Addresses

CE

OE

WE

AB DEFCG

#

#

#

Data

Out

Compare

Data

Erase

Verification

Proceed per

Erase-

Verify

A0h

Transition

(6 µs)

Data

V

CC

V

PP

AB DEFCG

Bus Cycle Write Write Time-out Write Time-out Read Standby

Command 20h 20h N/A A0h N/A

Function

Erase

Setup

20h

Erase

20h

Erase

(10 ms)

Figure 2. AC Waveforms For Erase Operations

ANALYSIS OF ERASE TIMING WAVEFORM

Note: This analysis does not include the requirement

to program the entire array to 00h data prior to erasure.
Refer to the Flashrite

Programming algorithm.

Erase Setup/Erase

This analysis illustrates the use of two-cycle erase
commands (section A and B). The first erase com­mand (20h) is a Setup command and does not affect
the array data (section A). The second erase com­mand (20h) initiates the erase operation (section B)
on the risi ng ed ge o f thi s W E # pu lse. A ll bytes of t he
memory array are erased in parallel. No address infor­mation is required.

The erase pulse occurs in section C.

Time-Out

A software timing routine (10 ms duration) must be ini­tiated on the rising edge of the WE# pulse of section B.

Note: An integrated stop timer prevents any possibil­ity of overerasure by limiting each time-out period of
10 ms.

Erase-Verify

Upon completion of the erase software timing routine,
the micropro cessor must wr ite the Erase- verify com­mand (A0h). This command terminates the erase oper­ation on the rising edge of the WE# pulse (section D).
The Erase-verify command also stages the device for
data verification (section F).

11559G-7

N/A

Erase

Algorithm

After each erase operation each byte must be verified.
The byte address to be verified must be supplied with

14 Am28F256

the Erase-verify command (section D). Addresses are
latched on the falling edge of the WE# pulse.

Another software timing routine (6 µs duration) mus t be
ex ecuted to allow f or generati on of internal voltages f or
margin checking and read operation (section E).

During Erase-verification (section F) eac h address that
returns FFh data is successfully erased. Each address
of the array is sequentially verified in this manner by re­peating sections D thru F until the entire array is veri­fied or an address fails to verify. Should an address

FLASHRITE PROGRAMMING SEQUENCE
Program Setup

The device is programmed byte by byte. Bytes may be
programmed sequential ly or at random. Program Setup
is the first of a two-cycle program command. It stages
the device for byte programming. The Program Setup
operation is performed by writing 40h to the command
register.

Program

Only after the program S etup operation is complete d
will the next WE # pulse initiate the active programming
operation. The appropr iate address and data for pro­gramming must be av ailab le on the second WE# pulse.
Addresses and data are internally latched on the falling
and rising edge of the WE# pulse respectively. The ris­ing edge of WE# also begins the programming opera­tion. You must write the Program-verify command to
terminate the programming operation. This two step
sequence of the Setup and Program commands helps
to ensure that memor y contents are not accid entally
written. Also, programming can only occur when high
voltage is applied to the V
in their prope r state. In abse nce of this high voltage,
memory contents cannot be programmed.

Refer to AC Char acteristics and Wav ef orms for specific
timing parameters.

pin and all control pins are

PP

Program Verify Command

Following each programmin g operation, t he byte just
programmed must be verified.

Write C0h into the command register in order to initiate
the Program-ver ify operation. The rising edge of th is
WE pulse terminates the programming operation. The

location fail to verify to FFh data, erase the device
again. Repeat sect ions A thru F. Re sume verification
(section D) with the failed address.

Each data change sequence allows the device to use
up to 1,000 erase pulses to completely erase . Typically
100 erase pulses are required.

Note: All address locations must be programmed to
00h prior to erase. This equalizes the charge on all
memory cells and ensures reliable erasure.

Program-v erify oper ation stages the de vi ce for verifica­tion of the last byte programmed. Addresses were pre­viously latched. No new information is required.

Margin Verify

During the Program-verify operation, the dev ice applies
an internally generated margin voltage to the ad­dressed byte . A normal mi croprocessor read c ycle out­puts the data . A successful comp arison betwee n the
programmed byte and the true data indicates that the
byte was successfully programmed. The original pro­grammed data should be stored for comparison. Pro­grammin g then proceeds to the next desired byte
location. Should the byte fail to verify, reprogram (refer
to Program Setup/Program). Figure 3 and Table 5 indi­cate how instructions are combined with the bus oper­ations to perform byte programming. Refer to AC
Programming Characteristics and Waveforms for spe­cific timing parameters.

Flashrite Programming Algorithm

The device Flashrite Programming algorithm employs
an interactive closed loop flow to program data byte by
byte. Bytes ma y be pr ogrammed sequentiall y or at ran­dom. The Flashrite
programming pulses. Each operation is followed by a
byte veri fication to determine when the addressed b yte
has been successfully programmed. The pro gram al­gorithm allows f or up to 25 progr amming oper ations per
byte per reprogramming cycle. Most bytes verify after
the first or second pulse. The entire sequence of pro­gramming and byte verification is performed with high
voltage applied to the V
lustrate the programming algorithm.

Programming algorithm uses 10 µs

pin. Figure 3 and Table 5 il-

PP

Am28F256 15

Increment Address

Start

Apply V

PPH

PLSCNT = 0

Write Program Setup Command

Write Program C omma nd ( A/D)

Time out 10 µs

Write Progra m Verify Command

Time out 6 µs

Read Data from Device

Verify Byte

No

Yes

No

Last Address

Yes

Write Reset Command

Increment PLSCNT

No

PLSC NT =

25?

Yes

Apply V

PPL

Programming Completed

Figure 3. Flashrite Programming Algorithm

Apply V

PPL

Device Failed

11559G -8

16 Am28F256

Table 5. Flashrite Programming Algorithm

Bus Operations Command Comments

Standby

Wait for V
Initialize Pulse counter

Ramp to V

PP

PPH

(Note 1)

Prog ram Set up Data = 40h

Write

Program Valid Address/Data

Standby Duration of Programming Operation (t

WHWH1

)
Write Program-Verify (Note 2) Data = C0h Stops Program Operation
Standby Write Recovery Time before Read = 6 µs
Read Read Byte to Verify Programming
Standby Compare Data Output to Data Expected
Write Reset Data = FFh, resets the register for read operations.
Standby Wait for V

Ramp to V

PP

(Note 1)

PPL

Notes:

1. See AC and DC Characteristics for values of V
switchable. When V

is switched, V

PP

may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V.

PPL

parameters. The V

PP

power supply can be hard-wired to the device or

PP

2. Program Verify is perf ormed only afte r by te p rogram ming. A fin al read/c ompare may be pe rf ormed (opti onal) afte r the r egiste r
is written with the read command.

Am28F256 17

Section

Addresses

CE

OE

WE

A

B

DE FCG

#

#

#

Data

V

CC

V

PP

AB DEFCG

Bus Cycle Write Write Time-out Write Time-out Read Standby

Command 40h

Function

Program

Setup

20h

Program

Address,

Program Data

Program

Command

Latch

Address and

Data

Data

In

N/A

Program

(10 µs)

A0h

C0h

(Stops

Program)

Program

Verify

N/A

Transition

(6 µs)

Data

Out

Compare

Data

Program

Verification

11559G-9

N/A

Proceed per

Programming

Algorithm

Figure 4. AC Waveforms for Programming Operations

ANALYSIS OF PROGRAM TIMING WAVEFORMS
Program Setup/Program

Two-c ycle wr ite comm ands are required for program
operations (section A and B). The first program com­mand (40h) is a Setup command and does not affect
the array data (section A). The second program co m­mand latches address and data required for program­ming on the f al ling and rising edge of WE# respectiv ely
(section B). The rising edge of this WE# pulse (section
B) also initiates the programming pulse. The device is
programmed on a by te by b yte basis either sequenti ally
or randomly.

The program pulse occurs in section C.

18 Am28F256

Time-Out

A software timing routine (10 µs durati on) must be initi­ated on the rising edge of the WE# pulse of section B.

Note: An integrated stop timer pre v ents any possibility
of overprogramming by limiting each time-out period of
10 µs.

Program-Verify

Upon completion of the program timing routine, the mi­croprocessor must write the program-verify command
(C0h). This command terminates the programming op­eration on the rising edge of the WE# pulse (section D).
The program-verify comma nd also stages the d evice
for data verification (section F). Another software timing
routine (6 µs d uration) must be executed to all ow for

generation of internal v ol tages for margin checking and
read operations (section E).

During program-verification (section F) each byte just
programmed is read to compare arra y data with original
program data. When successfully verified, the next de­sired address is progr ammed. Should a byte f ail to v er­ify, reprogram the byte (repeat section A thru F). Each
data change sequence allows the device to use up to
25 program pulses per byte . Typically, bytes are v erified
within one or two pulses.

Parallel Device Erasure

Many applications will use more than one Flash
memory device. Total erase time may be minimized by
implementing a parallel erase algorithm. Flash
memories may erase at different rates. Therefore each
device must be verified separately. When a device is
completely erased and ver ified use a masking code to
prev ent further erasure. The other devic es will continue
to erase until verified. The masking code applied could
be the read command (00h).

Algorithm Timing Delays

There are four different timing delays associated with
the Flasherase

1. The first delay is associated with the V
when V
bus cause an RC ramp. A fter switching on the VPP,
the delay required is proportional to the number of
devices being erased and the 0.1 mF/device. V
must reach its final value 100 ns before commands
are executed.

2. The second dela y time is the erase time pulse width
(10 ms). A software timing routine should be run by
the local microprocessor to time out the delay. The
erase operation must be terminated at the conclu­sion of the timing routine or prior to executing any
system interrupts that may occur during the erase
operation. To ensure proper device operation, write
the Erase-verify operation after each pulse.

3. A third delay time is required for each programming
pulse width (10 ms). The programming algorithm is
interactive and verifies ea ch byte afte r a progra m
pulse. The program oper ation m ust be terminated at
the conclusion of the timing routine or prior to exe­cuting any system interrupts that may occur during
the programming operation.

4. A fourth timing delay associated with both the
Flasherase and Flashrite algorithms is the write re­covery time (6 ms). During this time internal circuitry
is changing voltage levels from the erase/ program
level to those used for margin verify and read oper­ations. An attempt to read the device during this pe­riod will result in possible false data (it may appear
the device is not properly erased or programmed).

Note: Software timing routines should be written in
machine language for each of the delays . Code written
in machine language requires knowledge of the appro­priat e microproce ssor clock spe ed in order to accu ­rately time each delay.

and Flashrite algorithms:

rise-time

first turns on. The capacitors on the V

PP

PP

PP

PP

Power-Up/Power-Down Sequence

The device powers-up in the Read only mode. Power
supply sequencing is not required. Note that if V

1.0 Volt, the voltage difference between V

PP

should not exceed 10.0 Volts. Also, the device has V

CC

and V

≤

CC

PP

rise time and fall time specification of 500 ns minimum.

Reset Command

The Reset command initializes the Flash memory de­vice to the Read mode. In addition, it also provides the
user with a safe method to abort any device operation
(including program or erase).

The Reset command must be wr itten two consecutive
times after the setup Program command (40h). This will
reset the device to the Read mode.

Following any oth er Flash co mmand wr ite th e Reset
command once to the device. This will safely abort any
previous operation and initialize the device to the
Read mode.

The Setup Program command (40h) is the only com­mand that r equires a two s equence res et cycle. The
first Rese t comma nd is inter prete d as program d ata.
However, FFh data is considered null data during pro­gramming operations (memory cells are only pro­grammed from a logical “1” to “0”). The second Reset
command safely aborts the programming operation
and resets the device to the Read mode.

Memory contents are not altered in any case.
This detailed information is for your reference. It may

prove easier to always issue the Reset command two
consecutive times. This eliminates the need to deter­mine if you are in the setup Program state or not.

Programming In-System

Flash memories can be programmed in-system or in a
standard PROM programmer. The device may be sol­dered to the circuit board upon recei pt of shipment and
programmed in-system. Alternatively, the device may
initially be programmed in a PROM programmer prior
to soldering the device to the board.

Am28F256 19

Auto Select Command

AMD’s Flash memories are designed for use in applica­tions where the local CPU alters memory contents. Ac­cordingly, ma nufacturer and device codes must be
accessible while the device resides in the target sys­tem. PROM programmers typically access the signa­ture codes by raisin g A9 to a hig h voltage. However,
multiplexing high voltage onto address lines is not a
generally desired system design practice.

The device contains an Auto Select operation to sup­plement traditional PROM programming methodology.
The operation is initiated by writing 80h or 90h into the
command register. Following this command, a read
cycle address 0000h retrieves the manufacturer code
of 01h. A read cycle from address 0001h returns the
device c ode. To terminate the operation, it is necessary
to write another valid command, such as Reset (FFh),
into the register.

20 Am28F256

ABSOLUTE MAXIMUM RATINGS

Storage Temperature . . . . . . . . . . . . –65 °C to +150°C

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . .–55°C to + 125°C

Voltage with Respect To Ground
All pins except A9 and V

V

(Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

CC

A9 (Note 2). . . . . . . . . . . . . . . . . . . .–2.0 V to +14.0 V

V

(Note 2). . . . . . . . . . . . . . . . . . .–2.0 V to +14.0 V

PP

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC v ol tage on i np ut o r I/O pins is – 0. 5 V. During
voltag e transit ions, inpu ts may ov ershoot V
periods of up to 20 ns. Maxim um DC volt age on input and
I/O pins is V
and I/O pins may overshoot to V
to 20ns.

2. Minimum DC input voltage on A9 and V
During volta ge transitions, A 9 and V

to –2.0 V for periods of up to 20 ns. Maximum DC

V

SS

input voltage on A9 and V
overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output shorted to g r ou nd a t a ti me . Du­ration of the short circuit should not be greater than one
second.

Stresses above those listed under “Absolut e Maximum
Ratings” may cause p ermanent damage to the device. This is
a stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera­tiona l sections of this spe c ificat ion is not i mplied. Exp osure of
the device to absolute maximum rating conditions for extended
periods may affe c t device reliabilit y.

+ 0.5 V. During voltage transitions, input

CC

(Note 1) .–2.0 V to +7.0 V

PP

to –2.0 V for

SS

+ 2.0 V for periods up

CC

pins is –0.5 V.

PP

may overshoot

PP

is +13.0 V which may

PP

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

Industrial (I) Devices

Ambient Temperature (T

Extended (E) Devices

Ambient Temperature (T

V

Supply Voltages

CC

V

. . . . . . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V

CC

Voltages

V

PP

Read . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.6 V

Program, Erase, and Verify. . . . . . +11.4 V to +12.6 V

Operating ranges define those limits between which the
functionality of the device is guaranteed.

). . . . . . . . . . . .0°C to +70°C

A

). . . . . . . . . .–40°C to +85°C

A

). . . . . . . . .–55°C to +125°C

A

Am28F256 21

MAXIMUM OVERSHOO T
Maximum Negative Input Overshoot

+0.8 V
–0.5 V

–2.0 V

Maximum Positive Input Overshoot

VCC + 2.0 V

V

+ 0.5 V

CC

2.0 V

20 ns

20 ns

20 ns

20 ns 20 ns

20 ns

11560F-10

Maximum VPP Overshoot

13.5 V

V

+ 0.5 V

CC

14.0 V

20 ns

11560F-11

20 ns

20 ns

11560F-12

22 Am28F256

DC CHARACTERISTICS over operating range unless otherwise specified
TTL/NMOS Compatible

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

I

I

CCS

I

CC1

I

CC2

I

CC3

I

PPS

I

PP1

I

PP2

I

PP3

V

V

V

V

V

V

V

I

LI

LO

IL

IH

OL

OH1

ID

I

ID

PPL

PPH

Input Leakage Current V
Output Leakage Current VCC = VCC Max, V

CC

= V

CC

Max, VIN = V

OUT

= VCC or V

VCC Standby Current VCC = VCC Max, CE # = V

VCC Active Read Current

VCC Programming Current

VCC Erase Current

V

Standby Current V

PP

V

Read Current

PP

V

Programming Current

PP

V

Erase Current

PP

V

CC = VCC

I

OUT

CE#
Programming in Progress (Note 4)

CE#
Erasure in Progress (Note 4)

PP

V

PP

V

PP

V

PP

Programming in Progress (Note 4)
V

PP

Erasure in Progress (Note 4)

Max, CE # = V

= 0 mA, at 6 MHz

= VIL

= VIL

= V

PPL

= V

PPH

= V

PPL

= V

PPH

= V

PPH

CC

IH

IL,

or V

SS

OE# = V

SS

0.2 1.0 mA

IH

20 30 mA

20 30 mA

20 30 mA

70 200

10 30 mA

10 30 mA

±1.0 µA
±1.0 µA

±1.0 µA

µA

±1.0

Input Low Voltage –0.5 0.8 V
Input High Voltage 2.0 VCC + 0.5 V
Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V
Output High Voltage IOH = –2.5 mA, VCC = VCC Min 2.4 V
A9 Auto Select Voltage A9 = V

ID

11.5 13.0 V
A9 Auto Select Current A9 = VID Max, VCC = VCC Max 5 50 µA
V

during Re ad-Onl y

PP

Operations
V

during Read/Write

PP

Operations

Note: Erase/Program are inhibited
when V

PP

= V

PPL

0.0 VCC +2.0 V

11.4 12.6 V

V

LKO

Low VCC Lock-out Voltage 3.2 3.7 V

Notes:

1. Caution: The Am28 F256 m ust not be remo v ed from (or inserted into) a sock et when V
the voltage difference between V

and VCC should not exceed 10.0 Volts. Also, the Am28F256 has a VPP rise time and fall

PP

time specification of 500 ns minimum.

is tested with OE# = VIH to simulate open outputs.

2. I

CC1

3. Maximum active power usage is the sum of I

and IPP..

CC

4. Not 100% tested.

Am28F256 23

or VPP is applied. If VCC ≤ 1.0 V o lt,

CC

DC CHARACTERISTICS
CMOS Compatible

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

I

I

CCS

I

CC1

I

CC2

I

CC3

I

PPS

I

PP1

I

PP2

I

PP3

V

V

V
V
V

V

V

V

I

LI

LO

IL

IH

OL

OH1

OH2

ID

I

ID

PPL

PPH

Input Leakage Current V

CC

= V

CC

Max, VIN = V

Output Leakage Current VCC = VCC Max, V

= VCC or V

OUT

CC

or V

SS

SS

±1.0 µA
±1.0 µA

VCC Standby Current VCC = VCC Max, CE # = VCC + 0.5 V 15 100 µA

V

Active Read Current

CC

VCC Programming Current

VCC Erase Current

V

Standby Current V

PP

V

Read Current V

PP

V

Programming Current

PP

V

Erase Current

PP

CC

I

OUT

CE# = V

Max, CE # = V

CC

= 0 mA, at 6 MHz

IL

Programming in Progress (Note 4)
CE# = V

IL

Erasure in Progress (Note 4)

= V

PP

PPL

= V

PP

PPH

V

= V

PPH

PP

Programming in Progress (Note 4)
V

= V

PPH

PP

Erasure in Progress (Note 4)

OE# = V

IL,

IH

20 30 mA

20 30 mA

20 30 mA

±1.0 µA

70 200 µA

10 30 mA

10 30 mA

V

= V

Input Low Voltage –0.5 0.8 V
Input High Voltage 0.7 V

CC

V

CC

+ 0.5 V

Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V

Output High Voltage

IOH = –2.5 mA, VCC = VCC Min 0.85 V
IOH = –100 µA, V

A9 Auto Select Voltage A9 = V

= VCC Min VCC –0.4

CC

ID

CC

11.5 13.0 V

V

A9 Auto Select Current A9 = VID Max, VCC = VCC Max 5 50 µA
V

during Read-Only

PPL

Operations
V

during Read/Write

PP

Operations

Note: Erase/Program are inhibited
when V

PP

= V

PPL

0.0 VCC + 2.0 V

11.4 12.6 V

V

LKO

Low VCC Lock-out Voltage 3.2 3 .7 V

Notes:

1. Caution: T he Am 28F 256 m us t not be remov ed from (or inserted into ) a s oc ket when V
the voltage difference between V

and VCC should not exceed 10. 0 volt s . Al so, the Am28F256 has a VPP rise time and fall

PP

time specification of 500 ns minimum.

is tested with OE# = VIH to simulate open outputs.

2. I

CC1

3. Maximum active power usage is the sum of I

and IPP.

CC

4. Not 100% tested.

24 Am28F256

CC

or V

is appli ed. If VCC ≤ 1.0 volt ,

PP

25

20

ICC Active

in mA

15

55°C
0°C

10

5

0

01 23456789101112

Frequency in MHz

25°C
70°C
125°C

11560F-13

Figure 5. Am28F256—Average ICC Active vs. Frequency

V

= 5.5 V, Addressing Pattern = Minmax

CC

Data Pattern = Checkerboard

TEST CONDITIONS

Device

Under

Test

C

L

Note: Diodes are IN3064 or equivalent

Figure 6. Test Setup

6.2 k

Table 6. Test Specifications

5.0 V

2.7 k

Ω

Ω

11560G-14

Test Condition -70 All others Unit

Output Load 1 TTL gate
Output Load Cap acitance, C

(including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels 0.0–3.0 0.45–2 .4 V
Input timing measurement

reference levels
Output timing measurement

reference levels

L

30 100 pF

10 ns

≤

1.5 0.8, 2.0 V

1.5 0.8, 2.0 V

Am28F256 25

SWITCHING TEST WAVEFORMS

s

2.4 V

0.45 V

2.0 V
Test Points

Input Output

2.0 V

0.8 V0.8 V

AC Testing (all speed opt ions e xcept -70): Inp uts are driven at

2.4 V f or a logic “ 1” a nd 0.45 V for a logic “0”. I nput pul s e rise

≤

and fall times are

10 ns.

3 V

1.5 V

0 V

Input Output

Test Poin ts

AC Testing for -70 devices: Inputs are driven at 3.0 V for a
logic “1” and 0 V for a l ogic “0”. I nput pulse rise and fall time
are ≤10 ns.

SWITCHING CHARACTERISTICS over operating range unless otherwise specified
AC Char acteristics—Read Only Operation

Parameter Symbols

t

AVAV

t

ELQV

t

AVQV

t

GLQV

t

ELQX

t

t

t

ACC

t

RC

CE

OE

t

LZ

Parameter Description

Read Cycle Time (Note 2) Min 70 90 120 150 200 ns
Chip Enable AccessTime Max 70 90 120 150 200 ns
Address Access Time Max 70 90 120 150 200 ns
Output Enable Access Time M ax 35 35 50 55 55 ns
Chip Enable to Output in Low Z

(Note 2)

Min00000ns

Am28F256 Speed Options

1.5 V

11560G-15

UnitJEDEC Standar d -70 -90 -120 -150 -200

t

EHQZ

t

GLQX

t

GHQZ

t

AXQX

t

WHGL

t

VCS

t

t

OLZ

t

t

OH

Chip Disable to Output in High Z

DF

(Note 1)
Output Enable to Output in Low Z

(Note 2)
Output Disable to Output in High Z

DF

(Note 2)
Output Hold from first of Address,

CE#, or OE# Change (Note 2)
Write Recovery Time befo r e Read Min 6 6 6 6 6 µs
VCC Setup Time to Valid Read

(Note 2)

Notes:

1. Guaranteed by design not tested.

2. Not 100% tested.

Max2020303535ns

Min00000ns

Max2020303535ns

Min00000ns

Min5050505050µs

26 Am28F256

AC Characteristics—Write/Erase/Program Operations

Parameter Symbols

t

AVAV

t

AVWL

t

WLAX

t

DVWH

t

WHDX

t

WHGL

t

GHWL

t

ELWL

t

WHEH

t

WLWH

t

WHWL

t

WHWH1

t

WHWH2

t

WC

t
t
t

t

DH

t

WR

t
t

CH

t

WP

t

WPH

AS

AH

DS

CS

Am28F256 Speed Options

Parameter Description

UnitJEDEC Standard -70 -90 -120 -150 -200

Write Cycle Time (Note 4) Min 70 90 120 150 200 ns
Address Set-up Time Min 0 0 0 0 0 ns
Address Hold Time Min4545506075ns
Data Setup Time Min 45 45 50 50 50 ns
Data Hold Time M in 10 10 10 10 10 ns
Write Recovery Time

before Read
Read Recovery Time

before Write

Min66666µs

Min00000µs

Chip Enable Set-up Time M in 0 0 0 0 0 ns
Chip Enable Hold Time Min 0 0 0 0 0 ns
Write Pulse Width Min 45 45 50 60 60 ns
Wr ite Pulse

Width HIGH
Duration of Programming

Operation (Note 2)
Duration of

Erase Operation (Note 2)

Min2020202020ns

Min1010101010µs

Min 9.5 9.5 9.5 9.5 9.5 ms

t

VPEL

t

VCS

t

VPPR

t

VPPF

t

LKO

VPP Setup Time to
Chip Enable LOW (Note 4)

VCC Set-up Time to
Chip Enable LOW (Note 4)

VPP Rise Time

PPH

(Note 4)

90% V
VPP Fall Tim e

10% V
VCC < V

PPL

LKO

(Note 4)

to Reset (Note 4)

Min 100 100 100 100 100 ns

Min5050505050µs

Min 500 500 500 500 500 ns

Min 500 500 500 500 500 ns

Min 100 100 100 100 100 ns

Notes:

1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC
Characteristics for Read Only operations.

2. Maximum pulse widths not required because the on-chip program/erase stop timer will terminate the pulse widths internally
on the device.

3. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems wher e Chip-Ena bl e defines t he Write Pul se Wid th (withi n a longer W rite-Enab le t iming w av ef orm) all setup , hol d and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.

4. Not 100% tested.

Am28F256 27

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

SWITCHING WAVEFORMS

Power-up, Standby

Device and

Address Select ion

Outputs

Enabled

Steady

Changing from H to L

Changing from L to H

Data

V alid

Standby, Power-Down

Addresses

CE# (E#)

OE# (G#)

WE# (W#)

Data (DQ)

5.0 V
V

CC

0 V

t

VCS

Addresses Stable

t

(tRC)

AVAV

t

EHQZ

)

(t

DF

t

WHGL

t

(tOE)

GLQV

t

(tCE)

ELQV

t

(t

GLQX

OLZ

t

(tLZ)

t

AVQV

ELQX

(t

)

ACC

High Z High Z

t

AXQX (tOH

)

Output Valid

t

GHQZ

(t

)

DF

)

11560G-16

Figure 7. AC Waveforms for Read Operations

28 Am28F256

SWITCHING WAVEFORMS

Addresses

CE# (E#)

OE# (G#)

WE# (W#)

Data (DQ)

5.0 V
V

CC

0 V

V

PPH

V

PP

V

PPL

Pow er-up,

Standby

t

ELWL (tCS

t

WLWH (tWP

HIGH Z

Setup Eras e

Comman d

t

AVAV (tWC

)

)

t

DVWH (tDS

)

t

VCS

)

t

GHWL (tOES

DAT A IN

= 20h

t

VPEL

Erase

Comman d

t

WHEH (tCH

)

t

WHWL (tWPH

t

WHDX (tDH

t

AVWL (tAS

)

)

DATA IN

= 20h

Erasure

)

)

Erase-Verify

Command

t

WHWH2

t

WLAX (tAH

DAT A IN =

A0h

t

ELQX (tLZ

t

ELQV

t

WHGL

t

t

GLQV (tOE

)

(tCE)

Erase

Verification

t

AVAV (tRC

)

t

EHQZ (tDF

GHQZ (tDF

)

t

AXQX (tOH

Standby,

Power-down

)

)

)

t

)

VALID

DAT A

OUT

GLQX (tOLZ

)

Figure 8. AC Waveforms for Erase Operations

11560F-17

Am28F256 29

SWITCHING WAVEFORMS

Power-up,

Standby

Addresses

CE# (E#)

Setup Program

Command

t

AVAV (tWC

t

AVWL (tAS

)

)

Program

Command

Latch Address

and Data

Programming

t

WLAX (tAH

)

Verify

Command

Programming

Verification

t

AVAV (tRC

)

Standby,

Power-down

OE# (G#)

WE# (W#)

Data (DQ)

5.0 V
V

CC

0 V

V

PPH

V

PP

V

PPL

t

ELWL (tCS

t

WLWH (tWP

HIGH Z

)

)

t

DVWH (tDS

)

t

VCS

t

t

GHWL (tOES

DATA IN

= 40h

VPEL

t

WHEH (tCH

t

WHWL (tWPH

)

)

)

t

WHDX (tDH

DATA IN

t

WHWH1

t

WHGL

t

GLQV (tOE

t

GHQZ (tDF

)

DATA IN

= C0h

t

t

ELQV

ELQX (tLZ

(tCE)

)

Figure 9. AC Waveforms for Programming Operations

t

GHQZ (tDF

)

t

AXQX (tOH

)

)

)

t

GLQX (tOLZ

VALID

DAT A

OUT

)

11560F-18

30 Am28F256

ERASE AND PROGRAMMING PERFORMANCE

Limits

Typ

Parameter

Chip Erase Time 1 10 sec Excludes 00h programming prior to erasure
Chip Programming Time 0.5 3 sec Excludes system-level overhead
Write/Erase Cycles 10,000 Cycles

(Note 1)

Max

(Note 2) Unit

CommentsMin

Notes:

°

C, 12 V VPP.

1. 25

2. Maximum time specified is lower than worst case. Worst case is derived from the Flasherase/Flashrite pulse count
(Flashera se = 1000 max and Flashrite = 25 max). Typical worst case for progra m and erase is signific antly less than the actua l
device limit.

LATCHUP CHARACTERISTICS

Min Max

Input Voltage with respect to V
Input Voltage with respect to V
Current –100 mA +100 mA
Includes all pins except V

on all pins except I/O pins (Including A9 and VPP) –1.0 V 13.5 V

SS

on all pins I/O pins –1.0 V VCC + 1.0 V

SS

. Test conditions: VCC = 5.0 V, one pin at a time.

CC

PIN CAPACITANCE

Parameter

Symbol Parameter Description Test Conditions Typ Max Unit

C

IN

C

OUT

C

IN2

Note: Sampled, not 100% tested. Test conditions T

Input Capacitanc e VIN = 0 8 10 pF
Out put Ca pacitance V
VPP Input Capacitance VPP = 0 8 12 pF

= 25°C, f = 1.0 MHz.

A

= 0 8 1 2 pF

OUT

DATA RETENTION

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C10Years
125°C20Years

Am28F256 31

PHYSICAL DIMENSIONS
PD032—32-Pin Plastic DIP (measured in inches)

1.640

1.670

.120
.160

32

.140
.225

Pin 1 I.D.

.045
.065

.005 MIN

.090
.110

.016
.022

17

.530
.580

16

0°

10°

SEATING PLANE

.015
.060

PL032—32-Pin Plastic Leaded Chip Carrier (measured in inches)

.485
.495

.009
.015

.125
.140

.080
.095

SEATING

PLANE

.013
.021

.050 REF.

SIDE VIEW

.585
.595

.447
.453

Pin 1 I.D.

.547
.553

.026
.032

TOP VIEW

.600
.625

.009
.015

.630
.700

16-038-S_AG
PD 032
EC75
5-28-97 lv

.042
.056

.400

REF.

.490
.530

16-038FPO-5
PL 032
DA79
6-28-94 ae

32 Am28F256

PHYSICAL DIMENSIONS

B

TS032—32-Pin Standard Thin Small Outline Package (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

7.90

8.10

0.50

1.20

MAX

18.30

18.50

19.80

20.20

0.05

0.15

0.08

0.20

0.10

0°
5°

0.50

0.70

0.21

16-038-TSOP-2
TS 032
DA95
3-25-97 lv

Am28F256 33

PHYSICAL DIMENSIONS
TSR032—32-Pin Reversed Thin Small Outline Package (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

7.90

8.10

0.50 BSC

1.20

MAX

18.30

18.50

19.80

20.20

0.05

0.15

0.08

0.20

0.10

0°
5°

0.50

0.70

0.21

16-038-TSOP-2
TSR032
DA95
3-25-97 lv

34 Am28F256

DATA SHEET REVISION SUMMARY FOR AM28F256

Revision G

Deleted -75, -95, and -250 speed options. Matched for­matting to other current data sheets.

Revision G+1

Figure 3, Flashrite Programming Algorithm:

of arrow originating from Increment Address box so
that it points to the PLSCNT = 0 bo x, not the Write Pro­gram Ver ify Command box. This is a correction to the
diagram on page 6-189 of the 1998 Flash Memor y
Data Book.

Moved end

Revision G+2

Programming In A PROM Programmer:

Deleted the para graph “(Refer to the AUTO SELECT
paragraph in the ERASE, PROGRAM, and READ
MODE section for programming the Flash memory de­vice in-system).”

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am28F256 35