AMD Advanced Micro Devices AM28F256-90JEB, AM28F256-90JE, AM28F256-90JCB, AM28F256-90JC, AM28F256-90FIB Datasheet

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FINAL

Am28F256

256 Kilobit (32 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory

DISTINCTIVE CHARACTERISTICS

High performance

■

— 70 ns maximum access time

CMOS Low power consumption

■

— 30 mA maximum active current — 100 µA maximum standby current — No data retention power consumption

Compatible with JEDEC-standard byte-wide

■

32-Pin EPROM pinouts

— 32-pin PDIP — 32-pin PLCC — 32-pin TSOP

10,000 write/erase cycles minimum

■

Write and erase voltage 12.0 V ±5%

■

Latch-up protected to 100 mA from –1 V to V

Flasherase

+1 V

Electrical Bulk Chip-Erase

— One second typical chip-erase

Flashrite Programming

— 10 µs typical byte-program — 0.5 second typical chip program

Command register architecture for microprocessor/microcontroller compatible write interface

On-chip address and data latches Advanced CMOS flash memory technology

— Low cost single transistor memory cell

Automatic write/erase pulse stop timer

GENERAL DESCRIPTION

The Am28F256 is a 256 K Flash memory organized as 32 Kbytes of 8 bits each. AMD’s Flash memories offer the most cost-effective and reliable read/write nonvolatile random access memory. T he Am28F256 is packaged in 32- pin PDIP, PLCC, and TSOP versions. It is designed to be repr ogram med and erased in- system or in standard EPROM programmers. The Am28F256 is erased when shipped from the factory.

The standard Am28F256 offers acc ess times as f ast as 70 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention ,

the Am28F256 has separate chip enable (CE output enable (OE

) controls.

AMD’s Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The Am28F256 uses a comman d register to manage t his functiona lity, wh ile maintaini ng a standard J EDEC Flash Standard 32-pin pinout. The comma nd register allows for 100% TTL level control inputs and f ixed power supply levels during erase and programming.

AMD’s Flash technology reliably sto res memory contents even after 10,000 erase and program cycles.

) and

The AMD cell is de signed to optimize t he erase an d programming m echanisms. In a ddition, th e combination of advanc ed tunnel oxide processin g and low internal electric fields for erase and programming operations produces r eliable cycling. The Am28 F256 uses a 12.0 V±5% V the Flasherase

and Flashrite algorithms.

high voltage input to pe rform

The highest degree of latch-up protection is achieved with AMD’s proprietary non-epi process. Latch-up protection is provided for stresses up to 100 milliamps on address and data pins from –1 V to V

+1 V.

The Am28F256 is by te programmable using 10 µs programming pulses in accordance with AMD’s Flashrite programming algorithm. The typical room temperature programming time of the Am28F256 is a half a second. The entire chip is bulk erased using 10 ms erase pulses accordi ng to AMD’s Fla sheras e alrogithm. Typical erasure at room temperature is accomplished in less than one second. The windowed package and the 15-20 minute s required for EPROM erasure using ultra-violet light are eliminated.

Publicatio n# Issue Date:

Rev: GAmendm ent/

11560

January 1998

Commands are written to the command register using standard microprocessor write timings. Register contents se rve as inp uts to an internal state-machi ne which controls the erase and programming circ uitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. For system design simplification, the

Am28F256 is designed to support either WE

or CE

controlled writes. Dur ing a system write cycle, ad-

dresses are latched on the falling edge of WE

or CE

whiche v er o ccur s las t. Data is latc hed on the rising edge

or CE# whichev er occurs first . To simplify the fo l-

of WE

BLOCK DIAGRAM

Erase

Voltage

Switch

lowi ng discu ssion, the WE

pin is used as the write cycle

control pin throughout the rest of this text. All setup and

hold times are with respect to the WE

signal.

AMD’s Flash technology combines years of EPROM and EEPROM ex perience to produce the highest le vels of quality, reliability, and cost effectiveness. The Am28F2 56 electri cally eras es all bits simultane ously

using Fowler-N ordheim tunneling. The bytes are programmed one byte at a time using the EP ROM

programming mechanism of hot electron injection.

DQ0–DQ7

Input/Output

Buffers

To Array

Address

Latch

Chip Enable

Output Enable

Logic

Y-Decoder

X-Decoder

Data

Latch

Y-Gating

262,144

Bit

Cell Matrix

11560F-1

WE#

CE#

OE#

Low V

Detector

A0–A14

State

Control

Command

Program

Voltage

Switch

Program/Erase

Pulse Timer

PRODUCT SELECTOR GUIDE

Family Part Number Speed Options (V Max Access Time (ns) 70 90 120 150 200 CE# (E#) Access (ns) 70 90 120 150 200 OE# (G#) Access (ns) 35 35 50 55 55

= 5.0 V ± 10%)

-70 -90 -120 -150 -200

Am28F256

2 Am28F256

CONNECTION DIAGRAMS

NC NC

A12

A7 A6

A5 A4

A3 A2

A0 DQ0 DQ1

DQ2

1 2 3

4 5

6 7

8 9

10 11

12 13

14 15 16

PDIP

32 31 30 29 28

27 26

25 24 23 22 21

20 19

18 17

WE# (W#) NC A14

A13 A8 A9 A11 OE# (G#) A10

CE# (E#)

DQ7 DQ6

DQ5 DQ4

DQ3

11560F-2

A7 A6 A5

A4 A3 A2 A1 A0

DQ0

5 6

8 9 10

11 12 13

A12

DQ1

PLCC

DQ2

DQ3

VCCWE# (W#)

31 30

19 2016

DQ5

DQ4

29 28 27

26 25 24 23 22 21

DQ6

A14 A13

A9 A11 OE# (G#)

A10 CE# (E#) DQ7

11560F-3

Note: Pin 1 is marked for orientation.

Am28F256 3

CONNECTION DIAGRAMS (continued)

A11

A8 A13 A14

WE#

NC NC

A12

OE#

A10

CE#

D7 D6 D5 D4 D3

D2 D1 D0 A0 A1 A2 A3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

32-Pin TSOP—Sta ndard Pinout

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

OE# A10 CE# D7 D6 D5 D4 D3 V

D2 D1 D0 A0 A1 A2 A3

A11 A9 A8 A13 A14 NC WE# V

NC NC A12 A7 A6 A5 A4

LOGIC SYMBOL

32-Pin TSOP—Reverse Pinout

A0–A14

DQ0

–DQ7

CE# (E#) OE# (G#)

WE# (W#)

11560F-5

11560G-4

4 Am28F256

ORDERING INFORMATION Standard Products

AMD standard products are avai lable in sev eral pac kages and opera ting ranges . The order number (V alid Combinat ion) is formed by a combination of:

AM28F256 -70 J C

DEVICE NUMBER/DESCRIPTION

Am28F256 256 Kilobit (32 K x 8-Bit) CMOS Flash Memory

OPTIONAL PROCESSING

Blank = Standard Processing B=Burn-In

Contact an AMD representative for more information.

TEMP ERATURE RANGE

C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C)

PACKA GE TYPE

P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

AM28F256-70 AM28F256-90 AM28F256-120 AM28F256-150 AM28F256-200

Valid Combinations

PC, PI, PE,

JC, JI, JE,

EC, EI, EE,

FC, FI, FE

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Am28F256 5

PIN DESCRIPTION A0–A14

ddress Inputs for memory locations. Internal latches

hold addresses during write cycles.

CE# (E#)

Chip Enable activ e low i nput activates the chip’ s control logic and input buffers. Chip Enable high will deselect the device and operates the chip in stand-by mode.

DQ0–DQ7

Data Inputs during memory write cycles. Internal latches hold data during write cycles. Data Outputs during memory read cycles.

No Connect-correspond ing pin is not connecte d internally to the die.

Output Enable active lo w input gates the outputs of the device through the data buffers during memory read cy cles. O utput E nable i s high duri ng com mand sequencing and program/erase operations.

)

Po wer supply f or de vice operation. (5.0 V ± 5% or 10%)

Program voltage input. VPP must be at high voltage in order to write to the command register. The command register co ntrols all fun ctions requ ired to alter the memor y array contents. Memor y cont ents canno t be

≤ V

altered when V

Ground

+2 V.

WE# (W#)

Write Enable active l ow input controls the write function of the command register to the memory array. The target address is latched on the falling edge of the Write Enable pulse and the appropriate data is latched on the rising edge of the pulse. Write Enable high inhibits writing to the device.

6 Am28F256

BASIC PRINCIPLES

The device use s 100% TTL-l evel control inputs to manage the command register. Erase and reprogramming operations use a fixed 12.0 V ± 5% high voltage input.

Read Only Memory

Without high VPP voltage, the device functions as a read only memor y and operate s like a stand ard EPROM. The control inputs still manage traditional read, standby, output disable, and Auto select modes.

Command Register

The command register is enabled only when high voltage is applied to the V gramming operat ions are only acce ssed via the register. In addition, two-cycle commands are required for erase and reprogramming operations. The traditional read, standby, output disable, and Auto select modes are available via the register.

The device’s command register is writ ten using standard microp rocessor w rite timin gs. The re gister controls an internal state machine that manages all device operations. For syst em desig n simplificat ion, the de vice is designed to support either WE# or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the rising edge of WE# or CE# whichever occur first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal.

pin. The erase and repro-

Overview of Er as e/Progr am Ope ra ti on s

Flasherase™ Sequence

A multiple step command seq uence is require d to erase the Flash device (a two-cyc le Erase command and repeated one cycle verify commands).

Note: The Flash memory array must be completely programmed to 0’s prior to erasure. Refer to the Flashrite™ Programming Algorithm.

1. Erase Setup: Write the Setup Erase command to the command register.

2. Erase: Write the Erase command (same as Setup Erase comman d) to t he comman d register again. The second command initiates the er ase operation. The system software routine s must now time-ou t the erase pulse wid th (10 ms) prior t o issuing the Erase-verify command. An integrated stop timer prevents any possibility of overerasure.

3. Erase-Verify: Wr ite the Erase-verify command to the command register. This command terminates the erase ope ration. After the erase op eration, each byte of the array must be verified. Address in-

formation must be supplied with the Erase-verify command. This command verifies the mar gin and outputs the addressed byte in order to compare the array data with FFh data (Byte erased). After successful data verification the Erase-verify command is written again with new address information. Each byte of t he a rray is sequentially verified in this manner.

If data of the addressed location is not verified, the Erase sequence is repeated until the entire array is successfully verified or the sequence is repeated 1000 times.

Flashrite

A three step command sequence (a two- cycle Progr am command and one cycle Verify command) is required to program a byte of the Flash arra y. Refer to the Flashrite

1. Program Setup: Write the Setup Program com-

2. Program: Write the Program command to the com-

3. Program-Verify: Write the Program-verify com-

If data is not verified successfully, the Program sequence is repeat ed until a success ful comp arison is verified or the sequence is repeated 25 times.

Programming Sequence

Algorithm.

mand to the command register.

mand register with the appropriate Address and Data. The system software routines m ust no w timeout the program pulse width (10 µs) prior to issuing the Progr am-verify co mmand. An in tegrated sto p timer prevents any possibility of overprogramming.

mand to the command register. This command terminates the programming operation. In addition, this command verifies the margin and ou tputs the byte just progr ammed in or der to compare the arr a y data with the original data programmed. After successful data verification, the programming sequence is initiated again f or the ne xt b yte address to be programmed.

Data Protection

The device is designed to off er protection against accidental erasure or programming caused by spurious system lev el signals that ma y exist during power transitions. The de vic e power s up i n its read only s tate. A lso, with its co ntrol reg ister ar chitectu re, alteration of the memory contents only occurs after successful completion of specific command sequences.

The device also incorporates several features to prevent inadv ertent write cycles resulting fromV up and power-down transitions or system noise.

power-

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up and power-down, the device locks out write cycles for

Am28F256 7

VCC < V voltages). When V

(see DC C haracteristics section for

LKO

< V

, the command register is

LKO

disabled, al l internal pro gram/erase circuits are disabled, and the device resets to the read mode. The device ignores all writes until V

> V

. The user

LKO

must ensure that the control pins are in the correct logic state when V

> V

to prev ent uni nitentional writes.

LKO

Write Pulse “Glitch” Protection

Noise pulses of less than 10 ns (typical) on OE#, CE# or WE# will not initiate a write cycle.

FUNCTIONAL DESCRIPTION Description Of User Modes

Table 1. Am28F256 Device Bus Operations (Notes 7 and 8)

Logical Inhibit

Writing i s inhibi ted by holding any one of OE# = VIL, CE#

or WE# = VIH. To initiate a write cycle CE# and

= V

WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE# = CE# = VIL and OE# = V edge of WE # . The in te rn al st at e ma chine is a ut oma tically reset to the read mode on power-up.

will not accept commands on the rising

Read-Only

Read/Write

Operation

(E#)

Read V Standby V Output Disable V Auto-select Manufacturer

Code (Note 2) Auto-select Device

Code (Note 2) Read V

Standby (Note 5) V Output Disable V Write V

OE (G#)

XXV

WE (W#)

(Note 1) A0 A9 I/O

PPL

PPH

A0 A9 D

XXHIGH Z XXHIGH Z

(Note 3)

A0 A9

XXHIGH Z XXHIGH Z

A0 A9

Legend:

X = Don’t care, where Don’t Care is either V

of V

. 0 V < An < VCC + 2 V, (normal TTL or CMOS input levels, where n = 0 or 9).

PPH

or VIH levels. V

= VPP < VCC + 2 V. See DC Characteristics for voltage levels

PPL

Notes:

1. V

may be grounded, connected with a resi stor to ground, or < VCC + 2.0 V. V

PPL

the device. Refer to the DC characteristics. When V

= V

, memory contents can be read but not written or erased.

PPL

is the programming v oltage specified f or

PPH

2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2.

3. 11.5 < V

4. Read operation with V

5. With V

6. Refer to Table 3 for vali d D

7. All inputs are Don’t Care unless otherwise stated, where Don’t Care is either V addresses except A

8. If V

< 13.0 V. Minimum VID rise time and fall time (between 0 and VID voltages) is 500 ns.

= V

at high voltage, the standby current is ICC + IPP (standby).

≤

1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the Am 28F256 has a VPP

and A0 must be held at VIL.

may access array data or the Auto select codes.

PPH

during a write operation.

or VIH levels. In the Auto select mode all

rise time and fall time specification of 500 ns minimum.

OUT

CODE

(01h)

CODE

(A1h) D

OUT

(Note 4)

(Note 6)

8 Am28F256

READ ONLY MODE

When VPP is less than V is inactive. The device can either read array or autoselect data, or be standby mode.

+ 2 V, the command regist er

Read

The devic e functi ons as a read only memory when V < V

+ 2 V. The device has two control functions. Both

must be satisfied in order to output data. CE# controls power to the device. This pin should be used for specific device selection. OE# controls the device outputs and should be used to gate data to the output pins if a device is selected.

Address acce ss time t

is equal to the de lay from

ACC

stable addresses to valid output data. The chip enable access time t

is the delay from stable addresses and

stable CE# to valid data at the output pins. The output enable access time is the del a y from the falling edge of OE# to valid data at the output pins (assuming the addresses have been stable at least t

ACC–tOE

Standby Mode

The device has two standby mo des. The CMOS standby mode (CE # inp ut held a t V sumes less than 100 µA of current. TTL standby mode (CE# is held at V

) reduces the current requirements

to less than 1mA. When in the sta ndby mode the outputs are in a high impedance state, independent of the OE# input.

If the d evice is de select ed dur ing er asure, pr ogramming, or program/erase verification, the device will draw active current until the operation is terminated.

0.5 V), con-

Output Disable

Output from th e device is disabled when OE# is at a logic high level. When disa bled, output pins are in a high impedance state.

Auto Select

Flash memories can be programmed in-system or in a standard PROM programmer. The device may be soldered to the circuit board upon recei pt of shipment and programmed in-system. Alternatively, the device may initially be programmed in a PROM programmer prior to soldering the device to the board.

The Auto select mode allows the reading out of a binary code from the device that will identify its manufacturer and type. This mode is intended for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. Th is mode is functional over the entire temperature range of the device.

Programming In A PROM Programmer

To activate this mode, the programming equipment must force V identifier bytes may then be sequenced from the de vice outputs by toggling addr ess A address lin es must be held at V less than or equal to V select mode. Byte 0 (A0 = V turer code and byte 1 (A0 = V code. For the de vi ce these tw o by tes are giv en in Table 2 below. All identifiers for manufacturer and device codes will exhibit odd parit y with the MSB (D Q7) defined as the parity bit.

(11.5 V to 13.0 V) on address A9. Two

from VIL to VIH. All other

, and VPP must be

+ 2.0 V while using this Auto

) represents the manuf ac-

) the device identifier

Ta ble 2. Am28F256 Auto Select Code

Type A0

Manufactur er Code V Device Code V

Am28F256 9

Code (HEX)

01 A1

ERASE, PROGRAM, AND READ MODE

When VPP is equal to 12.0 V ± 5%, the command register is active. All functions are available. That is, the device can program, erase, rea d array or a utoselec t data, or be standby mode.

Write Operations

High voltage must be applied to the VPP pin in order to activate the command register. Data written to the register serves as input to the internal state machine. The output of the state machine determines the operational function of the device.

Refer to AC Write Character istics and the Erase/Programming Waveforms for specific timing parameters.

Command Definitions

The contents of th e command register default to 00 h (Read Mode) in the absence of high voltage applied to the V ory. High voltage on the V register . D e vic e operations are selected by writing specific data codes into the command register. Table 3 defines these register commands.

pin. The device operates as a read only mem-

pin enables the command

The co mma nd r eg is ter does not occupy an addressable memory location. The register is a latch that stores the comman d, al on g wi th th e addr e ss and da ta in form at io n needed to execute the command. The register is written by bringing WE# and CE# to V

, while OE# is at VIH.

Addres ses ar e latc hed on th e fa lli ng edge of WE#, while data is latch ed on the ri sing edge of the WE# pulse. Standard microprocessor write timings are used.

The device requires the OE# pin to be V

for write op-

erations. This condition eliminates the possibility for bus contentio n during programmi ng operations. I n order to write, OE# must be V must be V

. If any pin is not in the correct state a write

, and CE# and WE#

command will not be executed.

Read Command

Memory contents can be accessed via the read command when V 00h into the command register . Standard micr oprocessor read cycles access data from the memory. The device will remain in th e read mode until t he command register contents are altered.

The command register defaults to 00h (read mode) upon V

fault helps ensure that inadvertent alteration of the memory contents does not occur during the V transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.

is high. To read from the device, write

power-up . The 00h (Read Mode) register de-

Ta ble 3. Am28F256 Command Definitions

First Bus Cycle Second Bus Cycle

Operation

Command (Note 4)

Read Memory Write X 00h/FFh Read RA RD Read Auto select Write X 80h or 90h Read 00h/01h 01h/A1h Erase Set-up/Erase Write Write X 20h Write X 20h

(Note 1)

Address

(Note 2)

Data

(Note 3)

Operation

(Note 1)

Address

(Note 2)

Data

(Note 3)

power

Erase-Verify Write EA A0h Read X EVD Program Setup/Program Write X 40h Write PA PD Program-Verify Write X C0h Read X PVD Reset Write X FFh Write X FFh

Notes:

1. Bus operations are defined in Table 1.

2. RA = Address of the memory location to be read. EA = Address of the memory location to be read during erase-verify. PA = Address of the memory location to be programmed. X = Don ’t care. Addresses are latched on the falling edge of the WE# pulse.

3. RD = Data read from location RA during read operation. EVD = Data read from location EA during erase-verify. PD = Data to be programmed at location PA. Data latched on the rising edge of WE#. PVD = Data read from location PA during program-verify. PA is latched on the Program command.

4. Refer to the appropriate section for algorithms and timing diagrams.

10 Am28F256

FLASHERASE ERASE SEQUENCE Erase Setup

Erase Setup is the first of a two-cycle erase command. It is a command-only operation that stages the device for bulk chip erase. The array contents are not altered with this command. 20h is written to the command register in order to perform the Erase Setup operation.

Erase

The second two-cycle erase command initiates the bulk erase operation. You must write the Erase command (20h) again to the register. The erase operation begins with the rising edge of the WE# pulse. The erase operation must be termina ted by writing a new command (Erase-verify) to the register.

This two step sequence of the Setup and Erase commands helps to ensure that memory contents are not accidentally erased. Also, chip erasure can only occur when high vol tage is applied to the V trol pins are in their proper state . In absence of this high voltage, memory contents cannot be altered. Refer to AC Erase Characteristics and Waveforms for specific timing parameters.

pin and all con-

Note: The Flash memory device must be fully programmed to 00h data prior to erasure. This equalizes the charge on all memory cells ensuring reliable erasure.

Erase-Verify Command

The erase operation erases all bytes of the array in parallel. After the erase operation, all bytes must be sequentially verified. The E rase- verify operation is initi -

ated by writing A0h to the register . The byte address to be verified mus t be supp lied with t he comman d. Addresses are latched on the falling edge of the WE# pulse or CE# pulse, whichever occurs later. The rising edge of the WE# pulse terminates the erase operation.

Margin Verify

During the Erase-verify operation, the device applies an internally generated margin voltage to the addressed byte. Reading FFh from the addressed byte indicates that all bits in the byte are properly erased.

Verify Next Address

You must write the Erase-verify command with the appropriate address to the register prior to verification of each address. Each new address is latched on the falling edge of WE# or CE# pulse, whichev er occurs later. The process continues for each byte in the memory array until a byte does n ot retur n FFh dat a or all the bytes in the array are accessed and verified.

If an address is not verified to FFh data, the entire chip is erased again (refer to Erase Setup/Erase). Erase verification then resumes at the address that failed to verify. Erase is complet e when all bytes in the array have been verified. The device is now ready to be programmed. At this point, the v erific ation operation is terminated by writing a valid command (e.g. Program Setup) to the command register. Figure 1 and Table 4, the Flasherase commands and bus operations are com bined to perform electrical erasure . Refer to AC Er ase Char acteristics and Waveforms for specific timing parameters.

electrical erase algorithm, illustr ate how

Am28F256 11

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