Datasheet AM28F020-90EI, AM28F020-90EEB, AM28F020-90EE, AM28F020-90ECB, AM28F020-70PIB Datasheet (AMD Advanced Micro Devices)

FINAL

Am28F020

2 Megabit (256 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory

DISTINCTIVE CHARACTERISTICS

■

High performance

— Access times as fast as 70 ns

■

CMOS low power consumption

— 30 mA max imum active current
— 100 µA maximum standby current
— No data retention power consumption

■

Compatible with JEDEC-standard byte-wide
32-pin EPROM pinouts

— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP

■

10,000 write/erase cycles minimum

■

Write and erase voltage 12.0 V ±5%

■

■

■

■

■

■

■

Latch-up protected to 100 mA from
–1 V to V

Flasherase Electrical Bulk Chip Erase

— One second typical chi p eras e time

Flashrite Programming

— 10 µs typical byte program time
— 4 s typical chip program time

Command regist er architecture for
microprocessor/microcontroller compatible
write interface

On-chi p add r es s and dat a latches
Advanced CMOS flash memory technology

— Low cost single transistor memory cell

Aut o matic write/eras e pulse sto p timer

CC

+1 V

GENERAL DESCRIPTION

The Am28F020 is a 2 Meg abit Flash memory orga­nize d as 25 6 Kb y tes of 8 bit s ea ch. AM D’s Flash mem­ories offer the most cost-effective and reliable read/
write non-volat ile random access memory. The
Am28F0 20 is packaged in 32-pin PDI P, PLCC, and
TSOP v ers ions . It i s des ign ed to be repr ogr amme d and
erased in-system or in standard EPROM programmers.
The Am28F020 is erased when shipped from
the factory.

The stan da rd Am28 F0 20 of f e rs acc es s ti m es of as f as t
as 70 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus conten­tion, the device has separate chip enable (CE#) and
output enable (OE#) controls.

AMD’s Flash memories augment EPROM funct ionality
with i n-circuit elec trical e rasure and programming. The
Am28F020 uses a command register to manage this
functiona lity, whil e maintai ning a JEDE C-stan dard 32­pin pinout. The command register allows for 100% TTL
level control inputs and fixed power supply lev els during
erase and programming, while maintaining maximum
EPROM compatibility.

AMD’s Flash technology reliably stores memory con­tents even after 10,000 erase and program cycles. The
AMD cell is designed to optimize the erase and pro-

gra mmin g m ec han i sms . I n ad di t io n, th e c o mbin a tio n of
advanced t unnel oxide pr ocessi ng and low in ternal
electric fields for erase and programming operations
produces reliable cycling. The Am28F 020 uses a

12.0±5% VPP supp ly in put to perfor m the Flash erase
and Flashrite functi on s.

The highest degree of latch-up protection is achieved
with AMD’s prop r ietary non -e pi pr oc e ss. Lat ch- up pro ­tection is provided for stresses up to 100 mA on
address and data pins from –1 V to VCC +1 V.

The Am28F020 is byte programmable using 10 µs
programming pulses in accordance with AMD’s
Flashrite programming algorithm. The typical room
temperature programm ing time of the Am28 F020 is
four seconds. The entire chip is bulk erased using 10
ms erase pulses according to AMD’s Flasherase
algorithm. Typical erasure at room temperature is
accomplished in less than one second. The wi ndowed
package and the 15–20 minutes required for EPROM
erasure using ultraviolet light are eliminated.

Commands are wr itten to the command register using
standard microprocessor write timings. Register con­tents serve as input to an internal state-machine, which
controls the erase and programming circuitry. During
write cycles, the command register internally latches

Publication#
Issu e Date:

Rev: FAmendment/

14727

January 1998

+2

address es and data neede d for the program ming and
erase operations. For system design simplification, the
Am28F020 is designed to s uppor t either W E# or CE#
controlled writes. During a system write cycle,
addresses are latched on the falling edge of WE# or
CE#, whichever occurs last. Data is latched on the rising
edge of WE# or CE#, whichever occurs first. To simplify
discussion, the WE# pin is used as the write cycle

PRODUCT SELECTOR GUIDE

control pin throughout the rest of this data sheet. All
setup and hold times are with respect to the WE# signal.

AMD’s Flash technology combines years of EPROM
and EEPROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. Th e
Am28F020 electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are pro­grammed one byte at a time using the EPROM
programming mechanism of hot electron injection.

Family Part Number
Speed Options (VCC = 5.0 V ± 10%)

-70 -90 -120 -150 -200

Am28F020

Max Access Time (ns) 70 90 120 150 200

(E#) Access (ns) 70 90 120 150 200

CE

#

(G#) Access (ns) 35 35 50 55 55

OE

#

BLOCK DIAGRAM

DQ0–DQ7

V

CC

V

SS

V

PP

WE#

CE#
OE#

State

Control

Command

Register

Program

Voltage

Switch

Erase

Voltage

Switch

Input/Output

Buffers

To Array

Chip Enable

Output Enable

Logic

Program/Erase

Pulse Timer

Low VCC
Detector

A0–A17

2 Am28F020

Address Latch

Y-Decoder

X-Decoder

Data Latch

Y-Gating

2,097,152

Bit

Cell Matrix

14727F-1

CONNECTION DIAGRAMS

PDIP

V

PP

A16

A15
A12

A7
A6
A5
A4
A3
A2

A1

A0
DQ0
DQ1
DQ2

V

SS

1
2
3
4
5

6
7

8
9
10
11
12

13
14
15
16

32
31
30
29
28

27
26

25
24
23
22
21

20
19

18
17

CE

14727F-2

V

CC

WE# (W#)
A17
A14

A13
A8
A9
A11

(G#)

OE

#

A10

(E#)

#

DQ7
DQ6

DQ5
DQ4

DQ3

A7
A6
A5

A4
A3
A2
A1
A0

DQ0

5
6

7

8
9
10

11
12
13

14

A12

4

DQ1

15

A15

3

DQ2

PLCC

A16

2

17

SS

V

PP

V

VCCWE# (W#)

31 30

1

32

19 2016

18

DQ4

DQ3

DQ5

A17

29
28
27

26
25
24
23
22
21

DQ6

A14
A13

A8

A9
A11
OE# (G#)

A10
CE# (E#)
DQ7

14727F-3

Note: Pin 1 is marked for orientation.

Am28F020 3

CONNECTION DIAGRAMS (continued)

PP

1
2
3
4
5
6
7

#

8
9
10
11
12
13
14
15
16

32-P in TS OP—St an dard Pino u t

#

1
2

#

3
4
5
6
7
8
9
10
11
12
13
14
15
16

A11

A13

A14

A17

WE

V

V

A16

A15

A12

OE

A10

CE

V

A9
A8

CC

A7
A6
A5
A4

D7
D6
D5
D4
D3

SS

D2
D1
D0
A0
A1
A2
A3

TSOP

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

OE
A10
CE
D7
D6
D5
D4
D3
V

SS

D2
D1
D0
A0
A1
A2
A3

A11
A9
A8
A13
A14
A17
WE
V

CC

V

PP

A16
A15
A12
A7
A6
A5
A4

#
#

#

32-Pin TSOP—Reverse Pinout

LOGIC SYMBOL

18

A0–A17

DQ0–DQ7

CE

(E)

#

OE# (G#)
WE# (W#)

4 Am28F020

14727F-4

8

14727F-5

ORDERIN G IN FOR MATION
Standard Products

AMD standard pro ducts are avail able in several packages and operating rang es. The order ing number (Va lid Combinatio n) is
formed by a combination of the following:

AM28F020 -70 J C

DEVICE NUMBER/DESCRIPTION

Am28F020
2 Megabit (256 K x 8-Bit) CMOS Flash Memory

B

OPTIONAL PROCESSING

Blank = Standard Processing
B = Burn-In

Contact an AMD representative for more information.

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)

PACKAGE TYPE

P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

AM28F020-70
AM28F020-90
AM28F020-120
AM28F020-150
AM28F020-200

Valid Combinations

PC, PI, PE,

JC, JI, JE,

EC, EI, EE,

FC, FI, FE

Valid Combinations

Valid Combinations list configurations planned to be support­ed in volume for this device. Consult the local AMD sales of­fice to confirm availab ility of specific val id combination s and
to check on newly released combinations.

Am28F020 5

PIN DESCRIPTION
A0–A17

Address In puts for memor y lo cations. Inte rnal la tches
hold addresses during write cycles.

CE# (E#)

Chip Enable active low input activates the chip’s control
logic and input buffers. Chip Enable high will deselect
the device and operates the chip in stand-by mode.

DQ0–DQ7

Data Inputs during memory write cycles. Internal
latches hold data during write cycles. Data Outputs
during memory read cycles.

NC

No Connect-corresponding pin is not connected
internally to the die.

OE# (G#)

Output Enable active low input gates the outputs of the
device through the data buffers during memory read
cycles. Output Enable is high during com mand
sequencing and program/erase operations.

V

CC

Po w er supp ly for de vi ce oper at ion . (5.0 V ± 5% or 10%)

V

PP

Program voltage i nput. VPP must be at hi g h vol ta ge in
order to write to the command register. The command
register controls all functions required to alter the
memory array contents. Memor y contents cannot be
altered when VPP ≤ V

V

SS

Ground

CC

+2 V.

WE# (W#)

Write Enable active low input controls the write function
of the command register to the memory array. The
target address is latched on the falling edge of the
Write Enable pulse and the appropriate data is latched
on the rising edge of the pulse. Write Enable high
inhibits writing to the device.

6 Am28F020

BASIC PRINCIPLES

The device uses 100% TTL-level control inputs to
manage th e command register. Erase and rep ro­gramming opera tions use a fixed 12.0 V ± 5% high
voltage input.

Read Only Memory

Without high VPP voltage, the device functions as a
read only memory and operates like a standard
EPROM. Th e control inpu ts still ma nage traditi onal
read, standby, output disable, and Auto select modes.

Command Register

The command register is enabled only when high volt­age is applied to the VPP pin. The erase and repro­gramming operations are only accessed via the
register. In addition, two-cycle commands are required
for erase and reprogramming op erations. The tradi­tional read, standby, output disable, and Auto select
modes are available via the register.

The device’s com mand regi ster is wr itt en us ing stan­dard microprocessor write timings. The register con­trols an internal state machine that manages all device
operations. For system design simplification, the de­vice is designed to suppor t either WE# or CE# con­trolled writes. Durin g a system write cy cle, addresses
are latched on the falling edge of WE# or CE# which­ever occurs last. Data is latched on the rising edge of
WE# or CE# whichever occur first. To simplify the fol­lowing discussion, the WE# pin is used as the write
cycle control pin throughout the rest of this text. All
setup and hold times are with respect to the WE# sig­nal.

Overview of Erase/Program Operations

Flasherase™ Sequence

A multiple step command sequence is required to
erase the Flash device (a two-cycle Erase command
and repeated one cycle verify commands).

Note: The Flash memory array must be completely
programmed to 0’s prior to erasure. Refer to the
Flashrite™ Programming Algorithm.

1. Erase S etup: Write the Setup Erase command to
the command register.

2. Erase: Wr it e the Erase com mand (sam e as Setu p
Erase command) to the command register again.
The seco nd comm an d i n it iat es t he er a s e o per at i o n.
The system software routines must now time-out
the erase pulse width (10 ms) prior to issuing the
Erase-ver ify command. An integrate d stop time r
prevents any possibility of overerasure.

3. Erase-Verify: Write the Erase-verify command to
the command register. This command terminates
the erase operation. After the erase operation,
each byte of the array must be verified. Address in-

formation must be supplied with the Erase-verify
command. This command verifies the margin and
outputs t he add re ssed b y te in o rde r to co mpar e th e
array data with FFh data (Byte erased).
After successful data verification the Erase-verify
command is written again with new address infor­mation. Each byte of the array is sequentially veri­fied in this manner.

If data of the addressed loca tion is not verified, the
Erase sequence is repe ated until the entire array is
successfully verified or the sequence is repea ted
1000 times.

Flashrite Programming Sequence

A three step command sequence (a two-cycle Program
command and one cycle Verify command ) is required
to pr og r am a byte of t h e Fla sh arr ay. Refe r to th e Fl as h­rite Algorit h m.

1. Program Setup: Write the Setup Program com-
mand to the command regist er.

2. Pr ogram: Write the Program command to the com-
mand register with the appropriate Address and
Data. The system software routines must now time­out the program pulse width (10 µs) prior to issuing
the Program-verify command. An integrated stop
timer prevents any possibility of overprogramming.

3. Program-Verify: Write the Program-verify com-
mand t o th e com ma nd register. Thi s command ter ­minates the programming op eration. In additio n,
this command verifies the margin and outputs the
byte just programmed in order to compare the array
data with the original data programmed. After suc­cessful d ata ver ification, the programm ing se­quence is initiated again for the next byte address to
be programmed.

If data is n ot verified succes sfully, the Pr ogram se­quence is repeated until a successful comparison is
verified or the sequence is repeated 25 times.

Data Protection

The device is designed to offer protection aga inst acci ­dental erasure or programming ca used by spurious
system level signals that may exist during power transi­tions . The d evice po wers up in it s r ea d onl y st at e . A ls o,
with its control register architecture, alteration of the
memory contents only occurs after successful comple­tion of specific command sequences.

The device al so i ncor pora tes s everal feat ures t o pre ­vent inadvertent write cycles resulting fromVCC power­up and power-down transitions or system noise.

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up
and power-d own, the d evice locks out wr ite cycl es for

Am28F020 7

VCC < V
voltages) . Wh en VCC < V
disabled, all internal program/erase circuits are
disabled , an d th e d evice resets to the r ea d m od e. Th e
device ignores all writes until VCC > V
must ensure that the control pins are in the correct logic
state wh en VCC > V

Write Pulse “Glitch” Protection

Noise pul se s of less than 10 ns (typical) on OE#, CE#
or WE# will not initiate a write cycle.

(see DC Characteristics section for

LKO

LKO

, the comm an d r eg i ster i s

LKO

LKO

to prevent uninitentional writes.

. The user

Logical Inhibit

Writing is inhibited by holding an y one of OE# = VIL, CE#
= VIH or WE# = VIH. To initiate a write cycle CE# a nd
WE# must be a logical zero while OE# is a logical one.

Power- U p Wr ite Inhibi t

Power-up of the device with W E# = CE# = VIL and
OE# = VIH will not accept commands on the r ising
edge of WE#. The internal state machine is automat­ically reset to the read mode on power-up.

FUNCTIONAL DESCRIPTION
Description of User Modes

Table 1. Am28F020 Device Bus Operations

Operation CE# (E#)OE# (G#)WE# (W#)

VPP

(Note 1) A0 A9 I/O

Read-Only

Read/Write

Read V
Standby V
Output Disable V
Auto-Select Manufacturer

Code (Note 2)
Auto-Select Device Code

(Note 2)

Read V

Standby (Note 5) V
Output Disable V

Write V

IL

IH

IL

V

IL

V

IL

IL

IH

IL

IL

V

IL

XXV

V

IH

V

IL

V

IL

V

IL

XXV

V

IH

V

IH

XV

V

IH

V

IH

V

IH

V

IH

V

IH

V

IL

V

V

V

V

V

V

PPL

PPL

PPL

PPL

PPL

PPH

PPH

PPH

PPH

A0 A9 D

X X HIGH Z
X X HIGH Z

V

IL

V

IH

VID

(Note 3)

VID

(Note 3)

A0 A9

X X HIGH Z
X X HIGH Z

A0 A9

Legend:

X = Don’t care, where Don’t Care is either V

of V

. 0 V < An < VCC + 2 V, (normal TTL or CMOS input levels, where n = 0 or 9).

PPH

or VIH levels. V

IL

= VPP ≤ VCC + 2 V. See DC Characteristics for voltage levels

PPL

Notes:

1. V

may be grounded, connected with a resistor to ground, or < VCC + 2.0 V. V

PPL

the device. Refer to the DC characteristics. When V

PP

= V

, memory contents can be read but not written or erased.

PPL

is the programming voltage specified for

PPH

2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2.

3. 11.5 < V

4. Read operation with V

5. With V

6. Refer to Table 3 for valid D

7. All inputs are Don’t Care unless otherwise stated, where Don’t Care is either V

< 13.0 V. Minimum VID rise time and fall time (between 0 and VID voltages) is 500 ns.

ID

= V

PP

at high voltage, the standby current is ICC + IPP (standby).

PP

may access array data or the Auto select codes.

PPH

during a write operation.

IN

or VIH levels. In the Auto select mode all

IL

addresses except A9 and A0 must be held at VIL.

8. If V

1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the Am28F010 has a VPP

≤

CC

rise time and fall time specification of 500 ns minimum.

OUT

CODE

(01h)

CODE

(2Ah)

D

OUT

(Note 4)

D

IN

(Note 6)

8 Am28F020

READ ONLY MODE

When VPP is less than V
is inactive. The device can either read array or autose­lect data, or be standby mode.

+ 2 V, the comm and regis ter

CC

Read

The device f unc t ion s as a r ea d o nly m em ory wh en V
< V

+ 2 V . The de v ice ha s tw o con tro l fu ncti ons . Bo th

CC

must be satisfied in order to output data. CE# controls
power to the d evice. This pin sh ould be used for spe­cific device sele ctio n. OE# c ontro ls the device ou tputs
and shou ld be used to gate data to the output pin s if a
device is selected.

Address access time t

is equal to the delay from

ACC

stable addresses to valid ou tput data. Th e ch i p en able
access time tCE is the delay from stable addresses and
stable CE# to valid data at the output pins. The output
enable access time is the delay from the falling edge of
OE# to valid data at the output pins (assuming the ad­dresses have been stable at least t

ACC–tOE

).

PP

Standby Mode

The device has two standby modes. The CMOS
standby mode (CE# input held at V
sumes less t han 100 µA o f c urr ent . TTL s ta ndb y mode
(CE# is held at VIH) reduces the current requirements
to less than 1mA. When in the standby mode the out­puts are in a h igh imp eda nce s ta te , i nde pend ent of th e
OE# input.

If the device is deselected during eras ure, program­ming, or p rogram/erase verificati on, the device will
draw active current until the operation is terminated.

CC

±

0.5 V), con-

Output Dis a ble

Output from the device is disabled when OE# is at a
logic high level. When disabled, output pins are in a
high impedance state.

Auto Select

Flash memories can be programmed in-system or in a
standard PROM programmer. The device may be sol­dered to the circuit board upon receipt of shipment and
programmed in-system. Alternatively, the device may
initially be programmed in a PROM programmer pr ior
to soldering the device to the board.

The Auto select mode allows the reading out of a binary
code from the device that will identify its manufacturer
and type. T his mode is i ntended for the pu rpose
of automatically matching the device to be pro­grammed with its corresp onding programming algo­rithm. This mode is functional over the entire
temperature range of the device.

Programming In a PROM Programmer

To activate thi s mode, the programmin g equipm ent
must force VID (11.5 V to 13.0 V ) on addre ss A9 . Two
identi fie r b yte s ma y th en be seq uence d fr om th e de vi ce
outpu ts b y t oggli ng addr ess A0 from VIL to VIH. All other
address lines must be held at VIL, and VPP must be
less than or equal to VCC + 2.0 V while using this Auto
select mode. Byte 0 (A0 = VIL) repr esen ts th e man uf ac­turer code and byte 1 (A0 = VIH) the device identifier
code. For the device these two bytes are given in Table
2 of the device data sheet. All identifiers for manufac­turer and device codes will exhibit o dd parity with th e
MSB (DQ7) defined as the parity bit.

Table 2. Am28F020 Auto Select Code

Type
Manufacturer Code V
Device Code V

Am28F020 9

A0 Code (HEX)

IL

IH

01
2A

ERASE, PROGRAM, AND READ MODE

When VPP is equal to 12.0 V ± 5%, the command reg­ister is active. All fu nctions ar e available. Tha t is, the
device can program, erase, read array or autoselect
data, or be standby mode.

Write Operations

High voltage must be applied to the VPP pin in order to
activate the command register. Data written to the reg­ister serves as input to the internal state machine. The
output of the state machine determines the operational
function of the device.

Refer to AC Writ e Chara cteris tics and th e Erase/ Pro­gramming Waveforms for specific timing parameters.

Command Definitions

The contents of the command register default to 00h
(Read Mode) in the absence of high voltage applied to
the VPP pin. The device opera tes as a rea d only mem ­ory. High voltage on the VPP pin enables the co mma nd
regist e r. Device op er a t ion s ar e s e lec t e d by writin g s p e­cific data codes into the command register. Table 3 de­fines thes e re gist e r com m and s.

The command register does not occupy an addressable
memory location. The register is a latch that stores the
command, along with the address and data information
needed to execute the command. The register is written
by bringing WE# and CE# to VIL, while OE# is at VIH.
Addresses are latched on the falling edge of WE#, while
data is latched on the rising edge of the WE# pulse.
Standard microprocessor write timings are used.

The device requires the OE# pin to be VIH for write op­erations. This condition eliminates the possibility for
bus contention during programming operations. In
order to write, OE# must be VIH, and CE# and WE#
must be VIL. If any pin is not in the correct state a write
command will not be executed.

Read Command

Memor y conte nts can be acces sed via th e read com ­mand when VPP is high. To read from the device, write
00h into the command register. Standard microproces­sor read cycles access data from the memory. The de­vice will remain in the read mode until the command
register contents are altered.

The comma nd register defaults to 00h (r ead mode)
upon VPP power -up . The 00h (Re ad Mode ) regis ter de­fault helps ensure that inadvertent alteration of the
memory contents does not occur during the VPP power
transition. Refer to the AC Read Characteristics and
Waveform s for the spec ifi c timi n g para m ete rs.

Table 3. Am28F020 Command Definitions

First Bus Cycle Second Bus Cycle

Operation

Command (Note 4)

Read Memory Write X 00h/FFh Read RA RD
Read Auto select Write X 80h or 90h Read 00h/01h 01h/2Ah
Erase Setup/Erase Write Write X 20h Write X 20h

(Note 1)

Address

(Note 2)

Data

(Note 3)

Operation

(Note 1)

Address

(Note 2)

Data

(Note 3)

Erase-Verify Write EA A0h Read X EVD
Program Setup/Program Write X 40h Write PA PD
Program-Verify Write X C0h Read X PVD
Reset Write X FFh Write X FFh

Notes:

1. Bus operations are defined in Table 1.

2. RA = Address of the memory location to be read.
EA = Address of the memory location to be read during erase-verify.
PA = Address of the memory location to be programmed.
X = Don’t care.
Addresses are latched on the falling edge of the WE

3. RD = Data read from location RA during read operation.
EVD = Data Read from location EA during erase-verify.
PD = Data to be programmed at location PA. Data latched on the rising edge of WE
PVD = Data read from location PA during program-verify. PA is latched on the Program command.

4. Refer to the appropriate section for algorithms and timing diagrams.

pulse.

#

.

#

10 Am28F020

FLASHERASE ERASE SEQUENCE
Erase Setup

Erase Setup is the first of a two-cycle erase command.
It is a com mand -only ope ration th at stag es the device
for bulk chip erase. T he array cont ent s are no t altere d
with t his co mma nd . 20 h is wri tte n t o t h e com ma nd re g­ister in order to perform the Erase Setup operation.

Erase

The seco nd two-cycle e rase comman d initiates th e
bulk erase operation. You must write the Erase com­mand (20h) again to the register. The erase operation
begins with the rising edge of the WE# pulse. The
erase operation mu st be ter minated by writin g a new
command (Erase-verify) to the register .

This two ste p seq uenc e o f the Set up an d E rase c om­mands h elps to ensure th at memo ry c ontents are not
accidentally eras ed . Al so, chi p e rasu re ca n only occ u r
when hig h vo ltag e is appl ied to the VPP pin an d al l c o n­trol pins are in their proper state. In absence of this high
voltage, me mor y contents c annot be altere d. Refer to
AC Erase Characteristics and Waveforms for specific
timing parame ters.

Note: The Flash memory device must be fully
programmed to 00h data prior to erasure. This
equalizes the charge on all memory cells ensuring
reliable era sure.

Erase-V erify Command

The erase op eration erases all bytes of the array
in parallel. After the e ras e op era ti on , all byte s mu s t b e
sequentially verified. The Erase-verify operation is initi-

ated b y w ri tin g A 0 h to t he reg i s ter. The byte ad dr es s to
be verified must be supplied with the command. Ad­dresses are latc hed on the falling edge of the WE #
pulse or CE# pulse, whichever occurs later. The rising
edge of the WE# pulse terminates the erase operation.

Margin Verify

During the Erase-verify operation, the device applies
an internally generated margin voltage to the
addressed byte. Reading FFh from the addressed byte
indicates that all bits in the byte are properly erased.

Verify Next Address

You must write the Erase-verify command with the ap­propriate address to the register prior to verification of
each address. Each new address is latched on the fall­ing edge of WE# or CE# pulse, whichever occurs later.
The process co ntinues for each byte in the memor y
array until a byte does not return FFh data or all the
bytes in the array are accessed and verified.

If an address is not verified to FFh data, the entire chip
is erased again (refer to Erase Setup/Erase). Erase
verifica tion then resumes at the ad dress tha t failed to
verify. Erase is complete when all bytes in the array
have been verified. The device is now ready to be pro­grammed. At this point, the verification operation is ter­minated by writing a valid command (e.g. Program
Setup) to the command register. Figure 1 and Table 4,
the Flasherase electrical erase algorithm, illustrate how
commands and bus operations are combined to per­form electrical erasure. Refer to AC Erase Characteris­tics and Waveforms for specific timing parameters.

Am28F020 11

Start

Yes

Data = 00h

No

Program All Bytes to 00h

No

PLSCNT =

Apply V

Erase Error

1000

Yes

PPL

Increment

PLSCNT

Apply V

PPH

Address = 00h

PLSCNT = 0

Write Erase Setup Command

Write Erase Command

Time out 10 ms

Write Erase Verify

Time out 6 µs

Read Data from Device

No

Data = FFh

Yes

Last Address

No

Yes

Write Reset Command

Increment Address

Apply V

Erasure Completed

Figure 1. Flashera se Electrical Erase Algorithm

12 Am28F020

PPL

11559G-6

FLASHERASE ELECTRICAL ERASE ALGORITHM

This Flash memory device erases the entire array in
parallel . Th e era s e tim e de pe nd s on VPP, temperature,
and number o f erase /program cycle s on th e device. In
general, reprogramming time increases as the number
of erase/program cycles increases.

The Flasherase electrical erase algorithm employs an
interact ive clo sed lo op flow to simul ta ne ou s ly erase all
bits in the array . Erasure begins with a read of the mem­ory conte nt s. The dev ice i s era sed wh en shipped from
the factory. Reading FFh data from the device would
immedi at el y be f o l lo w ed b y e xecutin g t he Fla s hrit e pr o­gramming algorithm with the appropriate data pattern.

Should the device be currently programmed, data other
than FFh will be returned from address locations.
Follow the Fla sherase algor ithm. Uniform and reli able
erasure is en sured by fir st programm ing all bits i n the
device to their charged state (Data = 00h). This is
accomplished using the Flashr ite Programming

Table 4. Flasherase Electrical Erase Algorithm

Bus Operations Command Comments

algorithm. Erasure then continues with an initial erase
operation. Erase verification (Data = FFh) begins at
addres s 0 00 0h and co ntinues thro ugh t he array to the
last address, or until data other than FFh is
encountered. If a byte fails to verify, the device is
erased again. With each erase operation, an
increasing number of bytes verify to the erased state.
Typically, devices are erased in less than 100 pulses
(one second). Erase efficie ncy may be improved by
storing the address of the last byte that fails to verify in
a regist er. Following the next erase operation,
verification may start at the store d address location . A
total of 1000 erase pulses are allowed per reprogram
cycle, which corresponds to approximately 10 seconds
of cumul at iv e era se tim e. The ent ire se quen ce of era se
and byte verificat ion is performed with high voltage
applied to the VPP pin. Figure 1 illustrates the electrical
eras e algorithm.

Entire memory must = 00h before erasure (Note 3)

Note: Use Flashrite
programming.

Wait for V

Standby

Write

Standby Duration of Erase Operation (t

Write Erase-Verify (Note 2)

Standby Write Recovery Time before Read = 6 µs
Read Read byte to verify erasure

Standby

Write Reset Data = FFh, reset the register for read operations
Standby Wait for V

Notes:

1. See AC and DC Characteristics for values of V
switchable. When V

2. Erase Verify is performed only after chip erasure. A final read compare may be performed (optional) after the register is written
with the read command.

3. The erase algorithm Must Be Followed to ensure proper and reliable operation of the device.

Erase Setup Data = 20h
Erase Data = 20h

parameters. The V

is switched, V

PP

PPL

PP

may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V.

Initialize:
Addresses
PLSCNT (Pulse count)

Address = Byte to Verify
Data = A0h
Stops Erase Operation

Compare output to FFh
Increment pulse count

Ramp to V

PP

Ramp to V

PP

power supply can be hard-wired to the device or

PP

programming algorithm (Figure 4) for

(Note 1)

PPH

)

WHWH2

(Note 1)

PPL

Am28F020 13

Section

Addresses

CE

OE

WE

AB DEFCG

#

#

#

Data

Out

Compare

Data

Erase

Verific ation

Proceed per

Erase-

Verify

A0h

Transition

(6 µs)

Data

V

CC

V

PP

AB DEFCG

Bus Cycle Write Write Time-out Write Time-out Read Standby

Command 20h 20h N/A A0h N/A

Function

Erase
Setup

20h

Erase

20h

Erase

(10 ms)

Figure 2. AC Waveforms For Erase Operations

Analysis of Erase Timing Waveform

Note: This analysis d oes not in clud e the requi rem ent

to pr og r am th e en t ire ar r ay to 00 h da ta p ri or t o era s ur e .
Refer to the Flashrite Programming algorithm.

Erase Setup/Erase

This analysis illustr ates the use of two-cycle erase
comman ds (section A and B). T he first era se com­mand (20h) is a Setup command and does not affect
the array da ta (section A). The s econd erase com­mand (20h) initiates the erase operation (section B)
on the rising edge of this WE# pulse. All bytes of the
memory array are erased in parallel . No address inf or­mation is required.

The erase pulse occurs in section C.

Time-Out

A software timing routine (10 ms duration) must be ini­tiate d on t he ris ing edge of the WE# pul se of s ecti on B .

Note: An integrated stop timer prevents any possibil­ity of overerasure by limiting each time-out period of
10 ms.

Erase-V er ify

Upon co mpl etion of the era se sof tware timi ng r outine,
the microprocessor must write the Erase-verify com­mand (A0 h). This c ommand termi nates the era se ope r­ation on the rising edge of the WE# pulse (section D).
The Erase-verify comm and also stages th e device for
data verific ation (section F).

After each erase operation each byte must be verified.
The byte address to be verified must be supplied with

11559G-7

N/A

Erase

Algorithm

14 Am28F020

the Erase-ver ify co mma nd (sec tion D). Ad dresse s are
latched on the falling edge of the WE# pulse.

Anothe r sof tw are t imin g rout ine (6 µs du rat ion) must be
executed to allow for generation of internal v oltages for
margin checking and read oper ation (section E) .

During Erase-verification (section F) each address that
returns FFh data is successfully erased. Each address
of the array is sequentially verified in this manner by re­peating sections D thru F un til the entir e array is veri­fied or an address fails to verify. Sho uld an address

location fail to verify to FFh data, erase the device
again. Repeat sections A thru F. Resume verification
(secti on D) wi th the failed add re ss.

Each da ta change se quence al lows the devic e to use
up to 1,000 erase pulses to completely erase. Typically
100 erase pulses are required.

Note: All address locations must be programmed to
00h prior to erase. This equa lizes the charge on all
memory cells and ens u re s reli able era s ur e.

FLASHRITE PROGRAMMING SEQUENCE
Program Setup

The device is programmed byte by byte. Bytes may be
programmed sequentially or at random. Program Setup
is the first of a two-cycle program command. It stages
the device for byte program ming. Th e Progra m Setu p
operation is performed by writing 40h to the command
register.

Program

Only after the program Setup operation is completed
will the next WE# pulse initiate the active programming
operation. The appropriate address and data for pro­gramming must be available on the second WE# pulse.
Addresses and data are internally latched on the falling
and rising edge of the WE# pulse respectively. The ris­ing edg e o f WE# also begin s the pro gram min g op era ­tion. You must write the Program-verify command to
terminate the programming operation. This two step
sequen ce o f the Setu p and Program co mmands help s
to ensure that memory contents are not accidentally
written. Also, programming can only occur when high
vol tage is ap plie d to th e VPP pin an d al l c on tr ol pins are
in their proper state. In absence of this high voltage,
memory contents cannot be pr ogrammed.

Refer to AC Characteristics and W av ef orms for specific
timing parame ters.

Program Verify Command

Following each programming operation, the byte just
programm e d must be ver if ie d.

Write C0h into the command register in order to initiate
the Program-verify operation. The rising edge of this

WE pulse te rm ina tes the p rogram min g opera tion. Th e
Program-verify operation stages the device for verifica­tion of the last byte programmed. Addresses were pre­viously latched. No new information is required.

Margin Verify

During the P rog ra m-v erif y ope rat ion, th e de vi ce ap pli es
an internally gen erated margin voltage to the ad­dressed byte. A normal microprocessor read cycle out­puts the data. A successful comparison between the
programme d byte and the tr ue data indicate s that the
byte was successfully programmed. The original pro­grammed data should be stored for comparison. Pro­gramming then proceeds to the next desired byte
location. S h ou l d th e byte fail to ver ify, reprogram (refer
to Program Setup/Program). Figure 3 and Table 5 indi­cate how ins tr u ctions are com bin ed w it h th e bus op er ­ations to perform byte programm ing. Refer to AC
Programming Characteristics and Waveforms for spe­cific timing parameters.

Flashrite Programming Algorithm

The device Flashrit e Programm ing a lgorith m empl oys
an interactive closed loop flow to program data byte by
byte. Bytes may be programmed sequentially or at ran­dom. The Flashrite Programming algorithm uses 10 µs
programming pulses. Each operation is followed by a
byte verification to determine when the addressed byte
has been successfully programmed. The program al­gorithm allows for up to 25 programming operations per
byte per repro gramming cycle. Most byte s verify after
the first or second pul se. The entir e sequen ce of pro­gramming and byte verific ation is per formed wit h high
voltage appl ie d to th e VPP pin. Figure 3 and Table 5 i l­lustrate the programming algorithm.

Am28F020 15

Increment Address

Start

Apply V

PPH

PLSCNT = 0

Write Program Setup Command

Write Program Command (A/D)

Time out 10 µs

Write Program Verify Command

Time out 6 µs

Read Data from Device

Verify Byte

No

Yes

No

Last Address

Yes

Write Reset Command

Increment PLSCNT

No

PLSCNT =

25?

Yes

Apply V

PPL

Programming Completed

Figure 3. Flashrite Programming Algorithm

Apply V

PPL

Device Failed

11559G-8

16 Am28F020

Table 5. Flashrite Programming Algorithm

Bus Operations Command Comments

Standby

Wait for V

Ramp to V

PP

Initialize Pulse counter

PPH

(Note 1)

Program Setup Data = 40h

Write

Program Valid Address/Data

Standby Duration of Programming Operation (t

WHWH1

)
Write Program-Verify (Note 2) Data = C0h Stops Program Operation
Standby Write Recovery Time before Read = 6 µs
Read Read Byte to Verify Programming
Standby Compare Data Output to Data Expected
Write Reset Data = FFh, resets the register for read operations.
Standby Wait for V

Ramp to V

PP

PPL

(Note 1)

Notes:

1. See AC and DC Characteristics for values of V
switchable. When V

is switched, V

PP

may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V.

PPL

parameters. The V

PP

power supply can be hard-wired to the device or

PP

2. Program V erify is performed only after byte programming. A final read/compare may be performed (optional) after the register
is written with the read command.

Am28F020 17

Section

Addresses

CE

OE

WE

A

B

DE FCG

#

#

#

Data

V

CC

V

PP

AB DEFCG

Bus Cycle Write Write Time-out Write Time-out Read Standby

Command 40h

Function

Program

Setup

20h

Program
Address,

Program Data

Program

Command

Latch

Address and

Data

Data

In

N/A

Program

(10 µs)

A0h

C0h

(Stops

Program)

Program

Verify

N/A

Transi tion

(6 µs)

Data

Out

Compare

Data

Program

Verific ation

11559G-9

N/A

Proceed per

Programming

Algorithm

Figure 4. AC Waveforms for Programmin g Operations

ANALYSIS OF PROGRAM TIMING WAVEFORMS
Program Setup/Program

Two-cycle write commands are required for program
operations (section A and B). The first program com­mand (40h) is a Setu p comm and an d do es not a ffect
the array data (section A).The second program com­mand latch es addr ess and data req uired for program­ming on the falling and rising edge of WE# respectively
(section B). The rising edge of this WE# pulse (section
B) also initiates the programming pulse. The device is
programmed on a byte by byte basis either sequentially
or randomly.

The program pulse occurs in section C.

18 Am28F020

Time-Out

A software timing routine (10 µs duration) must be initi­ated on the rising edge of the WE# pulse of section B.

Note: An integ rated stop timer pre v ents an y possibility
of overprogramming by limiting each time-out period of
10 µs .

Program-Verify

Upon completion of the program timing routine, the mi­croprocessor must write the program- verify command
(C0h). This command terminates the programming op­eration on the rising edge of the WE# pulse (section D).
The program-verify command also stages the device
fo r data v eri fica tion (s ecti on F ). An oth er s oft war e ti ming

routine (6 µs duration) must be executed to allow for
gener a ti on o f int e rnal v o l tag es for mar gin c h ecking a nd
read operations (section E).

During program-verification (section F) each byte just
programmed is read to compare array data with original
program data. When successfully verified, the next de­sired address is programmed. Should a byte fail to ver­ify, repro gram th e byte (r epeat section A thr u F ) . E ac h
data ch ange sequ enc e a llows th e devic e to use up t o
25 pr ogr am pu ls es per b yte . Typicall y, byte s ar e v erif ied
within one or two pulses.

Algorithm Timing Delays

There are four different timing delays associated with
the Flasherase and Flashrite algorithms:

1. The first delay is associated with the VPP rise-time
when VPP first tur ns on. Th e ca pa ci to rs o n th e V
bus cause an RC ram p. Afte r switc hin g on the VPP,
the de lay requir ed i s pro por tio nal to the numbe r o f
device s being eras ed and the 0. 1 mF/d evice. V
must reach it s fin al valu e 10 0 ns be fore c om m and s
are executed.

2. The second delay time is the erase time pulse width
(10 ms). A software timing routine should be run by
the local m icropr ocessor to ti me out th e delay. The
erase op eration mus t be te rmina ted at the conclu ­sion of the ti ming ro utine or prior to executing any
system interrupts that may occur during the erase
operation. To ensure proper device operation, write
the Erase-verify operation after each pulse.

3. A third delay t ime is required for each programming
pulse w idth (10 ms) . The programming algorithm is
interactive and verifies each byte after a program
pulse. The program operation must be terminated at
the conclusion of the timing routine or prior to exe­cuting any system interrupts that may occur during
the programming operation.

4. A fourth timing delay associated with both the
Flasherase and Flashrite algorithms is the write re­covery time (6 ms). During this time internal circuitry
is chan ging volt age levels fro m the e rase/ program
level to those used for margin verify and read oper­ations. An at t emp t t o re ad t he device du ring t hi s p e­riod will result in possible false data (it may appear
the device is not properly erased or programmed).

Note: Software timing routines should be written in
machine language for each of the delays. Code written
in machine l anguage requires knowledge of the appro­priate microprocessor c lock speed in order to accu­rately time each delay.

PP

PP

Parallel Device Erasure

Many applica tions will us e more than one Flash
memory device. Total erase t ime may be minimized by
implementing a parallel erase algorithm. Flash
memories may erase at different rates. Theref ore each
device must be verified separately. When a device is
completely erased and verified use a masking code to
prevent further erasure. The other devices will continue
to er ase until verified. Th e masking code applied could
be the read command (00h).

Po wer-Up/Power-Do wn Sequence

The device powers -up in th e Rea d only mode. Power
supply sequencing is not required. Note that if VCC ≤

1.0 Volt, the voltage difference between V
should not exceed 10.0 Volts. Also, the device has V
rise time and fall t i me sp ec ifi cat i on of 500 n s mi nim um.

PP

and V

CC

PP

Reset Command

The Reset comm and initializes the Flash m emor y de­vice to the Read mode. In addition, it also provides the
user with a safe method to abort any device operation
(including program or erase).

The Rese t comm an d must b e wri tten two co nsecut ive
times after the setup Program command (40h). This will
reset the device to the Read mode.

Following any other Flash command write the Reset
command once to the de vice . Thi s will s afel y abort any
previous operation and initialize the device to the
Read mode.

The Setup Program command (40h) is the only com­mand that requires a two sequence reset cycle. The
first Reset command is interpreted as program data.
However, FF h data is c o nsidered nu ll data du r ing pro­gramming operations (memory cells are only pro­grammed from a logical “1” to “0”). T he second Reset
command safely abor ts the programmin g operation
and resets the device to the Read mode.

Memory contents are not altered in any case.
This deta iled inform ation is for your reference. It may

prove easier to alw ays issue the Rese t comman d two
consecutive times. This eliminates the need to deter­mine if you are in the setup Program state or not.

Programming In-System

Flash memories can be programmed in-system or in a
standard PROM programmer. The device may be sol­dered to the circuit board upon receipt of shipment and
programmed in-system. Alternatively, the device may
initially be programmed in a PROM programmer pr ior
to soldering the device to the board.

Am28F020 19

Auto Select Command

AMD’s Flash memories are designed for use in applica­tions where the local CPU alters memory contents. Ac­cordingly, manufacturer and device codes must be
accessible while the device resides in the target sys­tem. PROM programmers typically access the signa­ture codes by raising A9 to a high voltage. However,
multiplexing high voltage onto address lines is not a
generally de si re d syst e m des ign practice.

The device contains an Auto Select operation to sup­plement traditional PROM programming methodology.
The operation is initiated by writing 80h or 90h into the
command r egister. Following this command, a read
cycle address 0000h retrieves the manufacturer code
of 01h. A read cycle from address 0001h returns the
device code. To terminate the operation, it is necessary
to write anothe r valid command, suc h a s R eset (FFh),
into the register.

20 Am28F020

ABSOLUTE MAXIMUM RATINGS

Storage T emperature . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground
All pins except A9 and VPP (Note 1) .–2.0 V to +7.0 V

VCC (Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

A9, VPP (Note 2) . . . . . . . . . . . . . . .–2.0 V to +14.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V . During
voltage transitions, input or I/O pins may overshoot V
–2.0 V for periods of up to 20 ns. Maximum DC voltage on
input or I/O pins is V
input or I/O pins may overshoot to VCC +2.0 V for periods
up to 20 ns.

2. Minimum DC input voltage on pins A9 and V
During voltage transitions, A9 and V
VSS to –2.0 V for periods of up to 20 ns. Maximum DC
input voltage on pin A9 and V
overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.

4. Stresses abov e those list ed under “Absol ute Maxim um
Ratings” ma y cause permanent damage to the de vice. This
is a stress r atin g only ; fun ctio nal op era tion of th e de v ice a t
these or any other co nditi ons abov e th ose indi cate d in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions f or ext ended period s ma y aff ect d evi ce relia bility.

+0.5 V . During voltage transitions,

CC

PP

may overshoot

PP

is +13.0 V, which may

PP

to

SS

is –0.5 V.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA). . . . . . . . . . . .0°C to +70°C

Industrial (I) Devices

Ambient Temperature (TA). . . . . . . . . .–40°C to +85°C

Extended (E) Devices

Ambient Temperature (TA). . . . . . . . .–55°C to +125°C

VCC Supply Voltages

VCC . . . . . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V

VPP Voltages

Read . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.6 V

Program, Erase, and Verify. . . . . . +11.4 V to +12.6 V

Operating ranges define those limits between which the
functionality of the device is guaranteed.

Am28F020 21

MAXI MUM OVERSHOOT
Maximum Negative Input Overshoot

+0.8 V

–0.5 V

–2.0 V

Maximum Positive Input Overshoot

+ 2.0 V

V

CC

V

+ 0.5 V

CC

2.0 V

20 ns

20 ns

20 ns

20 ns 20 ns

20 ns

14727F-10

14727F-11

Maximum VPP Overshoot

13.5 V

V

+ 0.5 V

CC

14.0 V

20 ns

20 ns 20 ns

14727F-12

22 Am28F020

DC CHARACTERISTICS over operating range unless otherwise specified
TTL/NMOS Compatible

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

I

I

I

I

I

I

I

I

V

V

V

V

I

LI

I

LO

CCS

CC1

CC2

CC3

PPS

PP1

PP2

PP3

V

V

OL

OH1

V

I

ID

PPL

PPH

Input Leakage Current V
Output Leakage Current VCC = VCC Max, V
VCC Standby Current VCC = VCC Max, CE# = V

VCC Active Read Current

VCC Programming Current

VCC Erase Current

V

Standby Current V

PP

V

Read Current

PP

V

Programming Current

PP

V

Erase Current

PP

Input Low Voltage –0.5 0.8 V

IL

Input High Voltage 2.0 VCC + 0.5 V

IH

= V

CC

V

CC = VCC

I

OUT

CE

#

Max, VIN = V

CC

Max, CE# = V

= 0 mA, at 6 MHz

= VIL

OUT

or V

CC

SS

= VCC or V

IH

OE# = V

IL,

Programming in Progress (Note 4)
CE

#

= VIL

Erasure in Progress (Note 4)

= V

PP

PPL

V

= V

PP

PPH

= V

V

PP

PPL

= V

V

PP

PPH

Programming in Progress (Note 4)

= V

V

PP

PPH

Erasure in Progress (Note 4)

SS

0.2 1.0 mA

IH

20 30 mA

20 30 mA

20 30 mA

70 200

10 30 mA

10 30 mA

Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V
Output High Voltage IOH = –2.5 mA, VCC = VCC Min 2.4 V
A9 Auto Select Voltage A9 = V

ID

ID

11.5 13.0 V
A9 Auto Select Current A9 = VID Max, VCC = VCC Max 5 50 µA
V

during Read-Only

PP

Operations
V

during Read/Write

PP

Operations

Note: Erase/Program are inhibited

PP

= V

PPL

when V

0.0 VCC +2.0 V

11.4 12.6 V

±1.0 µA
±1.0 µA

±1.0 µA

µA

±1.0

V

LKO

Low VCC Lock-out Voltage 3.2 3.7 V

Notes:

1. Caution: The Am28F020 must not be removed from (or inserted into) a socket when V
the voltage difference between V

and VCC should not exceed 10.0 Volts. Also, the Am28F020 has a VPP rise time and fall

PP

time specification of 500 ns minimum.

2. I

3. Maximum active power usage is the sum of I

is tested with OE# = VIH to simulate open outputs.

CC1

CC

and IPP.

4. Not 100% tested.

Am28F020 23

or VPP is applied. If VCC ≤ 1.0 V olt,

CC

DC CHARACTERISTICS
CMOS Compatible

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

I

I

I

I

I

I

I

I

V
V
V

V

V

I

LI

I

LO

CCS

CC1

CC2

CC3

PPS

PP1

PP2

PP3

V

V

OL

OH1

OH2

V

I

ID

PPL

PPH

Input Leakage Current V
Output Leakage Current VCC = VCC Max, V
VCC Standby Current VCC = VCC Max, CE

V

Active Read Current

CC

VCC Programming Current

VCC Erase Current

V

Standby Current V

PP

V

Read Current V

PP

V

Programming Current

PP

V

Erase Current

PP

Input Low Voltage –0.5 0.8 V

IL

Input High Voltage 0.7 V

IH

= V

Max, VIN = V

CC

= V

Max, CE# = V

CC

= 0 mA, at 6 MHz
= V

IL

V
I

OUT

CE

CC

CC

#

OUT

or V

CC

SS

= VCC or V

= VCC + 0.5 V 15 100 µA

#

OE# = V

IL,

Programming in Progress (Note 4)
CE

= V

#

IL

Erasure in Progress (Note 4)

= V

PP

PPL

= V

PP

PPH

= V

V

PP

PPH

Programming in Progress (Note 4)
V

= V

PPH

PP

Erasure in Progress (Note 4)

SS

IH

20 30 mA

20 30 mA

20 30 mA

70 200 µA

10 30 mA

10 30 mA

CC

Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V

Output High Voltage

A9 Auto Select Voltage A9 = V

ID

IOH = –2.5 mA, VCC = VCC Min 0.85 V
IOH = –100 µA, V

ID

= VCC Min VCC –0.4

CC

CC

11.5 13.0 V
A9 Auto Select Current A9 = VID Max, VCC = VCC Max 5 50 µA
VPP during Read-Only

Operations
V

during Read/Write

PP

Operations

Note: Erase/Program are inhibited

PP

= V

PPL

when V

0.0 VCC + 2.0 V

11.4 12.6 V

1.0 µA

±

1.0 µA

±

1.0 µA

±

V

+ 0.5 V

CC

V

V

LKO

Low VCC Lock-out Voltage 3.2 3.7 V

Notes:

1. Caution: The Am28F020 must not be removed from (or inserted into) a socket when V
the voltage difference between V

and VCC should not exceed 10.0 volts. Also, the Am28F020 has a VPP rise time and fall

PP

time specification of 500 ns minimum.

2. I

3. Maximum active power usage is the sum of I

is tested with OE# = VIH to simulate open outputs.

CC1

CC

and IPP.

4. Not 100% tested.

24 Am28F020

or VPP is applied. If VCC ≤ 1.0 volt,

CC

30

25

20

Active in mA

15

CC

I

–55°C
0°C

10

5

0

25°C
70°C
125°C

0123456789101112

Figure 5 . Am28F0 20—Average ICC Active vs. Frequency

TEST CONDITIONS

Device

Under

Test

C

L

Note: Diodes are IN3064 or equivalent

6.2 k

Frequency in MHz

VCC = 5.5 V, Addressing Pattern = Minmax

Data Pattern = Checkerboard

5.0 V

2.7 k

Ω

Ω

14727F-14

Output Load 1 TTL gate
Output Load Capacitance, C

(including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels 0.0–3.0 0.45–2.4 V
Input timing measurement

reference levels
Output timing measurement

reference levels

Table 6. Test Specifications

Test Condition -70 All others Unit

14727F-13

L

30 100 pF

10 ns

≤

1.5 0.8, 2.0 V

1.5 0.8, 2.0 V

Am28F020 25

SWITCHING TEST WAVEFORMS

s

2.4 V

0.45 V

2.0 V
Test Points

Input Output

2.0 V

0.8 V0.8 V

AC Testing (all speed options except -70): Inputs are driven at

2.4 V for a logic “1” and 0.45 V for a logic “0”. Input pulse rise
and fall times are

10 ns.

≤

3 V

1.5 V

0 V

Input Output

Test Points

1.5 V

AC Testing for -70 devices: Inputs are driven at 3.0 V for a
logic “1” and 0 V for a logic “0”. Input pulse rise and fall time
are ≤10 ns.

14727F-15

SWITCHING CHARACTERISTICS over operating range unless otherwise specified
AC Character istics—Read-Only Operations

Parameter

Symbols Am28F020 Speed Options

JEDEC Standard Parameter Description -70 -90 -120 -150 -200 Unit

t

AVAV

t

ELQV

t

AVQV

t

GLQV

t

ELQX

t

EHQZ

t

GLQX

t

GHQZtDF

t

AXQX

t
t
t
t
t
t
t

t

RC

CE

ACC

OE

LZ

DF

OLZ

OH

Read Cycle Time (Note 2) Min 70 90 120 150 200 ns
Chip Enable AccessTime Max 70 90 120 150 200 ns
Address Access Time Max 70 90 120 150 200 ns
Output Enable Access Time Max 35 35 50 55 55 ns
Chip Enable to Output in Low Z (Note 2)Min00000ns
Chip Disable to Output in High Z (Note 1) Max 20 20 30 35 35 ns
Output Enable to Output in Low Z (Note 2) Min 00000ns
Output Disable to Output in High Z (Note 2) Max 20 20 30 35 35 ns
Output Hold from first of Address, CE#, or

OE# Change (Note 2)

Min00000ns

t

WHGL

t

VCS

Write Recovery Time before Read Min66666µs
VCC Setup Time to Valid Read (Note 2) Min 50 50 50 50 50 µs

Notes:

1. Guaranteed by design; not tested.

2. Not 100% tested.

26 Am28F020

AC Character istics—Write (Erase/Program) Operations

Parameter Symbols Am28F020 Speed Options
JEDEC Standard Description -70 -90 -120 -150 -200 Unit

t

AVAV

t

AVWL

t

WLAXtAH

t

DVWHtDS

t

WHDXtDH

t

WHGLtWR

t

GHWL

t

ELWL

t

WHEHtCH

t

WLWHtWP

t

WHWLtWPH

t

WHWH1

t

WHWH2

t

VPEL

t

VCS

t

VPPR

t

VPPF

t

LKO

t
t

t

WC

AS

CS

Write Cycle Time (Note 4) Min 70 90 120 150 200 ns
Address Setup Time Min 0 0 0 0 0 ns
Address Hold Time Min 45 45 50 60 75 ns
Data Setup Time Min 45 45 50 50 50 ns
Data Hold Time Min 10 10 10 10 10 ns
Write Recovery Time Before Read Min 6 6 6 6 6 µs
Read Recovery Time Before Write Min 0 0 0 0 0 µs
CE# Setup Time Min 0 0 0 0 0 ns
CE# Hold Time Min 0 0 0 0 0 ns
Write Pulse Width Min 45 45 50 60 60 ns
Write Pulse Width High Min 20 20 20 20 20 ns
Duration of Programming Operation (Note 2) Min 10 10 10 10 10 µs
Duration of Erase Operation (Note 2) Min 9.5 9.5 9.5 9.5 9.5 ms
VPP Setup Time to Chip Enable Low (Note 4) Min 100 100 100 100 100 ns
VCC Setup Time to Chip Enable Low (Note 4) Min 50 50 50 50 50 µs
VPP Rise Time (Note 4) 90% V
VPP Fall Time (Note 4) 10% V
VCC < V

to Reset (Note 4) Min 100 100 100 100 100 ns

LKO

PPH

PPL

Min 500 500 500 500 500 ns
Min 500 500 500 500 500 ns

Notes:

1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC
Characteristics for Read Only operations.

2. Maximum pulse widths not required because the on-chip program/erase stop timer will terminate the pulse widths internally
on the device.

3. Chip Enable-Controlled Writes: Write operations are driven by the valid combination of Chip Enable (CE#) and Write Enable
(WE#). In systems where CE# defines the Write Pulse Width (within a longer WE# timing waveform) all setup, hold and
inactive WE# times should be measured relative to the CE# waveform.

4. Not 100% tested.

Am28F020 27

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

SWITCHING WAVEFORMS

Steady

Changing from H to L

Changing from L to H

Addresses

CE# (E#)

OE# (G#)

WE# (W#)

Data (DQ)

5.0 V
V

CC

0 V

Power-up, Standby

t

VCS

High Z High Z

Device and

Address Selection

Outputs

Enabled

Data

Valid

Addresses Stable

t

(tRC)

AVAV

t

WHGL

t

(tOE)

GLQV

t

(tCE)

t

ELQX

ELQV

(tLZ)

t

GLQX

(t

)

OLZ

t

AXQX (tOH

Output Valid

t

(t

ACC

)

AVQV

Figure 7. AC Waveforms for Read Operations

Standby, Power-Down

t

EHQZ

(t

)

DF

t

GHQZ

(t

)

DF

)

14727F-14

28 Am28F020

SWITCHING WAVEFORMS

Addresses

CE# (E#)

OE# (G#)

WE# (W

#

Data (DQ)

5.0 V
V

CC

0 V
V

PPH

V

PP

V

PPL

Po wer-up,

Standby

t

ELWL (tCS

)

)

t

WLWH (tWP

t

DVWH (tDS

HIGH Z

Setup Erase

Command

t

AVAV (tWC

)

)

)

DATA IN

t

VCS

t

VPEL

Command

t

GHWL (tOES

t

WHWL (tWPH

= 20h

Erase

t

AVWL (tAS

t

WHEH (tCH

)

)

t

WHDX (tDH

)

)

DATA IN

= 20h

Erasure

)

Erase-V erify

Command

t

WHWH2

t

WLAX (tAH

DAT A IN =

A0h

t

ELQX (tLZ

t

ELQV

t

WHGL

t

GLQV (tOE

)

(tCE)

Erase

Verification

t

AVAV (tRC

)

t

EHQZ (tDF

t

GHQZ (tDF

)

t

AXQX (tOH

Power-down

)

)

)

)

VALID

DA T A

OUT

Standby,

t

GLQX (tOLZ

)

Figur e 8. AC Waveforms for Erase Operations

14727F-16

Am28F020 29

SWITCHING WAVEFORMS

Power-up,

Standby

Addresses

Setup Program

Command

Program

Command

Latch Address

and Data

Programming

V erify

Command

Programming

V erification

Standby,

Power-down

(E#)

CE

#

OE

(G#)

#

WE

(W#)

#

Data (DQ)

5.0 V
V

CC

0 V
V

PPH

V

PP

V

PPL

t

ELWL (tCS

t

WLWH (tWP

t

HIGH Z

t

AVAV (tWC

t

AVWL (tAS

)

)

DVWH (tDS

)

t

VCS

t

)

)

t

GHWL (tOES

DATA IN

= 40h

VPEL

t

WHEH (tCH

t

WHWL (tWPH

)

)

t

WHDX (tDH

DATA IN

t

WLAX (tAH

)

)

)

t

WHWH1

t

DATA IN

= C0h

t

ELQX (tLZ

t

(tCE)

ELQV

t

WHGL

t

GHQZ (tDF

GLQV (tOE

)

t

AVAV (tRC

t

GHQZ (tDF

)

t

AXQX (tOH

)

)

)

)

VALID

DA T A

OUT

t

GLQX (tOLZ

14727F-17

)

Figure 9. AC Waveforms for Programming

30 Am28F020

ERASE AND PROGRAMMING PERF ORMANCE

Limits

Typ

Parameter

Chip Erase Time 1 10 sec Excludes 00h programming prior to erasure
Chip Programming Time 4 25 sec Excludes system-level overhead
Write/Erase Cycles 10,000 Cycles

(Note 1)

Max

(Note 2) Unit

CommentsMin

Notes:

C, 12 V VPP.

1. 25

°

2. Maximum time specified is lower than worst case. Worst case is derived from the Flasherase/Flashrite pulse count
(Flasherase = 1000 max and Flashrite = 25 max). T ypical worst case for program and erase is significantly less than the actual
device limit.

LATCHUP CHARACTERISTICS

Parameter Min Max

Input Voltage with respect to V
Input Voltage with respect to V
Current –100 mA +100 mA
Includes all pins except V

on all pins except I/O pins (Including A9 and VPP) –1.0 V 13.5 V

SS

on all pins I/O pins –1.0 V VCC + 1.0 V

SS

Test conditions: VCC = 5.0 V, one pin at a time.

CC

PIN CAPACITANCE

Parameter

Symbol Parameter Description Test Conditions Typ Max Unit

C

IN

C

OUT

C

IN2

Note: Sampled, not 100% tested. Test conditions T

Input Capacitance VIN = 0 8 10 pF
Output Capacitance V
VPP Input Capacitance VPP = 0 8 12 pF

= 25°C, f = 1.0 MHz.

A

= 0 8 12 pF

OUT

DATA RETENTION

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C10Years
125°C20Years

Am28F020 31

PHYSICAL DIMENSIONS
PD032—32-Pin Plastic DIP (measured in inches)

1.640

1.670

.120
.160

32

.140
.225

Pin 1 I.D.

.045
.065

.005 MIN

.090
.110

.016
.022

17

.530
.580

16

0°

10°

SEATING PLANE

.015
.060

PL032—32-Pin Plastic Leaded Chip Carrier (measured in inches)

.485
.495

.009
.015

.125
.140

.080
.095

SEATING

PLANE

.013
.021

.050 REF.

SIDE VIEW

.585
.595

.447
.453

Pin 1 I.D.

.547
.553

.026
.032

TOP VIEW

.600
.625

.009
.015

.630
.700

16-038-S_AG
PD 032
EC75
5-28-97 lv

.042
.056

.400

REF.

.490
.530

16-038FPO-5
PL 032
DA79
6-28-94 ae

32 Am28F020

PHYSICAL DIMENSIONS
TS032—32-Pin Standard Thin Small Outline Package (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

7.90

8.10

0.50 BSC

1.20

MAX

18.30

18.50

19.80

20.20

0.05

0.15

0.08

0.20

0.10

0°
5°

0.50

0.70

0.21

16-038-TSOP-2
TS 032
DA95
3-25-97 lv

33 Am28F020

PHYSICAL DIMENSIONS
TSR032—32-Pin Reversed Thin Small Outline Package (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

7.90

8.10

0.50 BSC

1.20
MAX

18.30

18.50

19.80

20.20

0.05

0.15

0.08

0.20

0.10

0°
5°

0.50

0.70

0.21

16-038-TSOP-2
TSR032
DA95
3-25-97 lv

Am28F020 34

DATASHEET REVISION SUMMARY FOR AM28F020

Revision E+1

Distinctive Characteristics:

High Performan ce:

is now 70 ns.

General Description:

Paragraph 2: Changed fastest speed option to 70 ns.

Product Selector Guide:

Added -70, deleted -95 and -250 speed options.

Ordering Information, Standard Products:

The -70 speed option is now listed in the example.

Valid Combinations:

combinations.

Operating Ranges:

VCC Suppl y Voltages:

speed options.

AC Characteristics:

Read Onl y Operati ons Chara cter istics:

column and test conditi ons.
Deleted -95 and -250 speed options.

The fastest spee d option available

Added -7 0, de leted -95 and -25 0

Added -70, deleted -95 and -250

Added the -7 0

AC Characte ris ti cs :

Write/Erase/Program Operations:

umn. Deleted -95 and -250 speed options. Changed
speed option in Note 2 to -70.

Switching Test Waveforms:

In the 3.0 V waveform caption, changed -95 to -70.

Added the -70 col-

Revision F

Matched formatting to other current data sheets.

Revision F+1

Figure 3, Flashrite Programming Algorithm:

of arrow originating from Incremen t Address box so
that it points to the PLSCNT = 0 box, not the Write Pro­gram Verify Com mand box. This i s a corr ectio n to the
diagram on page 6-189 of the 1998 Flash Memory
Data Book .

Move d end

Revision F+2

Programming In A PROM Progra mmer:

Deleted the paragraph “(Refer to the AUTO SELECT
paragraph in the ER ASE, PROGRAM, and READ
MODE section for programming the Flash memory de­vice in-system).”

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

35 Am28F020