Datasheet AM27C64-90DI, AM27C64-90DEB, AM27C64-90DE, AM27C64-90DCB, AM27C64-90DC Datasheet (AMD Advanced Micro Devices)

FINAL

Am27C64

64 Kilobit (8 K x 8-Bit) CMOS EPROM

DISTINCTIVE CHARACTERISTICS

■ Fast access time

— Speed options as fast as 45 ns

■ Low power consumption

— 20 µA typical CMOS standby current

■ JEDEC-approved pinout

■ Single +5 V power supply

■ ±10% power supply tolerance standard

■ 100% Flashrite™ programming

— Typical programming time of 1 second

GENERAL DESCRIPTION

The Am27C64 is a 64-Kbit, ultraviolet erasable pro­grammable read-only memory. It is organized as 8K
words by 8 bits per word, operates from a single +5 V
supply, has a static standby mode, and features fast
single address location programming. Products are
available in windowed ceramic DIP packages, as well
as plastic one time programmable (OTP) PDIP and
PLCC packages.

Data can be typically accessed in less than 45 ns, al­lowing high-p erformance m icroproces sors to ope rate
without any WAIT states. The device offers separate
Output Enable (OE# ) and Chip Enable (CE#) controls,

■ Latch-up protected to 100 mA from –1 V to

+ 1 V

V

CC

■ High noise immunity

■ Versatile features for simple interfacing

— B oth CMOS and TTL input/output compatibility
— Two line control functions

■ Standard 28-pin DIP, PDIP, and 32-pin PLCC

packages

thus eliminating bus contention in a mul tiple bus micro­processor system.

AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 80 mW in active mode, and
100 µW in standby mode.

All signals are TTL levels, including programming sig­nals. Bit locations may be programmed singly, in
blocks, or at random. The device suppor ts AMD’s
Flashrite programming alg orithm (100 µs pulses), re­sulting in a typical programming time of 1 second.

BLOCK DIAGRAM

PGM#

A0–A12
Address

Inputs

OE#
CE#

V

CC

V

SS

V

PP

Output Enable

Chip Enable

and

Prog Logic

Y

Decoder

X

Decoder

Data Outputs

DQ0–DQ7

Output
Buffers

Y

Gating

65,538
Bit Cell

Matrix

Publication# 11419 Rev: E Amendment/0
Issue Date: May 1998

11419E-1

PRODUCT SELECTOR GUIDE

Family Part Number Am27C64

= 5.0 V ± 5% -255

V

Speed Options

Max Access Time (ns) 45 55 70 90 120 150 200 250
CE# (E#) Access (ns) 45 55 70 90 120 150 200 250
OE# (G#) Access (ns) 30 35 40 40 50 50 50 50

CC

= 5.0 V ± 10% -45 -55 -70 -90 -120 -150 -200

V

CC

CONNECTION DIAGRAMS
Top View

DIP PLCC

28
27
26
25
24
23
22
21
20
19
18
17
16
15

V

CC

PGM# (P#)
NC
A8
A9
A11
OE# (G#)
A10
CE# (E#)
DQ7
DQ6

DQ5
DQ4
DQ3

11419E-2

A6
A5
A4

A3
A2
A1
A0

NC

DQ0

5
6

7

8
9
10

11
12
13

14

A7

15

DQ1

A12

DQ2

PP

CC

PGM# (P#)

DU

V

13130234

32

17

18

SS

DU

V

V

19 2016

DQ3

DQ4

NC

29
28
27

26
25
24
23
22
21

DQ5

A8
A9

A11

NC
OE# (G#)
A10

CE# (E#)
DQ7
DQ6

11419E-3

V

PP

A12

A7
A6
A5
A4
A3
A2
A1
A0

DQ0
DQ1

DQ2

V

SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14

Notes:

1. JEDEC nomenclature is in parenthesis.

2. Don’t use (DU) for PLCC.

PIN DESIGNATIONS

LOGIC SYMBOL

A0–A12 = Address Inputs
CE# (E#) = Chip Enable Input
DQ0–DQ7 = Data Input/Outputs
OE# (G#) = Output Enable Input
PGM# (P#) = Program Enable Input
V

CC

V

PP

V

SS

=VCC Supply Voltage
= Program Voltage Input
= Ground

NC = No Internal Connection

2 Am27C64

13

A0–A12

CE# (E#)
PMG# (P#)

OE# (G#)

8

DQ0–DQ7

11419E-4

ORDERING INFORMATION
UV EPROM Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:

AM27C64 -45 D C

DEVICE NUMBER/DESCRIPTION

Am27C64
64 Kilobit (8 K x 8-Bit) CMOS UV EPROM

B

OPTIONAL PROCESSING

Blank = Standard Processing
B = Burn-In

TEMPERATURE RANGE

C = Commercial (0°C to +70
I=Industrial (–40

E = Extended (–55°C to +125°C)

PACKAGE TYPE

D = 28-Pin Ceramic DIP (CDV028)

SPEED OPTION

See Product Selector Guide and Valid Combinations

°C to +85°C)

°C)

AM27C64-45
AM27C64-55
AM27C64-70

AM27C64-90
AM27C64-120
AM27C64-150
AM27C64-200
AM27C64-255

= 5.0 V ± 5%

V

CC

Valid Combinations

DC, DCB, DI, DIB

DC, DCB, DI, DIB, DE, DEB

DC, DCB, DI, DIB

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

Am27C64 3

ORDERING INFORMATION
OTP EPROM Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:

AM27C64 -55 P C

OPTIONAL PROCESSING

Blank = Standard Processing

TEMPERATURE RANGE

C = Commercial (0
I=Industrial (–40

E = Extended (–55°C to +125°C)

PACKAGE TYPE

P = 28-Pin Plastic DIP (PD 028)
J = 32-Pin Plastic Leaded Chip Carrier (PL 032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

°C to +70°C)

°C to +85°C)

AM27C64-55

AM27C64-70

AM27C64-90
AM27C64-120
AM27C64-150
AM27C64-200
AM27C64-255

Valid Combinations

JC, PC, JI, PI

DEVICE NUMBER/DES CR IP TIO N

Am27C64
64 Kilobit (8 K x 8-Bit) CMOS OTP EPROM

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

4 Am27C64

FUNCTIONAL DESCRIPTION
Device Erasure

In order to clear all locations of their programmed con­tents, the device m ust be exp osed to an ultra violet light
source. A dosage of 15 W seconds/cm

2

is required to

completely erase the device. This dosage can be ob-

tained by exposure to an ultraviolet lamp—wavelength
of 2537 Å—with intensity of 12,000 µW/cm

2

for 15 to 20
minutes. The device shoul d be directly under and about
one inch from the source, and all filters should be re­moved from the UV light source prior to erasure.

Note that all UV erasable devices will erase with light
sources having wav elengths shorter than 4000 Å, such
as fluorescent light and sunlight. Although the erasure
process happens over a much longer time period, ex­posure to any light source should be prevented fo r
maximum system reliability. Simply cover the package
window with an opaque label or substance.

Device Programming

Upon delivery, or after each er asure, the devic e has all
of its bits in the “ONE”, or HIGH state. “ZEROs” are
loaded into the device through the programming pro­cedure.

The device enters the programming mode when 12.75
V ± 0.25 V is applied to the V
PGM# are at V

.

IL

pin, and CE# and

PP

For program ming, the data to be programmed is ap­plied 8 bits in parallel to the data pins.

The flowchart in the Programming section of the
EPROM Products Data Book (Section 5, Figure 5-1)
shows AMD’s Flashrite algorithm. The F lashrite algo­rithm reduces programming time by using a 100 µs pro­gramming pulse and by giving each address only as
many pulses to reliably program the data. After each
pulse is applied to a given address, the data in that ad­dress is verified. If the data does not verify, additional
pulses are given until it verifies or the maximum pulses
allowed is reached. This process i s repeated while se­quencing through each address of the device. This part
of the algorithm is done at V

= 6.25 V to assure that

CC

each EPROM bit is programmed to a sufficiently high
threshold voltage. After the final address is completed,
the entire EPROM memory is verified at V

= VPP =

CC

5.25 V.
Please refer to Section 5 of the EPR OM Products Data

Book for additional programming inf ormation and spec­ifications.

Program Inhibit

Programming different data to multiple devices in par­allel is easily accomplished. Except for CE#, all like in­puts of the devices may be c ommon. A TTL low-level
program pulse applied to one device’s CE# input with

V

= 12.75 V ± 0.25 V and PGM# LOW will program

PP

that particular device. A high-level CE# input inhibits
the other devices from being programmed.

Program Verify

A verification should be performed on the programmed
bits to determine that they were correctly progr ammed.
The verify should be perfor med with OE# and CE#, at

, PGM# at VIH, and VPP between 12.5 V and 13.0 V.

V

IL

Autoselect Mode

The autosel ect mode provides ma nufacturer and de­vice identification through iden tifier codes on DQ0–
DQ7. This mode is primarily intended for programming
equipment to automatically match a device to be pro­grammed with its correspo nding programming algo­rithm. This mode is functional in the 25°C ± 5°C
ambient temperature range that is required when pro­gramming the device.

To activate this mode, the programming equipment
must force V

on address line A9. Two identifier bytes

H

may then be sequenced from the de vice outputs b y tog­gling address line A0 from V

to V

IL

(that is, changing

IH

the address from 00h to 01h). All other address lines
must be held at V

during the autoselect mode.

IL

Byte 0 (A0 = VIL) represents the manufacturer code,
and Byte 1 (A0 = V

), the device identifier code. Both

IH

codes have odd parity, with DQ7 as the parity bit.

Read Mode

T o obtain dat a at the device o utputs, Chip Enable ( CE#)
and Output Enable (OE#) must be driven lo w . CE# con­trols the power to the de vice and is typically used t o se­lect the device . OE# ena b l es the device to output data,
independent of device selection. Addresses must be
stable for at least t

ACC–tOE.

Refer to the Switching

Waveforms section for the timing diagram.

Standby Mode

The device enters the CMOS standby mode when CE#
is at V

± 0.3 V. Maximum V

CC

current is reduced to

CC

100 µA. The device enters the TTL-standby mode
when CE# is at V

. Maximum V

IH

current is reduced

CC

to 1.0 mA. When in either standby mode, the device
places its outputs in a high-impedance state, indepen­dent of the OE# input.

Output OR-Tieing

To accommodate multiple memor y connections, a
two-line control function provides:

■ Low memory power dissipation, and

■ Assurance that output b us content ion will not occ ur .

CE# should be decoded and used as the primary de­vice-selecting function, while OE# be made a common

Am27C64 5

connection to all devices in the array and connected to
the READ line from the system control bus. This as­sures that all deselected memory devices are in their
low-power standby mode and that the output pins are
only active when data is desired from a particular mem­ory device.

System Applications

During the switch between a ctive and standby condi­tions, transient current peaks are produced on the ris­ing and falling edges of Chip Enab le. The magnitude of

MODE SELECT TABLE

these transient current peaks is dependent on the out­put capacitance loading of the de vi ce. At a minim um, a

0.1 µF ceramic capacitor (high frequency, low inherent
inductance) sho uld be used on each device between

and VSS to minimize transient effects. In addition,

V

CC

to overcome the voltage drop caused by the inductive
effects of the printed circuit boar d traces on EPROM ar­rays, a 4.7 µF bul k electrolytic capacitor should be used
between V

and VSS for each eight de vices. The loca-

CC

tion of the capacitor should be close to where the
power supply is connected to the array.

Mode CE# OE # PGM# A0 A9 V

Read V

IL

Output Disable X V
Standby (TTL) V
Standby (CMOS) V
Program V
Program Verify V
Program Inhibit V

Autoselect
(Note 3)

Manufacturer Code V
Device Code V

IH

± 0.3 V X X X X X High Z

CC

IL

IL

IH

IL

IL

V

IL

IH

X X X X X High Z

XVILXXVPPD

V

IL

XXXXVPPHigh Z

V

IL

V

IL

XXXXD
X X X X High Z

V

IH

XVILV
XVIHV

XXVPPD

H

H

Notes:

1. V

= 12.0 V ± 0.5 V.

H

2. X = Either V

3. A1–A8 and A10–12 = V

4. See DC Programming Characteristics for V

or VIL.

IH

.

IL

voltage during programming.

PP

Outputs

PP

OUT

IN

OUT

X01h
X15h

6 Am27C64

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

OTP Products. . . . . . . . . . . . . . . . . . –65°C to +125°C

All Other Products . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to V
All pins except A9, VPP, VCC . . –0.6 V to VCC + 0.6 V

A9 and VPP (Note 2) . . . . . . . . . . . . .–0.6 V to 13.5 V

(Note 1). . . . . . . . . . . . . . . . . . . . .–0.6 V to 7.0 V

V

CC

Notes:

1. Minimum DC voltage on inpu t or I/O pins – 0.5 V. D uring

voltage transitions, the input may overshoot V
for periods of up to 20 ns. Max imum DC voltage o n inp ut
and I/O pins is V
and I/O pins may overshoot to V
to 20ns.

2. Minimum DC input voltage on A9 is –0.5 V . During voltage

transitions, A9 and V
periods of up to 20 ns. A9 and V
V at any time.

Stresses above those listed under “Abso lute Maximum Rat­ings” may cause per mane nt dam age to the device. This is a
stress rating only; fun ctio nal ope ration of t he d evice at these
or any other condition s above those indicated in the opera­tional sections of this specification is not implied. Exposure of
the device to absolute maximum ratings for extended periods
may affect device reliability.

CC

SS

to –2.0 V

SS

+ 5 V . During voltage transitions, input

+ 2.0 V for periods up

CC

may overshoot V

PP

PP

must not exceed+13.5

to –2.0 V for

SS

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

Industrial (I) Devices

Ambient Temperature (T

Extended (E) Devices

Ambient Temperature (T

Supply Read Voltages

for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V

V

CC

for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V

V

CC

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

) . . . . . . . . . . .0°C to +70°C

A

) . . . . . . . . .–40°C to +85°C

A

) . . . . . . . .–55°C to +125°C

A

Am27C64 7

DC CHARACTERISTICS over operating range (unless otherwise specified)

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

V

OH

V

OL

V

IH

V

IL

I

LI

Output HIGH Voltage IOH = –400 µA 2.4 V

Output LOW Voltage IOL = 2.1 mA 0.45 V
Input HIGH Voltage 2.0 VCC + 0.5 V
Input LOW Voltage –0.5 +0.8 V
Input Load Current VIN = 0 V to V

CC

1.0 µA

C/I Devices 1.0

I

I

CC1

I

CC2

I

CC3

I

PP1

LO

Output Leakage Current V

VCC Active Current (Note 2) CE# = VIL, f = 10 MHz,

VCC TTL Standby Current CE# = V
VCC CMOS Standby Current CE# = VCC ± 0.3 V 100 µA
VPP Supply Current (Read) CE# = OE# = VIL, VPP = V

I

OUT

OUT

= 0 V to V

= 0 mA

IH

CC

E Devices 5.0

CC

25 mA

1.0 mA

100 µA

Caution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied.
Notes:

must be applied simultaneously or before VPP, and removed simultaneously or after VPP..

1. V

CC

is tested with OE# = V

2. I

CC1

to simulate open outputs.

IH

3. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.

Maximum DC Voltage on output pins is V

+ 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns.

CC

µA

30

25

20

in mA

Supply Current

15

10

12345678910

Frequency in MHz

11419E-5

Figure 1. Typical Supply Current vs. Frequency

= 5.5 V, T = 25°C

V

CC

30

25

20

in mA

15

Supply Current

10

–75 –50 –55 0 25 50 75 100 125 150

Temperature in °C

11419E-6

Figure 2. Typical Supply Current vs. Temperature

= 5.5 V, f = 10 MHz

V

CC

8 Am27C64

TEST CONDITIONS

Device

Under

Test

C

L

6.2 kΩ

Note:

Diodes are IN3064 or equivalents.

Figure 3. Test Setup

SWITCHING TEST WAVEFORM

3 V

1.5 V

0 V

Input Output

Test Points

5.0 V

2.7 kΩ

11419E-7

1.5 V

Table 1. Test Specifications

-45, -55,

Test Condition

-70

Output Load 1 TTL gate
Output Load Capacitance, C

(including jig capacitance)

L

30 100 pF

Input Rise and Fall Times ≤ 20 ns
Input Pulse Levels 0.0–3.0 0.45–2.4 V

Input timing measurement
reference levels

Output timing measurement
reference levels

2.4 V

0.45 V

2.0 V

0.8 V

Input

1.5 0.8, 2.0 V

1.5 0.8, 2.0 V

Test Points

All

others Unit

2.0 V

0.8 V
Output

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

Note: For CL = 100 pF.Note: For CL = 30 pF.

11419E-8

Steady

Changing from H to L

Changing from L to H

KS000010-PAL

Am27C64 9

AC CHARACTERISTICS

Parameter Symbols

Am27C64

Description Test Setup

t

AVQV

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

t

ACC

t

CE

t

OE

t

DF

(Note 2)

Address to Output Delay

Chip Enable to Output Delay OE# = VILMax 45 55 70 90 120 150 200 250 ns
Output Enable to Output

Delay
Chip Enable High or Output

Enable High to Output High Z,
Whichever Occurs First

CE#,
OE# = V

CE# = V

Max 45 55 70 90 120 150 200 250 ns

IL

Max3035404050505050ns

IL

Max2525252530303030ns

Output Hold Time from

t

AXQX

t

OH

Addresses, CE# or OE#,

Min00000000ns

Whichever Occurs First

Caution: Do not remove the device from (or insert it into) a socket or board that has VPP or V

Notes:

CC

1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.

2. This parameter is sampled and not 100% tested.

3. Switching characteristics are over operating range, unless otherwise specified.

4. See Figure 3 and Table 1 for test specifications.

SWITCHING WAVEFORMS

UnitJEDEC Standard -45 -55 -70 -90 -120 -150 -200 -255

applied.

2.4

Addresses

0.45

2.0

0.8

CE#

t

CE

OE#

t

ACC

(Note 1)

Output

High Z

Notes:

1. OE# may be delayed up to t

is specified from OE# or CE#, whichever occurs first.

2. t

DF

– tOE after the falling edge of the addresses without impact on t

ACC

PACKAGE CAPACITANCE

Parameter

Symbol

C

IN

C

OUT

Notes:

1. This parameter is only sampled and not 100% tested.
= +25°C, f = 1 MHz.

2. T

A

Parameter

Description Test Conditions

Input Capacitance VIN = 0 810610510pF
Output Capacitance V

= 0 1114 8 12 8 10pF

OUT

Addresses Valid

t

OE

2.0

0.8

tDF (Note 2)

t

OH

Valid Output

.

ACC

CDV028 PL 032 PD 028

High Z

11419E-9

UnitTyp Max Typ Max Typ Max

10 Am27C64

PHYSICAL DIMENSIONS*

CDV028—28-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches)

DATUM D

CENTER PLANE

INDEX AND

TERMINAL NO. 1

I.D. AREA

BASE PLANE

SEATING PLANE

.005 MIN

1

TOP VIEW

1.435

1.490

.045
.065

.014
.026

UV Lens

.100 BSC

.015
.060

.565
.605

.125
.200

CENTER PLANE

.160
.220

DATUM D

.700

MAX

105°

.300 BSC

.600
BSC

94°

.008
.018

SIDE VIEW

* For reference only. BSC is an ANSI standard for Basic Space Centering.

PD 028—28-Pin Plastic Dual In-Line Package (measured in inches)

1.440

1.480

.120
.160

28

.140
.225

Pin 1 I.D.

.045
.065

.090
.110

.005 MIN

.014
.022

15

.530
.580

14

0°

10°

SEATING PLANE

.015
.060

END VIEW

16-000038H-3
CDV028
DF10
3-30-95 ae

.600
.625

.008
.015

.630
.700

16-038-SB-AG
PD 028
DG75
7-13-95 ae

Am27C64 11

PHYSICAL DIMENSIONS

PL 032—32-Pin Plastic Leaded Chip Carrier (measured in inches)

.485
.495

.009
.015

.125
.140

.080
.095

SEATING

PLANE

.013
.021

.050 REF.

SIDE VIEW

.585
.595

.447
.453

Pin 1 I.D.

.547
.553

.026
.032

TOP VIEW

.042
.056

.400

REF.

.490
.530

16-038FPO-5
PL 032
DA79
6-28-94 ae

REVISION SUMMARY FOR AM27C64
Revision E
Global

Changed formatting to match current data sheets.

Trademarks

Copyright © 1998 Advanced Micro D evices, Inc. All r ights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Flashrite is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

12 Am27C64