Datasheet AM27C4096-255DI, AM27C4096-255DCB, AM27C4096-255DC, AM27C4096-200PC, AM27C4096-200JI Datasheet (AMD Advanced Micro Devices)
...
FINAL
Am27C4096
4 Megabit (256 K x 16-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
■ Fast access time
— Speed options as fast as 90 ns
■ Low power consumption
— 100 µA maximum CMOS standby current
■ JEDEC-approved pinout
— Plug-in upgrade of 1 Mbit and 2 Mbit EPROMs
— 40-pin DIP/PDIP
— 44-pin PLCC
GENERAL DESCRIPTION
The Am27C4096 is a 4 Mbit, ultraviolet erasable programmable read-only memor y. It is organized as 256
Kwords, operates from a single +5 V supply, has a
static standby mode, and features fast single address
location programming. The Am27C4096 is ideal for use
in 16-bit microprocessor systems. The device is available in windowed ceramic DIP packages, and plastic
one time programmable (OTP) PDIP and PLCC packages.
Data can be typically accessed in less than 90 ns, allowing high-p erformance m icroproces sors to ope rate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
■ Single +5 V power supply
■ ±10% power supply tolerance standard
■ 100% Flashrite programming
— Typical programming time of 32 seconds
■ Latch-up protected to 100 mA from –1 V to
+ 1 V
V
CC
■ High noise immunity
thus eliminating bus contention in a mul tiple bus microprocessor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 125 mW in active mode,
and 125 µW in standby mode.
All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in
blocks, or at random. The devi ce supports AMD’s
Flashrite programming alg orithm (100 µs pulses), resulting in a typical programming time of 32 seconds.
BLOCK DIAGRAM
CE#/PGM#
A0–A17
Address
Inputs
OE#
V
CC
V
SS
V
PP
Output Enable
Chip Enable
and
Prog Logic
Y
Decoder
X
Decoder
Data Outputs
DQ0–DQ15
Output
Buffers
Y
Gating
4,194,304
Bit Cell
Matrix
Publication# 11408 Rev: F Amendment/0
Issue Date: May 1998
11408F-1
PRODUCT SELECTOR GUIDE
Family Part Number Am27C4096
= 5.0 V ± 5% -95 -105 -255
V
Speed Options
CC
= 5.0 V ± 10% -100 -120 -150 -200
V
CC
Max Access Time (ns) 90 100 120 150 200 250
CE# (E#) Access (ns) 90 100 120 150 200 250
OE# (G#) Access (ns) 50 50 50 65 75 75
CONNECTION DIAGRAMS
Top View
DIP PLCC
V
V
1
PP
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
V
SS
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CE# (E#)/PGM# (P#)
OE# (G#)
Notes:
1. JEDEC nomenclature is in parenthesis.
2. Don’t use (DU) for PLCC.
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CC
A17
A16
A15
A14
A13
A12
A11
A10
A9
V
SS
A8
A7
A6
A5
A4
A3
A2
A1
A0
11408F-2
DQ12
DQ11
DQ10
DQ9
DQ8
V
NC
DQ7
DQ6
DQ5
DQ4
DQ13
DQ14
DQ15
7
8
9
10
11
12
SS
13
14
15
16
17
DQ3
DQ2
DQ1
CE# (E#)/PGM# (P#)
VPPDU (Note 2)
VCCA17
A16
1 444342543264140
23 24 25 2619 20 21 2218 27 28
DQ0
A0A1A2A3A4
OE# (G#)
DU (Note 2)
A15
A14
39
38
37
36
35
34
33
32
31
30
29
11408F-3
A13
A12
A11
A10
A9
V
NC
A8
A7
A6
A5
SS
PIN DESIGNATIONS
LOGIC SYMBOL
A0–A17 = Address Inputs
CE# (E#)/ = Chip Enable Input/
PGM#/ (P#) Program Enable Input
DQ0–DQ15 = Data Input/Outputs
OE# (G#) = Output Enable Input
V
CC
V
PP
V
SS
=VCC Supply Voltage
= Program Voltage Input
= Ground
2 Am27C4096
18
A0–A17
16
DQ0–DQ15
CE# (E#)/PGM# (P#)
OE# (G#)
11408F-4
ORDERING INFORMATION
UV EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:
AM27C4096 -95 D C
DEVICE NUMBER/DESCRIPTION
Am27C4096
4 Megabit (256 K x 16-Bit) CMOS UV EPROM
B
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
TEMPERATURE RANGE
C = Commercial (0°C to +70
I=Industrial (–40
E = Extended (–55°C to +125°C)
PACKAGE TYPE
D = 40-Pin Ceramic DIP (CDV040)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
°C to +85°C)
°C)
AM27C4096-95
V
= 5.0 V ± 5%
CC
AM27C4096-100
AM27C4096-105
= 5.0 V ± 5%
V
CC
AM27C4096-120
AM27C4096-200
AM27C4096-255
= 5.0 V ± 5%
V
CC
Valid Combinations
DC, DCB, DI, DIB
DC, DCB, DE, DEB, DI, DIBAM27C4096-150
DC, DCB, DI, DIB
DC, DCB
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am27C4096 3
ORDERING INFORMATION
OTP EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:
AM27C4096 -105 P C
OPTIONAL PROCESSING
Blank = Standard Processing
TEMPERATURE RANGE
C = Commercial (0
I=Industrial (–40
PACKAGE TYPE
P = 40-Pin Plastic DIP (PD 040)
J = 44-Pin Plastic Leaded Chip Carrier (PL 044)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
°C to +70°C)
°C to +85°C)
AM27C4096-105
V
= 5.0 V ± 5%
CC
AM27C4096-120
AM27C4096-150
AM27C4096-200
AM27C4096-255
= 5.0 V ± 5%
V
CC
Valid Combinations
PC, PI, JC, JI
DEVICE NUMBER/DES CR IP TIO N
Am27C4096
4 Megabit (256 K x 16-Bit) CMOS OTP EPROM
Valid Combinations list configurations planned to be sup-
PC, JC
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Valid Combinations
4 Am27C4096
FUNCTIONAL DESCRIPTION
Device Erasure
In order to clear all locations of their programmed contents, the device m ust be exp osed to an ultra violet light
source. A dosage of 15 W seconds/cm
completely erase the device. This dosage can be ob-
tained by exposure to an ultraviolet lamp—wavelength
of 2537 Å—with intensity of 12,000 µW/cm
minutes. The device shoul d be directly under and about
one inch from the source, and all filters should be removed from the UV light source prior to erasure.
Note that all UV erasable devices will erase with light
sources having wav elengths shorter than 4000 Å, such
as fluorescent light and sunlight. Although the erasure
process happens over a much longer time period, exposure to any light source should be prevented for
maximum system reliability. Simply cover the package
window with an opaque label or substance.
2
is required to
2
for 15 to 20
CE#/PGM# input inhibits the other devices from being
programmed.
Program Verify
A verification should be performed on the programmed
bits to determine that they were correctly progr ammed.
The verify should be performed with OE# at V
PGM# at V
, and VPP between 12.5 V and 13.0 V.
IH
, CE#/
IL
Autoselect Mode
The autosel ect mode provides ma nufacturer and device identification through iden tifier codes on DQ0–
DQ7. This mode is primarily intended for programming
equipment to automatically match a device to be programmed with its correspo nding programming algorithm. This mode is functional in the 25°C ± 5°C
ambient temperature range that is required when programming the device.
Device Programming
Upon delivery, or after each erasure, the device has
all of its bits in t he “ONE”, or HIGH s tate . “ZER Os” are
loaded into the device through the programming procedure.
The device enters the programming mode when 12.75
V ± 0.25 V is applied to the V
and OE# is at VIH.
at V
IL
pin, and CE#/PGM# is
PP
For programming, the data to be programmed is applied 16 bits in parallel to the data pins.
The flowchart in the Programming section (Section 5,
Figure 5-1) shows AMD’s Flashrite algorithm. The
Flashrite algorithm reduces pro gramming time by using
a 100 µs programming pulse and by giving each address
only as many pulses to reliably program the data. After
each pulse is applied to a given address, the data in that
address is verified. If the data does not verify, additional
pulses are given until it verifies or the maximum pulses
allowed is reached. This process i s repeated while sequencing through each address of the device. This part
of the algorithm is done at V
= 6.25 V to assure that
CC
each EPROM bit is programmed to a sufficiently high
threshold voltage. After the final address is completed,
the entire EPROM memory is verified at V
= VPP =
CC
5.25 V.
Please refer to Section 5 f or additional progr amming in-
formation and specifications.
Program Inhibit
Programming different data to multiple devices in parallel is easily accomplished. Except for CE#/PGM#, all
like inputs of the devices may be common. A TTL
low-level program pulse applied to one device’s CE#/
PGM# input with V
HIGH will program that par ticular device. A high-level
= 12.75 V ± 0.25 V and OE#
PP
To activate this mode, the programming equipment
must force V
on address line A9. Two identifier bytes
H
may then be sequenced from the de vice outputs b y toggling address line A0 from V
IL
to V
(that is, changing
IH
the address from 00h to 01h). All other address lines
must be held at V
during the autoselect mode.
IL
Byte 0 (A0 = VIL) represents the manufacturer code,
and Byte 1 (A0 = V
), the device identifier code. Both
IH
codes have odd parity, with DQ7 as the parity bit.
Read Mode
T o obtain data at the de vice outputs , Chip Enable (CE#/
PGM#) and Output Enable (OE# ) must be driven low.
CE#/PGM# controls the power to the de vice and is typically used to select the device . OE# enables the de vice
to output data, independent of device selection. Addresses must be stable for at least t
ACC–tOE.
Refer to
the Switching Waveforms section for the tim ing diagram.
Standby Mode
The device enters the CMOS standby mode when
CE#/PGM# is at V
± 0.3 V. Maximum V
CC
current is
CC
reduced to 100 µA. The de vic e enters the TTL-standby
mode when CE#/PGM# is at V
. Maximum V
IH
CC
current is reduced to 1.0 mA. When in either standby
mode, the device places its outputs in a high-impe dance state, independent of the OE# input.
Output OR-Tieing
To accommodate multiple memor y connections, a
two-line control function provides:
■ low memory power dissipation, and
■ assurance that output bus contention will not occur .
CE#/PGM# should be decoded and used as the primary device-selecting function, while OE# be made a
Am27C4096 5
common connection to all devices in the arr a y and connected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.
System Applications
During the switch between a ctive and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enab le. The magnitude of
MODE SELECT TABLE
these transient current peaks is dependent on the output capacitance loading of the de vi ce. At a minim um, a
0.1 µF ceramic capacitor (high frequency, low inherent
inductance) sho uld be used on each device between
and VSS to minimize transient effects. In addition,
V
CC
to overcome the voltage drop caused by the inductive
effects of the printed circuit boar d traces on EPROM arrays, a 4.7 µF bul k electrolytic capacitor should be used
between V
and VSS for each eight de vices. The loca-
CC
tion of the capacitor should be close to where the
power supply is connected to the array.
Mode CE#/PGM# OE# A0 A9 V
Read V
Output Disable V
Standby (TTL) V
Standby (CMOS) V
CC
Program V
Program Verify V
Program Inhibit V
Autoselect
(Note 3)
Manufacturer Code V
Device Code V
IL
IL
IH
V
IL
V
IH
X X X X High Z
± 0.3 V X X X X High Z
IL
IH
IH
IL
IL
V
IH
V
IL
XX XVPPHigh Z
V
IL
V
IL
XX XD
X X X High Z
XXVPPD
XXVPPD
V
IL
V
IH
V
H
V
H
Notes:
1. V
= 12.0 V ± 0.5 V.
H
2. X = Either V
3. A1–A8 and A10–17 = V
4. See DC Programming Characteristics for V
or VIL.
IH
.
IL
voltage during programming.
PP
PP
Outputs
OUT
OUT
X 01h
X 19h
IN
6 Am27C4096
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
OTP Products. . . . . . . . . . . . . . . . . . –65°C to +125°C
All Other Products . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Voltage with Respect to V
All pins except A9, VPP, VCC . . –0.6 V to VCC + 0.6 V
A9 and VPP (Note 2) . . . . . . . . . . . . .–0.6 V to 13.5 V
(Note 1). . . . . . . . . . . . . . . . . . . . .–0.6 V to 7.0 V
V
CC
Notes:
1. Minimum DC voltage on inpu t or I/O pins – 0.5 V. D uring
voltage transitions, the input may overshoot V
for periods of up to 20 ns. Max imum DC voltage o n inp ut
and I/O pins is V
and I/O pins may overshoot to V
to 20 ns.
2. Minimum DC input voltage on A9 is –0.5 V . During voltage
transitions, A9 and V
periods of up to 20 ns. A9 and V
V at any time.
Stresses above those listed under “Abso lute Maximum Ratings” may cause per mane nt dam age to the device. This is a
stress rating only; fun ctio nal ope ration of t he d evice at these
or any other condition s above those indicated in the operational sections of this specification is not implied. Exposure of
the device to absolute maximum ratings for extended periods
may affect device reliability.
CC
SS
to –2.0 V
SS
+ 5 V . During voltage transitions, input
+ 2.0 V for periods up
CC
may overshoot V
PP
PP
must not exceed+13.5
to –2.0 V for
SS
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T
Industrial (I) Devices
Ambient Temperature (T
Extended (E) Devices
Ambient Temperature (T
Supply Read Voltages
for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V
V
CC
for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V
V
CC
Operating ranges define those limits between which the functionality of the device is guaranteed.
) . . . . . . . . . . .0°C to +70°C
A
) . . . . . . . . .–40°C to +85°C
A
) . . . . . . . .–55°C to +125°C
A
Am27C4096 7
DC CHARACTERISTICS over operating range (unless otherwise specified)
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
V
V
V
V
I
I
I
CC1
I
CC2
I
CC3
I
PP1
OH
OL
IH
IL
LI
LO
Output HIGH Voltage IOH = –400 µA 2.4 V
Output LOW Voltage IOL = 2.1 mA 0.45 V
Input HIGH Voltage 2.0 VCC + 0.5 V
Input LOW Voltage –0.5 +0.8 V
Input Load Current VIN = 0 V to V
Output Leakage Current V
VCC Active Current (Note 2)
VCC TTL Standby Current CE# = V
= 0 V to V
OUT
CE# = V
I
= 0 mA
OUT
, f = 5 MHz,
IL
IH
CC
CC
C/I Devices 50
E Devices 60
1.0 µA
5.0 µA
1.0 mA
VCC CMOS Standby Current CE# = VCC ± 0.3 V 100 µA
VPP Supply Current (Read) CE# = OE# = VIL, VPP = V
CC
100 µA
Caution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied.
Notes:
must be applied simultaneously or before VPP, and removed simultaneously or after VPP..
1. V
CC
is tested with OE# = V
2. I
CC1
to simulate open outputs.
IH
3. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.
Maximum DC Voltage on output pins is V
+ 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns.
CC
mA
35
30
25
in mA
Supply Current
20
15
12345678910
Frequency in MHz
11408F-5
Figure 1. Typical Supply Current vs. Frequency
= 5.5 V, T = 25°C
V
CC
35
30
25
in mA
20
Supply Current
15
–75 –50 –55 0 25 50 75 100 125 150
Temperature in °C
11408F-6
Figure 2. Typical Supply Current vs. Temperature
= 5.5 V, f = 5 MHz
V
CC
8 Am27C4096
TEST CONDITIONS
Device
Under
Test
C
L
6.2 kΩ
Note:
Diodes are IN3064 or equivalents.
Figure 3. Test Setup
SWITCHING TEST WAVEFORM
2.4 V
0.45 V
2.0 V
Test Points
0.8 V
Input
2.0 V
0.8 V
5.0 V
Output
2.7 kΩ
11408F-7
Table 1. Test Specifications
Test Condition All Unit
Output Load 1 TTL gate
Output Load Capacitance, C
(including jig capacitance)
Input Rise and Fall Times ≤ 20 ns
Input Pulse Levels 0.45–2.4 V
Input timing measurement reference
levels
Output timing measurement
reference levels
L
100 pF
0.8, 2.0 V
0.8, 2.0 V
Note: For CL = 100 pF.
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
11408F-8
Steady
Changing from H to L
Changing from L to H
KS000010-PAL
Am27C4096 9
AC CHARACTERISTICS
Parameter Symbols
Am27C4096
Description Test Setup
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
ACC
t
CE
t
OE
t
DF
(Note 2)
Address to Output Delay
Chip Enable to Output Delay OE# = VILMax 90 100 120 150 200 250 ns
Output Enable to Output Delay CE# = VILMax505050657575ns
Chip Enable High or Output Enable
High to Output High Z, Whichever
Occurs First
CE#,
OE# = V
Max 90 100 120 150 200 250 ns
IL
Max303040404060ns
Output Hold Time from Addresses,
t
AXQX
t
OH
CE# or OE#, Whichever Occurs
Min000000ns
First
Caution: Do not remove the device from (or insert it into) a socket or board that has VPP or V
Notes:
CC
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
2. This parameter is sampled and not 100% tested.
3. Switching characteristics are over operating range, unless otherwise specified.
4. See Figure 3 and Table 1 for test specifications.
SWITCHING WAVEFORMS
2.4
Addresses
0.45
2.0
0.8
Addresses Valid
2.0
0.8
UnitJEDEC Standard -95 -105 -120 -150 -200 -255
applied.
CE#/PGM#
t
CE
OE#
t
ACC
(Note 1)
Output
High Z
Notes:
1. OE# may be delayed up to t
is specified from OE# or CE#, whichever occurs first.
2. t
DF
– tOE after the falling edge of the addresses without impact on t
ACC
PACKAGE CAPACITANCE
Parameter
Symbol
C
IN
C
OUT
Notes:
1. This parameter is only sampled and not 100% tested.
= +25°C, f = 1 MHz.
2. T
A
Parameter
Description Test Conditions
Input Capacitance VIN = 0 10 13 6 8 10 13 pF
Output Capacitance V
= 0 10 13 8 10 1 2 14 pF
OUT
t
OE
Valid Output
t
OH
ACC
High Z
11408F-9
.
CDV040 PD 040 PL 044
UnitTyp Max Typ Max Typ Max
tDF (Note 2)
10 Am27C4096
PHYSICAL DIMENSIONS*
CDV040—40-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches)
DATUM D
CENTER PLANE
INDEX AND
TERMINAL NO. 1
I.D. AREA
BASE PLANE
SEATING PLANE
.005 MIN
1
TOP VIEW
2.035
2.080
.045
.065
.014
.026
UV Lens
.100 BSC
.015
.060
.565
.605
.125
.200
CENTER PLANE
.160
.220
DATUM D
.700
MAX
105°
.300 BSC
.600
BSC
94°
.008
.018
SIDE VIEW
* For reference only. BSC is an ANSI standard for Basic Space Centering.
PD 040—40-Pin Plastic Dual In-Line Package (measured in inches)
2.040
2.080
40
.140
.225
Pin 1 I.D.
.045
.065
.005 MIN
21
.530
.580
20
0°
10°
END VIEW
16-000038H-3
CDV040
DF11
3-30-95 ae
.600
.625
.008
.015
.630
.700
.120
.160
.090
.110
.014
.022
SEATING PLANE
.015
.060
16-038-SC_AF
PD 040
DG76
2-28-95 ae
Am27C4096 11
PHYSICAL DIMENSIONS
PL 044—44-Pin Plastic Leaded Chip Carrier (measured in inches)
.062
.685
.695
.650
.656
.042
.056
.083
.685
.695
.650
.656
.026
.032
Pin 1 I.D.
.050 REF
TOP VIEW
REVISION SUMMARY FOR AM27C4096
Revision F
Global
Changed formatting to match current data sheets.
.009
.015
.090
.120
.165
.180
SIDE VIEW
.590
.500
.630
REF
.013
.021
SEATING PLANE
16-038-SQ
PL 044
EC80
11.3.97 lv
Trademarks
Copyright © 1998 Advanced Micro D evices, Inc. All r ights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Flashrite is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
12 Am27C4096
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