FINAL
Publication# 06780 Rev: J Amendment/0
Issue Date: May 1998
Am27C1024
1 Megabit (65 K x 16-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
■ Fast access time
— Speed options as fast as 55 ns
■ Low power consumption
— 20 µA typical CMOS standby current
■ JEDEC-approved pinout
— 40-Pin DIP/PDIP
— 44-Pin PLCC
■ Single +5 V power supply
■ ±10% power supply tolerance standard
■ 100% Flashrite™ programming
— Typical programming time of 8 seconds
■ Latch-up protected to 100 mA from –1 V to
V
CC
+ 1 V
■ High noise immunity
■ Versatile features for simple interfacing
— Both CMOS and TTL input/output compatibility
— Two line control functions
GENERAL DESCRIPTION
The Am27C1024 is a 1 Megabit, ultraviolet erasable
programmable read-only memory. It is orga nize d as 64
Kwords by 16 bits per word, operates fro m a single
+5 V supply, has a static standby mode, and features
fast single address location programming. Products are
available in windowed ceramic DIP packages, as well
as plastic one time programmable (OTP) PDIP and
PLCC packages.
Data can be typically accessed in less than 55 ns, allowing high-p erformance m icroproces sors to ope rate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
thus eliminating bus contention in a mul tiple bus microprocessor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 125 mW in active mode,
and 100 µW in standby mode.
All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming alg orithm (100 µs pulses), resulting in a typical programming time of 8 seconds.
BLOCK DIAGRAM
06780J-1
A0–A15
Address
Inputs
PGM#
CE#
OE#
V
CC
V
SS
V
PP
Data Outputs
DQ0–DQ15
Output
Buffers
Y
Gating
1,048,576
Bit Cell
Matrix
X
Decoder
Y
Decoder
Output Enable
Chip Enable
and
Prog Logic