Datasheet AM27C040-200PC, AM27C040-200JI, AM27C040-200JC, AM27C040-200DIB, AM27C040-200DI Datasheet (AMD Advanced Micro Devices)
...
FINAL
Am27C040
4 Megabit (512 K x 8-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
■ Fast access time
— Available in speed options as fast as 90 ns
■ Low power consumption
— <10 µA typical CMOS standby current
■ JEDEC-approved pinout
— Plug-in upgrade for 1 Mbit and 2 Mbit EPROMs
— Easy upgrade from 28-pin JEDEC EPROMs
GENERAL DESCRIPTION
The Am27C040 is a 4 Mbit ultraviolet erasable programmable read-only memory. It is organized as 512K
bytes, operates from a single +5 V supply, has a static
standby mode, and features fast single address location programming. The device is available in windowed
ceramic DIP packages and plastic one-time programmable (OTP) packages.
Data can be typically accessed in less than 90 ns, allowing high-p erformance m icroproces sors to ope rate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
■ Single +5 V power supply
■ ±10% power supply tolerance standard
■ 100% Flashrite™ programming
— Typical programming time of 1 minute
■ Latch-up protected to 100 mA from –1 V to
+ 1 V
V
CC
■ High noise immunity
■ Compact 32-pin DIP, PDIP, PLCC packages
thus eliminating bus contention in a mul tiple bus microprocessor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 100 mW in active mode,
and 50 µW in standby mode.
All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 µs pulses) resulting in typical programming time of 1 minute.
BLOCK DIAGRAM
OE#
CE#/PGM#
A0–A18
Address
Inputs
V
CC
V
SS
V
PP
Output Enable
Chip Enable
and
Prog Logic
Y
Decoder
X
Decoder
Data Outputs
DQ0–DQ7
Output
Buffers
Y
Gating
4,194,304-Bit
Cell Matrix
Publication# 14971 Rev: G Amendment/0
Issue Date: May 1998
14971G-1
FINAL
PRODUCT SELECTOR GUIDE
Family Part Number Am27C040
Speed Options (V
= 5.0 V ± 10%) -90 -120 -150 -200
CC
Max Access Time (ns) 90 120 150 200
CE# (E#) Access (ns) 90 120 150 200
OE# (G#) Access (ns) 40 50 65 75
CONNECTION DIAGRAMS
Top View
DIP PLCC
32
V
PP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
CC
31
A18
30
A17
29
A14
28
A13
27
A8
26
A9
25
A11
24
OE# (G#)
23
A10
22
CE# (E#)/PGM# (P#)
21
DQ7
DQ6
20
19
DQ5
18
DQ4
17
DQ3
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
A12
DQ1
A15
DQ2
A16
VPPVCCA18
1
17 18 19 20161514
SS
V
DQ3
A17
31 3023432
DQ4
DQ5
DQ6
29
A14
28
A13
27
A8
26
A9
25
A11
24
OE# (G#)
23
A10
22
CE# (E#)/PGM# (P#)
21
DQ7
14971G-3
14971G-2
Notes:
1. JEDEC nomenclature is in parenthesis.
2. The 32-pin DIP to 32-pin PLCC configuration varies from the JEDEC 28-pin DIP to 32-pin PLCC configuration.
PIN DESIGNATIONS
LOGIC SYMBOL
A0–A18 = Address Inputs
CE# (E#)/PGM# (P#)= Chip Enable/Program Enable Input
DQ0–DQ7 = Data Inputs/Outputs
OE# (G#) = Output Enable Input
V
CC
V
PP
V
SS
=VCC Supply Voltage
= Program Voltage Input
= GroundLogic Symbol
19
A0–A18
DQ0–DQ7
CE# (E#)/PGM#(P#)
OE# (G#)
2 Am27C040
8
14971E-4
FINAL
ORDERING INFORMATION
UV EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:
AM27C040 -90 D C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
TEMPERATURE RANGE
C = Commercial (0
I=Industrial (–40
E = Extended (–55°C to +125°C)
PACKAGE TYPE
D = 32-Pin Ceramic DIP (CDV032)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
°C to +70°C)
°C to +85°C)
AM27C040-90
AM27C040-120
AM27C040-150
AM27C040-200
DEVICE NUMBER/DESCRIPTION
Am27C040
4 Megabit (512K x 8-Bit) CMOS UV EPROM
Valid Combinations
DC, DCB, DI, DIB, DE, DEB
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am27C040 3
FINAL
ORDERING INFORMATION
OTP EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:
AM27C040 -90 J C
OPTIONAL PROCESSING
Blank = Standard Processing
TEMPERATURE RANGE
C = Commercial (0
I=Industrial (–40
E = Extended (–55
PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
°C to +70°C)
°C to +85°C)
°C to 125°C)
AM27C040-90
AM27C040-120
AM27C040-150
AM27C040-200
Valid Combinations
PC, PI, JC, JI
DEVICE NUMBER/DES CR IP TIO N
Am27C040
4 Megabit (512K x 8-Bit) CMOS OTP EPROM
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
4 Am27C040
FINAL
FUNCTIONAL DESCRIPTION
Device Erasure
In order to clear all locations of their programmed
contents, the device must be exposed to an ultraviolet
light source. A dosage of 15 W seconds/cm
to completely erase the device. This dosage can be ob-
tained by exposure to an ultraviolet lamp — wavelength
of 2537 Å — with intensity of 12,000 µW/cm
minutes. The device should be directly under and about
one inch from the source an d all filters should be removed from the UV light source prior to erasure.
Note that all UV erasable devices will erase with light
sources having wav elengths shorter than 4000 Å, such
as fluorescent light and sunlight. Although the erasure
process happens over a much longer time period, exposure to any light source should be prevented for
maximum system reliability. Simply cover the package
window with an opaque label or substance.
2
is required
2
for 15 to 20
that particular device. A high-level CE#/PGM# input inhibits the other dev ices from being programmed.
Program Verify
A verification should be performed on the programmed
bits to determine that they were correctly progr ammed.
The verify should be performed with OE# at V
PGM# at V
, and VPP between 12.5 V and 13.0 V.
IH
, CE#/
IL
Auto Select Mode
The autosel ect mode provides ma nufacturer and device identification through iden tifier codes on DQ0–
DQ7. This mode is primarily intended for programming
equipment to automatically match a device to be programmed with its correspo nding programming algorithm. This mode is functional in the 25°C ± 5°C
ambient temperature range that is required when programming the device.
Device Programming
Upon delivery, or after each erasure, the device has
all of its bits in t he “ONE”, or HIGH s tate . “ZER Os” are
loaded into the device through the programming procedure.
The programming mode is entered when 12.75 V ±
0.25 V is applied to the V
pin, CE#/PGM# is at V
PP
and OE# is at VIH .
For programming, the data to be programmed is ap-
plied 8 bits in parallel to the data output pins.
The flowchart in the EPROM Products Data Book, Pro-
gramming section (Section 5, Figure 5-1) shows AMD’s
Flashrite algorithm. The Flashrite algorithm reduces programming time by using a 100 µs programming pulse
and by giving each address only as many pulses to reliably program the data. After each pulse is applied to a
given address, the data in that address is verified. If the
data does not verify, additional pulses are given until it
verifies or the maximum pulses allowed is reached. This
process is repeated while sequencing through each address of the device. This part of the algorithm is done at
= 6.25 V to assure that each EPROM bit is pro-
V
CC
grammed to a suffici ently high thresh old voltage. After
the final address is completed, the entire EPROM memory is verified at V
= VPP = 5.25 V.
CC
Please refer to the EPROM Products Data Book, Section 5 for the programming flow chart and characteristics.
Program Inhibit
Programming different data to multiple devices in parallel is easily accomplished. Except for CE#/PGM#, all
like inputs of the devices may be common. A TTL
low-level program pulse applied to one device’s CE#/
PGM# input with V
= 12.75 V ± 0.25 V will program
PP
To activate this mode, the programming equipment
must force V
on address line A9. Two identifier bytes
H
may then be sequenced from the de vice outputs b y toggling address line A0 from V
IL
to V
(that is, changing
IH
the address from 00h to 01h). All other address lines
must be held at V
during the autoselect mode.
IL
Byte 0 (A0 = VIL) represents the manufacturer code,
IL
and Byte 1 (A0 = V
), the device identifier code. Both
IH
codes have odd parity, with DQ7 as the parity bit.
Read Mode
T o obtain data at the de vice outputs , Chip Enable (CE#/
PGM#) and Output Enable (OE#) must be driven low.
CE#/PGM# controls the power to the de vice and is typically used to select the device . OE# enables the de vice
to output data, independent of device selection. Addresses must be stable for at least t
ACC–tOE.
Refer to
the Switching Waveforms section for the tim ing diagram.
Standby Mode
The device enters the CMOS standby mode when
CE#/PGM# is at V
± 0.3 V. Maximum V
CC
current is
CC
reduced to 100 µA. The de vic e enters the TTL-standby
mode when CE#/PGM# is at V
. Maximum V
IH
CC
current is reduced to 1.0 mA. When in either standby
mode, the device places its outputs in a high-impe dance state, independent of the OE# input.
Output OR-Tieing
To accommodate multiple memor y connections, a
two-line control function is provided to allow for:
■ Low memory power dissipation, and
■ Assurance that output bus contention will not occur
CE#/PGM# should be decoded and used as the primary device-selecting function, while OE# be made a
Am27C040 5
FINAL
common connection to all devices in the arr a y and connected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.
System Applications
During the switch between a ctive and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enab le. The magnitude of
these transient current peaks is dependent on the output capacitance loading of the de vi ce. At a minim um, a
0.1 µF ceramic capacitor (high frequency, low inherent
inductance) sho uld be used on each device between
and VSS to minimize transient effects. In addition,
V
CC
to overcome the voltage drop caused by the inductive
effects of the printed circuit boar d traces on EPROM arrays, a 4.7 µF bul k electrolytic capacitor should be used
between V
and VSS for each eight de vices. The loca-
CC
tion of the capacitor should be close to where the
power supply is connected to the array.
MODE SELECT TABLE
Mode CE#/PGM# OE# A0 A9 V
Read V
Output Disable V
Standby (TTL) V
Standby (CMOS) V
CC
Program V
Program Verify V
Program Inhibit V
Auto Select
(Note 3)
Manufacturer Code V
Device Code V
IL
IL
IH
V
IL
V
IH
X X X X HIGH Z
+ 0.3 V X X X X HIGH Z
IL
IL
IH
IL
IL
V
IH
V
IL
XXXVPPHIGH Z
V
IL
V
IL
XXXD
X X X HIGH Z
XXVPPD
XXVPPD
V
IL
V
IH
V
H
V
H
PP
Outputs
OUT
OUT
X 01h
X 9Bh
IN
Note:
1. V
= 12.0 V ± 0.5 V.
H
2. X = Either V
3. A1 – A8 = A10 – A18 = V
IH
or V
IL
IL
4. See DC Programming Characteristics in the EPROM Products Data Book for V
voltage during programming
PP
6 Am27C040
FINAL
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
OTP Products. . . . . . . . . . . . . . . . –65°C to +125°C
All Other Products. . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . .–55°C to + 125°C
Voltage with Respect to V
All pins except A9, VPP,
(Note 1) . . . . . . . . . . . . . . –0.6 V to VCC +0.5 V
V
CC
A9 and VPP (Note 2) . . . . . . . . . . . .–0.6 V to +13.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .–0.6 V to +7.0 V
V
CC
1. During voltage transitions, inputs may overshoot VSS to –
2.0 V for periods of up to 20 ns. Maximum DC voltage on
input and I/O pins may overshoot to V
periods up to 20ns.
2. During voltage transitions, A9 a nd V
V
to –2.0 V for periods of up to 20 ns. A9 and VPP must
SS
not exceed +13.5 V at any time.
Stresses above thos e listed under “Ab solute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute m axi mum ratin g co ndi tions for
extended periods may affect device reliability.
SS
+ 2.0 V for
CC
may overshoot
PP
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T
Industrial (I) Devices
Ambient Temperature (T
Extended (E) Devices
Ambient Temperature (T
Supply Read Voltages
for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V
V
CC
for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V
V
CC
Operating ranges define those limits between which the
functionality of the device is guaranteed.
) . . . . . . . . . . .0°C to +70°C
A
) . . . . . . . . .–40°C to +85°C
A
) . . . . . . . .–55°C to +125°C
A
Am27C040 7
FINAL
DC CHARACTERISTICS over operating ranges unless otherwise specified
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
V
V
V
V
I
I
CC1
I
CC2
I
CC3
I
PP1
OH
OL
I
LO
IH
IL
LI
Output HIGH Voltage IOH = –400 µA 2.4 V
Output LOW Voltage IOL = 2.1 mA 0.45 V
Input HIGH Voltage 2.0 VCC + 0.5 V
Input LOW Voltage –0.5 +0.8 V
Input Load Current VIN = 0 V to V
CC
C/I Devices 1.0
µA
E Devices 5.0
Output Leakage Current V
VCC Active Current (Note 3)
VCC TTL Standby Current CE# = V
VCC CMOS Standby
Current
VPP Current During Read
= 0 V to V
OUT
CE# = V
= 0 MA
I
OUT
CC
, f = 10 MHz,
IL
IH
C/I Devices 40
E Devices 60
5.0 µA
mA
1.0 mA
CE# = VCC ± 0.3 V 100 µA
CE# = OE# = V
= V
CC
, VPP
IL
100 µA
Caution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied.
Notes:
must be applied simultaneously or before V
1. V
CC
2. I
is tested with OE# = V
CC1
to simulate open outputs.
IH
and removed simultaneously or after V
PP
PP
3. Minimum DC Input Voltage is –0.5. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns. Maxi-
mum DC Voltage on output pins is Vcc +0.5 V, which may overshoot to V
+2.0 V for periods less than 20 ns.
CC
25
20
15
in mA
Supply Current
10
5
1610
2345 78 9
Frequency in MHz
Figure 1. Typical Supply Current vs. Frequency
= 5.5 V, T = 25°C
V
CC
14971E-1
25
20
15
in mA
10
Supply Current
5
–75 50 150
–50 –25 0 25 75 100 125
Temperature in °C
Figure 2. Typical Supply Current vs. T emper ature
= 5.5 V, f = 10 MHz
V
CC
14971E-1
8 Am27C040
TEST CONDITIONS
FINAL
Device
Under
Test
C
L
6.2 kΩ
Note:
Diodes are IN3064 or equivalents.
Figure 1. Test Setup
SWITCHING TEST WAVEFORM
3 V
1.5 V
0 V
Input Output
Test Points
5.0 V
2.7 kΩ
14971G-5
1.5 V
Table 1. Test Specifications
Test Condition All Unit
Output Load 1 TTL gate
Output Load Capacitance, C
(including jig capacitance)
Input Rise and Fall Times ≤ 20 ns
Input Pulse Levels 0.45–2.4 V
Input timing measurement reference
levels
Output timing measurement
reference levels
2.4 V
0.45 V
Input
2.0 V
L
Test Points
100 pF
0.8, 2.0 V
0.8, 2.0 V
2.0 V
0.8 V0.8 V
Output
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
Note: For CL = 100 pF.Note: For CL = 30 pF.
14971G-6
Steady
Changing from H to L
Changing from L to H
KS000010-PAL
Am27C040 9
AC CHARACTERISTICS
FINAL
Parameter Symbols
Description Test Setup
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
t
ACC
t
CE
t
OE
t
DF
(Note 2)
t
OH
Address to Output Delay
Chip Enable to Output Delay OE# = VILMax 90 120 150 200 ns
Output Enable to Output Delay CE# = VILMax40506575ns
Chip Enable High or Output Enable High,
Whichever Occurs First, to Output High Z
Output Hold Time from Addresses, CE# or
OE#, Whichever Occurs First
CE# = OE#
= V
IL
Max 90 120 150 200 ns
Max30303040ns
Min0000ns
Caution: Do not remove the device from (or inserted into) a socket when VCC or VPP is applied.
Notes:
must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
1. V
CC
2. This parameter is sampled and not 100% tested.
3. Switching characteristics are over operating range, unless otherwise specified.
4. See Figure 1 and Table 1 for test specifications.
SWITCHING WAVEFORMS
2.4
Addresses
0.45
2.0
0.8
Addresses Valid
2.0
0.8
Am27C040
UnitJEDEC Std. -90 -120 -150 -200
CE#/PGM#
t
CE
OE#
t
OE
Output
High Z
t
ACC
(Note 1)
Note:
1. OE# may be delayed up to t
- tOE after the falling edge of the addresses without impact on t
ACC
2. tDF is specified from OE# or CE#, whichever occurs first.
PACKAGE CAPACITANCE
Parameter
Symbol
C
IN
C
OUT
Parameter
Description
Input Capacitance V
Output Capacitance V
Test
Conditions
= 0 V 10121012 8 10pF
IN
= 0 V 12151215 9 12pF
OUT
Notes:
1. This parameter is only sampled and not 100% tested.
= +25°C, f = 1 MHz.
2. T
A
CDV032 PD 032 PL 032
Valid Output
t
OH
t
DF
(Note 2)
High Z
ACC.
14971E-1
UnitTyp Max Typ Max Typ Max
10 Am27C040
FINAL
PHYSICAL DIMENSIONS
PD 032—32-Pin Plastic Dual In-Line Package (measured in inches)
.120
.160
32
.140
.225
Pin 1 I.D.
.045
.065
1.640
1.670
.090
.110
.005 MIN
.016
.022
17
16
.530
.580
.015
.060
SEATING PLANE
.600
.625
.009
.015
.630
.700
0°
10°
16-038-S_AG
PD 032
EC75
5-28-97 lv
PL 032—32-Pin Plastic Leaded Chip Carrier (measured in inches)
.485
.495
.009
.015
.125
.140
.080
.095
SEATING
PLANE
.013
.021
.050 REF.
SIDE VIEW
.585
.595
.447
.453
Pin 1 I.D.
.547
.553
.026
.032
TOP VIEW
.042
.056
.400
REF.
.490
.530
16-038FPO-5
PL 032
DA79
6-28-94 ae
Am27C040 11
FINAL
PHYSICAL DIMENSIONS*
CDV032—32-Pin Ceramic DIP, UV Lens (measured in inches)
DATUM D
CENTER PLANE
INDEX AND
TERMINAL NO. 1
I.D. AREA
BASE PLANE
SEATING PLANE
.005 MIN
1
TOP VIEW
1.635
1.680
.045
.065
.014
.026
UV Lens
.100 BSC
.015
.060
.565
.605
CENTER PLANE
.160
.220
.125
.200
DATUM D
.300 BSC
.700
MAX
.600
BSC
94°
105°
.008
.018
SIDE VIEW
* For reference only. BSC is an ANSI standard for Basic Space Centering.
REVISION SUMMARY FOR AM27C040
Revision E/1
Product Selector Guide:
Added -90 (90 ns, ±10% VCC) and deleted -100 speed options.
Ordering Information, UV EPROM Products:
The -90 part number is now listed in the example.
Valid Combinations:
Ordering Information, OTP EPROM Products:
The -90 part number is now listed in the example.
Valid Combinations:
Programming the Am27C040:
The fourth paragraph should read, “Please refer to Section 5 for programming…”.
Added -90 and deleted -100 speed options in valid combinations.
Added -90 and deleted -100 speed options in valid combinations.
END VIEW
16-000038H-3
CDV032
DF11
3-30-95 ae
12 Am27C040
FINAL
Operating Ranges:
Changed Supply Read V o ltages listings to match those
in the Product Selector Guide.
AC Characteristics:
Added -90 and deleted -100 speed options in tabl e , rearranged notes, moved text from table title to Note 4,
renamed table.
Revision F
Deleted -255 speed option.
Changed all active low signal designations from over-
bars or trailing “#”s.
Revision G
Global
Made formatting and layout consistent with other data
sheets. Used updated common tables and diagr ams.
Distinctive Characteristics:
Low Po wer Consumption:
to “<10 µA typical”.
TSOP package deleted.
General Description:
In the third paragraph, changed “100 µW in standby
mode” to 50 µW in standby mode”.
Connection Diagrams:
Deleted TSOP Pinout figure.
Pin Designations:
Changed “Chip Enable Input” to “Chip Enable/ Progr am
Enable Input”.
Changed “100 µA maximum”
OTP EPROM Products:
Changed -75 speed option to
-90.
Temperature Range:
125°C)
”.
Package Type:
Added “E = Extended (–55°C to
Deleted “E = 32-pin Thin Small Outline
Package (TSOP) Standard Pinout (TS 032)”.
Valid Combinations:
Deleted EC and EI options.
Functional Description:
Replaced device specific text with generic text.
Test Conditions:
New section with Test Setup Figure and T est Spec ifications Table.
Switching Test Waveform:
Modified figure.
Operating Ranges:
Supply Read Voltages:
Replaced with generic data.
DC Characteristics:
Modified Figures 1 and 2.
Switching Waveform:
Corrected “DF” to “t
” in Note 2.
DF
Package Capacitance:
Deleted TSOP data.
Physical Dimensions:
New section, added figures f or the 32-Pin Ceramic DIP,
32-Pin Plastic DIP, and 32-Pin Plastic Leaded Chip
Carrier.
Ordering Information:
UV EPROM Products:
Changed -75 speed option to
-90.
Trademarks
Copyright © 1998 Advanced Micro D evices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Flashrite is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am27C040 13
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