AMCC PPC405CR DATA SHEET

Part Number PPC405CR

Revision 1.02 – January 11, 2005

AMCC 1

PPC405CR

PowerPC 405CR Embedded Processor

Data Sheet

Features

•PowerPC® 405 32-bit RISC processor core
operating up to 266MHz

- Memory Management Unit

- 16KB instruction and 8 KB data caches

- Multiply-Accumulate (MAC) function,

including fast multiply unit

- Programmable Timers

• Synchronous DRAM (SDRAM) interface oper­ating up to 133MHz

- 32-bit interface for non-ECC applications

- 40-bit interface serves 32 bits of data plus 8

check bits for ECC applications

• External Peripheral Bus

- Flash ROM/Boot ROM interface

- Direct support for 8-, 16-, or 32-bit SRAM and

external peripherals

- Up to eight devices

- External Mastering supported

• DMA support for external peripherals, internal
UART and memory

- Scatter-gather chaining supported

- Four channels

• Programmable Interrupt Controller supports
interrupts from a variety of sources

- Supports 7 external and 10 internal interrupts

- Edge triggered or level-sensitive

- Positive or negative active

- Non-critical or critical interrupt to processor

core

- Programmable critical interrupt priority

ordering

• Two serial ports (16550 compatible UART)

• One IIC interface

• General Purpose I/O (GPIO) available

• Supports JTAG for board level testing

• Internal Processor Local Bus (PLB) runs at
SDRAM interface frequency

Description

The PowerPC 405CR (PPC405CR) is a 32-bit RISC
embedded controller. High performance, peripheral
integration, and low cost make the device ideal for
wired communications, network printers, and other
computing applications.

This device is an easy upgrade for systems based on
PowerPC 403xx embedded processors, while provid­ing a base for custom chip designs.

The controller is powered by a PPC405 embedded
core. This core tightly couples a 266 MHz CPU, MMU,
instruction and data caches, and debug logic. Fine­tuning of the core reduces data transfer overhead,
minimizes pipeline stalls, and improves performance.

The PPC405CR employs the IBM CoreConnect

™

bus
architecture. This architecture, as implemented on the
PPC405CR, consists of a 64-bit, 133-MHz Processor
Local Bus (PLB) and a 32-bit, 66-MHz On-Chip
Peripheral Bus (OPB). High-performance peripherals
attach to the PLB and less performance-critical periph­erals attach to the OPB.

Technology: CMOS SA-12E 0.25 µm (0.18 µm L

eff

)

Package: 27mm, 316-ball enhanced plastic ball grid
array (E-PBGA)

Power (estimated): Typical 0.8W, Maximum 2.0W at
200MHz.

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PPC405CR – PowerPC 405CR Embedded Processor

2 AMCC

Revision 1.02 – January 11, 2005

Data Sheet

Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Address Map Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Intialization Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Pull-Up and Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Unused I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

External Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

PPC405CR – PowerPC 405CR Embedded Processor

Revision 1.02 – January 11, 2005

AMCC 3

Data Sheet

List of Figures

Figure 1. PPC405CR Embedded Controller Functional Block Diagram .................................................................. 5

Figure 2. 27mm, 316-Ball E-PBGA Package ......................................................................................................... 10

Figure 3. Package Thermal Specifications ............................................................................................................ 28

Figure 4. 5V-Tolerant I/O Input Current ................................................................................................................. 30

Figure 5. Timing Waveform .................................................................................................................................... 32

Figure 6. Input Setup and Hold Waveform ............................................................................................................. 35

Figure 7. Output Delay and Float Timing Waveform .............................................................................................. 35

List of Tables

Table 1. System Memory Address Map 4GB System Memory ................................................................................ 6

Table 2. DCR Address Map 4KB Device Configuration Register ............................................................................. 6

Table 3. Signals Listed Alphabetically ................................................................................................................... 11

Table 4. Signals Listed by Ball Assignment ........................................................................................................... 18

Table 5. Pin Summary ........................................................................................................................................... 21

Table 6. Signal Functional Description .................................................................................................................. 23

Table 7. Absolute Maximum Ratings ..................................................................................................................... 28

Table 8. Recommended DC Operating Conditions ................................................................................................ 29

Table 9. Input Capacitance .................................................................................................................................... 30

Table 10. Clocking Specifications .......................................................................................................................... 32

Table 11. Peripheral Interface Clock Timings ........................................................................................................ 34

Table 12. I/O Specifications—All speeds ............................................................................................................... 36

Table 13. I/O Specifications—133 and 200MHz .................................................................................................... 37

Table 14. I/O Specifications—266MHz .................................................................................................................. 38

Table 15. Strapping Pin Assignments .................................................................................................................... 39

PPC405CR – PowerPC 405CR Embedded Processor

4 AMCC

Revision 1.02 – January 11, 2005

Data Sheet

Ordering, PVR, and JTAG Information

This section provides the part numbering nomenclature for the PPC405CR. For availability, contact your local
AMCC sales office.

Each part number contains a revision code. This refers to the die mask revision number and is specified in the part
numbering scheme for identification purposes only.

The PVR (Processor Version Register) is software accessible and contains additional information about the revi­sion level of the part. Refer to the PPC405CR Embedded Processor User’s Manual for details on the register
content.

Part Number Key

Product Name

Order Part Number

1, 2

Processor
Frequency

Package

Rev

Level

PVR Value JTAG ID

PPC405CR PPC405CR-3BC133C 133MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049

PPC405CR PPC405CR-3BC133CZ 133MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049

PPC405CR PPC405CR-3KC133C 133MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049

PPC405CR PPC405CR-3KC133CZ 133MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049

PPC405CR PPC405CR-3BC200C 200MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049

PPC405CR PPC405CR-3BC200CZ 200MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049

PPC405CR PPC405CR-3KC200C 200MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049

PPC405CR PPC405CR-3KC200CZ 200MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049

PPC405CR PPC405CR-3BC266C 266MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049

PPC405CR PPC405CR-3BC266CZ 266MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049

PPC405CR PPC405CR-3KC266C 266MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049

PPC405CR PPC405CR-3KC266CZ 266MHz 27mm, 316 ball E-PBGA C 0x40110145 0x42051049

Notes: 1. Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray.

2. Package type B contains lead; package type K is lead-free.

Part Number

PPC405CR-3BC266Cx

Package (E-PBGA)

Processor Speed

Grade 3 Reliability

Operational Case Temperature

Revision Level

Shipping Package

Blank = Tray

Z = Tape and reel

(-40°C to +85°C)

Range

200MHz
266MHz

133MHz

PPC405CR – PowerPC 405CR Embedded Processor

Revision 1.02 – January 11, 2005

AMCC 5

Data Sheet

Figure 1. PPC405CR Embedded Controller Functional Block Diagram

The PPC405CR is designed using the IBM Microelectronics Blue Logic

®

methodology in which major functional
blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent
way to create complex ASICs using IBM CoreConnect

™

Bus Architecture.

PPC405

Processor Core

DCU

ICU

DCR Bus

16KB

On-chip Peripheral Bus (OPB)

GPIO

IIC UART UART

DMA

Bridge

Processor Local Bus (PLB)

SDRAM

Code

Decompression

External

Bus

Controller

Controller

Clock
Control
Reset

Power

Mgmt

JTAG

Trace

Timers

MMU

Controller

OPB

Interrupt

Controller

Arb

32-bit addr
32-bit data

13-bit addr

32-bit data

External

Bus Master

Controller

Universal

I-Cache

8KB

D-Cache

(4-Channel)

(CodePack™)

DCRs

Arb

PPC405CR – PowerPC 405CR Embedded Processor

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Revision 1.02 – January 11, 2005

Data Sheet

Address Map Support

The PPC405CR incorporates two simple and separate address maps. The first address map defines the possible
use of address regions that the processor can access. The second address map is for Device Configuration Regis­ters (DCRs). The DCRs are accessed by software running on the PPC405CR processor through the use of mtdcr
and mfdcr instructions.

Table 1. System Memory Address Map (4GB System Memory)

Function Subfunction Start Address End Address Size

General Use

SDRAM and External Peripherals
Note: Any of the address ranges listed at

right may be use for any of the above
functions.

0x00000000 0xEF5FFFFF 3830MB

0xF0000000 0xFFFFFFFF 256MB

Boot-up

Peripheral Bus Boot

1

0xFFE00000 0xFFFFFFFF 2MB

Internal Peripherals

UART0 0xEF600300 0xEF600307 8B

UART1 0xEF600400 0xEF600407 8B

IIC0 0xEF600500 0xEF60051F 32B

OPB Arbiter 0xEF600600 0xEF60063F 64B

GPIO Controller Registers 0xEF600700 0xEF60077F 128B

Notes:

1. When peripheral bus boot is selected, Peripheral bank 0 is automatically configured at reset to the address range listed above.

2. After the boot process, software may reassign the boot memory region for other uses.

3. All address ranges not listed above are reserved.

Table 2. DCR Address Map

Function Start Address End Address Size

Total DCR Address Space

1

0x000 0x3FF

1KW (4KB)

1

Reserved 0x000 0x00F 16W

Memory Controller Registers 0x010 0x011 2W

External Bus Controller Registers 0x012 0x013 2W

Decompression Controller Registers 0x014 0x015 2W

Reserved 0x016 0x07F 106W

PLB Registers 0x080 0x08F 16W

Reserved 0x090 0x09F 16W

OPB Bridge Out Registers 0x0A0 0x0A7 8W

Reserved 0x0A8 0x0AF 8W

Clock, Control, and Reset 0x0B0 0x0B7 8W

Power Management 0x0B8 0x0BF 8W

Interrupt Controller 0x0C0 0x0CF 16W

Reserved 0x0D0 0x0FF 48W

DMA Controller Registers 0x100 0x13F 64W

Reserved 0x140 0x3FF 704W

Notes:

1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit
(word) register, or 1 kiloword (KW) (which equals 4 KB).

PPC405CR – PowerPC 405CR Embedded Processor

Revision 1.02 – January 11, 2005

AMCC 7

Data Sheet

SDRAM Memory Controller

The PPC405CR Memory Controller core provides a low latency access path to SDRAM memory. A variety of sys­tem memory configurations are supported. The memory controller supports up to four logical banks. Up to 256MB
per bank are supported, up to a maximum of 1GB. Memory timings, address and bank sizes, and memory
addressing modes are programmable.

Features include:

• 11x8 to 13x11 addressing for SDRAM (2- and 4-bank)

• 32-bit memory interface support

• Programmable address compare for each bank of memory

• Industry standard 168-pin DIMMS are supported (some configurations)

• 4MB to 256MB per bank

• Programmable address mapping and timing

• Auto refresh

• Page mode accesses with up to 4 open pages

• Power Management (self-refresh)

• Error Checking and Correction (ECC) support

- Standard SEC/DED coverage

- Aligned nibble error detect

- Address error logging

External Peripheral Bus Controller (EBC)

• Supports eight banks of ROM, EPROM, SRAM, Flash memory, or slave peripheral I/O

• Up to 66MHz operation

• Burst and non-burst devices

• 8-, 16-, 32-bit byte-addressable data bus width support

• Programmable 2K clock time-out counter with disable for Ready

• Programmable access timing per device

- 0–255 wait states for non-burst devices

- 0–31 burst wait states for first access and up to 7 wait states for subsequent accesses

- Programmable CSon, CSoff relative to address

- Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS

• Programmable address mapping

• Peripheral device pacing with external “Ready”

• External master interface

- Write posting from external master

- Read prefetching on PLB for external master reads

- Bursting capable from external master

- Allows external master access to all non-EBC PLB slaves

- External master can control EBC slaves for own access and control

DMA Controller

• Supports the following transfers:

- Memory-to-memory transfers

- Buffered peripheral to memory transfers

PPC405CR – PowerPC 405CR Embedded Processor

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Revision 1.02 – January 11, 2005

Data Sheet

- Buffered memory to peripheral transfers

• Four channels

• Scatter/Gather capability for programming multiple DMA operations

• 8-, 16-, 32-bit peripheral support (OPB and external)

• 32-bit addressing

• Address increment or decrement

• Internal 32-byte data buffering capability

• Supports internal and external peripherals

• Support for memory mapped peripherals

• Support for peripherals running on slower frequency buses

UART

• One 8-pin UART and one 4-pin UART interface provided

• Selectable internal or external serial clock to allow wide range of baud rates

• Register compatibility with NS16550 register set

• Complete status reporting capability

• Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode

• Fully programmable serial-interface characteristics

• Supports DMA using internal DMA engine

IIC Bus Interface

• Compliant with Phillips® Semiconductors I2C Specification, dated 1995

• Operation at 100kHz or 400 kHz

•8-bit data

• 10- or 7-bit address

• Slave transmitter and receiver

• Master transmitter and receiver

• Multiple bus masters

• Supports fixed V

DD

IIC interface

• Two independent 4 x 1 byte data buffers

• Twelve memory-mapped, fully programmable configuration registers

• One programmable interrupt request signal

• Provides full management of all IIC bus protocol

• Programmable error recovery

General Purpose IO (GPIO) Controller

• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus
master accesses.

• All GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabil­ities acts as a GPIO or is used for another purpose. The 23 GPIOs are multiplexed with:

- 7 of 8 chip selects.

- All seven external interrupts.

- All nine instruction trace pins.

• Each GPIO output is separately programmable to emulate an open-drain driver (two states, drive to zero or
open circuit).

PPC405CR – PowerPC 405CR Embedded Processor

Revision 1.02 – January 11, 2005

AMCC 9

Data Sheet

Universal Interrupt Controller (UIC)

The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the
various sources of interrupts and the local PowerPC processor.

Features include:

• Supports 7 external and 10 internal interrupts

• Edge triggered or level-sensitive

• Positive or negative active

• Non-critical or critical interrupt to PPC405 processor core

• Programmable critical interrupt priority ordering

• Programmable critical interrupt vector for faster vector processing

JTAG

• IEEE 1149.1 test access port

• IBM RISCWatch debugger support

• JTAG Boundary Scan Description Language (BSDL)

PPC405CR – PowerPC 405CR Embedded Processor

10 AMCC

Revision 1.02 – January 11, 2005

Data Sheet

Figure 2. 27mm, 316-Ball E-PBGA Package

M

1.27 TYP

0.75 ± 0.15 SOLDERBALL x 316

27.0

24.13

27.0

B

A

C

0.20

∅ 0.30
∅ 0.15

C

27.0 REF

Reserved Area for Ejector Pin Mark x 4 TYP
Corner Shape is Chamferred or Rounded

0.20

C

C

2.65 MAX

0.6 ± 0.1

PCB
Substrate

Mold
Compound

Thermal Balls

Top View

Bottom View

0.25

0.35

C

C

Y

W

V

U

T

R

P
N
M

L

K

J
H
G

F
E
D
C
B
A

M

A B

7.5 TYP

15.0 TYP

Gold Gate Release
Corresponds to
A1 Ball Location

27.0

20

19

18

17

166789101112

13

14

15

54321

Notes:

1. All dimensions are in mm.

2. Package available in leaded and lead-free configurations.

PPC405CR – PowerPC 405CR Embedded Processor

Revision 1.02 – January 11, 2005

AMCC 11

Data Sheet

Pin Lists

In this section there are two tables that correlate the external signals to the physical package pin (ball) on which
they appear.

The following table lists all the external signals in alphabetical order and shows the ball number on which the signal
appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate
signal in brackets. The page number listed gives the page in “Signal Functional Description” on page 23 where the
signals in the indicated interface group begin.

Table 3. Signals Listed Alphabetically

(Sheet 1 of 7)

Signal Name Ball Interface Group Page

AV

DD

E20 Power 27

BA0
BA1

J17

H18

SDRAM 23

BankSel0
BankSel1
BankSel2
BankSel3

L19
N17
P17
U19

SDRAM 23

BusReq P2 External Master Peripheral 25

CAS

K17 SDRAM 23

ClkEn0
ClkEn1

J19
G20

SDRAM 23

DMAAck0
DMAAck1
DMAAck2
DMAAck3

C16
B17
B16
A14

External Slave Peripheral 23

DMAReq0
DMAReq1
DMAReq2
DMAReq3

A19
C15
B15

A8

External Slave Peripheral 23

DQM0
DQM1
DQM2
DQM3

U18

W14

Y10

U8

SDRAM 23

DQMCB V19 SDRAM 23

DrvrInh1
DrvrInh2

F17
C19

System 26

ECC0
ECC1
ECC2
ECC3
ECC4
ECC5
ECC6
ECC7

V17
Y18
U14
V13
Y13
V12

W11

V11

SDRAM 23

EOT0/TC0
EOT1/TC1
EOT2/TC2
EOT3/TC3

G4
F2

W1

Y2

External Slave Peripheral 23

ExtAck
ExtReq
ExtReset

U5
Y3P4External Master Peripheral 25

PPC405CR – PowerPC 405CR Embedded Processor

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Revision 1.02 – January 11, 2005

Data Sheet

GND

A1

A6
A10
A15
A20

B2
B19

C3
C18

D4
D17

E5
E10
E11
E16

F1
F20

J9
J10
J11
J12

K5

K9
K10
K11
K12
K16
K20

L1
L5

L9
L10
L11
L12
L16

M9
M10
M11
M12

R1
R20

Power
Note: J9–J12, K9–K12, L9–L12, and M9–M12 are also thermal balls. 27

GND (cont)

T5
T10
T11
T16

U4
U17

V3
V18

W2

W19

Y1

Y6
Y11
Y15
Y20

Power 27

Table 3. Signals Listed Alphabetically (Sheet 2 of 7)

Signal Name Ball Interface Group Page

PPC405CR – PowerPC 405CR Embedded Processor

Revision 1.02 – January 11, 2005

AMCC 13

Data Sheet

GPIO1[TS1E]
GPIO2[TS2E]
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5[TS3]
GPIO6[TS4]
GPIO7[TS5]
GPIO8[TS6]
GPIO9[TrcClk]

B18
D16
C17
P18
T17

W18

Y19

W13

V6

System 26

Halt

E19 System 26

HoldAck
HoldPri
HoldReq

T4

T3V2External Master Peripheral 25

IICSCL U15 Internal Peripheral 25

IICSDA W17 Internal Peripheral 25

IRQ0[GPIO17]
IRQ1[GPIO18]
IRQ2[GPIO19]
IRQ3[GPIO20]
IRQ4[GPIO21]
IRQ5[GPIO22]
IRQ6[GPIO23]

D18
C20
E18
D20
G17
F18

W20

Interrupts 26

MemAddr0
MemAddr1
MemAddr2
MemAddr3
MemAddr4
MemAddr5
MemAddr6
MemAddr7
MemAddr8
MemAddr9
MemAddr10
MemAddr11
MemAddr12

Y7

W7

V8

U7

Y4

U6

W4

V5

W3

V4

U3

V1

T2

SDRAM
Note: During a CAS

cycle MemAddr0 is the least significant bit (lsb) on this

bus.

23

MemClkOut0
MemClkOut1

H20
G18

SDRAM 23

Table 3. Signals Listed Alphabetically (Sheet 3 of 7)

Signal Name Ball Interface Group Page