Altera Viterbi Compiler User Manual

Viterbi IP Core User Guide

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TOC-2

Contents

About the Viterbi IP Core...................................................................................1-1

Viterbi IP Core Getting Started..........................................................................2-1

Altera DSP IP Core Features...................................................................................................................... 1-1

Viterbi II IP Core Features......................................................................................................................... 1-1

DSP IP Core Device Family Support.........................................................................................................1-2

DSP IP Core Verification............................................................................................................................1-2

Viterbi IP Core Release Information.........................................................................................................1-2

Viterbi IP Core Performance and Resource Utilization.........................................................................1-3

Installing and Licensing IP Cores..............................................................................................................2-1

OpenCore Plus IP Evaluation........................................................................................................ 2-1

Viterbi IP Core OpenCore Plus Timeout Behavior.................................................................... 2-2

IP Catalog and Parameter Editor...............................................................................................................2-2

Specifying IP Core Parameters and Options............................................................................................2-3

Files Generated for Altera IP Cores...............................................................................................2-4

Simulating Altera IP Cores in other EDA Tools..................................................................................... 2-7

DSP Builder Design Flow............................................................................................................................2-8

Viterbi IP Core Functional Description.............................................................3-1

Decoder......................................................................................................................................................... 3-1

Convolutional Encoder...............................................................................................................................3-1

Trellis Coded Modulation...........................................................................................................................3-2

Half-Rate Convolutional Codes.....................................................................................................3-2

Trellis Decoder.................................................................................................................................3-4

About Converting Received Signals..............................................................................................3-5

Trellis Termination..........................................................................................................................3-7

Trellis Initialization .........................................................................................................................3-7

Viterbi IP Core Parameters........................................................................................................................ 3-7

Architecture......................................................................................................................................3-7

Code Sets...........................................................................................................................................3-9

Viterbi Parameters.........................................................................................................................3-10

Test Data......................................................................................................................................... 3-12

Viterbi IP Core Interfaces and Signals....................................................................................................3-14

Avalon-ST Interfaces in DSP IP Cores....................................................................................... 3-14

Global Signals.................................................................................................................................3-14

Avalon-ST Sink Signals.................................................................................................................3-14

Avalon Source-ST Signals.............................................................................................................3-16

Configuration Signals....................................................................................................................3-17

Status Signals.................................................................................................................................. 3-18

Viterbi IP Core Timing Diagrams...............................................................................................3-18

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Document Revision History................................................................................4-1

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About the Viterbi IP Core

1

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Altera DSP IP Core Features

• Avalon® Streaming (Avalon-ST) interfaces

• DSP Builder ready

• Testbenches to verify the IP core

• IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators

Viterbi II IP Core Features

• High-speed parallel architecture:

• Performance of over 250 megabits per second (Mbps)

• Fully parallel operation

• Optimized block decoding and continuous decoding

• Low to medium-speed, hybrid architecture:

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• Configurable number of add compare and select (ACS) units

• Memory-based architecture

• Wide range of performance; wide range of logic area

• Fully parameterized Viterbi decoder, including:

• Number of coded bits

• Constraint length

• Number of soft bits

• Traceback length

• Polynomial for each coded bit

• Variable constraint length

• Trellis coded modulation (TCM) option

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.

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DSP IP Core Device Family Support

DSP IP Core Device Family Support

Altera® offers the following device support levels for Altera IP cores:

• Preliminary support—Altera verifies the IP core with preliminary timing models for this device family.
The IP core meets all functional requirements, but might still be undergoing timing analysis for the
device family. You can use it in production designs with caution.

• Final support—Altera verifies the IP core with final timing models for this device family. The IP core
meets all functional and timing requirements for the device family. You can use it in production
designs.

Table 1-1: DSP IP Core Device Family Support

Device Family Support

Arria® II GX Final
Arria II GZ Final
Arria V Final
Arria 10 Final

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Cyclone® IV Final
Cyclone V Final
MAX® 10 FPGA Final
Stratix® IV GT Final
Stratix IV GX/E Final
Stratix V Final
Other device families No support

DSP IP Core Verification

Before releasing a version of an IP core, Altera runs comprehensive regression tests to verify its quality
and correctness. Altera generates custom variations of the IP core to exercise the various parameter
options and thoroughly simulates the resulting simulation models with the results verified against master
simulation models.

Viterbi IP Core Release Information

Use the release information when licensing the IP core.

Table 1-2: Release Information

Version 14.1

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Item Description

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Item Description

Viterbi IP Core Performance and Resource Utilization

Release Date December 2014

Ordering Code IP-VITERBI/HS (parallel architecture) IP-VITERBI/SS (hybrid

Product ID 0037 (parallel architecture) 0038 (hybrid architecture)

Vendor ID 6AF7

Altera verifies that the current version of the Quartus II software compiles the previous version of each IP
core. Altera does not verify that the Quartus II software compiles IP core versions older than the previous
version. The Altera IP Release Notes lists any exceptions.

Related Information

• Altera IP Release Notes

• Errata for Viterbi IP core in the Knowledge Base

Viterbi IP Core Performance and Resource Utilization

This typical expected performance uses different architectures and constraint length, L, combinations,
and ACS units, A, and the Quartus II software. Performance largely depends on constraint length, L.

1-3

architecture)

Hybrid Architecture

The typical expected performance for a hybrid Viterbi IP core uses the Quartus II software with the Arria
V (5AGXFB3H4F40C4), Cyclone V (5CGXFC7D6F31C6), and Stratix V (5SGSMD4H2F35C2) devices
and the following parameters:

• v = 6 × L

• softbits = 3

• N = 2

where:

• v is the traceback length

• L is the constraint length

• N is the number of coded bits

• A is the number of ACS units

Table 1-3: Typical Performance

Parameters

L A M10K M20K Primary Secondary

Device ALM f

MAX

(MHz)

Memory Registers

5 1 Arria 10 401 383 -- 3 422 40
5 1 Arria V 323 201 5 -- 390 60
5 1 Cyclone V 324 172 5 -- 390 53
5 1 Stratix V 316 432 -- 5 388 44
7 1 Arria 10 521 370 -- 4 559 50

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Viterbi IP Core Performance and Resource Utilization

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Parameters

L A M10K M20K Primary Secondary

Device ALM f

MAX

(MHz)

Memory Registers

7 1 Arria V 427 207 6 -- 507 58
7 1 Cyclone V 427 185 6 -- 507 74
7 1 Stratix V 417 438 -- 6 506 51
7 2 Arria 10 622 363 -- 4 670 51
7 2 Arria V 529 215 6 -- 625 71
7 2 Cyclone V 532 180 6 -- 625 74
7 2 Stratix V 502 408 -- 6 625 56
7 4 Arria 10 835 366 -- 4 885 101
7 4 Arria V 744 204 6 -- 856 99
7 4 Cyclone V 746 173 6 -- 856 100
7 4 Stratix V 652 382 -- 6 856 82
9 1 Arria 10 932 343 -- 9 970 88

1 Arria V 792 190 11 -- 927 90
9 1 Cyclone V 794 176 11 -- 926 96
9 1 Stratix V 777 393 -- 11 924 94
9 16 Arria V 2,118 188 17 -- 2,743 309
9 16 Cyclone V 2,119 163 17 -- 2,744 275
9 16 Stratix V 1,887 348 -- 17 2,738 198
9 2 Arria 10 1,029 363 -- 9 1,091 74
9 2 Arria V 889 205 11 -- 1,053 98
9 2 Cyclone V 889 180 11 -- 1,053 96
9 2 Stratix V 883 377 -- 11 1,053 115
9 4 Arria 10 1,240 298 -- 9 1,321 87
9 4 Arria V 1,097 201 11 -- 1,302 137
9 4 Cyclone V 1,096 159 11 -- 1,302 126
9 4 Stratix V 1,021 390 -- 11 1,302 119
9 8 Arria V 1,465 197 13 -- 1,788 193
9 8 Cyclone V 1,465 163 13 -- 1,789 191
9 8 Stratix V 1,398 351 -- 13 1,790 154

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Parallel Architecture

The typical expected performance for a parallel Viterbi IP core uses the Quartus II software with the Arria
V (5AGXFB3H4F40C4), Cyclone V (5CGXFC7D6F31C6), and Stratix V (5SGSMD4H2F35C2) devices.
The following parameters apply:

• v = 6 ×L

• N = 2
where:

• v is the traceback length

• L is the constraint length

• N is the number of coded bits

Table 1-4: Typical Performance

Viterbi IP Core Performance and Resource Utilization

1-5

Parameters

softbits L Optimiz

ation

Best

State

Finder

Device ALMs

fMAX

(MHz)

Memory Registers

M10K M20K Primary Seconda

5 3 — On Arria 10 420 400 -- 5 500 63
7 3 — On Arria 10 453 351 -- 5 534 75
3 3 — Off Arria 10 396 423 -- 5 473 39
5 3 — Off Arria 10 420 400 -- 5 500 63
7 3 — Off Arria 10 453 351 -- 5 534 75
3 7 Block Off Arria 10 1,454 354 -- 3 817 154
3 7 Block Off Arria V 1,537 201 5 -- 1,166 168
3 7 Block Off CycloneV1,544 149 5 -- 1,167 88

3 7 Block Off Stratix V 1,521 352 -- 3 1,167 154
3 3 — Off Arria V 378 237 5 -- 456 67
3 3 — Off CycloneV378 200 5 -- 456 84

3 3 — Off Stratix V 378 405 -- 5 455 45

ry

5 3 — Off Arria V 397 210 5 -- 483 68
5 3 — Off CycloneV397 188 5 -- 484 81

5 3 — Off Stratix V 396 406 -- 5 482 92
3 3 — On Arria V 378 237 5 -- 456 67
3 3 — On CycloneV378 200 5 -- 456 84

3 3 — On Stratix V 378 405 -- 5 455 45
5 3 — On Arria V 397 210 5 -- 483 68

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Viterbi IP Core Performance and Resource Utilization

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Parameters

softbits L Optimiz

ation

Best

State

Finder

Device ALMs

fMAX

(MHz)

Memory Registers

M10K M20K Primary Seconda

5 3 — On CycloneV397 188 5 -- 484 81

5 3 — On Stratix V 396 406 -- 5 482 92
7 3 — On Arria V 424 219 5 -- 518 82
7 3 — On CycloneV424 185 5 -- 519 76

7 3 — On Stratix V 424 408 -- 5 517 69
7 3 — Off Arria V 424 219 5 -- 518 82
7 3 — Off CycloneV424 185 5 -- 519 76

7 3 — Off Stratix V 424 408 -- 5 517 69
7 4 — Off Arria V 424 219 5 -- 518 82
7 4 — Off CycloneV424 185 5 -- 519 76

ry

7 4 — Off Stratix V 424 408 -- 5 517 69
3 7 Continu

Off Arria 10 1,180 365 -- 5 829 178

ous

3 7 Continu

Off Arria V 1,222 187 9 -- 1,137 250

ous

3 7 Continu

Off CycloneV1,223 157 9 -- 1,137 187

ous

3 7 Continu

Off Stratix V 1,220 325 -- 5 1,137 168

ous

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acds

quartus - Contains the Quartus II software
ip - Contains the Altera IP Library and third-party IP cores

altera - Contains the Altera IP Library source code

<IP core name> - Contains the IP core source files

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Viterbi IP Core Getting Started

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Installing and Licensing IP Cores

The Altera IP Library provides many useful IP core functions for your production use without purchasing
an additional license. Some Altera MegaCore® IP functions require that you purchase a separate license
for production use. However, the OpenCore® feature allows evaluation of any Altera IP core in simulation
and compilation in the Quartus® II software. After you are satisfied with functionality and perfformance,
visit the Self Service Licensing Center to obtain a license number for any Altera product.

Figure 2-1: IP Core Installation Path

Note:

The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is
<home directory>/altera/ <version number>.

Related Information

• Altera Licensing Site

• Altera Software Installation and Licensing Manual

OpenCore Plus IP Evaluation

Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and
hardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to take
your design to production. OpenCore Plus supports the following evaluations:

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.

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Viterbi IP Core OpenCore Plus Timeout Behavior

• Simulate the behavior of a licensed IP core in your system.

• Verify the functionality, size, and speed of the IP core quickly and easily.

• Generate time-limited device programming files for designs that include IP cores.

• Program a device with your IP core and verify your design in hardware.
OpenCore Plus evaluation supports the following two operation modes:

• Untethered—run the design containing the licensed IP for a limited time.

• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a
connection between your board and the host computer.

Note: All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times

out.

Viterbi IP Core OpenCore Plus Timeout Behavior

All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached. If
there is more than one IP core in a design, the time-out behavior of the other IP cores may mask the time­out behavior of a specific IP core .

For IP cores, the untethered time-out is 1 hour; the tethered time-out value is indefinite. Your design
stops working after the hardware evaluation time expires. The Quartus II software uses OpenCore Plus
Files (.ocp) in your project directory to identify your use of the OpenCore Plus evaluation program. After
you activate the feature, do not delete these files..

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When the evaluation time expires the decbit signal goes low .

Related Information

• AN 320: OpenCore Plus Evaluation of Megafunctions

IP Catalog and Parameter Editor

The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and
integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize,
and generate files representing your custom IP variation.

Note:

The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard™ Plug-In
Manager for IP selection and parameterization, beginning in Quartus II software version 14.0. Use
the IP Catalog and parameter editor to locate and paramaterize Altera IP cores.

The IP Catalog lists installed IP cores available for your design. Double-click any IP core to launch the
parameter editor and generate files representing your IP variation. The parameter editor prompts you to
specify an IP variation name, optional ports, and output file generation options. The parameter editor
generates a top-level Qsys system file (.qsys) or Quartus II IP file (.qip) representing the IP core in your
project. You can also parameterize an IP variation without an open project.

Use the following features to help you quickly locate and select an IP core:

• Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have no
project open, select the Device Family in IP Catalog.

• Type in the Search field to locate any full or partial IP core name in IP Catalog.

• Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's
installation folder, and view links to documentation.

• Click Search for Partner IP, to access partner IP information on the Altera website.

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Search for installed IP cores

Double-click to customize, right-click for
detailed information

Show IP only for target device

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Figure 2-2: Quartus II IP Catalog

Specifying IP Core Parameters and Options

2-3

Note: The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes

exclusive system interconnect, video and image processing, and other system-level IP that are not
available in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, refer
to Creating a System with Qsys in the Quartus II Handbook.

Specifying IP Core Parameters and Options

You can quickly configure a custom IP variation in the parameter editor. Use the following steps to
specify IP core options and parameters in the parameter editor. Refer to Specifying IP Core Parameters
and Options (Legacy Parameter Editors) for configuration of IP cores using the legacy parameter editor.

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.
The parameter editor appears.

2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation
settings in a file named <your_ip>.qsys. Click OK.

3. Specify the parameters and options for your IP variation in the parameter editor, including one or
more of the following. Refer to your IP core user guide for information about specific IP core
parameters.

Viterbi IP Core Getting Started

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