Altera Virtual JTAG IP Core User Manual
2014.03.19
www.altera.com
101 Innovation Drive, San Jose, CA 95134
Virtual JTAG Megafunction (sld_virtual_jtag)
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The Virtual JTAG (SLD_VIRTUAL_JTAG) megafunction is an Altera®-provided megafunction IP core
optimized for Altera device architectures. Using megafunctions in place of coding your own logic saves
valuable design time, and offers more efficient logic synthesis and device implementation. You can scale the
megafunction's size by setting parameters.
Introduction
The Virtual JTAG megafunction provides access to the PLD source through the JTAG interface.
The Quartus®II software or JTAG control host identifies each instance of this megafunction by a unique
index. Each megafunction instance functions in a flow that resembles the JTAG operation of a device. The
logic that uses this interface must maintain the continuity of the JTAG chain on behalf the PLD device when
this instance becomes active. The Virtual JTAG megafunction) allows you to create your own software
solution for monitoring, updating, and debugging designs through the JTAG port without using I/O pins
on the device, and is one feature in the On-Chip Debugging Tool Suite.
Note:
With the SLD Virtual JTAG megafunction you can build your design for efficient, fast, and productive
debugging solutions.Debugging solutions can bepart of an evaluation testwhere you use other logicanalyzers
to debug your design, or as part of a production test where you do not have a host running an embedded
logic analyzer. In addition to debugging features, you can use the Virtual JTAG megafunction to provide a
single channel or multiple serial channels through the JTAG port of the device. You can use serial channels
in applications to capture data or to force data to various parts of your logic.
When you create your megafunction, you can use the MegaWizard Plug-In Manager to generate a
netlist for third-party synthesis tools.
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Each feature in the On-Chip Debugging Tool Suite leverageson-chip resources to achieve real time visibility
to the logic under test. During runtime, each tool shares the JTAG connection to transmit collected test data
to the Quartus II software for analysis. The tool set consists of a set of GUIs, megafunction intellectual
property (IP) cores, and Tcl applicationprogramming interfaces (APIs). TheGUIs provide the configuration
of test signals and the visualization of data captured during debugging. The Tcl scripting interface provides
automation during runtime.
The Virtual JTAG megafunction provides you direct access to the JTAG control signals routed to the FPGA
core logic, which gives you a fine granularity of control over the JTAG resource and opens up the JTAG
resource as a general-purpose serial communication interface. A complete Tcl API is available for sending
and receiving transactions into your device during runtime. Because the JTAG pins are readily accessible
during runtime, this megafunction enables an easy way to customize a JTAG scan chain internal to the
device, which you can then use to create debugging applications.
©
2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
ISO
9001:2008
Registered
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Device Family Support
Examples of debugging applications include induced trigger conditions evaluated by a SignalTap®II Logic
Analyzer by exercising test signals connected to theanalyzer instance, areplacement for afront panel interface
during the prototyping phase of the design, or inserted test vectors for exercising the design under test.
The SLD infrastructure is an extension of the JTAG protocol for use with Altera-specific applications and
user applications, such as the SignalTap II Logic Analyzer.
Device Family Support
The Virtual JTAG megafunction supports the following Altera device families:
• Arria®series
• Stratix®series
• Cyclone®series
• HardCopy®series
• APEX™II, APEX 20KE, APEX 20KC
On-Chip Debugging Tool Suite
The On-Chip Debugging Tool Suite enables real time verification of a design and includes the following
tools:
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Table 1: On-Chip Debugging Tool Suite
SignalTap II Logic Analyzer
SignalProbe
Logic Analyzer Interface (LAI)
Uses FPGA resources to sample tests
nodes andoutputs the information to
the Quartus II software for display
and analysis.
Incrementally routes internal signals
to I/O pins while preserving the
results from your last place-androute.
Multiplexes a larger set of signals to
a smaller number of spare I/O pins.
LAI allows you to selectwhich signals
are switched onto the I/O pins over a
JTAG connection.
Typical Circumstances for UseDescriptionTool
You have spare on-chip memory
and want functional verification
of your design running in
hardware.
You have spare I/O pins and want
to check the operation of a small
set of control pins using either an
external logic analyzer or an
oscilloscope.
You havelimited on-chip memory
and have a large set of internal
data buses that you want to verify
using an external logic analyzer.
Logic analyzer vendors, such as
Tektronics and Agilent, provide
integration with the tool to
improve usability.
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Virtual JTAG Megafunction (sld_virtual_jtag)
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Logic
Logic
JTAG
sld_virtual_jtag
sld_virtual_jtag
tck
tms
trst
tdi
tdo
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Applications of the Virtual JTAG Megafunction
Typical Circumstances for UseDescriptionTool
3
In-System Memory Content
Editor
In-System Sources and Probes
Displays and allows you to edit onchip memory.
Provides a way to drive and sample
logic values to and from internal
nodes using the JTAG interface.
Virtual JTAG Interface
Opens the JTAGinterface so that you
can develop your own custom
applications.
Related Information
System Debugging Tools Overview
Applications of the Virtual JTAG Megafunction
You caninstantiate single ormultiple instances of theVirtual JTAG megafunctionin your HDL code.During
synthesis, the Quartus II software assigns unique IDs to each instance, so that each instance is accessed
individually. You can instantiate up to 128 instances of the Virtual JTAG megafunction. The figure below
shows a typical application in a design with multiple instances of the megafunction.
You want to view and edit the
contents of either the instruction
cache or data cache of a Nios®II
processor application.
You want to prototype a front
panel withvirtual buttons foryour
FPGA design.
You want to generate a large set
of test vectors and send them to
your deviceover the JTAG port to
functionally verify your design
running in hardware.
Figure 1: Application Example
The SLD hub automatically arbitrates between multiple applications that share a single JTAG resource.
Therefore, you can use the megafunction in tandem with other on-chip debugging applications, such as the
SignalTap II Logic Analyzer, to increase debugging visibility. You can also use the megafunction to provide
Virtual JTAG Megafunction (sld_virtual_jtag)
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Serial
Data In
JTAG Device 1 JTAG Device 2
Serial
Data Out
Core
Logic
Core
Logic
Boundary-Scan Cell
IC Pin Signal
Interconnection
to be Tested
4
JTAG Protocol
simple stimulus patterns to solicit a response from the design under test during run-time, including the
following applications:
• To diagnose, sample, and update the values of internal parts of your logic. With this megafunction, you
can easily sample and update the values of the internal counters and state machines in your hardware
device.
• To build your own customsoftware debugging IP using the Tcl commands to debug your hardware. This
IP communicates with the instances of the Virtual JTAG megafunction inside your design.
• To construct your design to achieve virtual inputs and outputs.
• If youare building a debuggingsolution for a systemin which a microprocessor controls the JTAG chain,
you cannotuse the SignalTap IILogic Analyzer because theJTAG control must be withthe microprocessor.
You can use low-level controls for the JTAG port from the Tcl commands to direct microprocessors to
communicate with the Virtual JTAG megafunction inside the device core.
JTAG Protocol
The original intent of theJTAG protocol (standardized as IEEE 1149.1) wasto simplify PCBinterconnectivity
testing during the manufacturing stage. As access to integrated circuit (IC) pins became more limited due
to tighter lead spacing and FPGA packages, testing through traditional probing techniques, such as
“bed-of-nails” test fixtures, became infeasible. The JTAG protocol alleviates the need for physical access to
IC pins via a shift register chain placed near the I/O ring. This set of registers near the I/O ring, also known
as boundary scan cells (BSCs), samples and forces values out onto the I/O pins. The BSCs from
JTAG-compliant ICs are daisy-chained into a serial-shift chain and driven via a serial interface.
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During boundary scan testing, software shifts out test data over the serial interface to the BSCs of select ICs.
This test data forces a known pattern to the pins connected to the affected BSCs. If the adjacent IC at the
other end of the PCB trace is JTAG-compliant, the BSC of the adjacent IC samples the test pattern and feeds
the BSCs back to the software for analysis. The figure below illustrates the boundary-scan testing concept.
Figure 2: IEEE Std. 1149.1 Boundary-Scan Testing
Because the JTAG interface shifts in any information to the device, leaves a low footprint, and is available
on all Altera devices, it is considered a general purpose communication interface. In addition to boundary
scan applications, Altera devices use the JTAG port for other applications, such as device configuration and
on-chip debugging features available in the Quartus II software.
Related Information
IEEE 1149.1 JTAG Boundary-Scan Testing
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JTAG Circuitry Architecture
The basic architecture of the JTAG circuitry consists of the following components:
• A set of Data Registers (DRs)
• An Instruction Register (IR)
• A state machine to arbitrate data (known as the Test Access Port (TAP) controller)
• A four- or five-pin serial interface, consisting of the following pins:
• Test data in (TDI), used to shift data into the IR and DR shift register chains
• Test data out (TDO), used to shift data out of the IR and DR shift register chains
• Test mode select (TMS), used as an input into the TAP controller
• TCK, used as the clock source for the JTAG circuitry
• TRST resets the TAP controller. This is an optional input pin defined by the 1149.1 standard.
The TRST pin is not present in the Cyclone device family.Note:
The bank of DRs is the primary data path of the JTAG circuitry. It carries the payload data for all JTAG
transactions. Each DRchain is dedicated to serving a specific function. Boundaryscan cells form the primary
DR chain. The other DR chains are used for identification, bypassing the IC during boundary scan tests, or
a custom set of register chains with functions defined by the IC vendor. Altera uses two of the DR chains
with user-defined IP that requires the JTAG chain as a communication resource, such as the on-chip
debugging applications. The Virtual JTAG megafunction, in particular, allows you to extend the two DR
chains to a user-defined custom application.
JTAG Circuitry Architecture
5
You use the instruction register to select the bank of Data Registers to which the TDI and TDO must connect.
It functions as an address register for the bank of Data Registers. Each IR instruction maps to a specific DR
chain.
All shift registers that area part of the JTAG circuitry (IR and DR register chains) are composedof two kinds
of registers: shift registers, which capture new serial shift input from the TDI pin, and parallel hold registers,
which connect to each shift register to hold the current input in place when shifting. The parallel hold
registers ensure stability in the output when new data is shifted.
The figure below shows a functional model of the JTAG circuitry. The TRST pin is an optional pin in the
1149.1 standard and not available in Cyclone devices. The TAP controller is a hard controller; it is not created
using programmable resources. The major function of the TAP controller is to route test data between the
IR and DR register chains.
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IR Shift Registers
IR Update Registers
DR Shift Register 1
DR Update Register 1
DR Shift Register 2
DR Update Register 2
DR Shift Register n
DR Update Register n
JTAG TAP
Controller
(2)
TDI TDO
Tap
Controller
Output (3)
Tap
Controller
Output (3)
TRST (1)
TCK
TMS
6
System-Level Debugging Infrastructure
Figure 3: Functional Model of the JTAG Circuitry
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System-Level Debugging Infrastructure
On-chip debugging tools that require the JTAG resources share two Data Register chain paths; USER1 and
USER0 instructions select the Data Register chain paths. The datapaths are anextension of theJTAG circuitry
for use with the programmable logic elements in Altera devices.
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Because the JTAG resource is shared among multiple on-chip applications, an arbitration scheme must
define how the USER0 and USER1 scan chains are allocated between the different applications. The systemlevel debugging (SLD) infrastructure defines the signaling convention and the arbitration logic for all
programmable logic applications using a JTAG resource. The figure below shows the SLD infrastructure
architecture.
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JTAG Tap
Controller
TC
TM
TD
TD
FPGA
SLD Node
SLD Node
SLD Node
SLD Node
SLD Hub
User’s Design
(Core Logic)
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Transaction Model of the SLD Infrastructure
Figure 4: System Level Debugging Infrastructure Functional Model
7
Transaction Model of the SLD Infrastructure
In the presence of an application that requires the JTAG resource, the Quartus II software automatically
implements the SLD infrastructure to handle the arbitration of the JTAG resource. The communication
interface between JTAG and any IP cores is transparent to the designer. All components of the SLD
infrastructure, except for the JTAG TAP controller, are built using programmable logic resources.
The SLD infrastructure mimics the IR/DR paradigm defined by the JTAG protocol. Each application
implements an Instruction Register, and a set of Data Registers that operate similarly to the Instruction
Register and Data Registers in the JTAG standard. Note that the Instruction Register and the Data Register
banks implemented by each application are a subset of the USER1 and USER0 Data Register chains. The SLD
infrastructure consists of three subsystems: the JTAG TAP controller, the SLD hub, and the SLD nodes.
The SLD hub acts as the arbiter that routes the TDI pin connection between each SLD node, and is a state
machine that mirrors the JTAG TAP controller state machine.
The SLDnodes represent thecommunication channels for theend applications. Each instanceof IP requiring
a JTAGcommunication resource, such as theSignalTap II Logic Analyzer, wouldhave its own communication
channel in the form of a SLD node interface to the SLD hub. Each SLD node instance has its own Instruction
Register and bank of DR chains. Up to 255 SLD nodes can be instantiated, depending on resources available
in your device.
Together, the sld_hub and the SLD nodes form a virtual JTAG scan chain within the JTAG protocol. It is
virtual in the sense that both the Instruction Register and DR transactions for each SLD node instance are
encapsulated within a standard DR scan shift of the JTAG protocol.
The Instruction Register and Data Registers for the SLD nodes are a subset of the USER1 and USER0 Data
Registers. Because the SLD Node IR/DR register set is not directly part of the IR/DR register set of the JTAG
protocol, the SLD node Instruction Register and Data Register chains are known as Virtual IR (VIR) and
Virtual DR (VDR) chains. The figure below shows the transaction model of the SLD infrastructure.
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IR Shift Registers
IR Update Registers
DR Shift Register 1
DR Update Register 1
USER 0 Data Registers
USER 1 Data Registers
TDI TDO
TAP
Controller
Output
TAP
Controller
Output
Altera PLD JTAG Extension
Altera PLD JTAG Extension
Node 1
Node N
USER0 / USER1 and
SLD_HUB Control Signals
TDI TDO
VIR
VDR 1
VDR N
VIR
VIR 1
VIR N
8
SLD Hub Finite State Machine
Figure 5: Extension of the JTAG Protocol for PLD Applications
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SLD Hub Finite State Machine
The SLDhub decodes TMS independently from the hard JTAGTAP controller state machineand implements
an equivalent state machine (calledthe “SLD hubfinite state machine”) for the internal JTAG path. The SLD
hub performs a similar function for the VIR and VDR chains that the TAP controller performs for the JTAG
IR and DR chains. It enables an SLD node as the active path for the TDI pin, selects the TDI data between
the VIR and VDR registers, controls the start and stop of any shift transactions, and controls the data flow
between the parallel hold registers and the parallel shift registers of the VIR and VDR.
Because all shifts to VIR and VDR are encapsulated within a DR shift transaction, an additional control
signal is necessary to select between the VIR and VDR data paths. The SLD hub uses the USER1 command
to select the VIR data path and the USER0 command to select the VDR data path.
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USR0 USR1
JTAG_Test_Logic_Reset
JTAG_Run_Test_Idle Virtual_Select_DR_Scan (1) Virtual_Select_IR_Scan (1)
Virtual_Capture_DR
Virtual_Shift_DR
Virtual_Exit1_DR
Virtual_Pause_DR
Virtual_Exit2_DR
Virtual_Update_DR
Virtual_Capture_IR
Virtual_Shift_IR (1)
Virtual_Exit1_IR (1)
Virtual_Pause_IR (1)
Virtual_Exit2_IR (1)
Virtual_Update_IR
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Description of the Virtual JTAG Interface
This state information, including a bank of enable signals, is forwarded to each of the SLD nodes. The SLD
nodes perform the updates to the VIR and VDR according to the control states provided by the sld_hub.
The SLD nodes are responsible for maintaining continuity between the TDI and TDO pins.
The figure below shows the SLD hub finite state machine. There is no direct state signal available to use for
application design.
Figure 6: sld_hub Finite State Machine
9
Description of the Virtual JTAG Interface
The Virtual JTAG Interface implements an SLD node interface, which provides a communication interface
Virtual JTAG Megafunction (sld_virtual_jtag)
to the JTAG port. The megafunction exposes control signals that are part of the SLD hub; namely, JTAG
port signals, all finite state machine controller states of the TAP controller, and the SLD hub finite state
machine. Additionally, each instance of the Virtual JTAG megafunctions contain the virtual Instruction
Register for the SLD node. Instantiation of this megafunction automatically infers the SLD infrastructure,
and one SLD node is added for each instantiation.
The Virtual JTAG megafunction provides a port interface that mirrors the actual JTAG ports. The interface
contains the JTAG port pins, a one-hot decoded output of all JTAG states, and a one-hot decoded output
of all the virtual JTAG states. Virtual JTAG states are the states decoded from the SLD hub finite state
machine. The ir_in and ir_out ports are the parallel input and output to and from the VIR. The VIR ports
are used toselect theactive VDR datapath. The JTAG states and TMSoutput ports are provided for debugging
purposes only. Only the virtual JTAG, TDI, TDO, and the IR signals are functional elements of the
megafunction. When configuring this megafunction using the MegaWizard™Plug-In Manager, you can
hide TMS and the decoded JTAG states.
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Inputs
One-Hot Decoded Outputs
from the SLD Hub FSM
One-Hot Decoded Outputs
from the TAP Controller
10
Input Ports
The figure below shows the input and output ports of the virtual JTAG megafunction. The JTAG TAP
controller outputs and TMS signals are used for informational purposes only. These signals can be exposed
using the Create primitive JTAG state signal ports option on page 3 of the MegaWizard Plug-In Manager.
Figure 7: Input and Output Ports of the Virtual JTAG Megafunction
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Input Ports
Table 2: Input Ports for the Virtual JTAG Megafunction
Yestdo
Writes to the TDO pin on the
device.
Noir_out[]
Virtual JTAG instruction register
output. The value is captured
whenever virtual_state_cir is
high.
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CommentsDescriptionRequiredPort name
Input port [SLD_IR_WIDTH-
1..0] wide. Specify the width
of this bus with the SLD_IR_
WIDTH parameter.
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Output Ports
Table 3: Output Ports for the Virtual JTAG Megafunction
Output Ports
CommentsDescriptionRequiredPort Name
11
JTAG test clock.Yestck
Yestdi
TDI inputdata on the device.Used
when virtual_state_sdr is high.
Noir_in[]
Virtual JTAG instruction register
data. The value is available and
latched when virtual_state_uir
is high.
Table 4: High-Level Virtual JTAG State Signals
Novirtual_state_cdr
Yesvirtual_state_sdr
Novirtual_state_e1dr
Indicates thatvirtual JTAG is in
Capture_DR state.
Indicates thatvirtual JTAG is in
Shift_DR state.
Indicates thatvirtual JTAG is in
Exit1_DR state.
Connected directly to the TCK
device pin. Shared among all
virtual JTAG instances.
Shared amongall virtual JTAG
instances.
Output port [SLD_IR_WIDTH-
1..0] wide. Specify the width
of this bus with the SLD_IR_
WIDTH parameter.
CommentsDescriptionRequiredPort Name
In this state, this instance is
required to establish the
JTAG chain for this device.
Virtual JTAG Megafunction (sld_virtual_jtag)
Novirtual_state pdr
Indicates thatvirtual JTAG is in
Pause_DR state.
The QuartusII software does
not cycle through this state
using the Tcl command.
Novirtual_state_e2dr
Indicates thatvirtual JTAG is in
Exit2_DR state.
The QuartusII software does
not cycle through this state
using the Tcl command.
Novirtual_state_udr
Indicates thatvirtual JTAG is in
Update_DR state.
Novirtual_state_cir
Indicates thatvirtual JTAG is in
Capture_IR state.
Novirtual_state_uir
Indicates thatvirtual JTAG is in
Update_IR state.
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Output Ports
Table 5: Low-Level Virtual JTAG State Signals
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CommentsDescriptionRequiredPort Name
Nojtag_state_tlr
Indicates that the device JTAG
controller is in the Test_Logic_
Shared among all virtual
JTAG instances.
Reset state.
Nojtag_state_rti
Indicates that the device JTAG
controller is in the Run_Test/
Shared among all virtual
JTAG instances.
Idle state.
Nojtag_state_sdrs
Indicates that the device JTAG
controller is in the Select_DR_
Shared among all virtual
JTAG instances.
Scan state.
Nojtag_state_cdr
Indicates that the device JTAG
controller is in the Capture_DR
Shared among all virtual
JTAG instances.
state.
Nojtag_state_sdr
Indicates that the device JTAG
controller is in the Shift_DR
Shared among all virtual
JTAG instances.
state.
Nojtag_state_e1dr
Indicates that the device JTAG
controller is in the Exit1_DR
Shared among all virtual
JTAG instances.
state.
Nojtag_state_pdr
Indicates that the device JTAG
controller is in the Pause_DR
Shared among all virtual
JTAG instances.
state.
Nojtag_state_e2dr
Indicates that the device JTAG
controller is in the Exit2_DR
Shared among all virtual
JTAG instances.
state.
Nojtag_state_udr
Indicates that the device JTAG
controller is in the Update_DR
Shared among all virtual
JTAG instances.
state.
Nojtag_state_sirs
Indicates that the device JTAG
controller is in the Select_IR_
Shared among all virtual
JTAG instances.
Scan state.
Nojtag_state_cir
Indicates that the device JTAG
controller is in the Capture_IR
Shared among all virtual
JTAG instances.
state.
Nojtag_state_sir
Indicates that the device JTAG
controller is in the Shift_IR
Shared among all virtual
JTAG instances.
state.
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Parameters
CommentsDescriptionRequiredPort Name
13
Nojtag_state_e1ir
Indicates that the device JTAG
controller is in the Exit1_IR
state.
Nojtag_state_pir
Indicates that the device JTAG
controller is in the Pause_IR
state.
Nojtag_state_e2ir
Indicates that the device JTAG
controller is in the Exit2_IR
state.
jtag_state_uir
Indicates that the device JTAG
controller is in the Update_IR
state.
TMS input pin on the device.tms
Parameters
Table 6: Parameters for the Virtual JTAG Megafunction
Shared among all virtual
JTAG instances.
Shared among all virtual
JTAG instances.
Shared among all virtual
JTAG instances.
Shared among all virtual
JTAG instances.
Shared among all virtual
JTAG instances.
DescriptionRequiredTypeParameter
YesStringSLD_AUTO_INSTANCE_INDEX
Specifies whether the Compiler automatically
assigns an index to the Virtual JTAG instance.
Values are YES or NO. When you specify NO,
you can find the auto assigned value of
INSTANCE_ID in the quartus_map file. When
you specify NO, you must define INSTANCE_
INDEX. If the index specified is not unique in a
design, the Compiler automatically reassigns
an index to the instance. The default value is
YES.
NoIntegerSLD_INSTANCE_INDEX
Specifies a unique identifier for every instance
of alt_virtual_jtag when AUTO_INSTANCE_
ID is specified to YES. Otherwise, this value is
ignored.
YesIntegerSLD_IR_WIDTH
Specifies the width of the instruction register
ir_in[] of this virtual JTAG between 1 and 24.
If omitted, the default is 1.
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