Altera Unique Chip ID User Manual
2014.09.02
www.altera.com
101 Innovation Drive, San Jose, CA 95134
Altera Unique Chip ID IP Core User Guide
ug-altchipid
Subscribe
The Altera Unique Chip ID (ALTCHIP_ID) IP core allows you to uniquely identify the target FPGA before
device programming. This protects your device from receiving unauthorized programming data. Use the
IP Catalog and parameter editor to customize and generate the ALTCHIP_ID IP core.
The chip ID block has a 64 bit unique ID per die. The unique chip ID is read out from a 90 bit circular shift
register by a three pin serial interface. The initial 64 bits contain the unique ID value. The last 26 bits are a
concatenation of various fuse bits set during the manufacturing flow; these bits have Altera reserved values.
The Unique Chip ID register is implemented as a barrel shift register. For more information about customizing
IP cores.
This IP core is not supported for Arria 10 designs.Note:
Related Information
• Introduction to Altera IP Cores
• Altera IP Release Notes
Functional Description
Send Feedback
At the initial state, the data_valid signal is low because no data is read from the chip ID block. After feeding
a clock signal to the clkin input port, the ALTCHIP_ID IP core begins to acquire the unique chip ID via
the chip ID block. After acquiring the unique chip ID, the IP core asserts the data_valid signal to indicate
that the unique chip ID value at the output port is ready for retrieval.
The operation repeats only when you provide another clock signal while the data_valid signal is low. If
the data_valid signal is high when you provide another clock signal, the operation stops because the
chip_id[63..0] output holds the chip ID.
A minimum of 67 clock cycles are required for the data_valid signal to go high.
The chip_id [63:0]output port holds the value of the unique chip ID until you reconfigure the device or
reset the IP core.
Installing and Licensing IP Cores
The Altera IP Library provides many useful IP core functions for production use without purchasing an
additional license. You can evaluate any Altera IP core in simulation and compilation in the Quartus II
software using the OpenCore evaluation feature. Some Altera IP cores, such as MegaCore®functions, require
©
2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
ISO
9001:2008
Registered
acds
quartus - Contains the Quartus II software
ip - Contains the Altera IP Library and third-party IP cores
altera - Contains the Altera IP Library source code
<IP core name> - Contains the IP core source files
2
Customizing and Generating IP Cores
that you purchase a separate license for production use. You can use the OpenCore Plus feature to evaluate
IP that requires purchase of an additional license until you are satisfied with the functionality and performance.
After you purchase a license, visit the Self Service Licensing Center to obtain a license number for any Altera
product.
Figure 1: IP Core Installation Path
ug-altchipid
2014.09.02
Note:
The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it
is <home directory>/altera/ <version number>.
Related Information
• Altera Licensing Site
• Altera Software Installation and Licensing Manual
Customizing and Generating IP Cores
You can customize IP cores to support a wide variety of applications. The Quartus II IP Catalog and parameter
editor allow you to quickly select and configure IP core ports, features, and output files.
IP Catalog and Parameter Editor (replaces MegaWizard Plug-In Manager)
The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and integrate
IP cores into your project. You can use the IP Catalog and parameter editor to select, customize, and generate
files representing your custom IP variation.
Note:
The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard™Plug-In Manager
for IP selection and parameterization, beginning in Quartus II software version 14.0. Use the IP
Catalog and parameter editor to locate and paramaterize Altera IP cores.
The IP Catalog lists IP cores available for your design. Double-click any IP core to launch the parameter
editor and generate files representing your IP variation. The parameter editor prompts you to specify an IP
variation name, optional ports, and output file generation options. The parameter editor generates a toplevel Qsys system file (.qsys) or Quartus II IP file (.qip) representing the IP core in your project. You can
also parameterize an IP variation without an open project.
Use the following features to help you quickly locate and select an IP core:
• Filter IP Catalog to Show IP for active device family or Show IP for all device families.
• Search to locate any full or partial IP core name in IP Catalog. Click Search for Partner IP, to access
partner IP information on the Altera website.
• Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's
installation folder, andor view links to documentation.
Altera Corporation
Altera Unique Chip ID IP Core User Guide
Send Feedback
Search and filter IP for your target device
Double-click to customize, right-click for information
ug-altchipid
2014.09.02
Figure 2: Quartus II IP Catalog
Using the Parameter Editor
3
Note:
The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes exclusive
system interconnect, video and image processing, and other system-level IP that are not available in
the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, refer to Creating
a System with Qsys in the Quartus II Handbook.
Related Information
• Creating a System with Qsys
Using the Parameter Editor
The parameter editor helps you to configure IP core ports, parameters, and output file generation options.
• Use preset settings in the parameter editor (where provided) to instantly apply preset parameter values
for specific applications.
• View port and parameter descriptions, and links to documentation.
• Generate testbench systems or example designs (where provided).
Altera Unique Chip ID IP Core User Guide
Send Feedback
Altera Corporation
View IP port
and parameter
details
Apply preset parameters for
specific applications
Specify your IP variation name
and target device
Legacy parameter
editors
4
Using the Parameter Editor
Figure 3: IP Parameter Editors
ug-altchipid
2014.09.02
Altera Corporation
Altera Unique Chip ID IP Core User Guide
Send Feedback
Loading...