Altera Triple Speed Ethernet MegaCore Function User Manual

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Triple-Speed Ethernet MegaCore Function

User Guide

Last updated for Altera Complete Design Suite: 14.0

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TOC-2

Triple-Speed Ethernet MegaCore Function User Guide

About This MegaCore Function.........................................................................1-1

About This MegaCore Function................................................................................................................1-1

Device Family Support................................................................................................................................1-1

Features.........................................................................................................................................................1-1

10/100/1000 Ethernet MAC Versus Small MAC.....................................................................................1-2

High-Level Block Diagrams........................................................................................................................1-3

Example Applications..................................................................................................................................1-5

MegaCore Verification................................................................................................................................1-6

Optical Platform...............................................................................................................................1-7

Copper Platform...............................................................................................................................1-7

Performance and Resource Utilization.....................................................................................................1-7

Release Information...................................................................................................................................1-11

Getting Started with Altera IP Cores..................................................................2-1

Introduction to Altera IP Cores.................................................................................................................2-1

Installing and Licensing IP Cores..............................................................................................................2-1

OpenCore Plus IP Evaluation....................................................................................................................2-2

Upgrading Outdated IP Cores...................................................................................................................2-2

IP Catalog and Parameter Editor...............................................................................................................2-4

Using the Parameter Editor............................................................................................................2-5

Design Walkthrough...................................................................................................................................2-6

Creating a New Quartus II Project................................................................................................2-6

Specifying IP Core Parameters and Options................................................................................2-7

Generating a Design Example or Simulation Model..................................................................2-7

Simulate the System.........................................................................................................................2-8

Compiling the Triple-Speed Ethernet MegaCore Function Design.........................................2-8

Programming an FPGA Device.....................................................................................................2-8

Generated Files.............................................................................................................................................2-9

Design Constraint File No Longer Generated...........................................................................2-10

Parameter Settings..............................................................................................3-1

Altera Corporation

Parameter Settings.......................................................................................................................................3-1

Core Configuration......................................................................................................................................3-1

Triple-Speed Ethernet MegaCore Function User Guide

TOC-3

Ethernet MAC Options...............................................................................................................................3-2

FIFO Options................................................................................................................................................3-4

Timestamp Options.....................................................................................................................................3-5

PCS/Transceiver Options...........................................................................................................................3-5

Functional Description.......................................................................................4-1

10/100/1000 Ethernet MAC.......................................................................................................................4-1

MAC Architecture...........................................................................................................................4-2

MAC Interfaces................................................................................................................................4-3

MAC Transmit Datapath................................................................................................................4-4

MAC Receive Datapath...................................................................................................................4-7

MAC Transmit and Receive Latencies........................................................................................4-11

FIFO Buffer Thresholds................................................................................................................4-12

Congestion and Flow Control......................................................................................................4-16

Magic Packets.................................................................................................................................4-17

MAC Local Loopback....................................................................................................................4-18

MAC Error Correction Code.......................................................................................................4-19

MAC Reset......................................................................................................................................4-19

PHY Management (MDIO).........................................................................................................4-20

Connecting MAC to External PHYs...........................................................................................4-22

1000BASE-X/SGMII PCS With Optional Embedded PMA................................................................4-24

1000BASE-X/SGMII PCS Architecture......................................................................................4-25

Transmit Operation.......................................................................................................................4-26

Receive Operation..........................................................................................................................4-27

Transmit and Receive Latencies...................................................................................................4-28

SGMII Converter...........................................................................................................................4-28

Auto-Negotiation...........................................................................................................................4-29

Ten-bit Interface............................................................................................................................4-32

PHY Loopback...............................................................................................................................4-33

PHY Power-Down.........................................................................................................................4-33

1000BASE-X/SGMII PCS Reset...................................................................................................4-34

Altera IEEE 1588v2 Feature......................................................................................................................4-35

IEEE 1588v2 Supported Configurations.....................................................................................4-35

IEEE 1588v2 Features....................................................................................................................4-36

IEEE 1588v2 Architecture.............................................................................................................4-37

IEEE 1588v2 Transmit Datapath.................................................................................................4-37

IEEE 1588v2 Receive Datapath....................................................................................................4-38

IEEE 1588v2 Frame Format.........................................................................................................4-38

Altera Corporation

TOC-4

Triple-Speed Ethernet MegaCore Function User Guide

Triple-Speed Ethernet with IEEE 1588v2 Design Example................................5-1

Software Requirements...............................................................................................................................5-1

Triple-Speed Ethernet with IEEE 1588v2 Design Example Components...........................................5-2

Base Addresses..................................................................................................................................5-3

Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Files...............................................5-3

Creating a New Triple-Speed Ethernet MAC with IEEE 1588v2 Design............................................5-4

Triple-Speed Ethernet with IEEE 1588v2 Testbench .............................................................................5-4

Triple-Speed Ethernet with IEEE 1588v2 Testbench Files.........................................................5-5

Triple-Speed Ethernet with IEEE 1588v2 Testbench Simulation Flow....................................5-5

Simulating Triple-Speed Ethernet with IEEE 1588v2 Testbench with ModelSim

Simulator.....................................................................................................................................5-6

Configuration Register Space.............................................................................6-1

MAC Configuration Register Space..........................................................................................................6-1

Base Configuration Registers (Dword Offset 0x00 – 0x17).......................................................6-3

Statistics Counters (Dword Offset 0x18 – 0x38).......................................................................6-11

Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)............................6-13

Supplementary Address (Dword Offset 0xC0 – 0xC7)............................................................6-15

IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6).................................................................6-16

IEEE 1588v2 Feature PMA Delay................................................................................................6-17

PCS Configuration Register Space..........................................................................................................6-18

Control Register (Word Offset 0x00)..........................................................................................6-20

Status Register (Word Offset 0x01).............................................................................................6-22

Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05)................................6-23

An_Expansion Register (Word Offset 0x06).............................................................................6-26

If_Mode Register (Word Offset 0x14)........................................................................................6-26

Register Initialization................................................................................................................................6-27

Triple-Speed Ethernet System with MII/GMII or RGMII.......................................................6-28

Triple-Speed Ethernet System with SGMII................................................................................6-30

Triple-Speed Ethernet System with 1000BASE-X Interface....................................................6-31

Interface Signals..................................................................................................7-1

Altera Corporation

Interface Signals...........................................................................................................................................7-1

10/100/1000 Ethernet MAC Signals..............................................................................................7-2

10/100/1000 Multiport Ethernet MAC Signals..........................................................................7-12

10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals.....................................7-16

Triple-Speed Ethernet MegaCore Function User Guide

10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals...................7-20

10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA

Signals........................................................................................................................................7-22

10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded

PMA...........................................................................................................................................7-25

1000BASE-X/SGMII PCS Signals................................................................................................7-34

1000BASE-X/SGMII PCS and PMA Signals..............................................................................7-38

Timing.........................................................................................................................................................7-39

Avalon-ST Receive Interface........................................................................................................7-39

Avalon-ST Transmit Interface.....................................................................................................7-41

GMII Transmit...............................................................................................................................7-41

GMII Receive..................................................................................................................................7-41

RGMII Transmit............................................................................................................................7-42

RGMII Receive...............................................................................................................................7-42

MII Transmit..................................................................................................................................7-43

MII Receive.....................................................................................................................................7-43

IEEE 1588v2 Timestamp...............................................................................................................7-43

TOC-5

Design Considerations........................................................................................8-1

Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA.............................8-1

MAC and PCS With GX Transceivers..........................................................................................8-2

MAC and PCS With LVDS Soft-CDR I/O...................................................................................8-4

Sharing PLLs in Devices with LVDS Soft-CDR I/O................................................................................8-6

Sharing PLLs in Devices with GIGE PHY................................................................................................8-6

Sharing Transceiver Quads.........................................................................................................................8-7

Migrating From Old to New User Interface For Existing Designs.......................................................8-7

Exposed Ports in the New User Interface.....................................................................................8-7

Timing Constraints.............................................................................................9-1

Creating Clock Constraints........................................................................................................................9-1

Recommended Clock Frequency...............................................................................................................9-3

Testbench...........................................................................................................10-1

Triple-Speed Ethernet Testbench Architecture ....................................................................................10-1

Testbench Components............................................................................................................................10-1

Testbench Verification..............................................................................................................................10-2

Testbench Configuration..........................................................................................................................10-3

Altera Corporation

TOC-6

Triple-Speed Ethernet MegaCore Function User Guide

Test Flow.....................................................................................................................................................10-3

Simulation Model......................................................................................................................................10-4

Generate the Simulation Model...................................................................................................10-4

Simulate the IP Core......................................................................................................................10-4

Simulation Model Files.................................................................................................................10-5

Software Programming Interface.....................................................................11-1

Driver Architecture...................................................................................................................................11-1

Directory Structure....................................................................................................................................11-2

PHY Definition .........................................................................................................................................11-2

Using Multiple SG-DMA Descriptors....................................................................................................11-4

Using Jumbo Frames.................................................................................................................................11-4

API Functions.............................................................................................................................................11-5

alt_tse_mac_get_common_speed().............................................................................................11-5

alt_tse_mac_set_common_speed().............................................................................................11-5

alt_tse_phy_add_profile()............................................................................................................11-6

alt_tse_system_add_sys().............................................................................................................11-6

triple_speed_ethernet_init().........................................................................................................11-7

tse_mac_close()..............................................................................................................................11-7

tse_mac_raw_send()......................................................................................................................11-8

tse_mac_setGMII mode().............................................................................................................11-9

tse_mac_setMIImode().................................................................................................................11-9

tse_mac_SwReset()........................................................................................................................11-9

Constants..................................................................................................................................................11-10

Ethernet Frame Format......................................................................................A-1

Simulation Parameters.......................................................................................B-1

Time-of-Day (ToD) Clock..................................................................................C-1

Altera Corporation

Basic Frame Format....................................................................................................................................A-1

VLAN and Stacked VLAN Frame Format..............................................................................................A-1

Pause Frame Format...................................................................................................................................A-3

Pause Frame Generation................................................................................................................A-3

Functionality Configuration Parameters.................................................................................................B-1

Test Configuration Parameters.................................................................................................................B-3

ToD Clock Features....................................................................................................................................C-1

Triple-Speed Ethernet MegaCore Function User Guide

ToD Clock Device Family Support...........................................................................................................C-1

ToD Clock Performance and Resource Utilization................................................................................C-1

ToD Clock Parameter Setting....................................................................................................................C-2

ToD Clock Interface Signals......................................................................................................................C-3

ToD Clock Avalon-MM Control Interface Signals....................................................................C-3

ToD Clock Avalon-ST Transmit Interface Signals.....................................................................C-4

ToD Clock Configuration Register Space................................................................................................C-5

Adjusting ToD Clock Drift............................................................................................................C-6

TOC-7

ToD Synchronizer..............................................................................................D-1

ToD Synchronizer Block............................................................................................................................D-2

ToD Synchronizer Parameter Settings.....................................................................................................D-3

ToD Synchronizer Signals.........................................................................................................................D-4

ToD Synchronizer Common Clock and Reset Signals..............................................................D-4

ToD Synchronizer Interface Signals.............................................................................................D-4

Packet Classifier..................................................................................................E-1

Packet Classifier Block................................................................................................................................E-1

Packet Classifier Signals..............................................................................................................................E-2

Packet Classifier Common Clock and Reset Signals..................................................................E-2

Packet Classifier Avalon-ST Interface Signals.............................................................................E-2

Packet Classifier Ingress Control Signals.....................................................................................E-3

Packet Classifier Control Insert Signals........................................................................................E-4

Packet Classifier Timestamp Field Location Signals..................................................................E-5

Additional Information......................................................................................F-1

Document Revision History.......................................................................................................................F-2

How to Contact Altera................................................................................................................................F-7

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2014.06.30

www.altera.com

101 Innovation Drive, San Jose, CA 95134

About This MegaCore Function

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About This MegaCore Function

The Altera®Triple-Speed Ethernet MegaCore®function is a configurable intellectual property (IP) core that complies with the IEEE 802.3 standard. The IP core was tested and successfully validated by the University of New Hampshire (UNH) interoperability lab. It combines the features of a 10/100/1000-Mbps Ethernet media access controller (MAC) and 1000BASE-X/SGMII physical coding sublayer (PCS) with an optional physical medium attachment (PMA).

Device Family Support

For new additions and enhancements to the latest Quartus II software and Altera IP, refer to the What’s

New for Altera IP page of the Altera website.

For a list of IP support for all device families, refer to the All Intellectual Property page of the Altera website.

Features

• Complete triple-speed Ethernet IP: 10/100/1000-Mbps Ethernet MAC, 1000BASE-X/SGMII PCS, and embedded PMA.

• Successful validation from the University of New Hampshire (UNH) InterOperability Lab.

• 10/100/1000-Mbps Ethernet MAC features:

• Multiple variations: 10/100/1000-Mbps Ethernet MAC in full duplex, 10/100-Mbps Ethernet MAC

in half duplex, 10/100-Mbps or 1000-Mbps small MAC (resource-efficient variant), and multiport MAC that supports up to 24 ports.

• Support for basic, VLAN, stacked VLAN, and jumbo Ethernet frames. Also supports control frames

including pause frames.

• Optional internal FIFO buffers, depth from 64 bytes to 256 Kbytes.

• Optional statistics counters.

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO 9001:2008 Registered

1-2

10/100/1000 Ethernet MAC Versus Small MAC

• 1000BASE-X/SGMII PCS features:

• Compliance with Clause 36 of the IEEE standard 802.3.

• Optional embedded PMA implemented with serial transceiver or LVDS I/O and soft CDR in Altera

devices that support this interface at 1.25-Gbps data rate.

• Support for auto-negotiation as defined in Clause 37.

• Support for connection to 1000BASE-X PHYs. Support for 10BASE-T, 100BASE-T, and 1000BASE-

T PHYs if the PHYs support SGMII.

• MAC interfaces:

• Client side—8-bit or 32-bit Avalon®Streaming (Avalon-ST)

• Network side—medium independent interface (MII), gigabit medium independent interface (GMII),

or reduced gigabit medium independent interface (RGMII) on the network side. Optional loopback on these interfaces.

• Optional management data I/O (MDIO) master interface for PHY device management.

• PCS interfaces:

• Client side—MII or GMII

• Network side—ten-bit interface (TBI) for PCS without PMA; 1.25-Gbps serial interface for PCS with

PMA implemented with serial transceiver or LVDS I/O and soft CDR in Altera devices that support this interface at 1.25-Gbps data rate.

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• Programmable features via 32-bit configuration registers:

• FIFO buffer thresholds.

• Pause quanta for flow control.

• Source and destination MAC addresses.

• Address filtering on receive, up to 5 unicast and 64 multicast MAC addresses.

• Promiscuous mode—receive frame filtering is disabled in this mode.

• Frame length—in MAC only variation, up to 64 Kbytes including jumbo frames. In all variants

containing 1000BASE-X/SGMII PCS, the frame length is up to 10 Kbytes.

• Optional auto-negotiation for the 1000BASE-X/SGMII PCS.

• Error correction code protection feature for internal memory blocks.

• Optional IEEE 1588v2 feature for 10/100/1000-Mbps Ethernet MAC with SGMII PCS and embedded

serial PMA variation operating without internal FIFO buffer in full-duplex mode, 10/100/1000-Mbps MAC with SGMII PCS and embedded LVDS I/O, or MAC only variation operating without internal FIFO buffer in full-duplex mode. These features are supported in Arria V, Arria 10, Cyclone V, MAX 10, and Stratix V device families.

10/100/1000 Ethernet MAC Versus Small MAC

Table 1-1: Feature Comparison between 10/100/1000 Ethernet MAC and Small MAC

Small MAC10/100/1000 Ethernet MACFeature

interfaces

Altera Corporation

10/100 Mbps or 1000 MbpsTriple speed (10/100/1000 Mbps)Speed

MII/GMII or RGMIIExternal

MII only for 10/100 Mbps small MAC, GMII or RGMII for 1000 Mbps small MAC

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10/100/1000-Mbps

Ethernet MAC

MII/GMII/RGMII

Client Side

Network Side

Avalon-ST

(Transmitand Receive)

Avalon-MM

(Management and Control)

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High-Level Block Diagrams

Small MAC10/100/1000 Ethernet MACFeature

1-3

interface registers

options

Fully programmableControl

Limited programmable options. The following options are fixed:

• Maximum frame length is fixed to 1518. Jumbo frames are not supported.

• FIFO buffer thresholds are set to fixed values.

• Store and forward option is not available.

• Interpacket gap is set to 12.

• Flow control is not supported; pause quanta is not in

use.

• Checking of payload length is disabled.

• Supplementary MAC addresses are disabled.

• Padding removal is disabled.

• Sleep mode and magic packet detection is not

supported.

Fully configurableSynthesis

Limited configurable options. The following options are NOT available:

• Flow control

• VLAN

• Statistics counters

• Multicast hash table

• Loopback

• TBI and 1.25 Gbps serial interface

• 8-bit wide FIFO buffers

High-Level Block Diagrams

About This MegaCore Function

High-level block diagrams of different variations of the Triple-Speed Ethernet MegaCore function.

Figure 1-1: 10/100/1000-Mbps Ethernet MAC

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10/100/1000-Mbps

Ethernet MAC

MII/GMII/RGMII

Client Side

Network Side

Avalon-ST

(Transmitand Receive)

Avalon-MM

(Management and Control)

10/100/1000-Mbps

Ethernet MAC

MII/GMII/RGMII

Avalon-ST

(Transmitand Receive)

Multi-Port MAC

10/100/1000-Mbps

Ethernet MAC

MII/ GMII

Client Side

Network Side

Avalon-ST

(Transmitand

Receive)

Avalon-MM

(Management

and Control)

1.25-Gbps Serial

MAC and PCS with Optional Embedded PMA

1000BASE-X/SGMII

PCS

PMA

(Optional)

TBI

MII/GMII

Client Side

Network Side

1.25-Gbps Serial

PCS with Optional Embedded PMA

1000BASE-X/SGMII

PCS

PMA

(Optional)

TBI

1-4

High-Level Block Diagrams

Figure 1-2: Multi-port MAC

Figure 1-3: 10/100/1000-Ethernet MAC and 1000BASE-X/SGMII PCS with Optional PMA

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Figure 1-4: 1000BASE-X/SGMII PCS with Optional PMA

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Gigabit or Fast

Ethernet PHY

Device

User

Application

Host Interface MDIO Master

Altera Device

Triple-Speed Ethernet MegaCore Function

Management

Application

MDIO

Copper

MII/GMII/RGMII

Avalon-STAvalon-MM

10/100/1000-Mbps

Ethernet MAC

Gigabit or Fast

Ethernet PHY

Device

User

Application

Host Interface MDIO Master

Altera Device

Triple-Speed Ethernet MegaCore Function

Management

Application

MDIO

Copper

MII/GMII/RGMII

Avalon-STAvalon-MM

10/100/1000-Mbps

Ethernet MAC

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Figure 1-5: Stand-Alone 10/100/1000 Mbps Ethernet MAC

Example Applications

1-5

This section shows example applications of different variations of the Triple-Speed Ethernet MegaCore function.

The 10/100/1000-Gbps Ethernet MAC only variation can serve as a bridge between the user application and standard fast or gigabit Ethernet PHY devices.

Figure 1-6: Stand-Alone 10/100/1000 Mbps Ethernet MAC

Example application using this variation for a copper network.

When configured to include the 1000BASE-X/SGMII PCS function, the MegaCore function can seamlessly connect to any industry standard gigabit Ethernet PHY device via a TBI. Alternatively, when the 1000BASEX/SGMII PCS function is configured to include an embedded PMA, the MegaCore function can connect

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GMII

PMA

Fiber

GBIC/SFP

Module

1.25

Gbps

Serial

Altera Device

Triple-SpeedEthernet MegaCore Function

TBI

10/100/1000-Mbps

Ethernet MAC

1000BASE-X

PCS

Copper

MII/GMII

SGMII PCS PMA

10/100/1000

1.25 Gbps

SGMII

Altera Device

TBI

Triple-SpeedEthernet MegaCore Function

BASE-T PHY

10/100/1000-Mbps

Ethernet MAC

1-6

MegaCore Verification

directly to a gigabit interface converter (GBIC), small form-factor pluggable (SFP) module, or an SGMII PHY.

Figure 1-7: 10/100/1000 Mbps Ethernet MAC and 1000BASE-X PCS with Embedded PMA

Example application using the Triple-Speed Ethernet MegaCore function with 1000BASE-X and PMA. The PMA block connects to an off-the-shelf GBIC or SFP module to communicate directly over the optical link.

Figure 1-8: 10/100/1000 Mbps Ethernet MAC and SGMII PCS with Embedded PMA—GMII/MII to 1.25-Gbps Serial Bridge Mode

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Example application using the Triple-Speed Ethernet MegaCore function with 1000BASE-X and PMA, in which the PCS function is configured to operate in SGMII mode and acts as a GMII-to-SGMII bridge. In this case, the transceiver I/O connects to an off-the-shelf Ethernet PHY that supports SGMII (10BASE-T, 100BASE-T, or 1000BASE-T Ethernet PHY).

MegaCore Verification

For each release, Altera verifies the Triple-Speed Ethernet MegaCore function through extensive simulation and internal hardware verification in various Altera device families. The University of New Hampshire (UNH) InterOperability Lab also successfully verified the MegaCore function prior to its release.

Altera used a highly parameterizeable transaction-based testbench to test the following aspects of the

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MegaCore function:

• Register access

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• MDIO access

• Frame transmission and error handling

• Frame reception and error handling

• Ethernet frame MAC address filtering

• Flow control

• Retransmission in half-duplex

Altera has also validated the Triple-Speed Ethernet MegaCore function in both optical and copper platforms using the following development kits:

• Altera Nios II Development Kit, Cyclone II Edition (2C35)

• Altera Stratix III FPGA Development Kit

• Altera Stratix IV FPGA Development Kit

• Quad 10/100/1000 Marvell PHY

• MorethanIP 10/100 and 10/100/1000 Ethernet PHY Daughtercards

Optical Platform

In the optical platform, the 10/100/1000 Mbps Ethernet MAC, 1000BASE-X/SGMII PCS, and PMA functions are instantiated.

The FPGA application implements the Ethernet MAC, the 1000BASE-X PCS, and an internal system using Ethernet connectivity. This internal system retrieves all frames received by the MAC function and returns them to the sender by manipulating the MAC address fields, thus implementing a loopback. A direct connection to an optical module is provided through an external SFP optical module. Certified 1.25 GBaud optical SFP transceivers are Finisar 1000BASE-SX FTLF8519P2BNL, Finisar 1000BASE-LX FTRJ-1319-3, and Avago Technologies AFBR-5710Z.

Optical Platform

1-7

Copper Platform

In the copper platform, Altera tested the Triple-Speed Ethernet MegaCore function with an external 1000BASE-T PHY devices. The MegaCore function is connected to the external PHY device using MII, GMII, RGMII, and SGMII, in conjunction with the 1000BASE-X/SGMII PCS and PMA functions.

A 10/100/1000 Mbps Ethernet MAC and an internal system are implemented in the FPGA. The internal system retrieves all frames received by the MAC function and returns them to the sender by manipulating the MAC address fields, thus implementing a loopback. A direct connection to an Ethernet link is provided through a combined MII to an external PHY module. Certified 1.25 GBaud copper SFP transceivers are Finisar FCMJ-8521-3, Methode DM7041, and Avago Technologies ABCU-5700RZ.

Performance and Resource Utilization

In the following tables, the f

of the configurations is more than 125 MHz.

MAX

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1-8

Performance and Resource Utilization

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Table 1-2: Arria II GX Performance and Resource Utilization

The estimated resource utilization and performance of the Triple-Speed Ethernet MegaCore function for the Arria II GX device family. The estimates are obtained by compiling the Triple-Speed Ethernet MegaCore function using the Quartus II software targeting an Arria II GX (EP2AGX260EF29I3) device with speed grade -3.

SettingsMegaCore Function

FIFO Buffer

Size (Bits)

Combina-

tional ALUTs

Logic

Registers

Memory

(M9K Blocks/

M144K Blocks/

MLAB Bits)

10/100/1000-Mbps Ethernet MAC

All MAC options enabled

26/0/1828394733572048x32RGMII

Full and half-duplex modes supported

8-port 10/100/1000Mbps Ethernet MAC

enabled

Full and half-duplex modes

32/0/146242229220201—MII/GMII All MAC options

supported

0/0/0661624—1000BASE-X

1000BASE-X/ SGMII PCS

1/0/16012141191—1000BASE-X SGMII bridge

enabled PMA block (GXB)

Table 1-3: Stratix IV Performance and Resource Utilization

The estimated resource utilization and performance of the Triple-Speed Ethernet MegaCore function for the Stratix IV device family. The estimates are obtained by compiling the Triple-Speed Ethernet MegaCore function using the Quartus II software targeting a Stratix IV GX (EP4SGX530NF45C4) device with speed grade -4.

Memory

(M9K Blocks/ M144K

Blocks/MLAB Bits)

Function

SettingsMegaCore

FIFO Buffer

Size (Bits)

Combina-

tional ALUTs

Logic

Registers

10/100Mbps Small MAC

1000-Mbps Small MAC

Altera Corporation

12/1/1408212714102048x32MII

Full and half-duplex modes supported

12/1/128189411572048x32MII All MAC options enabled

12/1/176182711602048x32GMII All MAC options enabled

12/1/176186111702048x32RGMII All MAC options enabled

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Performance and Resource Utilization

1-9

Function

10/100/ 1000-Mbps Ethernet MAC

12-port 10/ 100/1000Mbps Ethernet MAC

100/1000Mbps Ethernet MAC

SettingsMegaCore

MII/GMII Full and half-duplex modes supported

enabled

MII/GMII All MAC options enabled

FIFO Buffer

Size (Bits)

Combina-

tional ALUTs

Logic

Registers

Memory

(M9K Blocks/ M144K

Blocks/MLAB Bits)

0/0/336433952721—

8/0/3620397732012048x8

12/1/3364442533452048x32

12/1/2084399431252048x32MII/GMII All MAC options

12/1/2084402131332048x32RGMII All MAC options enabled

0/0/250083437227215—

0/0/500166840454123—24-port 10/

0/0/0661624—1000BASE-X

2/0/0986808—1000BASE-X SGMII bridge

1000BASEX/SGMII PCS

enabled

2/0/01057819—1000BASE-X SGMII bridge

enabled PMA block (LVDS_IO)

1/0/16012121189—1000BASE-X SGMII bridge

enabled PMA block (GXB)

10/100/ 1000-Mbps

bridge enabled

14/1/2084495039712048×32All MAC options enabled SGMII

Ethernet MAC and 1000BASEX/SGMII PCS

Table 1-4: Cyclone IV GX Performance and Resource Utilization

The estimated resource utilization and performance of the Triple Speed Ethernet MegaCore function for the Cyclone IV device family. The estimates are obtained by compiling the Triple-Speed Ethernet MegaCore function using the Quartus II software targeting a Cyclone IV GX (EP4CGX150DF27C7) device with speed grade -7.

Memory

(M9K Blocks/ Mi44K

Blocks/ MLAB Bits)

Function

SettingsMegaCore

FIFO Buffer

Size (Bits)

Logic

Elements

Logic

Registers

1000-Mbps Small MAC

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supported

24/0/0169921612048x32RGMII Only full-duplex mode

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Performance and Resource Utilization

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Memory

(M9K Blocks/ Mi44K

Blocks/ MLAB Bits)

31/0/0366656142048x32MII/GMII Full and half-duplex

Function

10/100/ 1000-Mbps

SettingsMegaCore

modes supported

FIFO Buffer

Size (Bits)

Logic

Elements

Logic

Registers

Ethernet MAC

4-port 10/ 100/ 1000Mbps Ethernet MAC

1000BASEX/SGMII PCS

enabled

Full and half-duplex modes supported

enabled PMA block (GXB)

36/0/01061217017—MII/GMII All MAC options

0/0/06611149—1000BASE-X

2/0/011272001—1000BASE-X SGMII bridge

Table 1-5: Stratix V Performance and Resource Utilization

The estimated resource utilization and performance of the Triple-Speed Ethernet MegaCore function for the Stratix V device family. The estimates are obtained by compiling the Triple-Speed Ethernet MegaCore function using the Quartus II software targeting a Stratix V GX (5SGXMA7N3F45C3) device with speed grade -3.

Memory

(M20K Blocks/ MLAB

Bits)

Function

SettingsMegaCore

FIFO Buffer

Size (Bits)

Combina-

tional ALUTs

Logic

Registers

10/100Mbps Small MAC

1000-Mbps Small MAC

10/100/ 1000-Mbps Ethernet MAC

Full and half-duplex modes supported

MII/GMII Full and half-duplex modes supported

enabled

11/0201812612048x32MII

11/0201812612048x32MII All MAC options enabled

10/128195912272048x32GMII All MAC options enabled

10/128198412372048x32RGMII All MAC options enabled

5/204842983137—

10/2048497136272048x8

16/2048514537772048x32

16/768492834542048x32MII/GMII All MAC options

16/768493334662048x32RGMII All MAC options enabled

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Release Information

1-11

Function

12-port 10/ 100/1000Mbps Ethernet MAC

100/1000Mbps Ethernet MAC

1000BASEX/SGMII PCS

SettingsMegaCore

MII/GMII All MAC options enabled

enabled

enabled PMA block (LVDS_IO)

enabled PMA block (GXB)

(reconfig controller has been compiled together with 1000BASE-X SGMII bridge enabled PMA block (GXB))

FIFO Buffer

Size (Bits)

Combina-

tional ALUTs

Logic

Registers

Memory

(M20K Blocks/ MLAB

Bits)

60/245764836535303—

120/491529609270079—24-port 10/

0/0786614—1000BASE-X

0/4801160839—1000BASE-X SGMII bridge

0/4801250857—1000BASE-X SGMII bridge

5/220819912203—1000BASE-X SGMII bridge

Combinational ALUTs =1441, Logic Registers = 903 and Memory(M20K Block/MLAB Bits) = 4/~2048

10/100/ 1000-Mbps

bridge enabled Ethernet MAC and 1000BASEX/SGMII

bridge enabled IEEE 1588v2

feature enabled

PCS

Release Information

Table 1-6: Triple-Speed Ethernet MegaCore Function Release Information

14.0Version

June 2014Release Date

16/1248613243062048×32All MAC options enabled SGMII

4/1536531850620Default MAC option SGMII

DescriptionItem

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Release Information

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DescriptionItem

IP-TRIETHERNETOrdering Code

Product ID(s)

00BD (Triple-Speed Ethernet MegaCore function)

0104 (IEEE 1588v2)

6AF7Vendor ID(s)

Altera verifies that the current version of the Quartus®II software compiles the previous version of each MegaCore function. The MegaCore IP Library Release Notes and Errata report any exceptions to this verification. Altera does not verify compilation with MegaCore function versions older than one release.

Related Information

MegaCore IP Library Release Notes and Errata

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Introduction to Altera IP Cores

Altera®and strategic IP partners offer a broad portfolio of off-the-shelf, configurable IP cores optimized for Altera devices. Altera delivers an IP core library with the Quartus®II software. OpenCore Plus IP evaluation enables fast acquisition, evaluation, and hardware testing of all Altera IP cores.

Nearly all complex FPGA designs include optimized logic from IP cores. You can integrate optimized and verified IP cores into your design to shorten design cycles and maximize performance. The Quartus II software includes the Altera IP Library, and supports IP cores from other sources. You can define and generate a custom IP variation to represent complex design logic in your project.

The Altera IP Library includes the following IP core types:

• Basic functions

• DSP functions

• Interface protocols

• Memory interfaces and controllers

• Processors and peripherals

Related Information

IP User Guide Documentation

Installing and Licensing IP Cores

The Quartus II software includes the Altera IP Library. The library provides many useful IP core functions for production use without additional license. You can fully evaluate any licensed Altera IP core in simulation and in hardware until you are satisfied with its functionality and performance. Some Altera IP cores, such as MegaCore®functions, require that you purchase a separate license for production use. After you purchase a license, visit the Self Service Licensing Center to obtain a license number for any Altera product.

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with

ISO 9001:2008 Registered

acds

quartus - Contains the Quartus II software

ip - Contains the Altera IP Library and third-party IP cores

altera - Contains the Altera IP Library source code

<IP core name> - Contains the IP core source files

2-2

OpenCore Plus IP Evaluation

Figure 2-1: IP Core Installation Path

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Note:

The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is <home directory>/altera/ <version number>.

Related Information

• Altera Licensing Site

• Altera Software Installation and Licensing Manual

OpenCore Plus IP Evaluation

Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and hardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to take your design to production. OpenCore Plus supports the following evaluations:

• Simulate the behavior of a licensed IP core in your system.

• Verify the functionality, size, and speed of the IP core quickly and easily.

• Generate time-limited device programming files for designs that include IP cores.

• Program a device with your IP core and verify your design in hardware

OpenCore Plus evaluation supports the following two operation modes:

• Untethered—run the design containing the licensed IP for a limited time.

• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a

connection between your board and the host computer.

All IP cores using OpenCore Plus in a design time out simultaneously when any IP core times out.Note:

Upgrading Outdated IP Cores

Each IP core has a release version number that corresponds to its Quartus II software release. When you include IP cores from a previous version of the Quartus II software in your project, click Project > Upgrade IP Components to identify and upgrade any outdated IP cores.

The Quartus II software prompts you to upgrade an IP core when the latest version includes port, parameter, or feature changes. The Quartus II software also notifies you when IP cores are unsupported or cannot upgrade in the current version of the Quartus II software. Most Altera IP cores support automatic simultaneous upgrade, as indicated in the Upgrade IP Components dialog box. IP cores unsupported by autoupgrade may require regeneration in the parameter editor, as indicated in the Upgrade IP Components dialog box.

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Displays upgrade status for all IP cores in the Project

Upgrades all IP core that support “Auto Upgrade”

Upgrades individual IP cores unsupported by “Auto Upgrade”

Indicates IP upgrade is: Required Optional Complete Unsupported

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Upgrading Outdated IP Cores

Before you begin

Upgrading IP cores changes your original design files. If you have not already preserved your original source files, click Project > Archive Project and save the project archive.

1. In the latest version of the Quartus II software, open the Quartus II project containing an outdated IP core variation.

2-3

Note:

File paths in a restored project archive must be relative to the project directory and you must reference the IP variation .v or .vhd file or .qsys file, not the .qip file.

2. Click Project > Upgrade IP Components. The Upgrade IP Components dialog box displays all outdated IP cores in your project, along with basic instructions for upgrading each core.

3. To simultaneously upgrade all IP cores that support automatic upgrade, click Perform Automatic Upgrade. The IP variation upgrades to the latest version.

4. To upgrade IP cores unsupported by automatic upgrade, follow these steps:

a. Select the IP core in the Upgrade IP Components dialog box. b. Click Upgrade in Editor. The parameter editor appears. c. Click Finish or Generate to regenerate the IP variation and complete the upgrade. The version number

updates when complete.

Note:

Example designs provided with any Altera IP core regenerate automatically whenever you upgrade the IP core in the Upgrade IP Components dialog box.

Figure 2-2: Upgrading Outdated IP Cores

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IP Catalog and Parameter Editor

Example 2-1: Upgrading IP Cores at the Command Line

Alternatively, you can upgrade IP cores at the command line. To upgrade a single IP core, type the following command:

quartus_sh --ip_upgrade -variation_files <my_ip_path> <project>

To upgrade a list of IP cores, type the following command:

quartus_sh --ip_upgrade -variation_files "<my_ip>.qsys;<my_ip>.<hdl>; <project>"

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Note:

IP cores older than Quartus II software version 12.0 do not support upgrade. Altera verifies that the current version of the Quartus II software compiles the previous version of each IP core. The MegaCore IP Library Release Notes reports any verification exceptions for MegaCore IP. The Quartus II Software and Device Support Release Notes reports any verification exceptions for other IP cores. Altera does not verify compilation for IP cores older than the previous two releases.

Related Information

• MegaCore IP Library Release Notes

• Quartus II Software and Device Support Release Notes

IP Catalog and Parameter Editor

The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize, and generate files representing your custom IP variation.

The IP Catalog automatically displays the IP cores available for your target device. Double-click any IP core name to launch the parameter editor and generate files representing your IP variation. The parameter editor prompts you to specify your IP variation name, optional ports, architecture features, and output file generation options. The parameter editor generates a top-level .qsys or .qip file representing the IP core in your project. Alternatively, you can define an IP variation without an open Quartus II project. When no project is open, select the Device Family directly in IP Catalog to filter IP cores by device.

Note:

Use the following features to help you quickly locate and select an IP core:

• Filter IP Catalog to Show IP for active device family or Show IP for all device families.

• Search to locate any full or partial IP core name in IP Catalog. Click Search for Partner IP, to access

partner IP information on the Altera website.

• Right-click an IP core name in IP Catalog to display details about supported devices, installation location, and links to documentation.

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The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes exclusive system interconnect, video and image processing, and other system-level IP that are not available in the Quartus II IP Catalog.

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Search and filter IP for your target device

Double-click to customize, right-click for information

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Figure 2-3: Quartus II IP Catalog

Using the Parameter Editor

2-5

Note:

The IP Catalog and parameter editor replace the MegaWizard™Plug-In Manager in the Quartus II software. The Quartus II software may generate messages that refer to the MegaWizard Plug-In Manager. Substitute "IP Catalog and parameter editor" for "MegaWizard Plug-In Manager" in these messages.

Using the Parameter Editor

The parameter editor helps you to configure your IP variation ports, parameters, architecture features, and output file generation options.

• Use preset settings in the parameter editor (where provided) to instantly apply preset parameter values for specific applications.

• View port and parameter descriptions, and links to documentation.

• Generate testbench systems or example designs (where provided).

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View IP port and parameter details

Apply preset parameters for specific applications

Specify your IP variation name and target device

Legacy parameter editors

2-6

Design Walkthrough

Figure 2-4: IP Parameter Editors

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Design Walkthrough

This walkthrough explains how to create a Triple-Speed Ethernet MegaCore function design using Qsys in the Quartus II software. After you generate a custom variation of the Triple-Speed Ethernet MegaCore function, you can incorporate it into your overall project.

This walkthrough includes the following steps:

1. Creating a New Quartus II Project on page 2-6

2. Specifying IP Core Parameters and Options on page 2-7

3. Generating a Design Example or Simulation Model on page 2-7

4. Simulate the System on page 2-8

5. Compiling the Triple-Speed Ethernet MegaCore Function Design on page 2-8

6. Programming an FPGA Device on page 2-8

Creating a New Quartus II Project

You need to create a new Quartus II project with the New Project Wizard, which specifies the working directory for the project, assigns the project name, and designates the name of the top-level design entity.

To create a new project, follow these steps:

1. From the Windows Start menu, select Programs > Altera > Quartus II <version> to launch the Quartus II software. Alternatively, you can use the Quartus II Web Edition software.

2. On the File menu, click New Project Wizard.

3. In the New Project Wizard: Directory, Name, Top-Level Entity page, specify the working directory, project name, and top-level design entity name. Click Next.

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Specifying IP Core Parameters and Options

2-7

4. In the New Project Wizard: Add Files page, select the existing design files (if any) you want to include in the project.

(1)

Click Next.

5. In the New Project Wizard: Family & Device Settings page, select the device family and specific device you want to target for compilation. Click Next.

6. In the EDA Tool Settings page, select the EDA tools you want to use with the Quartus II software to develop your project.

7. The last page in the New Project Wizard window shows the summary of your chosen settings. Click Finish to complete the Quartus II project creation.

Specifying IP Core Parameters and Options

Follow these steps to specify IP core parameters and options.

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears.

2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in your project. If prompted, also specify the target Altera device family and output file HDL preference. Click OK.

3. Specify parameters and options for your IP variation:

• Optionally select preset parameter values. Presets specify all initial parameter values for specific

applications (where provided).

• Specify parameters defining the IP core functionality, port configurations, and device-specific features.

• Specify options for generation of a timing netlist, simulation model, testbench, or example design

(where applicable).

• Specify options for processing the IP core files in other EDA tools.

4. Click Finish or Generate to generate synthesis and other optional files matching your IP variation specifications. The parameter editor generates the top-level .qip or .qsys IP variation file and HDL files for synthesis and simulation. Some IP cores also simultaneously generate a testbench or example design for hardware testing.

5. To generate a simulation testbench, click Generate > Generate Testbench System. Generate Testbench System is not available for some IP cores that do not provide a simulation testbench.

6. To generate a top-level HDL example for hardware verification, click Generate > HDL Example. Generate > HDL Example is not available for some IP cores.

The top-level IP variation is added to the current Quartus II project. Click Project > Add/Remove Files in Project to manually add a .qip or .qsys file to a project. Make appropriate pin assignments to connect ports.

Generating a Design Example or Simulation Model

After you have parameterized the MegaCore function, you can also generate a design example, in addition to generating the MegaCore component files.

In the parameter editor, click Example Design to create a functional simulation model (design example that includes a testbench). The testbench and the automated script are located in the <variation name>_testbench directory.

(1)

To include existing files, you must specify the directory path to where you installed the MegaCore function. You must also add the user libraries if you installed the MegaCore IP Library in a different directory from where you installed the Quartus II software.

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Simulate the System

Generating a design example can increase processing time.Note:

You can now integrate your custom IP core instance in your design, simulate, and compile. While integrating your IP core instance into your design, you must make appropriate pin assignments. You can create a virtual pin to avoid making specific pin assignments for top-level signals while you are simulating and not ready to map the design to hardware.

Related Information

• Testbench

More information about the MegaCore function simulation model.

• Quartus II Help

More information about the Quartus II software, including virtual pins.

Simulate the System

During system generation, Qsys generates a functional simulation model—or design example that includes a testbench—which you can use to simulate your system in any Altera-supported simulation tool.

Related Information

• Quartus II Software Release Notes

More information about the latest Altera-supported simulation tools.

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• Simulating Altera Designs

More information in volume 3 of the Quartus II Handbook about simulating Altera IP cores.

• System Design with Qsys

More information in volume 1 of the Quartus II Handbook about simulating Qsys systems.

Compiling the Triple-Speed Ethernet MegaCore Function Design

Before you begin

Refer to Design Considerations on page 8-1 chapter before compiling the Triple-Speed Ethernet MegaCore function design.

To compile your design, click Start Compilation on the Processing menu in the Quartus II software. You can use the generated .qip file to include relevant files into your project.

Related Information

Quartus II Help

More information about compilation in Quartus II software.

Programming an FPGA Device

After successfully compiling your design, program the targeted Altera device with the Quartus II Programmer and verify the design in hardware. For instructions on programming the FPGA device, refer to the Device Programming section in volume 3 of the Quartus II Handbook.

Related Information

Device Programming

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Generated Files

The type of files generated in your project directory and their names may vary depending on the custom variation of the MegaCore function you created.

Table 2-1: Generated Files

Generated Files

DescriptionFile Name

2-9

<variation_name>.v or

<variation_name>.vhd

A MegaCore function variation file, which defines a VHDL or Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside your design. Include this file when compiling your design in the Quartus II software.

<variation_name>.bsf

Quartus II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.

<variation_name>.qip and

<variation_name>.sip

<variation_name>.cmp

Contains Quartus II project information for your MegaCore function variations.

A VHDL component declaration file for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore.

<variation_name>.spd

Simulation Package Descriptor file. Specifies the files required for simulation.

Testbench Files (in <variation_name>_testbench folder)

Read me file for the testbench design.README.txt

generate_sim.qpf and

generate_sim.qsf

Dummy Quartus II project and project setting file. Use this to start the Quartus II in the correct directory to launch the generate_

sim_verilog.tcl and generate_sim_vhdl.tcl files.

generate_sim_verilog.tcl and

generate_sim_vhdl.tcl

/testbench_vhdl/<variation_name>/ <variation_name>_tb.vhd or

/testbench_verilog/<variation_name>/ <variation_name>_tb.v

<variation_name>_tb.tcl or

/testbench_verilog/<variation_name>/ run_ <variation_name>_tb.tcl

/testbench_vhdl/<variation_name>/ <variation_name>_wave.do or

/testbench_verilog/<variation_name>/ <variation_name>_wave.do

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A Tcl script to generate the DUT VHDL or Verilog HDL simulation model for use in the testbench.

VHDL or Verilog HDL testbench that exercises your MegaCore function variation in a third party simulator.

A Tcl script for use with the ModelSim simulation software./testbench_vhdl/<variation_name>/run_

A signal tracing macro script used with the ModelSim simulation software to display testbench signals.

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Design Constraint File No Longer Generated

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DescriptionFile Name

/testbench_vhdl/models or

/testbench_verilog/models

A directory containing VHDL and Verilog HDL models of the Ethernet generators and monitors used by the generated testbench.

Design Constraint File No Longer Generated

For a new Triple-Speed Ethernet MegaCore function created using the Quartus II software ACDS 13.0 or later, the Quartus II software no longer generate the <variation_name>_constraints.tcl file that contains the necessary constraints for the compilation of your MegaCore Function variation. Table 2-2 lists the recommended Quartus II pin assignments that you can set in your design.

Table 2-2: Recommended Quartus II Pin Assignments

Quartus II Pin

Assignment

INPUT_ REGISTER

OUTPUT_ REGISTER

IO_ STANDARD

Value

ONFAST_

1.4-V PCML or 1.5-V PCML

and TBI interface.

To optimize I/O timing for MII, GMII and TBI interface.

I/O standard for GXB serial input and output pins.

Design PinDescriptionAssignment

MII, GMII, RGMII, TBI input pins.To optimize I/O timing for MII, GMII

MII, GMII, RGMII, TBI output pins.

GXB transceiver serial input and output pins.

STANDARD

SIGNAL

LVDSIO_

I/O standard for LVDS/IO serial input and output pins.

Global clockGLOBAL_

To assign clock signals to use the global clock network. Use this setting to guide the Quartus II in the fitter process for better timing closure.

LVDS/IO transceiver serial input and output pins.

• ref_clk for MAC and PCS with

LVDS/IO (with internal FIFO).

• clk and reset pins for MAC

only (without internal FIFO).

• clk and ref_clk input pins for

MAC and PCS with transceiver (without internal FIFO).

Regional clockGLOBAL_

To assign clock signals to use the regional clock network. Use this setting to guide the Quartus II in the fitter process for better timing closure.

• rx_clk <n> and tx_clk <n>

input pins for MAC only using MII/GMII interface (without internal FIFO).

• rx_clk <n> input pin for MAC

only using RGMII interface (without internal FIFO).

OFFGLOBAL_

To prevent a signal to be used as a global signal.

Signals for Arria V devices:

• *reset_ff_wr and *reset_ff_

• *| altera_tse_reset_

synchronizer_chain_out

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Parameter Settings

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Parameter Settings

You customize the Triple-Speed Ethernet MegaCore function by specifying parameters using the Triple-Speed Ethernet parameter editor, launched from Qsys in the Quartus II software. The customization enables specific core features during synthesis and generation.

This chapter describes the parameters and how they affect the behavior of the MegaCore function. Each section corresponds to a page in the Parameter Settings tab in the parameter editor interface.

Core Configuration

Table 3-1: Core Configuration Parameters

Core Variation

• 10/100/1000 Mb Ethernet MAC

• 10/100/1000 Mb Ethernet MAC with 1000BASE-X/SGMII PCS

• 1000BASE-X/SGMII PCS only

• 1000 Mb Small MAC

• 10/100 Mb Small MAC

DescriptionValueName

Determines the primary blocks to include in the variation.

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with

On/OffEnable ECC protection

Turn on this option to enable ECC protection for internal memory blocks.

ISO 9001:2008 Registered

+ 193 hidden pages

Altera Triple Speed Ethernet MegaCore Function User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

About This MegaCore Function

About This MegaCore Function

Device Family Support

Features

10/100/1000 Ethernet MAC Versus Small MAC

High-Level Block Diagrams

Example Applications

MegaCore Verification

Optical Platform

Copper Platform

Performance and Resource Utilization

Release Information

Getting Started with Altera IP Cores

Introduction to Altera IP Cores

Installing and Licensing IP Cores

OpenCore Plus IP Evaluation

Upgrading Outdated IP Cores

IP Catalog and Parameter Editor

Using the Parameter Editor

Design Walkthrough

Creating a New Quartus II Project

Specifying IP Core Parameters and Options

Generating a Design Example or Simulation Model

Simulate the System

Compiling the Triple-Speed Ethernet MegaCore Function Design

Programming an FPGA Device

Generated Files

Design Constraint File No Longer Generated

Parameter Settings

Parameter Settings

Core Configuration