Altera Triple Speed Ethernet MegaCore Function User Manual

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Triple-Speed Ethernet MegaCore Function

User Guide

Last updated for Altera Complete Design Suite: 14.0

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TOC-2

Triple-Speed Ethernet MegaCore Function User Guide

About This MegaCore Function.........................................................................1-1

About This MegaCore Function................................................................................................................1-1

Device Family Support................................................................................................................................1-1

Features.........................................................................................................................................................1-1

10/100/1000 Ethernet MAC Versus Small MAC.....................................................................................1-2

High-Level Block Diagrams........................................................................................................................1-3

Example Applications..................................................................................................................................1-5

MegaCore Verification................................................................................................................................1-6

Optical Platform...............................................................................................................................1-7

Copper Platform...............................................................................................................................1-7

Performance and Resource Utilization.....................................................................................................1-7

Release Information...................................................................................................................................1-11

Getting Started with Altera IP Cores..................................................................2-1

Introduction to Altera IP Cores.................................................................................................................2-1

Installing and Licensing IP Cores..............................................................................................................2-1

OpenCore Plus IP Evaluation....................................................................................................................2-2

Upgrading Outdated IP Cores...................................................................................................................2-2

IP Catalog and Parameter Editor...............................................................................................................2-4

Using the Parameter Editor............................................................................................................2-5

Design Walkthrough...................................................................................................................................2-6

Creating a New Quartus II Project................................................................................................2-6

Specifying IP Core Parameters and Options................................................................................2-7

Generating a Design Example or Simulation Model..................................................................2-7

Simulate the System.........................................................................................................................2-8

Compiling the Triple-Speed Ethernet MegaCore Function Design.........................................2-8

Programming an FPGA Device.....................................................................................................2-8

Generated Files.............................................................................................................................................2-9

Design Constraint File No Longer Generated...........................................................................2-10

Parameter Settings..............................................................................................3-1

Altera Corporation

Parameter Settings.......................................................................................................................................3-1

Core Configuration......................................................................................................................................3-1

Triple-Speed Ethernet MegaCore Function User Guide

TOC-3

Ethernet MAC Options...............................................................................................................................3-2

FIFO Options................................................................................................................................................3-4

Timestamp Options.....................................................................................................................................3-5

PCS/Transceiver Options...........................................................................................................................3-5

Functional Description.......................................................................................4-1

10/100/1000 Ethernet MAC.......................................................................................................................4-1

MAC Architecture...........................................................................................................................4-2

MAC Interfaces................................................................................................................................4-3

MAC Transmit Datapath................................................................................................................4-4

MAC Receive Datapath...................................................................................................................4-7

MAC Transmit and Receive Latencies........................................................................................4-11

FIFO Buffer Thresholds................................................................................................................4-12

Congestion and Flow Control......................................................................................................4-16

Magic Packets.................................................................................................................................4-17

MAC Local Loopback....................................................................................................................4-18

MAC Error Correction Code.......................................................................................................4-19

MAC Reset......................................................................................................................................4-19

PHY Management (MDIO).........................................................................................................4-20

Connecting MAC to External PHYs...........................................................................................4-22

1000BASE-X/SGMII PCS With Optional Embedded PMA................................................................4-24

1000BASE-X/SGMII PCS Architecture......................................................................................4-25

Transmit Operation.......................................................................................................................4-26

Receive Operation..........................................................................................................................4-27

Transmit and Receive Latencies...................................................................................................4-28

SGMII Converter...........................................................................................................................4-28

Auto-Negotiation...........................................................................................................................4-29

Ten-bit Interface............................................................................................................................4-32

PHY Loopback...............................................................................................................................4-33

PHY Power-Down.........................................................................................................................4-33

1000BASE-X/SGMII PCS Reset...................................................................................................4-34

Altera IEEE 1588v2 Feature......................................................................................................................4-35

IEEE 1588v2 Supported Configurations.....................................................................................4-35

IEEE 1588v2 Features....................................................................................................................4-36

IEEE 1588v2 Architecture.............................................................................................................4-37

IEEE 1588v2 Transmit Datapath.................................................................................................4-37

IEEE 1588v2 Receive Datapath....................................................................................................4-38

IEEE 1588v2 Frame Format.........................................................................................................4-38

Altera Corporation

TOC-4

Triple-Speed Ethernet MegaCore Function User Guide

Triple-Speed Ethernet with IEEE 1588v2 Design Example................................5-1

Software Requirements...............................................................................................................................5-1

Triple-Speed Ethernet with IEEE 1588v2 Design Example Components...........................................5-2

Base Addresses..................................................................................................................................5-3

Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Files...............................................5-3

Creating a New Triple-Speed Ethernet MAC with IEEE 1588v2 Design............................................5-4

Triple-Speed Ethernet with IEEE 1588v2 Testbench .............................................................................5-4

Triple-Speed Ethernet with IEEE 1588v2 Testbench Files.........................................................5-5

Triple-Speed Ethernet with IEEE 1588v2 Testbench Simulation Flow....................................5-5

Simulating Triple-Speed Ethernet with IEEE 1588v2 Testbench with ModelSim

Simulator.....................................................................................................................................5-6

Configuration Register Space.............................................................................6-1

MAC Configuration Register Space..........................................................................................................6-1

Base Configuration Registers (Dword Offset 0x00 – 0x17).......................................................6-3

Statistics Counters (Dword Offset 0x18 – 0x38).......................................................................6-11

Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)............................6-13

Supplementary Address (Dword Offset 0xC0 – 0xC7)............................................................6-15

IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6).................................................................6-16

IEEE 1588v2 Feature PMA Delay................................................................................................6-17

PCS Configuration Register Space..........................................................................................................6-18

Control Register (Word Offset 0x00)..........................................................................................6-20

Status Register (Word Offset 0x01).............................................................................................6-22

Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05)................................6-23

An_Expansion Register (Word Offset 0x06).............................................................................6-26

If_Mode Register (Word Offset 0x14)........................................................................................6-26

Register Initialization................................................................................................................................6-27

Triple-Speed Ethernet System with MII/GMII or RGMII.......................................................6-28

Triple-Speed Ethernet System with SGMII................................................................................6-30

Triple-Speed Ethernet System with 1000BASE-X Interface....................................................6-31

Interface Signals..................................................................................................7-1

Altera Corporation

Interface Signals...........................................................................................................................................7-1

10/100/1000 Ethernet MAC Signals..............................................................................................7-2

10/100/1000 Multiport Ethernet MAC Signals..........................................................................7-12

10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals.....................................7-16

Triple-Speed Ethernet MegaCore Function User Guide

10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals...................7-20

10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA

Signals........................................................................................................................................7-22

10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded

PMA...........................................................................................................................................7-25

1000BASE-X/SGMII PCS Signals................................................................................................7-34

1000BASE-X/SGMII PCS and PMA Signals..............................................................................7-38

Timing.........................................................................................................................................................7-39

Avalon-ST Receive Interface........................................................................................................7-39

Avalon-ST Transmit Interface.....................................................................................................7-41

GMII Transmit...............................................................................................................................7-41

GMII Receive..................................................................................................................................7-41

RGMII Transmit............................................................................................................................7-42

RGMII Receive...............................................................................................................................7-42

MII Transmit..................................................................................................................................7-43

MII Receive.....................................................................................................................................7-43

IEEE 1588v2 Timestamp...............................................................................................................7-43

TOC-5

Design Considerations........................................................................................8-1

Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA.............................8-1

MAC and PCS With GX Transceivers..........................................................................................8-2

MAC and PCS With LVDS Soft-CDR I/O...................................................................................8-4

Sharing PLLs in Devices with LVDS Soft-CDR I/O................................................................................8-6

Sharing PLLs in Devices with GIGE PHY................................................................................................8-6

Sharing Transceiver Quads.........................................................................................................................8-7

Migrating From Old to New User Interface For Existing Designs.......................................................8-7

Exposed Ports in the New User Interface.....................................................................................8-7

Timing Constraints.............................................................................................9-1

Creating Clock Constraints........................................................................................................................9-1

Recommended Clock Frequency...............................................................................................................9-3

Testbench...........................................................................................................10-1

Triple-Speed Ethernet Testbench Architecture ....................................................................................10-1

Testbench Components............................................................................................................................10-1

Testbench Verification..............................................................................................................................10-2

Testbench Configuration..........................................................................................................................10-3

Altera Corporation

TOC-6

Triple-Speed Ethernet MegaCore Function User Guide

Test Flow.....................................................................................................................................................10-3

Simulation Model......................................................................................................................................10-4

Generate the Simulation Model...................................................................................................10-4

Simulate the IP Core......................................................................................................................10-4

Simulation Model Files.................................................................................................................10-5

Software Programming Interface.....................................................................11-1

Driver Architecture...................................................................................................................................11-1

Directory Structure....................................................................................................................................11-2

PHY Definition .........................................................................................................................................11-2

Using Multiple SG-DMA Descriptors....................................................................................................11-4

Using Jumbo Frames.................................................................................................................................11-4

API Functions.............................................................................................................................................11-5

alt_tse_mac_get_common_speed().............................................................................................11-5

alt_tse_mac_set_common_speed().............................................................................................11-5

alt_tse_phy_add_profile()............................................................................................................11-6

alt_tse_system_add_sys().............................................................................................................11-6

triple_speed_ethernet_init().........................................................................................................11-7

tse_mac_close()..............................................................................................................................11-7

tse_mac_raw_send()......................................................................................................................11-8

tse_mac_setGMII mode().............................................................................................................11-9

tse_mac_setMIImode().................................................................................................................11-9

tse_mac_SwReset()........................................................................................................................11-9

Constants..................................................................................................................................................11-10

Ethernet Frame Format......................................................................................A-1

Simulation Parameters.......................................................................................B-1

Time-of-Day (ToD) Clock..................................................................................C-1

Altera Corporation

Basic Frame Format....................................................................................................................................A-1

VLAN and Stacked VLAN Frame Format..............................................................................................A-1

Pause Frame Format...................................................................................................................................A-3

Pause Frame Generation................................................................................................................A-3

Functionality Configuration Parameters.................................................................................................B-1

Test Configuration Parameters.................................................................................................................B-3

ToD Clock Features....................................................................................................................................C-1

Triple-Speed Ethernet MegaCore Function User Guide

ToD Clock Device Family Support...........................................................................................................C-1

ToD Clock Performance and Resource Utilization................................................................................C-1

ToD Clock Parameter Setting....................................................................................................................C-2

ToD Clock Interface Signals......................................................................................................................C-3

ToD Clock Avalon-MM Control Interface Signals....................................................................C-3

ToD Clock Avalon-ST Transmit Interface Signals.....................................................................C-4

ToD Clock Configuration Register Space................................................................................................C-5

Adjusting ToD Clock Drift............................................................................................................C-6

TOC-7

ToD Synchronizer..............................................................................................D-1

ToD Synchronizer Block............................................................................................................................D-2

ToD Synchronizer Parameter Settings.....................................................................................................D-3

ToD Synchronizer Signals.........................................................................................................................D-4

ToD Synchronizer Common Clock and Reset Signals..............................................................D-4

ToD Synchronizer Interface Signals.............................................................................................D-4

Packet Classifier..................................................................................................E-1

Packet Classifier Block................................................................................................................................E-1

Packet Classifier Signals..............................................................................................................................E-2

Packet Classifier Common Clock and Reset Signals..................................................................E-2

Packet Classifier Avalon-ST Interface Signals.............................................................................E-2

Packet Classifier Ingress Control Signals.....................................................................................E-3

Packet Classifier Control Insert Signals........................................................................................E-4

Packet Classifier Timestamp Field Location Signals..................................................................E-5

Additional Information......................................................................................F-1

Document Revision History.......................................................................................................................F-2

How to Contact Altera................................................................................................................................F-7

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2014.06.30

www.altera.com

101 Innovation Drive, San Jose, CA 95134

About This MegaCore Function

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About This MegaCore Function

The Altera®Triple-Speed Ethernet MegaCore®function is a configurable intellectual property (IP) core that complies with the IEEE 802.3 standard. The IP core was tested and successfully validated by the University of New Hampshire (UNH) interoperability lab. It combines the features of a 10/100/1000-Mbps Ethernet media access controller (MAC) and 1000BASE-X/SGMII physical coding sublayer (PCS) with an optional physical medium attachment (PMA).

Device Family Support

For new additions and enhancements to the latest Quartus II software and Altera IP, refer to the What’s

New for Altera IP page of the Altera website.

For a list of IP support for all device families, refer to the All Intellectual Property page of the Altera website.

Features

• Complete triple-speed Ethernet IP: 10/100/1000-Mbps Ethernet MAC, 1000BASE-X/SGMII PCS, and embedded PMA.

• Successful validation from the University of New Hampshire (UNH) InterOperability Lab.

• 10/100/1000-Mbps Ethernet MAC features:

• Multiple variations: 10/100/1000-Mbps Ethernet MAC in full duplex, 10/100-Mbps Ethernet MAC

in half duplex, 10/100-Mbps or 1000-Mbps small MAC (resource-efficient variant), and multiport MAC that supports up to 24 ports.

• Support for basic, VLAN, stacked VLAN, and jumbo Ethernet frames. Also supports control frames

including pause frames.

• Optional internal FIFO buffers, depth from 64 bytes to 256 Kbytes.

• Optional statistics counters.

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO 9001:2008 Registered

1-2

10/100/1000 Ethernet MAC Versus Small MAC

• 1000BASE-X/SGMII PCS features:

• Compliance with Clause 36 of the IEEE standard 802.3.

• Optional embedded PMA implemented with serial transceiver or LVDS I/O and soft CDR in Altera

devices that support this interface at 1.25-Gbps data rate.

• Support for auto-negotiation as defined in Clause 37.

• Support for connection to 1000BASE-X PHYs. Support for 10BASE-T, 100BASE-T, and 1000BASE-

T PHYs if the PHYs support SGMII.

• MAC interfaces:

• Client side—8-bit or 32-bit Avalon®Streaming (Avalon-ST)

• Network side—medium independent interface (MII), gigabit medium independent interface (GMII),

or reduced gigabit medium independent interface (RGMII) on the network side. Optional loopback on these interfaces.

• Optional management data I/O (MDIO) master interface for PHY device management.

• PCS interfaces:

• Client side—MII or GMII

• Network side—ten-bit interface (TBI) for PCS without PMA; 1.25-Gbps serial interface for PCS with

PMA implemented with serial transceiver or LVDS I/O and soft CDR in Altera devices that support this interface at 1.25-Gbps data rate.

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• Programmable features via 32-bit configuration registers:

• FIFO buffer thresholds.

• Pause quanta for flow control.

• Source and destination MAC addresses.

• Address filtering on receive, up to 5 unicast and 64 multicast MAC addresses.

• Promiscuous mode—receive frame filtering is disabled in this mode.

• Frame length—in MAC only variation, up to 64 Kbytes including jumbo frames. In all variants

containing 1000BASE-X/SGMII PCS, the frame length is up to 10 Kbytes.

• Optional auto-negotiation for the 1000BASE-X/SGMII PCS.

• Error correction code protection feature for internal memory blocks.

• Optional IEEE 1588v2 feature for 10/100/1000-Mbps Ethernet MAC with SGMII PCS and embedded

serial PMA variation operating without internal FIFO buffer in full-duplex mode, 10/100/1000-Mbps MAC with SGMII PCS and embedded LVDS I/O, or MAC only variation operating without internal FIFO buffer in full-duplex mode. These features are supported in Arria V, Arria 10, Cyclone V, MAX 10, and Stratix V device families.

10/100/1000 Ethernet MAC Versus Small MAC

Table 1-1: Feature Comparison between 10/100/1000 Ethernet MAC and Small MAC

Small MAC10/100/1000 Ethernet MACFeature

interfaces

Altera Corporation

10/100 Mbps or 1000 MbpsTriple speed (10/100/1000 Mbps)Speed

MII/GMII or RGMIIExternal

MII only for 10/100 Mbps small MAC, GMII or RGMII for 1000 Mbps small MAC

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10/100/1000-Mbps

Ethernet MAC

MII/GMII/RGMII

Client Side

Network Side

Avalon-ST

(Transmitand Receive)

Avalon-MM

(Management and Control)

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High-Level Block Diagrams

Small MAC10/100/1000 Ethernet MACFeature

1-3

interface registers

options

Fully programmableControl

Limited programmable options. The following options are fixed:

• Maximum frame length is fixed to 1518. Jumbo frames are not supported.

• FIFO buffer thresholds are set to fixed values.

• Store and forward option is not available.

• Interpacket gap is set to 12.

• Flow control is not supported; pause quanta is not in

use.

• Checking of payload length is disabled.

• Supplementary MAC addresses are disabled.

• Padding removal is disabled.

• Sleep mode and magic packet detection is not

supported.

Fully configurableSynthesis

Limited configurable options. The following options are NOT available:

• Flow control

• VLAN

• Statistics counters

• Multicast hash table

• Loopback

• TBI and 1.25 Gbps serial interface

• 8-bit wide FIFO buffers

High-Level Block Diagrams

About This MegaCore Function

High-level block diagrams of different variations of the Triple-Speed Ethernet MegaCore function.

Figure 1-1: 10/100/1000-Mbps Ethernet MAC

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10/100/1000-Mbps

Ethernet MAC

MII/GMII/RGMII

Client Side

Network Side

Avalon-ST

(Transmitand Receive)

Avalon-MM

(Management and Control)

10/100/1000-Mbps

Ethernet MAC

MII/GMII/RGMII

Avalon-ST

(Transmitand Receive)

Multi-Port MAC

10/100/1000-Mbps

Ethernet MAC

MII/ GMII

Client Side

Network Side

Avalon-ST

(Transmitand

Receive)

Avalon-MM

(Management

and Control)

1.25-Gbps Serial

MAC and PCS with Optional Embedded PMA

1000BASE-X/SGMII

PCS

PMA

(Optional)

TBI

MII/GMII

Client Side

Network Side

1.25-Gbps Serial

PCS with Optional Embedded PMA

1000BASE-X/SGMII

PCS

PMA

(Optional)

TBI

1-4

High-Level Block Diagrams

Figure 1-2: Multi-port MAC

Figure 1-3: 10/100/1000-Ethernet MAC and 1000BASE-X/SGMII PCS with Optional PMA

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Figure 1-4: 1000BASE-X/SGMII PCS with Optional PMA

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Gigabit or Fast

Ethernet PHY

Device

User

Application

Host Interface MDIO Master

Altera Device

Triple-Speed Ethernet MegaCore Function

Management

Application

MDIO

Copper

MII/GMII/RGMII

Avalon-STAvalon-MM

10/100/1000-Mbps

Ethernet MAC

Gigabit or Fast

Ethernet PHY

Device

User

Application

Host Interface MDIO Master

Altera Device

Triple-Speed Ethernet MegaCore Function

Management

Application

MDIO

Copper

MII/GMII/RGMII

Avalon-STAvalon-MM

10/100/1000-Mbps

Ethernet MAC

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Figure 1-5: Stand-Alone 10/100/1000 Mbps Ethernet MAC

Example Applications

1-5

This section shows example applications of different variations of the Triple-Speed Ethernet MegaCore function.

The 10/100/1000-Gbps Ethernet MAC only variation can serve as a bridge between the user application and standard fast or gigabit Ethernet PHY devices.

Figure 1-6: Stand-Alone 10/100/1000 Mbps Ethernet MAC

Example application using this variation for a copper network.

When configured to include the 1000BASE-X/SGMII PCS function, the MegaCore function can seamlessly connect to any industry standard gigabit Ethernet PHY device via a TBI. Alternatively, when the 1000BASEX/SGMII PCS function is configured to include an embedded PMA, the MegaCore function can connect

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GMII

PMA

Fiber

GBIC/SFP

Module

1.25

Gbps

Serial

Altera Device

Triple-SpeedEthernet MegaCore Function

TBI

10/100/1000-Mbps

Ethernet MAC

1000BASE-X

PCS

Copper

MII/GMII

SGMII PCS PMA

10/100/1000

1.25 Gbps

SGMII

Altera Device

TBI

Triple-SpeedEthernet MegaCore Function

BASE-T PHY

10/100/1000-Mbps

Ethernet MAC

1-6

MegaCore Verification

directly to a gigabit interface converter (GBIC), small form-factor pluggable (SFP) module, or an SGMII PHY.

Figure 1-7: 10/100/1000 Mbps Ethernet MAC and 1000BASE-X PCS with Embedded PMA

Example application using the Triple-Speed Ethernet MegaCore function with 1000BASE-X and PMA. The PMA block connects to an off-the-shelf GBIC or SFP module to communicate directly over the optical link.

Figure 1-8: 10/100/1000 Mbps Ethernet MAC and SGMII PCS with Embedded PMA—GMII/MII to 1.25-Gbps Serial Bridge Mode

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Example application using the Triple-Speed Ethernet MegaCore function with 1000BASE-X and PMA, in which the PCS function is configured to operate in SGMII mode and acts as a GMII-to-SGMII bridge. In this case, the transceiver I/O connects to an off-the-shelf Ethernet PHY that supports SGMII (10BASE-T, 100BASE-T, or 1000BASE-T Ethernet PHY).

MegaCore Verification

For each release, Altera verifies the Triple-Speed Ethernet MegaCore function through extensive simulation and internal hardware verification in various Altera device families. The University of New Hampshire (UNH) InterOperability Lab also successfully verified the MegaCore function prior to its release.

Altera used a highly parameterizeable transaction-based testbench to test the following aspects of the

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MegaCore function:

• Register access

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• MDIO access

• Frame transmission and error handling

• Frame reception and error handling

• Ethernet frame MAC address filtering

• Flow control

• Retransmission in half-duplex

Altera has also validated the Triple-Speed Ethernet MegaCore function in both optical and copper platforms using the following development kits:

• Altera Nios II Development Kit, Cyclone II Edition (2C35)

• Altera Stratix III FPGA Development Kit

• Altera Stratix IV FPGA Development Kit

• Quad 10/100/1000 Marvell PHY

• MorethanIP 10/100 and 10/100/1000 Ethernet PHY Daughtercards

Optical Platform

In the optical platform, the 10/100/1000 Mbps Ethernet MAC, 1000BASE-X/SGMII PCS, and PMA functions are instantiated.

The FPGA application implements the Ethernet MAC, the 1000BASE-X PCS, and an internal system using Ethernet connectivity. This internal system retrieves all frames received by the MAC function and returns them to the sender by manipulating the MAC address fields, thus implementing a loopback. A direct connection to an optical module is provided through an external SFP optical module. Certified 1.25 GBaud optical SFP transceivers are Finisar 1000BASE-SX FTLF8519P2BNL, Finisar 1000BASE-LX FTRJ-1319-3, and Avago Technologies AFBR-5710Z.

Optical Platform

1-7

Copper Platform

In the copper platform, Altera tested the Triple-Speed Ethernet MegaCore function with an external 1000BASE-T PHY devices. The MegaCore function is connected to the external PHY device using MII, GMII, RGMII, and SGMII, in conjunction with the 1000BASE-X/SGMII PCS and PMA functions.

A 10/100/1000 Mbps Ethernet MAC and an internal system are implemented in the FPGA. The internal system retrieves all frames received by the MAC function and returns them to the sender by manipulating the MAC address fields, thus implementing a loopback. A direct connection to an Ethernet link is provided through a combined MII to an external PHY module. Certified 1.25 GBaud copper SFP transceivers are Finisar FCMJ-8521-3, Methode DM7041, and Avago Technologies ABCU-5700RZ.

Performance and Resource Utilization

In the following tables, the f

of the configurations is more than 125 MHz.

MAX

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1-8

Performance and Resource Utilization

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Table 1-2: Arria II GX Performance and Resource Utilization

The estimated resource utilization and performance of the Triple-Speed Ethernet MegaCore function for the Arria II GX device family. The estimates are obtained by compiling the Triple-Speed Ethernet MegaCore function using the Quartus II software targeting an Arria II GX (EP2AGX260EF29I3) device with speed grade -3.

SettingsMegaCore Function

FIFO Buffer

Size (Bits)

Combina-

tional ALUTs

Logic

Registers

Memory

(M9K Blocks/

M144K Blocks/

MLAB Bits)

10/100/1000-Mbps Ethernet MAC

All MAC options enabled

26/0/1828394733572048x32RGMII

Full and half-duplex modes supported

8-port 10/100/1000Mbps Ethernet MAC

enabled

Full and half-duplex modes

32/0/146242229220201—MII/GMII All MAC options

supported

0/0/0661624—1000BASE-X

1000BASE-X/ SGMII PCS

1/0/16012141191—1000BASE-X SGMII bridge

enabled PMA block (GXB)

Table 1-3: Stratix IV Performance and Resource Utilization

The estimated resource utilization and performance of the Triple-Speed Ethernet MegaCore function for the Stratix IV device family. The estimates are obtained by compiling the Triple-Speed Ethernet MegaCore function using the Quartus II software targeting a Stratix IV GX (EP4SGX530NF45C4) device with speed grade -4.

Memory

(M9K Blocks/ M144K

Blocks/MLAB Bits)

Function

SettingsMegaCore

FIFO Buffer

Size (Bits)

Combina-

tional ALUTs

Logic

Registers

10/100Mbps Small MAC

1000-Mbps Small MAC

Altera Corporation

12/1/1408212714102048x32MII

Full and half-duplex modes supported

12/1/128189411572048x32MII All MAC options enabled

12/1/176182711602048x32GMII All MAC options enabled

12/1/176186111702048x32RGMII All MAC options enabled

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Performance and Resource Utilization

1-9

Function

10/100/ 1000-Mbps Ethernet MAC

12-port 10/ 100/1000Mbps Ethernet MAC

100/1000Mbps Ethernet MAC

SettingsMegaCore

MII/GMII Full and half-duplex modes supported

enabled

MII/GMII All MAC options enabled

FIFO Buffer

Size (Bits)

Combina-

tional ALUTs

Logic

Registers

Memory

(M9K Blocks/ M144K

Blocks/MLAB Bits)

0/0/336433952721—

8/0/3620397732012048x8

12/1/3364442533452048x32

12/1/2084399431252048x32MII/GMII All MAC options

12/1/2084402131332048x32RGMII All MAC options enabled

0/0/250083437227215—

0/0/500166840454123—24-port 10/

0/0/0661624—1000BASE-X

2/0/0986808—1000BASE-X SGMII bridge

1000BASEX/SGMII PCS

enabled

2/0/01057819—1000BASE-X SGMII bridge

enabled PMA block (LVDS_IO)

1/0/16012121189—1000BASE-X SGMII bridge

enabled PMA block (GXB)

10/100/ 1000-Mbps

bridge enabled

14/1/2084495039712048×32All MAC options enabled SGMII

Ethernet MAC and 1000BASEX/SGMII PCS

Table 1-4: Cyclone IV GX Performance and Resource Utilization

The estimated resource utilization and performance of the Triple Speed Ethernet MegaCore function for the Cyclone IV device family. The estimates are obtained by compiling the Triple-Speed Ethernet MegaCore function using the Quartus II software targeting a Cyclone IV GX (EP4CGX150DF27C7) device with speed grade -7.

Memory

(M9K Blocks/ Mi44K

Blocks/ MLAB Bits)

Function

SettingsMegaCore

FIFO Buffer

Size (Bits)

Logic

Elements

Logic

Registers

1000-Mbps Small MAC

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supported

24/0/0169921612048x32RGMII Only full-duplex mode

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Performance and Resource Utilization

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Memory

(M9K Blocks/ Mi44K

Blocks/ MLAB Bits)

31/0/0366656142048x32MII/GMII Full and half-duplex

Function

10/100/ 1000-Mbps

SettingsMegaCore

modes supported

FIFO Buffer

Size (Bits)

Logic

Elements

Logic

Registers

Ethernet MAC

4-port 10/ 100/ 1000Mbps Ethernet MAC

1000BASEX/SGMII PCS

enabled

Full and half-duplex modes supported

enabled PMA block (GXB)

36/0/01061217017—MII/GMII All MAC options

0/0/06611149—1000BASE-X

2/0/011272001—1000BASE-X SGMII bridge

Table 1-5: Stratix V Performance and Resource Utilization

The estimated resource utilization and performance of the Triple-Speed Ethernet MegaCore function for the Stratix V device family. The estimates are obtained by compiling the Triple-Speed Ethernet MegaCore function using the Quartus II software targeting a Stratix V GX (5SGXMA7N3F45C3) device with speed grade -3.

Memory

(M20K Blocks/ MLAB

Bits)

Function

SettingsMegaCore

FIFO Buffer

Size (Bits)

Combina-

tional ALUTs

Logic

Registers

10/100Mbps Small MAC

1000-Mbps Small MAC

10/100/ 1000-Mbps Ethernet MAC

Full and half-duplex modes supported

MII/GMII Full and half-duplex modes supported

enabled

11/0201812612048x32MII

11/0201812612048x32MII All MAC options enabled

10/128195912272048x32GMII All MAC options enabled

10/128198412372048x32RGMII All MAC options enabled

5/204842983137—

10/2048497136272048x8

16/2048514537772048x32

16/768492834542048x32MII/GMII All MAC options

16/768493334662048x32RGMII All MAC options enabled

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Release Information

1-11

Function

12-port 10/ 100/1000Mbps Ethernet MAC

100/1000Mbps Ethernet MAC

1000BASEX/SGMII PCS

SettingsMegaCore

MII/GMII All MAC options enabled

enabled

enabled PMA block (LVDS_IO)

enabled PMA block (GXB)

(reconfig controller has been compiled together with 1000BASE-X SGMII bridge enabled PMA block (GXB))

FIFO Buffer

Size (Bits)

Combina-

tional ALUTs

Logic

Registers

Memory

(M20K Blocks/ MLAB

Bits)

60/245764836535303—

120/491529609270079—24-port 10/

0/0786614—1000BASE-X

0/4801160839—1000BASE-X SGMII bridge

0/4801250857—1000BASE-X SGMII bridge

5/220819912203—1000BASE-X SGMII bridge

Combinational ALUTs =1441, Logic Registers = 903 and Memory(M20K Block/MLAB Bits) = 4/~2048

10/100/ 1000-Mbps

bridge enabled Ethernet MAC and 1000BASEX/SGMII

bridge enabled IEEE 1588v2

feature enabled

PCS

Release Information

Table 1-6: Triple-Speed Ethernet MegaCore Function Release Information

14.0Version

June 2014Release Date

16/1248613243062048×32All MAC options enabled SGMII

4/1536531850620Default MAC option SGMII

DescriptionItem

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Release Information

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DescriptionItem

IP-TRIETHERNETOrdering Code

Product ID(s)

00BD (Triple-Speed Ethernet MegaCore function)

0104 (IEEE 1588v2)

6AF7Vendor ID(s)

Altera verifies that the current version of the Quartus®II software compiles the previous version of each MegaCore function. The MegaCore IP Library Release Notes and Errata report any exceptions to this verification. Altera does not verify compilation with MegaCore function versions older than one release.

Related Information

MegaCore IP Library Release Notes and Errata

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Introduction to Altera IP Cores

Altera®and strategic IP partners offer a broad portfolio of off-the-shelf, configurable IP cores optimized for Altera devices. Altera delivers an IP core library with the Quartus®II software. OpenCore Plus IP evaluation enables fast acquisition, evaluation, and hardware testing of all Altera IP cores.

Nearly all complex FPGA designs include optimized logic from IP cores. You can integrate optimized and verified IP cores into your design to shorten design cycles and maximize performance. The Quartus II software includes the Altera IP Library, and supports IP cores from other sources. You can define and generate a custom IP variation to represent complex design logic in your project.

The Altera IP Library includes the following IP core types:

• Basic functions

• DSP functions

• Interface protocols

• Memory interfaces and controllers

• Processors and peripherals

Related Information

IP User Guide Documentation

Installing and Licensing IP Cores

The Quartus II software includes the Altera IP Library. The library provides many useful IP core functions for production use without additional license. You can fully evaluate any licensed Altera IP core in simulation and in hardware until you are satisfied with its functionality and performance. Some Altera IP cores, such as MegaCore®functions, require that you purchase a separate license for production use. After you purchase a license, visit the Self Service Licensing Center to obtain a license number for any Altera product.

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with

ISO 9001:2008 Registered

acds

quartus - Contains the Quartus II software

ip - Contains the Altera IP Library and third-party IP cores

altera - Contains the Altera IP Library source code

<IP core name> - Contains the IP core source files

2-2

OpenCore Plus IP Evaluation

Figure 2-1: IP Core Installation Path

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Note:

The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is <home directory>/altera/ <version number>.

Related Information

• Altera Licensing Site

• Altera Software Installation and Licensing Manual

OpenCore Plus IP Evaluation

Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and hardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to take your design to production. OpenCore Plus supports the following evaluations:

• Simulate the behavior of a licensed IP core in your system.

• Verify the functionality, size, and speed of the IP core quickly and easily.

• Generate time-limited device programming files for designs that include IP cores.

• Program a device with your IP core and verify your design in hardware

OpenCore Plus evaluation supports the following two operation modes:

• Untethered—run the design containing the licensed IP for a limited time.

• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a

connection between your board and the host computer.

All IP cores using OpenCore Plus in a design time out simultaneously when any IP core times out.Note:

Upgrading Outdated IP Cores

Each IP core has a release version number that corresponds to its Quartus II software release. When you include IP cores from a previous version of the Quartus II software in your project, click Project > Upgrade IP Components to identify and upgrade any outdated IP cores.

The Quartus II software prompts you to upgrade an IP core when the latest version includes port, parameter, or feature changes. The Quartus II software also notifies you when IP cores are unsupported or cannot upgrade in the current version of the Quartus II software. Most Altera IP cores support automatic simultaneous upgrade, as indicated in the Upgrade IP Components dialog box. IP cores unsupported by autoupgrade may require regeneration in the parameter editor, as indicated in the Upgrade IP Components dialog box.

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Displays upgrade status for all IP cores in the Project

Upgrades all IP core that support “Auto Upgrade”

Upgrades individual IP cores unsupported by “Auto Upgrade”

Indicates IP upgrade is: Required Optional Complete Unsupported

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Upgrading Outdated IP Cores

Before you begin

Upgrading IP cores changes your original design files. If you have not already preserved your original source files, click Project > Archive Project and save the project archive.

1. In the latest version of the Quartus II software, open the Quartus II project containing an outdated IP core variation.

2-3

Note:

File paths in a restored project archive must be relative to the project directory and you must reference the IP variation .v or .vhd file or .qsys file, not the .qip file.

2. Click Project > Upgrade IP Components. The Upgrade IP Components dialog box displays all outdated IP cores in your project, along with basic instructions for upgrading each core.

3. To simultaneously upgrade all IP cores that support automatic upgrade, click Perform Automatic Upgrade. The IP variation upgrades to the latest version.

4. To upgrade IP cores unsupported by automatic upgrade, follow these steps:

a. Select the IP core in the Upgrade IP Components dialog box. b. Click Upgrade in Editor. The parameter editor appears. c. Click Finish or Generate to regenerate the IP variation and complete the upgrade. The version number

updates when complete.

Note:

Example designs provided with any Altera IP core regenerate automatically whenever you upgrade the IP core in the Upgrade IP Components dialog box.

Figure 2-2: Upgrading Outdated IP Cores

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IP Catalog and Parameter Editor

Example 2-1: Upgrading IP Cores at the Command Line

Alternatively, you can upgrade IP cores at the command line. To upgrade a single IP core, type the following command:

quartus_sh --ip_upgrade -variation_files <my_ip_path> <project>

To upgrade a list of IP cores, type the following command:

quartus_sh --ip_upgrade -variation_files "<my_ip>.qsys;<my_ip>.<hdl>; <project>"

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Note:

IP cores older than Quartus II software version 12.0 do not support upgrade. Altera verifies that the current version of the Quartus II software compiles the previous version of each IP core. The MegaCore IP Library Release Notes reports any verification exceptions for MegaCore IP. The Quartus II Software and Device Support Release Notes reports any verification exceptions for other IP cores. Altera does not verify compilation for IP cores older than the previous two releases.

Related Information

• MegaCore IP Library Release Notes

• Quartus II Software and Device Support Release Notes

IP Catalog and Parameter Editor

The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize, and generate files representing your custom IP variation.

The IP Catalog automatically displays the IP cores available for your target device. Double-click any IP core name to launch the parameter editor and generate files representing your IP variation. The parameter editor prompts you to specify your IP variation name, optional ports, architecture features, and output file generation options. The parameter editor generates a top-level .qsys or .qip file representing the IP core in your project. Alternatively, you can define an IP variation without an open Quartus II project. When no project is open, select the Device Family directly in IP Catalog to filter IP cores by device.

Note:

Use the following features to help you quickly locate and select an IP core:

• Filter IP Catalog to Show IP for active device family or Show IP for all device families.

• Search to locate any full or partial IP core name in IP Catalog. Click Search for Partner IP, to access

partner IP information on the Altera website.

• Right-click an IP core name in IP Catalog to display details about supported devices, installation location, and links to documentation.

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The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes exclusive system interconnect, video and image processing, and other system-level IP that are not available in the Quartus II IP Catalog.

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Search and filter IP for your target device

Double-click to customize, right-click for information

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Figure 2-3: Quartus II IP Catalog

Using the Parameter Editor

2-5

Note:

The IP Catalog and parameter editor replace the MegaWizard™Plug-In Manager in the Quartus II software. The Quartus II software may generate messages that refer to the MegaWizard Plug-In Manager. Substitute "IP Catalog and parameter editor" for "MegaWizard Plug-In Manager" in these messages.

Using the Parameter Editor

The parameter editor helps you to configure your IP variation ports, parameters, architecture features, and output file generation options.

• Use preset settings in the parameter editor (where provided) to instantly apply preset parameter values for specific applications.

• View port and parameter descriptions, and links to documentation.

• Generate testbench systems or example designs (where provided).

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View IP port and parameter details

Apply preset parameters for specific applications

Specify your IP variation name and target device

Legacy parameter editors

2-6

Design Walkthrough

Figure 2-4: IP Parameter Editors

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Design Walkthrough

This walkthrough explains how to create a Triple-Speed Ethernet MegaCore function design using Qsys in the Quartus II software. After you generate a custom variation of the Triple-Speed Ethernet MegaCore function, you can incorporate it into your overall project.

This walkthrough includes the following steps:

1. Creating a New Quartus II Project on page 2-6

2. Specifying IP Core Parameters and Options on page 2-7

3. Generating a Design Example or Simulation Model on page 2-7

4. Simulate the System on page 2-8

5. Compiling the Triple-Speed Ethernet MegaCore Function Design on page 2-8

6. Programming an FPGA Device on page 2-8

Creating a New Quartus II Project

You need to create a new Quartus II project with the New Project Wizard, which specifies the working directory for the project, assigns the project name, and designates the name of the top-level design entity.

To create a new project, follow these steps:

1. From the Windows Start menu, select Programs > Altera > Quartus II <version> to launch the Quartus II software. Alternatively, you can use the Quartus II Web Edition software.

2. On the File menu, click New Project Wizard.

3. In the New Project Wizard: Directory, Name, Top-Level Entity page, specify the working directory, project name, and top-level design entity name. Click Next.

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Specifying IP Core Parameters and Options

2-7

4. In the New Project Wizard: Add Files page, select the existing design files (if any) you want to include in the project.

(1)

Click Next.

5. In the New Project Wizard: Family & Device Settings page, select the device family and specific device you want to target for compilation. Click Next.

6. In the EDA Tool Settings page, select the EDA tools you want to use with the Quartus II software to develop your project.

7. The last page in the New Project Wizard window shows the summary of your chosen settings. Click Finish to complete the Quartus II project creation.

Specifying IP Core Parameters and Options

Follow these steps to specify IP core parameters and options.

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears.

2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in your project. If prompted, also specify the target Altera device family and output file HDL preference. Click OK.

3. Specify parameters and options for your IP variation:

• Optionally select preset parameter values. Presets specify all initial parameter values for specific

applications (where provided).

• Specify parameters defining the IP core functionality, port configurations, and device-specific features.

• Specify options for generation of a timing netlist, simulation model, testbench, or example design

(where applicable).

• Specify options for processing the IP core files in other EDA tools.

4. Click Finish or Generate to generate synthesis and other optional files matching your IP variation specifications. The parameter editor generates the top-level .qip or .qsys IP variation file and HDL files for synthesis and simulation. Some IP cores also simultaneously generate a testbench or example design for hardware testing.

5. To generate a simulation testbench, click Generate > Generate Testbench System. Generate Testbench System is not available for some IP cores that do not provide a simulation testbench.

6. To generate a top-level HDL example for hardware verification, click Generate > HDL Example. Generate > HDL Example is not available for some IP cores.

The top-level IP variation is added to the current Quartus II project. Click Project > Add/Remove Files in Project to manually add a .qip or .qsys file to a project. Make appropriate pin assignments to connect ports.

Generating a Design Example or Simulation Model

After you have parameterized the MegaCore function, you can also generate a design example, in addition to generating the MegaCore component files.

In the parameter editor, click Example Design to create a functional simulation model (design example that includes a testbench). The testbench and the automated script are located in the <variation name>_testbench directory.

(1)

To include existing files, you must specify the directory path to where you installed the MegaCore function. You must also add the user libraries if you installed the MegaCore IP Library in a different directory from where you installed the Quartus II software.

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Simulate the System

Generating a design example can increase processing time.Note:

You can now integrate your custom IP core instance in your design, simulate, and compile. While integrating your IP core instance into your design, you must make appropriate pin assignments. You can create a virtual pin to avoid making specific pin assignments for top-level signals while you are simulating and not ready to map the design to hardware.

Related Information

• Testbench

More information about the MegaCore function simulation model.

• Quartus II Help

More information about the Quartus II software, including virtual pins.

Simulate the System

During system generation, Qsys generates a functional simulation model—or design example that includes a testbench—which you can use to simulate your system in any Altera-supported simulation tool.

Related Information

• Quartus II Software Release Notes

More information about the latest Altera-supported simulation tools.

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• Simulating Altera Designs

More information in volume 3 of the Quartus II Handbook about simulating Altera IP cores.

• System Design with Qsys

More information in volume 1 of the Quartus II Handbook about simulating Qsys systems.

Compiling the Triple-Speed Ethernet MegaCore Function Design

Before you begin

Refer to Design Considerations on page 8-1 chapter before compiling the Triple-Speed Ethernet MegaCore function design.

To compile your design, click Start Compilation on the Processing menu in the Quartus II software. You can use the generated .qip file to include relevant files into your project.

Related Information

Quartus II Help

More information about compilation in Quartus II software.

Programming an FPGA Device

After successfully compiling your design, program the targeted Altera device with the Quartus II Programmer and verify the design in hardware. For instructions on programming the FPGA device, refer to the Device Programming section in volume 3 of the Quartus II Handbook.

Related Information

Device Programming

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Generated Files

The type of files generated in your project directory and their names may vary depending on the custom variation of the MegaCore function you created.

Table 2-1: Generated Files

Generated Files

DescriptionFile Name

2-9

<variation_name>.v or

<variation_name>.vhd

A MegaCore function variation file, which defines a VHDL or Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside your design. Include this file when compiling your design in the Quartus II software.

<variation_name>.bsf

Quartus II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.

<variation_name>.qip and

<variation_name>.sip

<variation_name>.cmp

Contains Quartus II project information for your MegaCore function variations.

A VHDL component declaration file for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore.

<variation_name>.spd

Simulation Package Descriptor file. Specifies the files required for simulation.

Testbench Files (in <variation_name>_testbench folder)

Read me file for the testbench design.README.txt

generate_sim.qpf and

generate_sim.qsf

Dummy Quartus II project and project setting file. Use this to start the Quartus II in the correct directory to launch the generate_

sim_verilog.tcl and generate_sim_vhdl.tcl files.

generate_sim_verilog.tcl and

generate_sim_vhdl.tcl

/testbench_vhdl/<variation_name>/ <variation_name>_tb.vhd or

/testbench_verilog/<variation_name>/ <variation_name>_tb.v

<variation_name>_tb.tcl or

/testbench_verilog/<variation_name>/ run_ <variation_name>_tb.tcl

/testbench_vhdl/<variation_name>/ <variation_name>_wave.do or

/testbench_verilog/<variation_name>/ <variation_name>_wave.do

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A Tcl script to generate the DUT VHDL or Verilog HDL simulation model for use in the testbench.

VHDL or Verilog HDL testbench that exercises your MegaCore function variation in a third party simulator.

A Tcl script for use with the ModelSim simulation software./testbench_vhdl/<variation_name>/run_

A signal tracing macro script used with the ModelSim simulation software to display testbench signals.

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Design Constraint File No Longer Generated

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DescriptionFile Name

/testbench_vhdl/models or

/testbench_verilog/models

A directory containing VHDL and Verilog HDL models of the Ethernet generators and monitors used by the generated testbench.

Design Constraint File No Longer Generated

For a new Triple-Speed Ethernet MegaCore function created using the Quartus II software ACDS 13.0 or later, the Quartus II software no longer generate the <variation_name>_constraints.tcl file that contains the necessary constraints for the compilation of your MegaCore Function variation. Table 2-2 lists the recommended Quartus II pin assignments that you can set in your design.

Table 2-2: Recommended Quartus II Pin Assignments

Quartus II Pin

Assignment

INPUT_ REGISTER

OUTPUT_ REGISTER

IO_ STANDARD

Value

ONFAST_

1.4-V PCML or 1.5-V PCML

and TBI interface.

To optimize I/O timing for MII, GMII and TBI interface.

I/O standard for GXB serial input and output pins.

Design PinDescriptionAssignment

MII, GMII, RGMII, TBI input pins.To optimize I/O timing for MII, GMII

MII, GMII, RGMII, TBI output pins.

GXB transceiver serial input and output pins.

STANDARD

SIGNAL

LVDSIO_

I/O standard for LVDS/IO serial input and output pins.

Global clockGLOBAL_

To assign clock signals to use the global clock network. Use this setting to guide the Quartus II in the fitter process for better timing closure.

LVDS/IO transceiver serial input and output pins.

• ref_clk for MAC and PCS with

LVDS/IO (with internal FIFO).

• clk and reset pins for MAC

only (without internal FIFO).

• clk and ref_clk input pins for

MAC and PCS with transceiver (without internal FIFO).

Regional clockGLOBAL_

To assign clock signals to use the regional clock network. Use this setting to guide the Quartus II in the fitter process for better timing closure.

• rx_clk <n> and tx_clk <n>

input pins for MAC only using MII/GMII interface (without internal FIFO).

• rx_clk <n> input pin for MAC

only using RGMII interface (without internal FIFO).

OFFGLOBAL_

To prevent a signal to be used as a global signal.

Signals for Arria V devices:

• *reset_ff_wr and *reset_ff_

• *| altera_tse_reset_

synchronizer_chain_out

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Parameter Settings

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Parameter Settings

You customize the Triple-Speed Ethernet MegaCore function by specifying parameters using the Triple-Speed Ethernet parameter editor, launched from Qsys in the Quartus II software. The customization enables specific core features during synthesis and generation.

This chapter describes the parameters and how they affect the behavior of the MegaCore function. Each section corresponds to a page in the Parameter Settings tab in the parameter editor interface.

Core Configuration

Table 3-1: Core Configuration Parameters

Core Variation

• 10/100/1000 Mb Ethernet MAC

• 10/100/1000 Mb Ethernet MAC with 1000BASE-X/SGMII PCS

• 1000BASE-X/SGMII PCS only

• 1000 Mb Small MAC

• 10/100 Mb Small MAC

DescriptionValueName

Determines the primary blocks to include in the variation.

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with

On/OffEnable ECC protection

Turn on this option to enable ECC protection for internal memory blocks.

ISO 9001:2008 Registered

3-2

Ethernet MAC Options

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DescriptionValueName

Interface

• MII

• GMII

• RGMII

• MII/GMII

On/OffUse internal FIFO

1, 4, 8, 12, 16, 20, and 24Number of ports

Determines the Ethernet-side interface of the MAC block.

• MII—The only option available for 10/100 Mb Small MAC core variations.

• GMII—Available only for 1000 Mb Small MAC core variations.

• RGMII—Available for 10/100/1000 Mb Ethernet MAC and 1000 Mb Small MAC core variations.

• MII/GMII—Available only for 10/100/1000 Mb Ethernet MAC core variations. If this is selected, media independent interface (MII) is used for the 10/100 interface, and gigabit media independent interface (GMII) for the gigabit interface.

Turn on this option to include internal FIFO buffers in the core. You can only include internal FIFO buffers in single-port MACs.

Specifies the number of Ethernet ports supported by the IP core. This parameter is enabled if the parameter Use internal FIFO is turned off. A multiport MAC does not support internal FIFO buffers.

Transceiver type

Ethernet MAC Options

These options are enabled when your variation includes the MAC function. In small MACs, only the following options are available:

• None

• LVDS I/O

• GXB

This option is only available for variations that include the PCS block.

• None—the PCS block does not include an integrated transceiver module. The PCS block implements a ten-bit interface (TBI) to an external SERDES chip.

• LVDS I/O or GXB—the MegaCore function includes an integrated transceiver module to implement a 1.25 Gbps transceiver. Respective GXB module is included for target devices with GX transceivers. For target devices with LVDS I/O including Soft-CDR such as Stratix III, the ALTLVDS module is included.

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• Enable MAC 10/100 half duplex support (10/100 Small MAC variations)

• Align packet headers to 32-bit boundary (10/100 and 1000 Small MAC variations)

Table 3-2: MAC Options Parameters

Ethernet MAC Options

DescriptionValueName

3-3

duplex support

GMII/RGMII

unicast addresses

counters

On/OffEnable MAC 10/100 half

Turn on this option to include support for half duplex operation on 10/100 Mbps connections.

On/OffEnablelocal loopback on MII/

Turn on this option to enable local loopback on the MAC’s MII, GMII, or RGMII interface. If you turn on this option, the loopback function can be dynamically enabled or disabled during system operation via the MAC configuration register.

On/OffEnable supplemental MAC

Turn on this option to include support for supplementary destination MAC unicast addresses for fast hardware-based received frame filtering.

On/OffInclude statistics counters

Turn on this option to include support for simple network monitoring protocol (SNMP) management information base (MIB) and remote monitoring (RMON) statistics counter registers for incoming and outgoing Ethernet packets.

By default, the width of all statistics counters are 32 bits.

On/OffEnable 64-bit statistics byte

Turn on this option to extend the width of selected statistics counters— aOctetsTransmit-

tedOK, aOctetsReceivedOK, and etherStatsOctets—to 64 bits.

boundary

Parameter Settings

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On/OffInclude multicast hashtable

Turn on this option to implement a hash table, a fast hardware-based mechanism to detect and filter multicast destination MAC address in received Ethernet packets.

On/OffAlignpacket headers to 32-bit

Turn on this option to include logic that aligns all packet headers to a 32-bit boundary. This helps reduce software overhead processing in realignment of data buffers.

This option is available for MAC variations with 32 bits wide internal FIFO buffers and MAC variations without internal FIFO buffers.

You must turn on this option if you intend to use the Triple-Speed Ethernet MegaCore function with the Interniche TCP/IP protocol stack.

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FIFO Options

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DescriptionValueName

control

MDIO Module

(MDC/MDIO)

On/OffEnable full-duplex flow

Turn on this option to include the logic for fullduplex flow control that includes pause frames generation and termination.

On/OffEnable VLAN detection

Turn on this option to include the logic for VLAN and stacked VLAN frame detection. When turned off, the MAC does not detect VLAN and staked VLAN frames. The MAC forwards these frames to the user application without processing them.

On/OffEnablemagic packet detection

Turn on this option to include logic for magic packet detection (Wake-on LAN).

On/OffInclude MDIO module

Turn on this option if you want to access external PHY devices connected to the MAC function. When turned off, the core does not include the logic or signals associated with the MDIO interface.

—Host clock divisor

Clock divisor to divide the MAC control interface clock to produce the MDC clock output on the MDIO interface. The default value is 40.

For example, if the MAC control interface clock frequency is 100 MHz and the desired MDC clock frequency is 2.5 MHz, a host clock divisor of 40 should be specified.

FIFO Options

The FIFO options are enabled only for MAC variations that include internal FIFO buffers.

Table 3-3: FIFO Options Parameters

Width

Depth

Transmit

Receive

8 Bits and 32 BitsWidth

Between 64 and 64K

Altera recommends that the division factor is defined such that the MDC frequency does not exceed 2.5 MHz.

ParameterValueName

Determines the data width in bits of the transmit and receive FIFO buffers.

Determines the depth of the internal FIFO buffers.

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Timestamp Options

Table 3-4: Timestamp Options Parameters

Timestamp

Timestamp Options

ParameterValueName

3-5

On/OffEnable timestamping

On/OffEnable PTP 1-step clock

—Timestamp fingerprint width

PCS/Transceiver Options

The PCS/Transceiver options are enabled only if your core variation includes the PCS function.

Table 3-5: PCS/Transceiver Options Parameters

PCS Options

Turn on this parameter to enable time stamping on the transmitted and received frames.

Turn on this parameter to insert timestamp on PTP messages for 1-step clock based on the TX Timestamp Insert Control interface.

This parameter is disabled if you do not turn on Enable timestamping.

Use this parameter to set the width in bits for the timestamp fingerprint on the TX path. The default value is 4 bits.

ParameterValueName

Transceiver Options—apply only to variations that include GXB transceiver blocks

Parameter Settings

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Configures the PHY ID of the PCS block.—PHY ID (32 bit)

On/OffEnable SGMII bridge

Turn on this option to add the SGMII clock and rate-adaptation logic to the PCS block. This option allows you to configure the PCS either in SGMII mode or 1000Base-X mode. If your application only requires 1000BASE-X PCS, turning off this option reduces resource usage.

In Cyclone IV GX devices, REFCLK[0,1] and

REFCLK[4,5] cannot connect directly to the

GCLK network. If you enable the SGMII bridge, you must connect ref_clk to an alternative dedicated clock input pin.

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3-6

PCS/Transceiver Options

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ParameterValueName

powerdown signal

reconfiguration

On/OffExport transceiver

This option is not supported in Stratix V, Arria V, Arria V GZ, and Cyclone V devices.

Turn on this option to export the powerdown signal of the GX transceiver to the top-level of your design. Powerdown is shared among the transceivers in a quad. Therefore, turning on this option in multiport Ethernet configurations maximizes efficient use of transceivers within the quad.

Turn off this option to connect the powerdown signal internally to the PCS control register interface. This connection allows the host processor to control the transceiver powerdown in your system.

On/OffEnable transceiver dynamic

This option is always turned on in devices other than Arria GX and Stratix II GX. When this option is turned on, the MegaCore function includes the dynamic reconfiguration signals.

For designs targeting devices other than Arria V, Cyclone V, Stratix V, and Arria 10, Altera recommends that you instantiate the ALTGX_ RECONFIG megafunction and connect the megafunction to the dynamic reconfiguration signals to enable offset cancellation.

For Arria V, Cyclone V, and Stratix V designs, Altera recommends that you instantiate the Transceiver Reconfiguration Controller megafunction and connect the megafunction to the dynamic reconfiguration signals to enable offset cancellation. The transceivers in the Arria V, Cyclone V, and Stratix V designs are configured with Altera Custom PHY IP core. The Custom PHY IP core require two reconfiguration interfaces for external reconfiguration controller. For more information on the reconfiguration interfaces required, refer to the

Altera Transceiver PHY IP Core User Guide

and the respective device handbook.

For more information about quad sharing considerations, refer to Sharing PLLs in Devices

with GIGE PHY on page 8-6 .

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Parameter Settings

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PCS/Transceiver Options

ParameterValueName

3-7

0 – 284Starting channel number

Series V GXB Transceiver Options

TX PLLs type

• CMU

• ATX

Specifies the channel number for the GXB transceiver block. In a multiport MAC, this parameter specifies the channel number for the first port. Subsequent channel numbers are in four increments.

In designs with multiple instances of GXB transceiver block (multiple instances of TripleSpeed Ethernet IP core with GXB transceiver block or a combination of Triple-Speed Ethernet IP core and other IP cores), Altera recommends that you set a unique starting channel number for each instance to eliminate conflicts when the GXB transceiver blocks share a transceiver quad.

This option is not supported in Arria V, Cyclone V, Stratix V, and Arria 10 devices. For these devices, the channel numbers depends on the dynamic reconfiguration controller.

This option is only available for variations that include the PCS block for Stratix V and Arria V GZ devices.

Specifies the TX phase-locked loops (PLLs) type—CMU or ATX—in the GXB transceiver for Series V devices.

On/OffEnable SyncE Support

Turn on this option to enable SyncE support by separating the TX PLL and RX PLL reference clock.

TX PLL clock network

• x1

• xN

This option is only available for variations that include the PCS block for Arria V and Cyclone V devices.

Specifies the TX PLL clock network type.

Arria 10 GXB Transceiver Options

Turn on this option for the MegaCore function to include the dynamic reconfiguration signals.

dynamic reconfiguration

Note:

You must configure the Arria 10 Transceiver ATX PLL with an output clock frequency of 1250.0

On/OffEnable Arria 10 transceiver

MHz (instead of applying the default value of 625 MHz) when using the Arria 10 Transceiver Native PHY with the Triple-Speed Ethernet IP core.

Refer to the respective device handbook for more information on dynamic reconfiguration in Altera devices.

Related Information

Arria 10 Transceiver PHY User Guide

More information about the Arria 10 Transceiver ATX PLL.

Parameter Settings

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Functional Description

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The Triple-Speed Ethernet MegaCore function includes the following functions:

• 10/100/1000 Ethernet MAC

• 1000BASE-X/SGMII PCS With Optional Embedded PMA

• Altera IEEE 1588v2

10/100/1000 Ethernet MAC

The Altera 10/100/1000 Ethernet MAC function handles the flow of data between user applications and Ethernet network through an internal or external Ethernet PHY. Altera offers the following MAC variations:

• Variations with internal FIFO buffers—supports only single port.

• Variations without internal FIFO buffers—supports up to 24 ports and the ports can operate at different

speeds.

• Small MAC—provides basic functionalities of a MAC function using minimal resources.

Refer to 10/100/1000 Ethernet MAC Versus Small MAC on page 1-2 for a feature comparison between the 10/100/1000 Ethernet MAC and small MAC.

The MAC function supports the following Ethernet frames: basic, VLAN and stacked VLAN, jumbo, and control frames. For more information about these frame formats, refer to Ethernet Frame Format on page 12-1.

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with

ISO 9001:2008 Registered

Receive

FIFO Buffer

Transmit

FIFO Buffer

Configuration and

Statistics

MDIO Master

CRC Check

Pause Frame

Termination

MII/GMII/RGMII Receive

Local

Loopback

Receiver Control

MII/GMII/RGMII Transmit

PHY Management Interface

Control Interface

(Avalon-MM)

Magic Packet

Detection

Ethernet SideSystem Side

CRC

Generation

Pause Frame

Generation

Transmitter Control

MAC Transmit

Interface

(Avalon-ST)

MAC Receive

Interface

(Avalon-ST)

10/100/1000 Ethernet MAC with Internal FIFO Buffers

4-2

MAC Architecture

Figure 4-1: 10/100/1000 Ethernet MAC With Internal FIFO Buffers

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The FIFO buffers, which you can configure to 8- or 32-bits wide, store the transmit and receive data. The buffer width determines the data width on the Avalon-ST receive and transmit interfaces. You can configure the FIFO buffers to operate in cut-through or store-and-forward mode using the rx_section_full and

tx_section_full registers.

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Functional Description

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Configurationand

Statistics

CRC Check

Pause Frame

Termination

Port 0

Loopback

ReceiverControl

TransmitterControl

Magic Packet

Detection

CRC Generation

Pause Frame

Generation

Port n

. . .

MDIO Master

Configurationand

Statistics

CRC Check

Pause Frame

Termination

Loopback

ReceiverControl

TransmitterControl

Magic Packet

Detection

CRC Generation

Pause Frame

Generation

Shared

Configuration

Multiport MAC (Without Internal FIFO Buffers)

Ethernet Side (MII/GMII/RGMII)

System Side (Avalon-ST)

Transmit / Receive

Interfaces

Transmit / Receive

Interfaces

To/From

External PHY

To/From

External PHY

Avalon-MM Interface

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Figure 4-2: Multiport MAC Without Internal FIFO Buffers

MAC Interfaces

4-3

Functional Description

In a multiport MAC, the instances share the MDIO master and some configuration registers. You can use the Avalon-ST Multi-Channel Shared Memory FIFO core in Qsys to store the transmit and receive data.

Related Information

MAC Configuration Register Space on page 6-1

MAC Interfaces

The MAC function implements the following interfaces:

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MAC Transmit Datapath

• Avalon-ST on the system side.

• Avalon-ST sink port on transmit with the following properties:

• Fixed data width, 8 bits, in MAC variations without internal FIFO buffers; configurable data width,

8 or 32 bits, in MAC variations with internal FIFO buffers.

• Packet support using start-of-packet (SOP) and end-of-packet (EOP) signals, and partial final packet signals.

• Error reporting.

• Variable-length ready latency specified by the tx_almost_full register.

• Avalon-ST source port on receive with the following properties:

• Fixed data width of 8 bits in MAC variations without internal FIFO buffers; configurable data

width, 8 or 32 bits, in MAC variations with internal FIFO buffers.

• Backpressure is supported only in MAC variations with internal FIFO buffers. Transmission stops when the level of the FIFO buffer reaches the respective programmable thresholds.

• Packet support using SOP and EOP signals, and partial final packet signals.

• Error reporting.

• Ready latency is zero in MAC variations without internal FIFO buffers. In MAC variations with

internal FIFO buffers, the ready latency is two.

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• Media independent interfaces on the network side—select MII, GMII, or RGMII by setting the Interface

option on the Core Configuration page or the ETH_SPEED bit in the command_config register.

• Control interface—an Avalon-MM slave port that provides access to 256 32-bit configuration and status

registers, and statistics counters. This interface supports the use of waitrequest to stall the interconnect fabric for as many cycles as required.

• PHY management interface—implements the standard MDIO specification, IEEE 803.2 standard Clause 22, to access the PHY device management registers. This interface supports up to 32 PHY devices.

MAC variations without internal FIFO buffers implement the following additional interfaces:

• FIFO status interface—an Avalon-ST sink port that streams in the fill level of an external FIFO buffer. Only MAC variations without internal buffers implement this interface.

• Packet classification interface—an Avalon-ST source port that streams out receive packet classification information. Only MAC variations without internal buffers implement this interface.

Related Information

• Transmit Thresholds on page 4-15

• Interface Signals on page 7-1

• MAC Configuration Register Space on page 6-1

• Avalon Interface Specifications

More information about the Avalon interfaces.

MAC Transmit Datapath

On the transmit path, the MAC function accepts frames from a user application and constructs Ethernet frames before forwarding them to the PHY. Depending on the MAC configuration, the MAC function could perform the following tasks: realigns the payload, modifies the source address, calculates and appends the

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CRC-32 field, and inserts interpacket gap (IPG) bytes. In half-duplex mode, the MAC function also detects collision and attempts to retransmit frames when a collision occurs. The following conditions trigger transmission:

• In MAC variations with internal FIFO buffers:

• Cut-through mode—transmission starts when the level of the FIFO level hits the transmit section-full

• Store and forward mode—transmission starts when a full packet is received.

• In MAC variations without internal FIFO buffers, transmission starts as soon as data is available on the

Avalon-ST transmit interface.

Related Information

Ethernet Frame Format on page 12-1

IP Payload Re-alignment

If you turn the Align packet headers to 32-bit boundaries option, the MAC function removes the additional two bytes from the beginning of Ethernet frames.

Related Information

IP Payload Alignment on page 4-11

threshold.

IP Payload Re-alignment

4-5

Address Insertion

By default, the MAC function retains the source address received from the user application. You can configure the MAC function to replace the source address with the primary MAC address or any of the supplementary addresses by setting the TX_ADDR_INS bit in the command_config register to 1. The TX_ADDR_SEL bits in the

command_config register determines the address selection.

Related Information

Command_Config Register (Dword Offset 0x02) on page 6-7

Frame Payload Padding

The MAC function inserts padding bytes (0x00) when the payload length does not meet the minimum length required:

• 46 bytes for basic frames

• 42 bytes for VLAN tagged frames

• 38 bytes for stacked VLAN tagged frames

CRC-32 Generation

To turn on CRC-32 generation, you must set the OMIT_CRC bit in the tx_cmd_stat register to 0 and send the frame to the MAC function with the ff_tx_crc_fwd signal deasserted.

The following equation shows the CRC polynomial, as specified in the IEEE 802.3 standard:

FCS(X) = X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X1+1

The 32-bit CRC value occupies the FCS field with X31 in the least significant bit of the first byte. The CRC bits are thus transmitted in the following order: X31, X30,..., X1, X0.

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MAC Transmit

Control

MAC Transmit

Datapath

PHY Interface

Retransmission Block

PHY Control

LFSR

Col

Rd _en

Frame

Discard

MAC Transmit

Backoff

Period

Retransmit

Buffer

Control

64x8

Retransmit

Buffer

Avalon-ST Interface

WAddr RAddr

4-6

Interpacket Gap Insertion

In full-duplex mode, the MAC function maintains the minimum number of IPG configured in the

tx_ipg_length register between transmissions. You can configure the minimum IPG to any value between

64 and 216 bit times, where 64 bit times is the time it takes to transmit 64 bits of raw data on the medium.

In half-duplex mode, the MAC function constantly monitors the line. Transmission starts only when the line has been idle for a period of 96 bit times and any backoff time requirements have been satisfied. In accordance with the standard, the MAC function begins to measure the IPG when the m_rx_crs signal is deasserted.

Collision Detection in Half-Duplex Mode

Collision occurs only in a half-duplex network. It occurs when two or more nodes transmit concurrently. The PHY device asserts the m_rx_col signal to indicate collision.

When the MAC function detects collision during transmission, it stops the transmission and sends a 32-bit jam pattern instead. A jam pattern is a fixed pattern, 0x648532A6, and is not compared to the CRC of the frame. The probability of a jam pattern to be identical to the CRC is very low, 0.532%.

If the MAC function detects collision while transmitting the preamble or SFD field, it sends the jam pattern only after transmitting the SFD field, which subsequently results in a minimum of 96-bit fragment.

If the MAC function detects collision while transmitting the first 64 bytes, including the preamble and SFD fields, the MAC function waits for an interval equal to the backoff period and then retransmits the frame. The frame is stored in a 64-byte retransmit buffer. The backoff period is generated from a pseudo-random process, truncated binary exponential backoff.

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Figure 4-3: Frame Retransmission

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The backoff time is a multiple of slot times. One slot is equal to a 512 bit times period. The number of the delay slot times, before the Nth retransmission attempt, is chosen as a uniformly distributed random integer in the following range:

0 ≤ r < 2k

k = min(n, N), where n is the number of retransmissions and N = 10.

For example, after the first collision, the backoff period, in slot time, is 0 or 1. If a collision occurs during the first retransmission, the backoff period, in slot time, is 0, 1, 2, or 3.

The maximum backoff time, in 512 bit times slots, is limited by N set to 10 as specified in the IEEE Standard

802.3.

If collision occurs after 16 consecutive retransmissions, the MAC function reports an excessive collision condition by setting the EXCESS_COL bit in the command_config register to 1, and discards the current frame from the transmit FIFO buffer.

In networks that violate standard requirements, collision may occur after the transmission of the first 64 bytes. If this happens, the MAC function stops transmitting the current frame, discards the rest of the frame from the transmit FIFO buffer, and resumes transmitting the next available frame.

MAC Receive Datapath

The MAC function receives Ethernet frames from the network via a PHY and forwards the payload with relevant frame fields to the user application after performing checks, filtering invalid frames, and removing the preamble and SFD.

MAC Receive Datapath

4-7

Preamble Processing

The MAC function uses the SFD (0xD5) to identify the last byte of the preamble. If an SFD is not found after the seventh byte, the MAC function rejects the frame and discards it.

The IEEE standard specifies that frames must be separated by an interpacket gap (IPG) of at least 96 bit times. The MAC function, however, can accept frames with an IPG of less than 96 bit times; at least 8-bytes and 6-bytes in RGMII/GMII (1000 Mbps operation) and RGMII/MII (10/100 Mbps operation) respectively.

The MAC function removes the preamble and SFD fields from valid frames.

Collision Detection in Half-Duplex Mode

In half-duplex mode, the MAC function checks for collisions during frame reception. When collision is detected during the reception of the first 64 bytes, the MAC function discards the frame if the RX_ERR_DISC bit is set to 1. Otherwise, the MAC function forwards the frame to the user application with error.

Address Checking

The MAC function can accept frames with the following address types:

• Unicast address—bit 0 of the destination address is 0.

• Multicast address—bit 0 of the destination address is 1.

• Broadcast address—all 48 bits of the destination address are 1.

The MAC function always accepts broadcast frames. If promiscuous mode is enabled (PROMIS_EN bit in the command_config register = 1), the MAC function omits address filtering and accepts all frames.

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Hash

Generate

multicast_match

frame destination

address (47:0)

write_port

din

read_addr(5:0)

dout

hash_addr(5:0)

hash_wren

hash_data

wclk

Look-Up Table (64x1 DPRAM)

4-8

Unicast Address Checking

When promiscuous mode is disabled, the MAC function only accepts unicast frames if the destination address matches any of the following addresses:

• The primary address, configured in the registers mac_0 and mac_1

• The supplementary addresses, configured in the following registers: smac_0_0/smac_0_1,

smac_1_0/smac_1_1, smac_2_0/smac_2_1 and smac_3_0/smac_3_1

Otherwise, the MAC function discards the frame.

Multicast Address Resolution

You can use either a software program running on the host processor or a hardware multicast address resolution engine to resolve multicast addresses. Address resolution using a software program can affect the system performance, especially in gigabit mode.

The MAC function uses a 64-entry hash table in the register space, multicast hash table, to implement the hardware multicast address resolution engine as shown in figure below. The host processor must build the hash table according to the specified algorithm. A 6-bit code is generated from each multicast address by

XORing the address bits as shown in table below. This code represents the address of an entry in the hash

table. Write one to the most significant bit in the table entry. All multicast addresses that hash to the address of this entry are valid and accepted.

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You can choose to generate the 6-bit code from all 48 bits of the destination address by setting the MHASH_SEL bit in the command_config register to 0, or from the lower 24 bits by setting the MHASH_SEL bit to 1. The latter option is provided if you want to omit the manufacturer's code, which typically resides in the upper 24 bits of the destination address, when generating the 6-bit code.

Figure 4-4: Hardware Multicast Address Resolution Engine

Table 4-1: Hash Code Generation—Full Destination Address

Algorithm for generating the 6-bit code from the entire destination address.

xor multicast MAC address bits 7:00

ValueHash Code Bit

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xor multicast MAC address bits 15:81

xor multicast MAC address bits 23:162

xor multicast MAC address bits 31:243

xor multicast MAC address bits 39:324

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ValueHash Code Bit

xor multicast MAC address bits 47:405

Table 4-2: Hash Code Generation—Lower 24 Bits of Destination Address

Algorithm for generating the 6-bit code from the lower 24 bits of the destination address.

ValueHash Code Bit

xor multicast MAC address bits 3:00

xor multicast MAC address bits 7:41

xor multicast MAC address bits 11:82

xor multicast MAC address bits 15:123

xor multicast MAC address bits 19:164

xor multicast MAC address bits 23:205

The MAC function checks each multicast address received against the hash table, which serves as a fast matching engine, and a match is returned within one clock cycle. If there is no match, the MAC function discards the frame.

Frame Type Validation

4-9

All multicast frames are accepted if all entries in the hash table are one.

Frame Type Validation

The MAC function checks the length/type field to determine the frame type:

• Length/type < 0x600—the field represents the payload length of a basic Ethernet frame. The MAC function continues to check the frame and payload lengths.

• Length/type >= 0x600—the field represents the frame type.

• Length/type = 0x8100—VLAN or stacked VLAN tagged frames. The MAC function continues to

check the frame and payload lengths, and asserts the following signals:

• for VLAN frames, rx_err_stat[16] in MAC variations with internal FIFO buffers or

pkt_class_data[1] in MAC variations without internal FIFO buffers

• for stacked VLAN frames, rx_err_stat[17] in MAC variations with internal FIFO buffers or

pkt_class_data[0] in MAC variations without internal FIFO buffers.

• Length/type = 0x8088—control frames. The next two bytes, the Opcode field, indicate the type of

control frame.

• For pause frames (Opcode = 0x0001), the MAC function continues to check the frame and payload lengths. For valid pause frames, the MAC function proceeds with pause frame processing. The MAC function forwards pause frames to the user application only when the PAUSE_FWD bit in the

command_config register is set to 1.

• For other types of control frames, the MAC function accepts the frames and forwards them to the user application only when the CNTL_FRM_ENA bit in the command_config register is set to 1.

• For other field values, the MAC function forwards the receive frame to the user application.

Related Information

Remote Device Congestion on page 4-17

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Payload Pad Removal

You can turn on padding removal by setting the PAD_EN bit in the command_config register to 1. The MAC function removes the padding, prior to forwarding the frames to the user application, when the payload length is less than the following values for the different frame types:

• 46 bytes for basic MAC frames

• 42 bytes for VLAN tagged frames

• 38 bytes for stacked VLAN tagged frames

When padding removal is turned off, complete frames including the padding are forwarded to the AvalonST receive interface.

CRC Checking

The following equation shows the CRC polynomial, as specified in the IEEE 802.3 standard:

FCS(X) = X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X1+1

The 32-bit CRC value occupies the FCS field with X31 in the least significant bit of the first byte. The CRC bits are thus received in the following order: X31, X30,..., X1, X0.

If the MAC function detects CRC-32 error, it marks the frame invalid by asserting the following signals:

• rx_err[2] in MAC variations with internal FIFO buffers.

• data_rx_error[1] in MAC variations without internal FIFO buffers.

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The MAC function discards frames with CRC-32 error if the RX_ERR_DISC bit in the command_config register is set to 1.

The MAC function forwards the CRC-32 field to the user application if the CRC_FWD and PAD_EN bits in the

command_config register are 1 and 0 respectively. Otherwise, the CRC-32 field is removed from the frame.

Length Checking

The MAC function checks the frame and payload lengths of basic, VLAN tagged, and stacked VLAN tagged frames.

The frame length must be at least 64 (0x40) bytes and not exceed the following maximum value for the different frame types:

• Basic frames—the value specified in the frm_length register

• VLAN tagged frames—the value specified in the frm_length register plus four

• Stacked VLAN tagged frames—the value specified in the frm_length register plus eight

To prevent FIFO buffer overflow, the MAC function truncates the frame if it is more than 11 bytes longer than the allowed maximum length.

For frames of a valid length, the MAC function continues to check the payload length if the NO_LGTH_CHECK bit in the command_config register is set to 0. The MAC function keeps track of the payload length as it receives a frame, and checks the length against the length/type field in basic MAC frames or the client length/type field in VLAN tagged frames. The payload length is valid if it satisfies the following conditions:

• The actual payload length matches the value in the length/type or client length/type field.

• Basic frames—the payload length is between 46 (0x2E)and 1536 (0x0600) bytes, excluding 1536.

• VLAN tagged frames—the payload length is between 42 (0x2A)and 1536 (0x0600), excluding 1536.

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• Stacked VLAN tagged frames—the payload length is between 38 (0x26) and 1536 (0x0600), excluding

If the frame or payload length is not valid, the MAC function asserts one of the following signals to indicate length error:

• rx_err[1] in MACs with internal FIFO buffers.

• data_rx_error[0] in MACs without internal FIFO buffers.

Frame Writing

The MegaCore function removes the preamble and SFD fields from the frame. The CRC field and padding bytes may be removed depending on the configuration.

For MAC variations with internal FIFO buffers, the MAC function writes the frame to the internal receive FIFO buffers.For MAC variations without internal FIFO buffers, it forwards the frame to the Avalon-ST receive interface.

MAC variations without internal FIFO buffers do not support backpressure on the Avalon-ST receive interface. In this variation, if the receiving component is not ready to receive data from the MAC function, the frame gets truncated with error and subsequent frames are also dropped with error.

IP Payload Alignment

The network stack makes frequent use of the IP addresses stored in Ethernet frames. When you turn on the Align packet headers to 32-bit boundaries option, the MAC function aligns the IP payload on a 32-bit boundary by adding two bytes to the beginning of Ethernet frames. The padding of Ethernet frames are determined by the registers tx_cmd_stat and rx_cmd_stat on transmit and receive, respectively.

1536.

Frame Writing

4-11

Table 4-3: 32-Bit Interface Data Structure — Non-IP Aligned Ethernet Frame

Bits

Table 4-4: 32-Bit Interface Data Structure — IP Aligned Ethernet Frame

Bits

MAC Transmit and Receive Latencies

Altera uses the following definitions for the transmit and receive latencies:

• Transmit latency is the number of clock cycles the MAC function takes to transmit the first bit on the network-side interface (MII/GMII/RGMII) after the bit was first available on the Avalon-ST interface.

• Receive latency is the number of clock cycles the MAC function takes to present the first bit on the AvalonST interface after the bit was received on the network-side interface (MII/GMII/RGMII).

7...015...823...1631...24

Byte 3Byte 2Byte 1Byte 0

Byte 7Byte 6Byte 5Byte 4

7...015...823...1631...24

Byte 1Byte 0padded with zeros

Byte 5Byte 4Byte 3Byte 2

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FIFO Buffer Thresholds

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Table 4-5: Transmit and Receive Nominal Latency

The transmit and receive nominal latencies in various modes. The FIFO buffer thresholds are set to the typical values specified in this user guide when deriving the latencies.

MAC Configuration

Latency (Clock Cycles) (1)

ReceiveTransmit

MAC with Internal FIFO Buffers (2)

11032GMII in cut-through mode

21841MII in cut-through mode

11333RGMII in gigabit and cut-through mode

22142RGMII in 10/100 Mbps and cut-through mode

MAC without Internal FIFO Buffers (3)

3711GMII

7722MII

4012RGMII in gigabit mode

8023RGMII in10/100 Mbps

Notes to Table 4-5 :

1. The clocks in all domains are running at the same frequency.

2. The data width is set to 32 bits.

3. The data width is set to 8 bits.

Related Information

Base Configuration Registers (Dword Offset 0x00 – 0x17) on page 6-3

FIFO Buffer Thresholds

For MAC variations with internal FIFO buffers, you can change the operations of the FIFO buffers, and manage potential FIFO buffer overflow or underflow by configuring the following thresholds:

• Almost empty

• Almost full

• Section empty

• Section full

These thresholds are defined in bytes for 8-bit wide FIFO buffers and in words for 32-bit wide FIFO buffers. The FIFO buffer thresholds are configured via the registers.

Altera Corporation

Functional Description

Send Feedback

Network

Switch Fabric

Frame Buffer n

Frame Buffer n - 1

Frame Buffer k

Frame Buffer 2

Frame Buffer 1

The remaining

unwritten entries in

the FIFO buffer

before it is full.

Almost full

The remaining

unread entries in

the FIFO buffer

before it is empty.

Almost empty

An early indication that the FIFO buffer is getting full.

Section Empty

Sufficient unread entries in the FIFO buffer for the user application to start reading from it.

Section full

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Receive Thresholds

Figure 4-5: Receive FIFO Thresholds

Receive Thresholds

4-13

Functional Description

Table 4-6: Receive Thresholds

rx_almost_emptyAlmost

empty

Send Feedback

DescriptionRegister NameThreshold

The number of unread entries in the FIFO buffer before the buffer is empty. When the level of the FIFO buffer reaches this threshold, the MAC function asserts the ff_rx_a_empty signal. The MAC function stops reading from the FIFO buffer and subsequently stops transferring data to the user application to avoid buffer underflow.

When the MAC function detects an EOP, it transfers all data to the user application even if the number of unread entries is below this threshold.

Altera Corporation

4-14

Receive Thresholds

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DescriptionRegister NameThreshold

empty

rx_almost_fullAlmost full

The number of unwritten entries in the FIFO buffer before the buffer is full. When the level of the FIFO buffer reaches this threshold, the MAC function asserts the ff_rx_a_full signal. If the user application is not ready to receive data (ff_rx_rdy = 0), the MAC function performs the following operations:

• Stops writing data to the FIFO buffer.

• Truncates received frames to avoid FIFO buffer overflow.

• Asserts the rx_err[0] signal when the ff_rx_eop signal is

asserted.

• Marks the truncated frame invalid by setting the rx_err[3]

signal to 1.

If the RX_ERR_DISC bit in the command_config register is set to 1 and the section-full (rx_section_full) threshold is set to 0, the MAC function discards frames with error received on the AvalonST interface.

rx_section_emptySection

An early indication that the FIFO buffer is getting full. When the level of the FIFO buffer hits this threshold, the MAC function generates an XOFF pause frame to indicate FIFO congestion to the remote Ethernet device. When the FIFO level goes below this threshold, the MAC function generates an XON pause frame to indicate its readiness to receive new frames.

To avoid data loss, you can use this threshold as an early warning to the remote Ethernet device on the potential FIFO buffer congestion before the buffer level hits the almost-full threshold. The MAC function truncates receive frames when the buffer level hits the almost-full threshold.

rx_section_fullSection full

The section-full threshold indicates that there are sufficient entries in the FIFO buffer for the user application to start reading from it. The MAC function asserts the ff_rx_dsav signal when the buffer level hits this threshold.

Set this threshold to 0 to enable store and forward on the receive datapath. In the store and forward mode, the ff_rx_dsav signal remains deasserted. The MAC function asserts the ff_rx_dval signal as soon as a complete frame is written to the FIFO buffer.

Altera Corporation

Functional Description

Send Feedback

Network

Switch Fabric

Frame Buffer n

Frame Buffer n - 1

Frame Buffer k

Frame Buffer 1

The remaining

unwritten entries in

the FIFO buffer

before it is full.

Almost full

The remaining

unread entries in

the FIFO buffer

before it is empty.

Almost empty

An early indication that the FIFO buffer is getting full.

Section Empty

Sufficient unread entries in the FIFO buffer for the transmitter to start transmission.

Section full

Frame Buffer 2

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Transmit Thresholds

Figure 4-6: Transmit FIFO Thresholds

Transmit Thresholds

4-15

Functional Description

Table 4-7: Transmit Thresholds

tx_almost_emptyAlmost

empty

tx_almost_fullAlmost full

tx_section_emptySection

empty

tx_section_fullSection full

Send Feedback

DescriptionRegister NameThreshold

The number of unread entries in the FIFO buffer before the buffer is empty. When the level of the FIFO buffer reaches this threshold, the MAC function asserts the ff_tx_a_empty signal. The MAC function stops reading from the FIFO buffer and sends the Ethernet frame with GMII / MII/ RGMII error to avoid FIFO underflow.

The number of unwritten entries in the FIFO buffer before the buffer is full. When the level of the FIFO buffer reaches this threshold, the MAC function asserts the ff_tx_a_full signal. The MAC function deasserts the ff_tx_rdy signal to backpressure the Avalon-ST transmit interface.

An early indication that the FIFO buffer is getting full. When the level of the FIFO buffer reaches this threshold, the MAC function deasserts the ff_tx_septy signal. This threshold can serve as a warning about potential FIFO buffer congestion.

This threshold indicates that there are sufficient entries in the FIFO buffer to start frame transmission.

Set this threshold to 0 to enable store and forward on the transmit path. When you enable the store and forward mode, the MAC function forwards each frame as soon as it is completely written to the transmit FIFO buffer.

Altera Corporation

[1]

[2]

[5]

[3]

[4]

ff_tx_data

ff_tx_sop ff_tx_eop

ff_tx_rdy

ff_tx_wren

ff_tx_crc_fwd

ff_tx_err

ff_tx_septy

ff_tx_uflow

ff_tx_a_full

ff_tx_a_empty

gm_tx_err

gm_tx_en

gm_tx_d

GMII Transmit

Transmit FIFO

valid valid

valid

4-16

Transmit FIFO Buffer Underflow

If the transmit FIFO buffer hits the almost-empty threshold during transmission and the FIFO buffer does not contain the end-of-packet indication, the MAC function stops reading data from the FIFO buffer and initiates the following actions:

1. The MAC function asserts the RGMII/GMII/MII error signals (tx_control/gm_tx_err/m_tx_err) to indicate that the fragment transferred is not valid.

2. The MAC function deasserts the RGMII/GMII/MII transmit enable signals (tx_control/gm_tx_en/m_tx_en) to terminate the frame transmission.

3. After the underflow, the user application completes the frame transmission.

4. The transmitter control discards any new data in the FIFO buffer until the end of frame is reached.

5. The MAC function starts to transfer data on the RGMII/GMII/MII when the user application sends a

new frame with an SOP.

Figure 4-7: Transmit FIFO Buffer Underflow

Figure illustrates the FIFO buffer underflow protection algorithm for gigabit Ethernet system.

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Congestion and Flow Control

In full-duplex mode, the MAC function implements flow control to manage the following types of congestion:

• Remote device congestion—the receiving device experiences congestion and requests the MAC function to stop sending data.

• Receive FIFO buffer congestion—when the receive FIFO buffer is almost full, the MAC function sends a pause frame to the remote device requesting the remote device to stop sending data.

• Local device congestion—any device connected to the MAC function, such as a processor, can request the remote device to stop data transmission.

Related Information

MAC Configuration Register Space on page 6-1

Altera Corporation

Functional Description

Send Feedback

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Remote Device Congestion

When the MAC function receives an XOFF pause frame and the PAUSE_IGNORE bit in the command_config register is set to 0, the MAC function completes the transfer of the current frame and stops transmission for the amount of time specified by the pause quanta in 512 bit times increments. Transmission resumes when the timer expires or when the MAC function receives an XON frame.

You can configure the MAC function to ignore pause frames by setting the PAUSE_IGNORE bit in the

command_config register is set to 1.

Receive FIFO Buffer and Local Device Congestion

Pause frames generated are compliant to the IEEE Standard 802.3 annex 31A & B. The MAC function generates pause frames when the level of the receive FIFO buffer hits a level that can potentially cause an overflow, or at the request of the user application. The user application can trigger the generation of an XOFF pause frame by setting the XOFF_GEN bit in the command_config register to 1 or asserting the xoff_gen signal.

For MAC variations with internal FIFO buffers, the MAC function generates an XOFF pause frame when the level of the FIFO buffer reaches the section-empty threshold (rx_section_empty). If transmission is in progress, the MAC function waits for the transmission to complete before generating the pause frame. The fill level of an external FIFO buffer is obtained via the Avalon-ST receive FIFO status interface.

When generating a pause frame, the MAC function fills the pause quanta bytes P1 and P2 with the value configured in the pause_quant register. The source address is set to the primary MAC address configured in the mac_0 and mac_1 registers, and the destination address is set to a fixed multicast address, 01-80-C200-00-01 (0x010000c28001).

Remote Device Congestion

4-17

The MAC function automatically generates an XON pause frame when the FIFO buffer section-empty flag is deasserted and the current frame transmission is completed. The user application can trigger the generation of an XON pause frame by clearing the XOFF_GEN bit and signal, and subsequently setting the XON_GEN bit to 1 or asserting the XON_GEN signal.

When generating an XON pause frame, the MAC function fills the pause quanta (payload bytes P1 and P2) with 0x0000 (zero quanta). The source address is set to the primary MAC address configured in the mac_0 and mac_1 registers and the destination address is set to a fixed multicast address, 01-80-C2-00-00-01 (0x010000c28001).

In addition to the flow control mechanism, the MAC function prevents an overflow by truncating excess frames. The status bit, rx_err[3], is set to 1 to indicate such errors. The user application should subsequently discard these frames by setting the RX_ERR_DISC bit in the command_config register to 1.

Magic Packets

A magic packet can be a unicast, multicast, or broadcast packet which carries a defined sequence in the payload section. Magic packets are received and acted upon only under specific conditions, typically in power-down mode.

The defined sequence is a stream of six consecutive 0xFF bytes followed by a sequence of 16 consecutive unicast MAC addresses. The unicast address is the address of the node to be awakened.

The sequence can be located anywhere in the magic packet payload and the magic packet is formed with a standard Ethernet header, optional padding and CRC.

Functional Description

Send Feedback

Altera Corporation

4-18

Sleep Mode

You can only put a node to sleep (set SLEEP bit in the command_config register to 1 and deassert the

magic_sleep_n signal) if magic packet detection is enabled (set the MAGIC_ENA bit in the command_config

Altera recommends that you do not put a node to sleep if you disable magic packet detection.

Network transmission is disabled when a node is put to sleep. The receiver remains enabled, but it ignores all traffic from the line except magic packets to allow a remote agent to wake up the node. In the sleep mode, only etherStatsPkts and etherStatsOctets count the traffic statistics.

Magic Packet Detection

Magic packet detection wakes up a node that was put to sleep. The MAC function detects magic packets with any of the following destination addresses:

• Any multicast address

• A broadcast address

• The primary MAC address configured in the mac_0 and mac_1 registers

• Any of the supplementary MAC addresses configured in the following registers if they are enabled:

smac_0_0, smac_0_1, smac_1_0, smac_1_1, smac_2_0, smac_2_1, smac_3_0 and smac_3_1

When the MAC function detects a magic packet, the WAKEUP bit in the command_config register is set to 1, and the etherStatsPkts and etherStatsOctets statistics registers are incremented.

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Magic packet detection is disabled when the SLEEP bit in the command_config register is set to 0. Setting the

SLEEP bit to 0 also resets the WAKEUP bit to 0 and resumes the transmit and receive operations.

MAC Local Loopback

You can enable local loopback on the MII/GMII/RGMII of the MAC function to exercise the transmit and receive paths. If you enable local loopback, use the same clock source for both the transmit and receive clocks. If you use different clock sources, ensure that the difference between the transmit and receive clocks is less than ±100 ppm.

To enable local loopback:

1. Initiate software reset by setting the SW_RESET bit in command_config register to 1.

Software reset disables the transmit and receive operations, flushes the internal FIFOs, and clears the statistics counters. The SW_RESET bit is automatically cleared upon completion.

2. When software reset is complete, enable local loopback on the MAC's MII/GMII/RGMII by setting the

LOOP_ENA bit in command_config register to 1.

3. Enable transmit and receive operations by setting the TX_ENA and RX_ENA bits in command_config register to 1.

4. Initiate frame transmission.

5. Compare the statistics counters aFramesTransmittedOK and aFramesReceivedOK to verify that the

transmit and receive frame counts are equal.

6. Check the statistics counters ifInErrors and ifOutErrors to determine the number of packets transmitted and received with errors.

7. To disable loopback, initiate a software reset and set the LOOP_ENA bit in command_config register to 0.

Altera Corporation

Functional Description

Send Feedback

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MAC Error Correction Code

The error correction code feature is implemented to memory instances in the MegaCore function. This feature is capable of detecting single and double bit errors, and can fix single bit errors in the corrupted data.

Table 4-8: Core Variation and ECC Protection Support

MAC Error Correction Code

ECC Protection SupportCore Variation

4-19

10/100/1000 Mb Ethernet MAC

10/100/1000 Mb Ethernet MAC with 1000BASE-X/SGMII PCS

10/100 Mb Small MAC

Protects the following options:

transmit and receive FIFO buffer

Retransmit buffer (if half duplex is enabled)

Statistic counters (if enabled)

Multicast hashtable (if enabled)

Protects the following options:

transmit and receive FIFO buffer

Retransmit buffer (if half duplex is enabled)

Statistic counters (if enabled)

Multicast hashtable (if enabled)

SGMII bridge (if enabled)

Protects the SGMII bridge (if enabled)1000BASE-X/SGMII PCS only

Protects the transmit and receive FIFO buffer1000 Mb Small MAC

Protects the following options:

transmit and receive FIFO buffer

When you enable this feature, the following output ports are added for 10/100/1000 Mb Ethernet MAC and 1000BASE-X/SGMII PCS variants to provide ECC status of all the memory instances in the MegaCore function.

• Single channel core configuration—eccstatus[1:0] output ports.

• Multi-channel core configuration—eccstatus_<n>[1:0] output ports, where eccstatus_0[1:0] is for

channel 0, eccstatus_1[1:0] for channel 1, and so on.

MAC Reset

A hardware reset resets all logic. A software reset only disables the transmit and receive paths, clears all statistics registers, and flushes the receive FIFO buffer. The values of configuration registers, such as the MAC address and thresholds of the FIFO buffers, are preserved during a software reset.

When you trigger a software reset, the MAC function sets the TX_ENA and RX_ENA bits in the command_config register to 0 to disable the transmit and receive paths. However, the transmit and receive paths are only disabled when the current frame transmission and reception complete.

Functional Description

Send Feedback

Retransmit buffer (if half duplex is enabled)

Altera Corporation

Receive Frames

Transmit Frames

Flush FIFO

Clear Statistics

Counters

Yes Yes

Yes

RX _ENA =0 TX _ENA = 0

START

(SW_RESET = 1)

END

(SW_RESET = 0)

Frame

Reception

Completed?

Frame

Transmission

Completed?

MAC with

internal FIFO?

Receive

FIFO empty?

Statistics Counters Enabled?

4-20

PHY Management (MDIO)

• To trigger a hardware reset, assert the reset signal.

• To trigger a software reset, set the SW_RESET bit in the command_config register to 1. The SW_RESET bit

is cleared automatically when the software reset ends.

Altera recommends that you perform a software reset and wait for the software reset sequence to complete before changing the MAC operating speed and mode (full/half duplex). If you want to change the operating speed or mode without changing other configurations, preserve the command_config register before performing the software reset and restore the register after the changing the MAC operating speed or mode.

Figure 4-8: Software Reset Sequence

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Note:

If the SW_RESET bit is 1 when the line clocks are not available (for example, cable is disconnected), the statistics registers may not be cleared. The read_timeout register is then set to 1 to indicate that the statistics registers were not cleared.

PHY Management (MDIO)

This module implements the standard MDIO specification, IEEE 803.2 standard Clause 22, to access the PHY device management registers, and supports up to 32 PHY devices.

Altera Corporation

To access each PHY device, write the PHY address to the MDIO register (mdio_addr0/1) followed by the transaction data (MDIO Space 0/1). For faster access, the MAC function allows up to two PHY devices to be mapped in its register space at any one time. Subsequent transactions to the same PHYs do not require writing the PHY addresses to the register space thus reducing the transaction overhead. You can access the MDIO registers via the Avalon-MM interface.

For more information about the registers of a PHY device, refer to the specification provided with the device.

Functional Description

Send Feedback

PHY Addr

MDIO Frame

Generation and

Decoding

MDIO Interface

mdc

mdio_in

mdio_out

mdio_oen

PHY Addr

PHY

Management

Registers

MDIO Frame Generation &

Decoding

mdio

mdc

addr

PHY

Management

Registers

MDIO Frame Generation &

Decoding

mdio

mdc

addr

Avalon-MM Control

Interface

10/100/1000 Ethernet MAC

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MDIO Connection

Figure 4-9: MDIO Interface

MDIO Connection

4-21

For more information about the MDIO registers, refer to MAC Configuration Register Space on page 6-1.

MDIO Frame Format

The MDIO master communicates with the slave PHY device using MDIO frames. A complete frame is 64 bits long and consists of 32-bit preamble, 14-bit command, 2-bit bus direction change, and 16-bit data. Each bit is transferred on the rising edge of the MDIO clock, mdc.

Table 4-9: MDIO Frame Formats (Read/Write)

Field settings for MDIO transactions.

PREType

MSB LSB

Table 4-10: MDIO Frame Field Descriptions

Preamble. 32 bits of logical 1 sent prior to every transaction.PRE

Start indication. Standard MDIO (Clause 22): 0b01.ST

MSB LSB

Addr1

MSB LSB

Command

DescriptionName

MSB LSB

TAAddr2

MSB LSB

IdleData

ZxxxxxxxxxxxxxxxxZ0xxxxxxxxxx10011 ... 1Read

Zxxxxxxxxxxxxxxxx10xxxxxxxxxx01011 ... 1Write

Functional Description

Send Feedback

Opcode. Defines the transaction type.OP

Altera Corporation

Unused

Altera FPGA

ena_10 eth_mode

set_10

set_1000

tx_clk

m_tx_d(3:0) m_tx_en

m_tx_err

gm_tx_d(7:0) gm_tx_en gm_tx_err

rx_clk

m_rx_d(3:0) m_rx_en

gm_rx_d(7:0) gm_rx_dv gm_rx_err

m_rx_err

Reference Clock

125 MHz

Vcc

clk_in/xtali

gtx_clk

tx_en tx_err

rx_clk

rx_dv

rx_err

txd(7:0)

rxd(7:0)

10/100/1000

Ethernet

MAC

Gigabit

PHY

4-22

Connecting MAC to External PHYs

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DescriptionName

Addr1

The PHY device address (PHYAD). Up to 32 devices can be addressed. For PHY device 0, the Addr1 field is set to the value configured in the mdio_addr0 register. For PHY device 1, the Addr1 field is set to the value configured in the mdio_addr1 register.

Turnaround time. Two bit times are reserved for read operations to switch the data bus from write to read for read operations. The PHY device presents its register contents in the data phase and drives the bus from the 2ndbit of the turnaround phase.

16-bit data written to or read from the PHY device.Data

Between frames, the MDIO data signal is tri-stated.Idle

Connecting MAC to External PHYs

The MAC function implements a flexible network interface—MII for 10/100-Mbps interfaces, RGMII or GMII for 1000-Mbps interfaces—that you can use in multiple applications. This section provides the guidelines for implementing the following network applications:

• Gigabit Ethernet operation

• Programmable 10/100 Ethernet operation

• Programmable 10/100/1000 Ethernet operation

Gigabit Ethernet

You can connect gigabit Ethernet PHYs to the MAC function via GMII or RGMII. On the receive path, connect the 125-MHz clock provided by the PHY device to the MAC clock, rx_clk. On transmit, drive a 125-MHz clock to the PHY GMII or RGMII. Connect a 125-MHz clock source to the MAC transmit clock,

tx_clk.

Figure 4-10: Gigabit PHY to MAC via GMII

Altera Corporation

A technology specific clock driver is required to generate a clock centered with the GMII or RGMII data from the MAC. The clock driver can be a PLL, a delay line or a DDR flip-flop.

Functional Description

Send Feedback

Unused

Altera FPGA

Optional tie to 0

if not used

Reference Clock

25Mhz

ena_10 eth_mode set_10 set_1000

tx_clk m_tx_d(3:0) m_tx_en m_tx_err

gm_tx_d(7:0) gm_tx_en gm_tx_err

rx_clk m_rx_d(3: 0) m_rx_en

gm_rx_d(7 :0) gm_rx_dv gm_rx_err

m_rx_err

tx_clk

txd(3:0)

tx_en tx_err

clk_in/xtali

rx_clk

rxd(3:0)

rx_dv

rx_err

m_rx_col m_rx_crs

10/100/1000

Ethernet

MAC

10/100

PHY

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Programmable 10/100 Ethernet

Connect 10/100 Ethernet PHYs to the MAC function via MII. On the receive path, connect the 25-MHz (100 Mbps) or 2.5-MHz (10 Mbps) clock provided by the PHY device to the MAC clock, rx_clk. On the transmit path, connect the 25 MHz (100 Mbps) or a 2.5 MHz (10 Mbps) clock provided by the PHY to the MAC clock, tx_clk.

Figure 4-11: 10/100 PHY Interface

Programmable 10/100 Ethernet

4-23

Programmable 10/100/1000 Ethernet Operation

Typically, 10/100/1000 Ethernet PHY devices implement a shared interface that you connect to a 10/100-Mbps MAC via MII/RGMII or to a gigabit MAC via GMII/RGMII.

On the receive path, connect the clock provided by the PHY device (2.5 MHz, 25 MHz or 125 MHz) to the MAC clock, rx_clk. The PHY interface is connected to both the MII (active PHY signals) and GMII of the MAC function.

On the transmit path, standard programmable PHY devices operating in 10/100 mode generate a 2.5 MHz (10 Mbps) or a 25 MHz (100 Mbps) clock. In gigabit mode, the PHY device expects a 125-MHz clock from the MAC function. Because the MAC function does not generate a clock output, an external clock module is introduced to drive the 125 MHz clock to the MAC function and PHY devices. In 10/100 mode, the clock generated by the MAC to the PHY can be tri-stated.

During transmission, the MAC control signal eth_mode selects either MII or GMII. The MAC function asserts the eth_mode signal when the MAC function operates in gigabit mode, which subsequently drives the MAC GMII to the PHY interface. The eth_mode signal is deasserted when the MAC function operates in 10/100 mode. In this mode, the MAC MII is driven to the PHY interface.

Functional Description

Send Feedback

Altera Corporation

Altera FPGA

Unused

eth_mode set_1000

set_10

tx_clk

m_tx_d(3:0) m_tx_en m_tx_err gm_tx_d(7:0) gm_tx_en gm_tx_err

rx_clk m_rx_d(3:0) m_rx_en

gm_rx_d(7: 0 ) gm_rx_dv gm_rx_err

m_rx_err

en_10

25MHz

Osc

125/25/2.5 MHz

25MHz

clk_in/xtali

25/2.5 MHz

gtx_clk

txd(7:0)

tx_en

tx_err

tx_clk

rx_clk

rxd(7:0)

rx_dv rx_err

Clock Driver

10/100/1000

Ethernet

MAC

10/100/1000

PHY

Optional tieto 0

if notused

Altera FPGA

ena _10 eth_mode

set _10

set _1000

tx_clk tx_control

rgmii _out [3:0]

rx_clk rx_control

rgmii _in[3:0]

Reference Clock

125 MHz

gtx_clk

tx_en

txd[3:0 ]

rx_clk

rx_dv

rxd [3:0]

clk _in/xtali

Clock

Divider

10/100/1000

Ethernet

MAC

10/100/1000

PHY

Optional tie to 0

if not used

4-24

1000BASE-X/SGMII PCS With Optional Embedded PMA

Figure 4-12: 10/100/1000 PHY Interface via MII/GMII

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Figure 4-13: 10/100/1000 PHY Interface via RGMII

1000BASE-X/SGMII PCS With Optional Embedded PMA

The Altera 1000BASE-X/SGMII PCS function implements the functionality specified by IEEE 802.3 Clause

36. The PCS function is accessible via MII (SGMII) or GMII (1000BASE-X/SGMII). The PCS function

interfaces to an on- or off-chip SERDES component via the industry standard ten-bit interface (TBI).

Altera Corporation

Functional Description

Send Feedback

SGMII

Receive

Converter

SGMII

Transmit

Converter

Configuration

Encapsulation

De -encapsulation

Synchronization

Auto-Negotiation

1000BASE -X/SGMII PCS

TBI Receive

TBI Transmit

Status LEDs

Avalon -MM Interface

MII/GMII

Receive

MII/GMII Transmit

Ethernet Side

MAC Side

8b/10b

Decoder

8b/10b

Encoder

1000 Base-X PCS Receive Control

1000 Base-X PCS TransmitControl

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You can configure the PCS function to include an embedded physical medium attachment (PMA) with a a serial transceiver or LVDS I/O and soft CDR. The PMA interoperates with an external physical medium dependent (PMD) device, which drives the external copper or fiber network. The interconnect between Altera and PMD devices can be TBI or 1.25 Gbps serial.

The PCS function supports the following external PHYs:

• 1000 BASE-X PHYs as is.

• 10BASE-T, 100BASE-T and 1000BASE-T PHYs if the PHYs support SGMII.

1000BASE-X/SGMII PCS Architecture

Figure 4-14: 1000BASE-X/SGMII PCS

1000BASE-X/SGMII PCS Architecture

4-25

Functional Description

Send Feedback

Altera Corporation

SGMII

Receive

Converter

SGMII

Transmit

Converter

Configuration

Encapsulation

De -encapsulation

Synchronization

Auto-Negotiation

Status LEDs

Avalon -MM Interface

MII/GMII

Receive

MII/GMII Transmit

Serializer

PMA

PHY

Loopback

Ethernet Side

MAC Side

1000 Base-X PCS Receive Control

1000 Base-X PCS Transmit Control

8b/10b

Decoder

8b/10b

Encoder

1.25 Gbps Serial Receive

1.25 Gbps SerialTransmit

1000BASE-X/SGMII PCS with PMA

CDR &

Deserializer

4-26

Transmit Operation

Figure 4-15: 1000BASE-X/SGMII PCS with Embedded PMA

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Transmit Operation

The transmit operation includes frame encapsulation and encoding.

Frame Encapsulation

The PCS function replaces the first preamble byte in the MAC frame with the start of frame /S/ symbol. Then, the PCS function encodes the rest of the bytes in the MAC frame with standard 8B/10B encoded characters. After the last FCS byte, the PCS function inserts the end of frame sequence, /T/ /R/ /R/ or /T/ /R/, depending on the number of character transmitted. Between frames, the PCS function transmits /I/ symbols.

If the PCS function receives a frame from the MAC function with an error (gm_tx_err asserted during frame transmission), the PCS function encodes the error by inserting a /V/ character.

8b/10b Encoding

The 8B/10B encoder maps 8-bit words to 10-bit symbols to generate a DC balance and ensure disparity of the stream with a maximum run length of 5.

Altera Corporation

Functional Description

Send Feedback

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Receive Operation

The receive operation includes comma detection, decoding, de-encapsulation, synchronization, and carrier sense.

Comma Detection

The comma detection function searches for the 10-bit encoded comma character, K28.1/K28.5/K28.7, in consecutive samples received from PMA devices. When the K28.1/K28.5/K28.7 comma code group is detected, the PCS function realigns the data stream on a valid 10-bit character boundary. A standard 8b/10b decoder can subsequently decodes the aligned stream.

The comma detection function restarts the search for a valid comma character if the receive synchronization state machine loses the link synchronization.

8b/10b Decoding

The 8b/10b decoder performs the disparity checking to ensure DC balancing and produces a decoded 8-bit stream of data for the frame de-encapsulation function.

Frame De-encapsulation

The frame de-encapsulation state machine detects the start of frame when the /I/ /S/ sequence is received and replaces the /S/ with a preamble byte (0x55). It continues decoding the frame bytes and transmits them to the MAC function. The /T/ /R/ /R/ or the /T/ /R/ sequence is decoded as an end of frame.

Receive Operation

4-27

A /V/ character is decoded and sent to the MAC function as frame error. The state machine decodes sequences other than /I/ /I/ (Idle) or /I/ /S/ (Start of Frame) as wrong carrier.

During frame reception, the de-encapsulation state machine checks for invalid characters. When the state machine detects invalid characters, it indicates an error to the MAC function.

Synchronization

The link synchronization constantly monitors the decoded data stream and determines if the underlying receive channel is ready for operation. The link synchronization state machine acquires link synchronization if the state machine receives three code groups with comma consecutively without error.

When link synchronization is acquired, the link synchronization state machine counts the number of invalid characters received. The state machine increments an internal error counter for each invalid character received and incorrectly positioned comma character. The internal error counter is decremented when four consecutive valid characters are received. When the counter reaches 4, the link synchronization is lost.

The PCS function drives the led_link signal to 1 when link synchronization is acquired. This signal can be used as a common visual activity check using a board LED.

Carrier Sense

The carrier sense state machine detects an activity when the link synchronization is acquired and when the transmit and receive encapsulation or de-encapsulation state machines are not in the idle or error states.

The carrier sense state machine drives the mii_rx_crs and led_crs signals to 1 when it detects an activity. The led_crs signal can be used as a common visual activity check using a board LED.

Collision Detection

A collision happens when non-idle frames are received from the PHY and transmitted to the PHY simultaneously. Collisions can be detected only in SGMII and half-duplex mode.

Functional Description

Send Feedback

Altera Corporation

4-28

Transmit and Receive Latencies

When a collision happens, the collision detection state machine drives the mii_rx_col and led_col signals to 1. You can use the led_col signal as a visual check using a board LED.

Transmit and Receive Latencies

Altera uses the following definitions for the transmit and receive latencies for the PCS function with an embedded PMA:

• Transmit latency is the time the PCS function takes to transmit the first bit on the PMA-PCS interface after the bit was first available on the MAC side interface (MII/GMII).

• Receive latency is the time the PCS function takes to present the first bit on the MAC side interface (MII/GMII) after the bit was received on the PMA-PCS interface.

Table 4-11: PCS Transmit and Receive Latency

These latencies are derived from a simulation. For transceiver latency, refer to the transceiver handbook of the respective device family.

PCS Configuration

PCS with GX transceivers

Latency (ns)

ReceiveTransmit

2489336810-Mbps SGMII

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PCS with LVDS Soft-CDR I/O

SGMII Converter

You can enable the SGMII converter by setting the SGMII_ENA bit in the if_mode register to 1. When enabled and the USE_SGMII_AN bit in the if_mode register is set to 1, the SGMII converter is automatically configured with the capabilities advertised by the PHY. Otherwise, Altera recommends that you configure the SGMII converter with the SGMII_SPEED bits in the if_mode register.

In 1000BASE-X mode, the PCS function always operates in gigabit mode and data duplication is disabled.

Transmit

In gigabit mode, the PCS and MAC functions must operate at the same rate. The transmit converter transmits each byte from the MAC function once to the PCS function.

335488100-Mbps SGMII

1351841000-Mbps SGMII

40241000BASE-X

2344360010-Mbps SGMII

344440100-Mbps SGMII

1841921000-Mbps SGMII

104401000BASE-X

In 100-Mbps mode, the transmit converter replicates each byte received by the PCS function 10 times. In 10 Mbps, the transmit converter replicates each byte transmitted from the MAC function to the PCS function 100 times.

Altera Corporation

Functional Description

Send Feedback

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2014.06.30

Receive

In gigabit mode, the PCS and MAC functions must operate at the same rate. The transmit converter transmits each byte from the PCS function once to the MAC function.

In 100-Mbps mode, the receive converter transmits one byte out of 10 bytes received from the PCS function to the MAC function. In 10-Mbps, the receive converter transmits one byte out of 100 bytes received from the PCS function to the MAC function.

Auto-Negotiation

Auto-negotiation is an optional function that can be started when link synchronization is acquired during system start up. To start auto-negotiation automatically, set the AUTO_NEGOTIATION_ENABLE bit in the PCS

control register to 1. During auto-negotiation, the PCS function advertises its device features and exchanges

them with a link partner device.

If the SGMII_ENA bit in the if_mode register is set to 0, the PCS function operates in 1000BASE-X. Otherwise, the operating mode is SGMII. The following sections describe the auto-negotiation process for each operating mode.

When simulating your design, you can disable auto-negotiation to reduce the simulation time. If you enable auto-negotiation in your design, set the link_timer time to a smaller value to reduce the auto-negotiation link timer in the simulation.

Receive

4-29

Related Information

PCS Configuration Register Space on page 6-18

1000BASE-X Auto-Negotiation

When link synchronization is acquired, the PCS function starts sending a /C/ sequence (configuration sequence) to the link partner device with the advertised register set to 0x00. The sequence is sent for a time specified in the PCS link_timer register mapped in the PCS register space.

When the link_timer time expires, the PCS dev_ability register is advertised, with the ACK bit set to 0 for the link partner. The auto-negotiation state machine checks for three consecutive /C/ sequences received from the link partner.

The auto-negotiation state machine then sets the ACK bit to 1 in the advertised dev_ability register and checks if three consecutive /C/ sequences are received from the link partner with the ACK bit set to 1.

Auto-negotiation waits for the value configured in the link_timer register to ensure no more consecutive /C/sequences are received from the link partner. The auto-negotiation is successfully completed when three consecutive idle sequences are received after the link timer expires.

After auto-negotiation completes successfully, the user software reads both the dev_ability and

partner_ability register and proceed to resolve priority for duplex mode and pause mode. If the design

contains a MAC and PCS, the user software configures the MAC with a proper resolved pause mode by setting the PAUSE_IGNORE bit in command_config register. To disable pause frame generation based on the receive FIFO buffer level, you should set the rx_section_empty register accordingly.

Functional Description

Send Feedback

Altera Corporation

Data

Link Partner PCS

Link

Synchronization

Acquired

LinkTimer = 10 ms

/C/ with dev_ability register and

ACK bit set to 0

/C/ with dev_ability register and

ACK bit set to 1

Send /I/ (Idle) sequence

/C/ with 0x00 ability

3 Consecutive /C/

with Acknowledge

3 Consecutive /C/

LinkTimer

4-30

SGMII Auto-Negotiation

Figure 4-16: Auto-Negotiation Activity (Simplified)

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Once auto-negotiation completes successfully, the ability advertised by the link partner device is available in the partner_ability register and the AUTO_NEGOTIATION_COMPLETE bit in the status register is set to 1.

The PCS function restarts auto-negotiation when link synchronization is lost and reacquired, or when you set the RESTART_AUTO_NEGOTIATION bit in the PCS control register to 1.

SGMII Auto-Negotiation

In SGMII mode, the capabilities of the PHY device are advertised and exchanged with a link partner PHY device.

Possible application of SGMII auto-negotiation in MAC mode and PHY mode.

Altera Corporation

Functional Description

Send Feedback

SGMII PCS

(MAC Mode)

SGMII Link

Medium

Twisted

Copper

Pair

Device Ability

Link Partner Ability

Altera Device

Triple Speed Ethernet

MegaCore Function

SGMII PCS with PMA

(PHY Mode)

Device Ability

Link Partner Ability

Altera Device

Triple Speed Ethernet

MegaCore Function

Device Ability

10/100/1000BASE-T PHY 10/100/1000BASE-T PHY

Link Partner

Link Partner Ability

Device Ability

Link Partner Ability

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Figure 4-17: SGMII Auto-Negotiation in MAC Mode and PHY Mode

SGMII Auto-Negotiation

4-31

If the SGMII_ENA and USE_SGMII_AN bits in the if_mode register are 1, the PCS function is automatically configured with the capabilities advertised by the PHY device once the auto-negotiation completes.

If the SGMII_ENA bit is 1 and the USE_SGMII_AN bit is 0, the PCS function can be configured with the

SGMII_SPEED and SGMII_DUPLEX bits in the if_mode register.

If the SGMII_ENA bit is 1 and the SGMII_AN_MODE bit is 1 (SGMII PHY Mode auto-negotiation is enabled) the speed and duplex mode resolution will be resolved based on the value that you set in the dev_ability register once auto negotiation is done. You should use set to the PHY mode if you want to advertise the link speed and duplex mode to the link partner.

Functional Description

Send Feedback

Altera Corporation

Link Timer = 1.6 ms

Data

PHY

SGMII PCS

Link

Synchronization

Acquired

/C/ with 0x00 ability

/C/ with dev_ability/C/ with 0x0001

/C/ with dev_ability and ACK

Send /I/ (Idle) sequence

Link Timer Link Timer3 Consecutive /C/

3 Consecutive /C/

with Acknowledge

4-32

Ten-bit Interface

Figure 4-18: SGMII Auto-Negotiation Activity

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Altera Corporation

For more information, refer to CISCO Serial-GMII Specifications.

Ten-bit Interface

In PCS variations with embedded PMA, the PCS function implements a TBI to an external SERDES.

On transmit, the SERDES must serialize tbi_tx_d[0], the least significant bit of the TBI output bus first and tbi_tx_d[9], the most significant bit of the TBI output bus last to ensure the remote node receives the data correctly, as figure below illustrates.

Functional Description

Send Feedback

serialization

tbi_tx_d(9:0)

1.25Gbps

Serial Stream

9 0

de-serialization

tbi_rx_d(9:0)

1.25Gbps

Serial Stream

9 0

SERDES

Transmit

SERDES

Receive

SERDES

Serial Receive

Serial Transmit

PCS Transmit

PCS Receive

sd _loopback

Control

MDIO Slave

1000BASE-X PCS

Ten-bit

Interface

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PHY Loopback

Figure 4-19: SERDES Serialization Overview

On receive, the SERDES must serialize the TBI least significant bit first and the TBI most significant bit last, as figure below illustrates.

Figure 4-20: SERDES De-Serialization Overview

4-33

PHY Loopback

In PCS variations with embedded PMA targeting devices with GX transceivers, you can enable loopback on the serial interface to test the PCS and embedded PMA functions in isolation of the PMD. To enable loopback, set the sd_loopback bit in the PCS control register to 1.

The serial loopback option is not supported in Cyclone IV devices with GX transceiver.

Figure 4-21: Serial Loopback

PHY Power-Down

Power-down is controlled by the POWERDOWN bit in the PCS control register. When the system management agent enables power-down, the PCS function drives the powerdown signal, which can be used to control a technology specific circuit to switch off the PCS function clocks to reduce the application activity.

Functional Description

Send Feedback

Altera Corporation

MDIO Slave

powerdown

Control

Powerdown Control

(TechnologySpecific)

1000BASE-X PCS

PMA

POWERDOWN

CONTROL

pcs_pwrdn_out

gxb_pwrdn_in

1000BASE-XPCS

4-34

Power-Down in PCS Variations with Embedded PMA

When the PHY is in power-down state, the PCS function is in reset and any activities on the GMII transmit and the TBI receive interfaces are ignored. The management interface remains active and responds to management transactions from the MAC layer device.

Figure 4-22: Power-Down

Power-Down in PCS Variations with Embedded PMA

In PCS variations with embedded PMA targeting devices with GX transceivers, the power-down signal is internally connected to the power-down of the GX transceiver. In these devices, the power-down functionality is shared across quad-port transceiver blocks. Ethernet designs must share a common gbx_pwrdn_in signal to use the same quad-port transceiver block.

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For designs targeting devices other than Stratix V, you can export the power-down signals to implement your own power-down logic to efficiently use the transceivers within a particular transceiver quad. Turn on the Export transceiver powerdown signal parameter to export the signals.

Figure 4-23: Power-Down with Export Transceiver Power-Down Signal

1000BASE-X/SGMII PCS Reset

A hardware reset resets all logic synchronized to the respective clock domains whereas a software reset only resets the PCS state machines, comma detection function, and 8B10B encoder and decoder. To trigger a hardware reset on the PCS, assert the respective reset signals: reset_reg_clk, reset_tx_clk, and

reset_rx_clk. To trigger a software reset, set the RESET bit in the control register to 1.

In PCS variations with embedded PMA, assert the respective reset signals or the power-down signal to trigger a hardware reset. You must assert the reset signal subsequent to asserting the reset_rx_clk, reset_tx_clk, or gbx_pwrdn_in signal. The reset sequence is also initiated when the active-low rx_freqlocked signal goes low.

Altera Corporation

Functional Description

Send Feedback

PMA

Reset

Sequencer

Reset

Synchronizer

Reset

Synchronizer

PCS

reset

reset_tx_clk

reset_rx_clk

gbx_pwrdn_in

rx_freqlocked

PMA

Reset

Sequencer

Reset

Synchronizer

Reset

Synchronizer

MAC

reset

gbx_pwrdwn

PCS

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Altera IEEE 1588v2 Feature

Figure 4-24: Reset Distribution in PCS with Embedded PMA

For more information about the rx_freqlocked signal and transceiver reset, refer to the transceiver handbook of the respective device family.

Assert the reset or gxb_pwrdn_in signals to perform a hardware reset on MAC with PCS and embedded PMA variation.

You must assert the reset signal for at least three clock cycles.Note:

4-35

Figure 4-25: Reset Distribution in MAC with PCS and Embedded PMA

Altera IEEE 1588v2 Feature

The Altera IEEE 1588v2 feature provides timestamp for receive and transmit frames in the Triple-Speed Ethernet MegaCore function designs. The feature consists of Precision Time Protocol (PTP). PTP is a layer-3 protocol that accurately synchronizes all real time-of-day clocks in a network to a master clock.

This feature is supported in Arria V, Arria 10, Cyclone V, MAX10, and Stratix V device families.

IEEE 1588v2 Supported Configurations

Functional Description

Send Feedback

The Triple-Speed Ethernet MegaCore functions support the IEEE 1588v2 feature only in the following configurations:

Altera Corporation

4-36

IEEE 1588v2 Features

• 10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS and embedded serial PMA without FIFO buffer in full-duplex mode

• 10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS and embedded LVDS I/O without FIFO buffer in full-duplex mode

• 10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS

• 10/100/1000-Mbps MAC without FIFO buffer in full-duplex mode

IEEE 1588v2 Features

• Supports 4 types of PTP clock on the transmit datapath:

• Master and slave ordinary clock

• Master and slave boundary clock

• End-to-end (E2E) transparent clock

• Peer-to-peer (P2P) transparent clock

• Supports PTP message types:

• PTP event messages—Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp.

• PTP general messages—Follow_Up, Delay_Resp, Pdelay_Resp_Follow_Up, Announce, Management,

and Signaling.

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• Supports simultaneous 1-step and 2-step clock synchronizations on the transmit datapath.

• 1-step clock synchronization—The MAC function inserts accurate timestamp in Sync PTP message

or updates the correction field with residence time.

• 2-step clock synchronization—The MAC function provides accurate timestamp and the related

fingerprint for all PTP message.

• Supports the following PHY operating speed accuracy:

• random error:

• 10Mbps—NA

• 100Mbps—timestamp accuracy of ± 5 ns

• 1000Mbps—timestamp accuracy of ± 2 ns

• static error—timestamp accuracy of ± 3 ns

• Supports IEEE 802.3, UDP/IPv4, and UDP/IPv6 transfer protocols for the PTP frames.

• Supports untagged, VLAN tagged, Stacked VLAN Tagged PTP frames, and any number of MPLS labels.

• Supports configurable register for timestamp correction on both transmit and receive datapaths.

• Supports Time-of-Day (ToD) clock that provides a stream of 64-bit and 96-bit timestamps.

Altera Corporation

Functional Description

Send Feedback

IEEE 1588v2

Tx Logic

IEEE 1588v2

Rx Logic

PTP Software

Stack

Time-of-Day

Clock

PHY

MAC

PHY

tx_path_delay

rx_path_delay

Timestamp &

User Fingerprint

Correction

Time of Day

Timestamp Aligned to

Receive Frame

tx_egress_timestamp_request tx_ingress_timestamp

tx_time_of_day rx_time_of_day

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IEEE 1588v2 Architecture

Figure 4-26: Overview of the IEEE 1588v2 Feature

This figure shows only the datapaths related to the IEEE 1588v2 feature.

IEEE 1588v2 Architecture

4-37

IEEE 1588v2 Transmit Datapath

Functional Description

Send Feedback

The IEEE 1588v2 feature supports 1-step and 2-step clock synchronizations on the transmit datapath.

• For 1-step clock synchronization:

• Timestamp insertion depends on the PTP device and message type.

• The MAC function inserts a timestamp in the Sync PTP message if the PTP clock operates as ordinary

or boundary clock.

• Depending on the PTP device and message type, the MAC function updates the residence time in the

correction field of the PTP frame when the client asserts

tx_etstamp_ins_ctrl_residence_time_update. The residence time is the difference between the

egress and ingress timestamps.

• For PTP frames encapsulated using the UDP/IPv6 protocol, the MAC function performs UDP

checksum correction using extended bytes in the PTP frame.

• The MAC function re-computes and re-inserts CRC-32 into the PTP frames after each timestamp or

correction field insertion.

• For 2-step clock synchronization, the MAC function returns the timestamp and the associated fingerprint for all transmit frames when the client asserts tx_egress_timestamp_request_valid.

Altera Corporation

4-38

IEEE 1588v2 Receive Datapath

Table 4-12: Timestamp and Correction Insertion for 1-Step Clock Synchronization

This table summarizes the timestamp and correction field insertions for various PTP messages in different PTP clocks.

P2P Transparent ClockE2E Transparent ClockBoundary ClockOrdinary Clock

PTP Message

Insert

Timestamp

Insert

Correction

Insert

Timestamp

Insert

Correction

Insert

Timestamp

Insert

Correction

Insert

Timestamp

Insert

Correction

Yes(2)NoYes(2)NoNoYes(1)NoYes(1)Sync

Yes(2)NoYes(2)NoNoNoNoNoDelay_Req

NoNoYes(2)NoNoNoNoNoPdelay_Req

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NoPdelay_Resp

,(2)

NoYes(1)

,(2)

Follow_Up

Notes to Table 4-12 :

1. Applicable only when 2-step flag in flagField of the PTP frame is 0.

2. Applicable when you assert tx_ingress_timestamp_valid.

IEEE 1588v2 Receive Datapath

In the receive datapath, the IEEE 1588v2 feature provides a timestamp for all receive frames. The timestamp is aligned with the avalon_st_rx_startofpacket signal.

IEEE 1588v2 Frame Format

The MAC function, with the IEEE 1588v2 feature, supports PTP frame transfer for the following transport protocols:

NoYes(2)NoYes(1)

Yes(1) ,(2)

NoNoNoNoNoNoNoNoDelay_Resp

NoNoNoNoNoNoNoNoFollow_Up

NoNoNoNoNoNoNoNoPdelay_Resp_

NoNoNoNoNoNoNoNoAnnounce

NoNoNoNoNoNoNoNoSignaling

NoNoNoNoNoNoNoNoManagement

• IEEE 802.3

• UDP/IPv4

• UDP/IPv6

Altera Corporation

Functional Description

Send Feedback

flagField

correctionField

transportSpecific | messageType

reserved | versionPTP

reserved

1 Octet

2 Octets

8 Octets

reserved4 Octets

SourcePortIdentify10 Octets

sequenceId2 Octets

controlField1 Octet

logMessageInterval1 Octet

TimeStamp10 Octets

domainNumber

messageLength2 Octets

1 Octet

Length/Type = 0x88F7

Source Address

Destination Address

2 Octets

6 Octets

MAC Header

PTP Header

0..1500/9600 Octets

CRC

Payload

4 Octets

(1)

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PTP Frame in IEEE 802.3

Figure 4-27: PTP Frame in IEEE 8002.3

PTP Frame in IEEE 802.3

4-39

Note to Figure 4–27 :

1. For frames with VLAN or Stacked VLAN tag, add 4 or 8 octets offsets before the length/type field.

PTP Frame over UDP/IPv4

Checksum calculation is optional for the UDP/IPv4 protocol. The 1588v2 Tx logic should set the checksum to zero.

Functional Description

Send Feedback

Altera Corporation

MAC Header

UDP Header

IP Header

PTP Header

Time To Live

Protocol = 0x11

Version | Internet Header Length

Differentiated Services

Flags | Fragment Offsets

1 Octet

2 Octets

1 Octet

Header Checksum2 Octets

Source IP Address4 Octets

Destination IP Address4 Octets

Options | Padding0 Octet

Source Port2 Octets

Destination Port = 319 / 3202 Octets

Identification

Total Length2 Octets

2 Octets

Length/Type = 0x0800

Source Address

Destination Address

2 Octets

6 Octets

Checksum

Length

2 Octets

flagField

correctionField

transportSpecific | messageType

reserved | versionPTP

reserved

1 Octet

2 Octets

8 Octets

reserved4 Octets

SourcePortIdentify10 Octets

sequenceId2 Octets

controlField1 Octet

logMessageInterval1 Octet

TimeStamp10 Octets

domainNumber

messageLength2 Octets

1 Octet

CRC4 Octets

(1)

0..1500/9600 Octets Payload

4-40

PTP Frame over UDP/IPv6

Figure 4-28: PTP Frame over UDP/IPv4

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PTP Frame over UDP/IPv6

Note to Figure 4-28 :

1. For frames with VLAN or Stacked VLAN tag, add 4 or 8 octets offsets before the length/type field.

Checksum calculation is mandatory for the UDP/IPv6 protocol. You must extend 2 bytes at the end of the UDP payload of the PTP frame. The MAC function modifies the extended bytes to ensure that the UDP checksum remains uncompromised.

Altera Corporation

Functional Description

Send Feedback

Version | Traffic Class | Flow Label

Payload Length

4 Octet

2 Octets

Source IP Address16 Octets

Destination IP Address16 Octets

Source Port2 Octets

Destination Port = 319 / 3202 Octets

Hop Limit

Next Header = 0x111 Octet

1 Octet

Length/Type = 0x86DD

Source Address

Destination Address

2 Octets

6 Octets

Checksum

Length

2 Octets

flagField

correctionField

transportSpecific | messageType

reserved | versionPTP

reserved

1 Octet

2 Octets

8 Octets

reserved4 Octets

SourcePortIdentify10 Octets

sequenceId2 Octets

controlField1Octet

logMessageInterval1 Octet

TimeStamp10 Octets

extended bytes2 Octets

CRC4 Octets

domainNumber

messageLength2 Octets

1 Octet

MAC Header

UDP Header

IP Header

PTP Header

(1)

0..1500/9600 Octets Payload

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Figure 4-29: PTP Frame over UDP/IPv6

PTP Frame over UDP/IPv6

4-41

Note to Figure 4-29 :

1. For frames with VLAN or Stacked VLAN tag, add 4 or 8 octets offsets before the length/type field.

Functional Description

Send Feedback

Altera Corporation

Triple-Speed Ethernet with IEEE 1588v2 Design

www.altera.com

101 Innovation Drive, San Jose, CA 95134

2014.06.30

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Software Requirements

Altera uses the following software to test the Triple-Speed Ethernet with IEEE 1588v2 design example and testbench:

• Altera Complete Design Suite 14.0

• ModelSim-SE 10.0b or higher

Send Feedback

Example

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with

ISO 9001:2008 Registered

Ethernet

Packet

Classifier

Pulse Per

Second Module

Time of

Day

Clock

Time of Day

Triple-Speed

Ethernet

Avalon MM Master

Translator

Client Application

(Configuration,

Status & Statistics)

Transceiver

Reconfiguration

Bundle

External PHY

Serial Signal

64-Bit

Avalon ST

Time

of Day

32-Bit

Avalon MM

Reconfiguration

32-Bit

Avalon MM

64-Bit

Avalon ST

Pulse Per

Second

Timestamp & Fingerprint

Client Application

Altera FPGA

Design Example

5-2

Triple-Speed Ethernet with IEEE 1588v2 Design Example Components

Figure 5-1: Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Block Diagram

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The Triple-Speed Ethernet with IEEE 1588v2 design example comprises the following components:

• Triple-Speed Ethernet design that has the following parameter settings:

• 10/100/1000 Mbps Ethernet MAC with 1000BASE-X/SGMII PCS

• SGMII bridge enabled

• Used GXB transceiver block

• Number of port = 1

• Timestamping enabled

• PTP 1-step clock enabled

• Timestamp fingerprint width = 4

• Internal FIFO not used

• Transceiver Reconfiguration Controller—dynamically calibrates and reconfigures the features of the

PHY IP cores.

• Ethernet Packet Classifier—decodes the packet type of incoming PTP packets and returns the decoded information to the Triple-Speed Ethernet MAC.

• Ethernet ToD Clock—provides 64-bits and/or 96-bits time-of-day to TX and RX of Triple-Speed Ethernet MAC.

• Pulse Per Second Module—returns pulse per second (pps) to user.

Altera Corporation

Triple-Speed Ethernet with IEEE 1588v2 Design Example

Send Feedback

<ip_library>/ethernet/altera_eth_tse_design_example

tse_ieee1588

testbench

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Base Addresses

• Avalon-MM Master Translator—provides access to the registers of the following components through the Avalon-MM interface:

• Triple-Speed Ethernet MAC

• Transceiver Reconfiguration Controller

• ToD Clock

Base Addresses

Table below lists the design example components that you can reconfigure to suit your verification objectives. To reconfigure the components, write to their registers using the base addresses listed in the table and the register offsets described in the components' user guides.

Table 5-1: Base Addresses of Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Components

Base AddressComponent

0x0000Triple-Speed Ethernet

0x1000Time of Day Clock

0x2000Transceiver Reconfiguration Controller

5-3

Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Files

Figure 5-2: Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Folders

Table 5-2: Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Files

These files are located in the ..\tse_ieee1588 directory.

DescriptionFile Name

The top-level entity file of the design example for verification in hardware.tse_1588_top.v

tse_1588_top.sdc

tse_1588.qsys

The Quartus II SDC constraint file for use with the TimeQuest timing analyzer.

A Qsys file for the Triple-Speed Ethernet design example with IEEE 1588v2 option enabled.

Tcl script to run testbench simulation.tb_run_simulation.tcl

Triple-Speed Ethernet with IEEE 1588v2 Design Example

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Loopback

on serial interface

Testbench

Avalon-MM

Control

Avalon-ST

Transmit

Frame

Generator

Avalon-ST

Receive

Frame

Monitor

Ethernet

Packet

Monitor

Ethernet

Packet

Monitor

DUT

avalon_bfm_wrapper.sv

Avalon Driver

Avalon-ST

5-4

Creating a New Triple-Speed Ethernet MAC with IEEE 1588v2 Design

You can use the Quartus II software to create a new Triple-Speed Ethernet MAC with IEEE 1588v2 design. Altera provides a Qsys design example file that you can customize to facilitate the development of your Triple-Speed Ethernet MAC with IEEE 1588v2 design.

1. Launch the Quartus II software and open the tse_1588.top.v file from the project directory.

2. Launch Qsys from the Tools menu and open the tse_1588.qsys file. By default, the design example targets

the Stratix V device family. To change the target family, click on the Project Settings tab and select the desired device from the Device family list.

3. Turn off the additional module under the Use column if your design does not require it. This action disconnects the module from the Triple-Speed Ethernet MAC with IEEE 1588v2 system.

4. Double-click on triple_speed_ethernet_0 to launch the parameter editor.

5. Specify the required parameters in the parameter editor.

6. Click Finish.

7. On the Generation tab, select either a Verilog HDL or VHDL simulation model and make sure that the Create HDL design files for synthesis option is turned on.

8. Click Generate to generate the simulation and synthesis files.

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Triple-Speed Ethernet with IEEE 1588v2 Testbench

Altera provides a testbench for you to verify the Triple-Speed Ethernet with IEEE 1588v2 design example. The following sections describe the testbench, its components, and use.

The testbench operates in loopback mode. Figure 5-3 shows the flow of the packets in the design example.

Figure 5-3: Testbench Block Diagram

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Triple-Speed Ethernet with IEEE 1588v2 Testbench Files

The testbenches comprise the following modules:

• Device under test (DUT)—the design example.

• Avalon driver—uses Avalon-ST master bus functional models (BFMs) to exercise the transmit and receive

paths. The driver also uses the master Avalon-MM BFM to access the Avalon-MM interfaces of the design example components.

• Packet monitors—monitors the transmit and receive datapaths, and displays the frames in the simulator console.

Triple-Speed Ethernet with IEEE 1588v2 Testbench Files

The <ip library>/ethernet/altera_eth_tse_design_example/tse_ieee1588/ testbench directory contains the testbench files.

Table 5-3: Triple-Speed Ethernet with IEEE 1588v2 Testbench Files

A wrapper for the Avalon BFMs that the avalon_driver.sv file uses.avalon_bfm_wrapper.sv

5-5

DescriptionFile Name

avalon_driver.sv

avalon_if_params_pkg.sv

avalon_st_eth_packet_monitor.sv

default_test_params_pkg.sv

eth_mac_frame.sv

eth_register_map_params_pkg.sv

tb_testcase.sv

tb_top.sv

A SystemVerilog HDL driver that utilizes the BFMs to exercise the transmit and receive path, and access the Avalon-MM interface.

A SystemVerilog HDL testbench that contains parameters to configure the BFMs. Because the configuration is specific to the DUT, you must not change the contents of this file.

A SystemVerilog HDL testbench that monitors the Avalon-ST transmit and receive interfaces.

A SystemVerilog HDL package that contains the default parameter settings of the testbench.

A SystemVerilog HDL class that defines the Ethernet frames. The avalon_

driver.sv file uses this class.

A SystemVerilog HDL package that maps addresses to the Avalon-MM control registers.

A SystemVerilog HDL class that defines the timestamp in the testbench.ptp_timestamp.sv

A SystemVerilog HDL testbench file that controls the flow of the testbench.

The top-level testbench file. This file includes the customized TripleSpeed Ethernet MAC, which is the device under test (DUT), a client packet generator, and a client packet monitor along with other logic blocks.

wave.do

A signal tracing macro script for use with the ModelSim simulation software to display testbench signals.

Triple-Speed Ethernet with IEEE 1588v2 Testbench Simulation Flow

Upon a simulated power-on reset, each testbench performs the following operations:

1. Initializes the DUT by configuring the following options through the Avalon-MM interface:

Triple-Speed Ethernet with IEEE 1588v2 Design Example

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Simulating Triple-Speed Ethernet with IEEE 1588v2 Testbench with ModelSim Simulator

• Configures the MAC. In the MAC, sets the transmit primary MAC address to EE-CC-88-CC-AA-EE,

sets the speed to 1000 Mbps, enables TX and RX MAC, enables pad removal at receive, sets IPG to 12, and sets maximum packet size to 1518.

• Configures PCS and SGMII interface to 1000BASE-X.

• Configures Timestamp Unit in the MAC, by setting periods and path delay adjustments of the clocks.

• Configures ToD clock by loading a predefined time value.

• Configures clock mode of Packet Classifier to Ordinary Clock mode.

2. Starts packet transmission with different clock mode. The testbench sends a total of three packets:

• 1-step PTP Sync message over Ethernet

• 1-step PTP Sync message over UDP/IPv4 with VLAN tag

• 2-step PTP Sync message over UDP/IPv6 with stacked VLAN tag

3. Configures clock mode of Packet Classifier to End-to-end Transparent Clock mode.

4. Starts packet transmission. The testbench sends a total of three packets:

• 1-step PTP Sync message over Ethernet

• 1-step PTP Sync message over UDP/IPv4 with VLAN tag

• 2-step PTP Sync message over UDP/IPv6 with stacked VLAN tag

5. Ends transmission.

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Simulating Triple-Speed Ethernet with IEEE 1588v2 Testbench with ModelSim Simulator

To use the ModelSim simulator to simulate the testbench design:

1. Copy the respective design example directory to your preferred project directory: tse_ieee1588 from

<ip library>/ethernet/altera_eth_tse_design_example.

2. Launch Qsys from the Tools menu and open the tse_1588.qsys file.

3. On the Generation tab, select either a Verilog HDL or VHDL simulation model.

4. Click Generate to generate the simulation and synthesis files.

5. Run the following command to set up the required libraries, to compile the generated IP Functional

simulation model, and to exercise the simulation model with the provided testbench: do tb_run.tcl

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Configuration Register Space

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MAC Configuration Register Space

Use the registers to configure the different aspects of the MAC function and retrieve its status and statistics counters.

In multiport MACs, a contiguous register space is allocated for all ports and accessed via the Avalon-MM control interface. For example, if the register space base address for the first port is 0x00, the base address for the next port is 0x100 and so forth. The registers that are shared among the instances occupy the register space of the first port. Updating these registers in the register space of other ports has no effect on the configuration.

Table 6-1: Overview of MAC Register Space

Base Configuration0x00 – 0x17

Base registers to configure the MAC function. At the minimum, you must configure the following functions:

• Primary MAC address (mac_0/mac_1)

• Enable transmit and receive paths (TX_ENA and RX_ENA bits

in the command_config register)

DescriptionSectionDword Offset

The following registers are shared among all instances of a multiport MAC:

• rev

• scratch

• frm_length

• pause_quant

• mdio_addr0 and mdio_addr1

• tx_ipg_length

For more information about the base configuration registers, refer to Base Configuration Registers (Dword Offset 0x00 –

0x17) on page 6-3.

Statistics Counters0x18 – 0x38

Counters collecting traffic statistics. For more information about the statistics counters, refer to Statistics Counters (Dword Offset

0x18 – 0x38) on page 6-11.

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with

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6-2

MAC Configuration Register Space

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DescriptionSectionDword Offset

0x80 – 0x9F

Transmit Command0x3A

Receive Command0x3B

Extended Statistics Counters0x3C – 0x3E

Multicast Hash Table0x40 – 0x7F

MDIO Space 0

or PCS Function Configuration

MDIO Space 10xA0 – 0xBF

Transmit and receive datapaths control register. For more information about these registers, see Transmit and Receive

Command Registers (Dword Offset 0x3A – 0x3B) on page

6-13.

Upper 32 bits of selected statistics counters. These registers are used if you turn on the option to use extended statistics counters. For more information about these counters, refer to Statistics

Counters (Dword Offset 0x18 – 0x38) on page 6-11 .

Unused.Reserved0x3F

64-entry write-only hash table to resolve multicast addresses. Only bit 0 in each entry is significant. When you write a 1 to a dword offset in the hash table, the MAC accepts all multicast MAC addresses that hash to the value of the address (bits 5:0). Otherwise, the MAC rejects the multicast address. This table is cleared during reset.

Hashing is not supported in 10/100 and 1000 Mbps Small MAC core variations.

MDIO Space 0 and MDIO Space 1 map to registers 0 to 31 of the PHY devices whose addresses are configured in the mdio_

addr0 and mdio_addr1 registers respectively. For example,

Reading or writing to MDIO Space 0 or MDIO Space 1 immediately triggers a corresponding MDIO transaction to read or write the PHY register. Only bits [15:0] of each register are significant. Write 0 to bits [31:16] and ignore them on reads.

If your variation does not include the PCS function, you can use MDIO Space 0 and MDIO Space 1 to map to two PHY devices.

If your MAC variation includes the PCS function, the PCS function is always device 0 and its configuration registers (PCS

Configuration Register Space on page 6-18) occupy MDIO

Space 0. You can use MDIO Space 1 to map to a PHY device.

Supplementary Address0xC0 – 0xC7

Supplementary unicast addresses. For more information about these addresses, refer to Supplementary Address (Dword Offset

0xC0 – 0xC7) on page 6-15.

Unused.Reserved(1)0xC8 – 0xCF

IEEE 1588v2 Feature0xD0 – 0xD6

Registers to configure the IEEE 1588v2 feature. For more information about these registers, refer to IEEE 1588v2 Feature

(Dword Offset 0xD0 – 0xD6) on page 6-16.

Unused.Reserved(1)0xD7 – 0xFF

Note to Table 6-1 :

1. Altera recommends that you set all bits in the reserved registers to 0 and ignore them on reads.

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Base Configuration Registers (Dword Offset 0x00 – 0x17)

Table 6-2 lists the base registers you can use to configure the MAC function. A software reset does not reset

these registers except the first two bits (TX_ENA and RX_ENA = 0) in the command_config register.

Table 6-2: Base Configuration Register Map

Offset

6-3

HW ResetDescriptionR/WNameDword

ROrev0x00

• Bits[15:0]—Set to the current version of the MegaCore function.

• Bits[31:16]—Customer specific revision, specified by

the CUST_VERSION parameter defined in the top-level file generated for the instance of the MegaCore function. These bits are set to 0 during the configuration of the MegaCore function.

RWscratch(1)0x01

0Scratch register. Provides a memory location for you to

test the device memory operation.

RWcommand_config0x02

0MAC configuration register. Use this register to control and configure the MAC function. The MAC function starts operation as soon as the transmit and receive enable bits in this register are turned on. Altera, therefore, recommends that you configure this register last.

See Command_Config Register (Dword Offset 0x02) on page 6-7 for the bit description.

RWmac_00x03

significant bytes of the MAC address occupy mac_0 in reverse order. The last two bytes of the MAC address

06-byte MAC primary address. The first four most

0RWmac_10x04 occupy the two least significant bytes of mac_1 in reverse

order.

frm_length0x05

Configuration Register Space

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RW/

For example, if the MAC address is 00-1C-23-17-4A-CB, the following assignments are made:

mac_0 = 0x17231c00

mac_1 = 0x0000CB4a

Ensure that you configure these registers with a valid MAC address if you disable the promiscuous mode (PROMIS_EN bit in command_config = 0).

1518• Bits[15:0]—16-bit maximum frame length in bytes.

The MegaCore function checks the length of receive frames against this value. Typical value is 1518.

In 10/100 and 1000 Small MAC core variations, this register is RO and the maximum frame length is fixed to 1518.

• Bits[31:16]—unused.

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6-4

Base Configuration Registers (Dword Offset 0x00 – 0x17)

Offset

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HW ResetDescriptionR/WNameDword

RWpause_quant0x06

0• Bits[15:0]—16-bit pause quanta. Use this register to

specify the pause quanta to be sent to remote devices when the local device is congested. The MegaCore function sets the pause quanta (P1, P2) field in pause frames to the value of this register.

10/100 and 1000 Small MAC core variations do not support flow control.

• Bits[31:16]—unused.

rx_section_empty0x07

RW/

FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. This threshold is typically set

0Variable-length section-empty threshold of the receive

to (FIFO Depth – 16).

Set this threshold to a value that is below the rx_almost_

full threshold and above the rx_section_full or rx_ almost_empty threshold.

In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of (FIFO Depth – 16).

rx_section_full0x08

RW/

buffer. Use the depth of your FIFO buffer to determine this threshold.

0Variable-length section-full threshold of the receive FIFO

For cut-through mode, this threshold is typically set to

16. Set this threshold to a value that is above the rx_

almost_empty threshold.

For store-and-forward mode, set this threshold to 0.

In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 16.

tx_section_empty0x09

RW/

FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. This threshold is typically set

0Variable-length section-empty threshold of the transmit

to (FIFO Depth – 16).

Set this threshold to a value below the rx_almost_full threshold and above the rx_section_full or rx_

almost_empty threshold.

In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of (FIFO Depth – 16).

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Offset

Base Configuration Registers (Dword Offset 0x00 – 0x17)

6-5

HW ResetDescriptionR/WNameDword

tx_section_full0x0A

RW/

FIFO buffer. Use the depth of your FIFO buffer to determine this threshold.

0Variable-length section-full threshold of the transmit

For cut-through mode, this threshold is typically set to

16. Set this threshold to a value above the tx_almost_

empty threshold.

For store-and-forward mode, set this threshold to 0.

In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 16.

rx_almost_empty0x0B

RW/

FIFO buffer. Use the depth of your FIFO buffer to determine this threshold.

0Variable-length almost-empty threshold of the receive

Due to internal pipeline latency, you must set this threshold to a value greater than 3. This threshold is typically set to 8.

In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 8.

rx_almost_full0x0C

RW/

buffer. Use the depth of your FIFO buffer to determine this threshold.

0Variable-length almost-full threshold of the receive FIFO

Due to internal pipeline latency, you must set this threshold to a value greater than 3. This threshold is typically set to 8.

In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 8.

tx_almost_empty0x0D

RW/

FIFO buffer. Use the depth of your FIFO buffer to determine this threshold.

0Variable-length almost-empty threshold of the transmit

Due to internal pipeline latency, you must set this threshold to a value greater than 3. This threshold is typically set to 8.

In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 8.

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Base Configuration Registers (Dword Offset 0x00 – 0x17)

Offset

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HW ResetDescriptionR/WNameDword

tx_almost_full0x0E

RW/

FIFO buffer. Use the depth of your FIFO buffer to determine this threshold.

0Variable-length almost-full threshold of the transmit

You must set this register to a value greater than or equal to 3. A value of 3 indicates 0 ready latency; a value of 4 indicates 1 ready latency, and so forth. Because the maximum ready latency on the Avalon-ST interface is 8, you can only set this register to a maximum value of 11. This threshold is typically set to 3.

In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 3.

RWmdio_addr00x0F

the addresses of any connected PHY devices you want to access. The mdio_addr0 and mdio_addr1 registers

0• Bits[4:0]—5-bit PHY address. Set these registers to

1RWmdio_addr10x10

contain the addresses of the PHY whose registers are mapped to MDIO Space 0 and MDIO Space 1 respectively.

• Bits[31:5]—unused. Set to read-only value of 0.

RWholdoff_quant0x11

0xFFFF• Bit[15:0]—16-bit holdoff quanta. When you enable

the flow control, use this register to specify the gap between consecutive XOFF requests.

• Bits[31:16]—unused.

–

0x16

RWtx_ipg_length0x17

8 and 26 byte-times. If this register is set to an invalid value, the MAC still maintains a typical minimum IPG value of 12 bytes between packets, although a read back to the register reflects the invalid value written.

In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 12.

Bits[31:5]—unused. Set to read-only value 0.

Note to Table 6-2 :

1. Register is not available in 10/100 and 1000 Small MAC variations.

0——Reserved0x12

0• Bits[4:0]—minimum IPG. Valid values are between

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T X _E N A

R X _E N A

X O N _G E N

E T H _S P E E D

P R O M IS _E N

P A D _E N

C R C _F W D

P A U S E _F W D

P A U S E _IG N O R E

T X _A D D R _IN S

H D _E N A

E X C E S S _C O L

L A T E _C O L

S W _R E S E T

M H A S H _S E L

L O O P _E N A

T X _A D D R _S E L

M A G IC _E N A

S L E E P

W A K E U P

X O F F _G E N

C T R L _F R M _E N A

N O _L G T H _C H E C K

E N A _1 0

R X _E R R _D IS C

R E S E R V E D

C N T _R E S E T

31 30… 26 25 24 23 22 21 20 19 18…16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 027

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Command_Config Register (Dword Offset 0x02)

Figure 6-1: Command_Config Register Fields

At the minimum, you must configure the TX_ENA and RX_ENA bits to 1 to start the MAC operations. When configuring the command_config register, Altera recommends that you configure the TX_ENA and RX_ENA bits the last because the MAC function immediately starts its operations once these bits are set to 1.

Table 6-3: Command_Config Register Field Descriptions

Command_Config Register (Dword Offset 0x02)

6-7

DescriptionR/WNameBit(s)

RWTX_ENA0

Transmit enable. Set this bit to 1 to enable the transmit datapath. Self-clearing reset bit.

RWRX_ENA1

Receive enable. Set this bit to 1 to enable the receive datapath. Self-clearing reset bit.

RWXON_GEN2

Pause frame generation. When you set this bit to 1, the MAC function generates a pause frame with a pause quanta of 0, independent of the status of the receive FIFO buffer.

RWETH_SPEED3

Ethernet speed control.

• Set this bit to 1 to enable gigabit Ethernet operation. The

set_1000 signal is masked and does not affect the operation.

• If you set this bit to 0, gigabit Ethernet operation is enabled

only if the set_1000 signal is asserted. Otherwise, the MAC function operates in 10/100 Mbps Ethernet mode.

When the MAC operates in gigabit mode, the eth_mode signal is asserted. This bit is not available in the small MAC variation.

RWPROMIS_EN4

Promiscuous enable. Set this bit to 1 to enable promiscuous mode. In this mode, the MAC function receives all frames without address filtering.

RWPAD_EN5

Padding removal on receive. Set this bit to 1 to remove padding from receive frames before the MAC function forwards the frames to the user application. This bit has no effect on transmit frames.

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This bit is not available in the small MAC variation.

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Command_Config Register (Dword Offset 0x02)

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DescriptionR/WNameBit(s)

RWCRC_FWD6

CRC forwarding on receive.

• Set this bit to 1 to forward the CRC field to the user application.

• Set this bit to 0 to remove the CRC field from receive frames before the MAC function forwards the frame to the user application.

• The MAC function ignores this bit when it receives a padded frame and the PAD_EN bit is 1. In this case, the MAC function checks the CRC field and removes the checksum and padding from the frame before forwarding the frame to the user application.

RWPAUSE_FWD7

Pause frame forwarding on receive.

• Set this bit to 1 to forward receive pause frames to the user application.

• Set this bit to 0 to terminate and discard receive pause frames.

RWPAUSE_IGNORE8

Pause frame processing on receive.

• Set this bit to 1 to ignore receive pause frames.

• Set this bit to 0 to process receive pause frames. The MAC

function suspends transmission for an amount of time specified by the pause quanta.

RWTX_ADDR_INS9

MAC address on transmit.

• Set this bit to 1 to overwrite the source MAC address in transmit frames received from the user application with the MAC primary or supplementary address configured in the registers. The TX_ADDR_SEL bit determines the address selection.

• Set this bit to 0 to retain the source MAC address in transmit frames received from the user application.

RWHD_ENA10

Half-duplex enable.

• Set this bit to 1 to enable half-duplex.

• Set this bit to 0 to enable full-duplex.

• The MAC function ignores this bit if you set the ETH_SPEED

bit to 1.

ROEXCESS_COL11

Excessive collision condition.

• The MAC function sets this bit to 1 when it discards a frame after detecting a collision on 16 consecutive frame retransmissions.

• The MAC function clears this bit following a hardware or software reset. See the SW_RESET bit description.

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Command_Config Register (Dword Offset 0x02)

DescriptionR/WNameBit(s)

6-9

ROLATE_COL12

Late collision condition.

• The MAC function sets this bit to 1 when it detects a collision after transmitting 64 bytes and discards the frame.

• The MAC function clears this bit following a hardware or software reset. See the SW_RESET bit description.

RWSW_RESET13

Software reset. Set this bit to 1 to trigger a software reset. The MAC function clears this bit when it completes the software reset sequence.

When reset is triggered, the MAC function completes the current transmission or reception, and subsequently disables the transmit and receive logic, flushes the receive FIFO buffer, and resets the statistics counters.

RWMHASH_SEL14

Hash-code mode selection for multicast address resolution.

• Set this bit to 0 to generate the hash code from the full 48bit destination address.

• Set this bit to 1 to generate the hash code from the lower 24 bits of the destination MAC address.

RWLOOP_ENA15

Local loopback enable. Set this bit to 1 to enable local loopback on the RGMII/GMII/MII of the MAC. The MAC function sends transmit frames back to the receive path.

This bit is not available in the small MAC variation.

RWTX_ADDR_SEL[2:0]18 –

Source MAC address selection on transmit. If you set the TX_

ADDR_INS bit to 1, the value of these bits determines the MAC

address the MAC function selects to overwrite the source MAC address in frames received from the user application.

• 000 = primary address configured in the mac_0 and mac_1 registers.

• 100 = supplementary address configured in the smac_0_0 and smac_0_1 registers.

• 101 = supplementary address configured in the smac_1_0 and smac_1_1 registers.

• 110 = supplementary address configured in the smac_2_0 and smac_2_1 registers.

• 111 = supplementary address configured in the smac_3_0 and smac_3_1 registers.

RWMAGIC_ENA19

Magic packet detection. Set this bit to 1 to enable magic packet detection.

This bit is not available in the small MAC variation.

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Command_Config Register (Dword Offset 0x02)

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DescriptionR/WNameBit(s)

RWSLEEP20

Sleep mode enable. When the MAGIC_ENA bit is 1, set this bit to 1 to put the MAC function to sleep and enable magic packet detection.

This bit is not available in the small MAC variation.

ROWAKEUP21

Node wake-up request. Valid only when the MAGIC_ENA bit is

• The MAC function sets this bit to 1 when a magic packet is detected.

• The MAC function clears this bit when the SLEEP bit is set to 0.

RWXOFF_GEN22

Pause frame generation. Set this bit to 1 to generate a pause frame independent of the status of the receive FIFO buffer. The MAC function sets the pause quanta field in the pause frame to the value configured in the pause_quant register.

RWCNTL_FRM_ENA23

MAC control frame enable on receive.

• Set this bit to 1 to accept control frames other than pause frames (opcode = 0x0001) and forward them to the user application.

• Set this bit to 0 to discard control frames other than pause frames.

RWNO_LGTH_CHECK24

Payload length check on receive.

• Set this bit to 0 to check the actual payload length of receive frames against the length/type field in receive frames.

• Set this bit to 1 to omit length checking.

This bit is not available in the small MAC variation

RWENA_1025

10-Mbps interface enable. Set this bit to 1 to enable the 10-Mbps interface. The MAC function asserts the ena_10 signal when you enable the 10-Mbps interface. You can also enable the 10Mbps interface by asserting the set_10 signal.

RWRX_ERR_DISC26

Erroneous frames processing on receive.

• Set this bit to 1 to discard erroneous frames received. This applies only when you enable store and forward operation in the receive FIFO buffer by setting the rx_section_full register to 0.

• Set this bit to 0 to forward erroneous frames to the user application with rx_err[0] asserted.

RWDISABLE_READ_ TIMEOUT27

Set this bit to 1 to disable MAC configuration register read timeout.

——Reserved28 –

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Statistics Counters (Dword Offset 0x18 – 0x38)

DescriptionR/WNameBit(s)

6-11

RWCNT_RESET31

Statistics counters reset. Set this bit to 1 to clear the statistics counters. The MAC function clears this bit when the reset sequence completes.

Statistics Counters (Dword Offset 0x18 – 0x38)

Table 6-4 describes the read-only registers that collect the statistics on the transmit and receive datapaths.

A hardware reset clears these registers; a software reset also clears these registers except aMacID.

The register description uses the following definitions:

• Good frame—error-free frames with valid frame length.

• Error frame—frames that contain errors or whose length is invalid.

• Invalid frame—frames that are not addressed to the MAC function. The MAC function drops this frame.

Table 6-4: Statistics Counters

Offset

ROaMacID0x18

–

0x19

ROaFramesTransmittedOK0x1A

The MAC address. This register is wired to the primary MAC address in the mac_0 and mac_1 registers.

The number of frames that are successfully transmitted including the pause frames.

DescriptionR/WNameDword

0x1C

SequenceErrors

ROaFramesReceivedOK0x1B

The number of frames that are successfully received including the pause frames.

The number of receive frames with CRC error.ROaFrameCheck

The number of receive frames with alignment error.ROaAlignmentErrors0x1D

ROaOctetsTransmittedOK0x1E

The number of data and padding octets that are successfully transmitted.

This register contains the lower 32 bits of the aOctetsTrans-

mittedOK counter. The upper 32 bits of this statistics counter

reside at the dword offset 0x0F.

ROaOctetsReceivedOK0x1F

The number of data and padding octets that are successfully received.

The lower 32 bits of the aOctetsReceivedOK counter. The upper 32 bits of this statistics counter reside at the dword offset 0x3D.

The number of pause frames transmitted.ROaTxPAUSEMACCtrlFrames0x20

The number received pause frames received.ROaRxPAUSEMACCtrlFrames0x21

The number of errored frames received.ROifInErrors0x22

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6-12

Offset

Statistics Counters (Dword Offset 0x18 – 0x38)

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DescriptionR/WNameDword

ROifOutErrors0x23

The number of transmit frames with one the following errors:

• FIFO overflow error

• FIFO underflow error

• Errors defined by the user application

The number of valid unicast frames received.ROifInUcastPkts0x24

ROifInMulticastPkts0x25

The number of valid multicast frames received. The count does not include pause frames.

The number of valid broadcast frames received.ROifInBroadcastPkts0x26

—ifOutDiscards0x27

This statistics counter is not in use.

The MAC function does not discard frames that are written to the FIFO buffer by the user application.

The number of valid unicast frames transmitted.ROifOutUcastPkts0x28

ROifOutMulticastPkts0x29

The number of valid multicast frames transmitted, excluding pause frames.

The number of valid broadcast frames transmitted.ROifOutBroadcastPkts0x2A

ROetherStatsDropEvents0x2B

The number of frames that are dropped due to MAC internal errors when FIFO buffer overflow persists.

ROetherStatsOctets0x2C

The total number of octets received. This count includes both good and errored frames.

This register is the lower 32 bits of etherStatsOctets. The upper 32 bits of this statistics counter reside at the dword offset 0x3E.

The total number of good and errored frames received.ROetherStatsPkts0x2D

ROetherStatsUndersizePkts0x2E

The number of frames received with length less than 64 bytes. This count does not include errored frames.

ROetherStatsOversizePkts0x2F

The number of frames received that are longer than the value configured in the frm_length register. This count does not include errored frames.

ROetherStatsPkts64Octets0x30

The number of 64-byte frames received. This count includes good and errored frames.

ROetherStatsPkts65to127Octets0x31

The number of received good and errored frames between the length of 65 and 127 bytes.

ROetherStatsPkts128to255Octets0x32

The number of received good and errored frames between the length of 128 and 255 bytes.

ROetherStatsPkts256to511Octets0x33

The number of received good and errored frames between the length of 256 and 511 bytes.

ROetherStatsPkts512to1023Octets0x34

The number of received good and errored frames between the length of 512 and 1023 bytes.

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Offset

Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)

DescriptionR/WNameDword

6-13

ROetherStatsPkts1024to1518Octets0x35

The number of received good and errored frames between the length of 1024 and 1518 bytes.

ROetherStatsPkts1519toXOctets0x36

The number of received good and errored frames between the length of 1519 and the maximum frame length configured in the frm_length register.

Too long frames with CRC error.ROetherStatsJabbers0x37

Too short frames with CRC error.ROetherStatsFragments0x38

Unused—Reserved0x39

Extended Statistics Counters (0x3C – 0x3E)

0x3C

aOctetsTransmittedOK

ROmsb_

Upper 32 bits of the respective statistics counters. By default all statistics counters are 32 bits wide. These statistics counters

ROmsb_aOctetsReceivedOK0x3D

ROmsb_etherStatsOctets0x3E

can be extended to 64 bits by turning on the Enable 64-bit byte counters parameter.

Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)

Table 6-5 describes the registers that determine how the MAC function processes transmit and receive

frames. A software reset does not change the values in these registers.

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Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)

Table 6-5: Transmit and Receive Command Registers

Offset

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DescriptionR/WNameDword

RWtx_cmd_stat0x3A

Specifies how the MAC function processes transmit frames. When you turn on the Align packet headers to 32-bit boundaries option, this register resets to 0x00040000 upon a hardware reset. Otherwise, it resets to 0x00.

• Bits 0 to 16—unused.

• Bit 17 (OMIT_CRC)—Set this bit to 1 to omit CRC calculation

and insertion on the transmit path. The user application is therefore responsible for providing the correct data and CRC. This bit, when set to 1, always takes precedence over the ff_

tx_crc_fwd signal.

• Bit 18 (TX_SHIFT16)—Set this bit to 1 if the frames from the

user application are aligned on 32-bit boundary. For more information, refer to IP Payload Re-alignment on page 4-5.

This setting applies only when you turn on the Align packet headers to 32-bit boundary option and in MAC variations with 32-bit internal FIFO buffers. Otherwise, reading this bit always return a 0.

In MAC variations without internal FIFO buffers, this bit is a read-only bit and takes the value of the Align packet headers to 32-bit boundary option.

• Bits 19 to 31—unused.

RWrx_cmd_stat0x3B

Specifies how the MAC function processes receive frames. When you turn on the Align packet headers to 32-bit boundaries option, this register resets to 0x02000000 upon a hardware reset. Otherwise, it resets to 0x00.

• Bits 0 to 24—unused.

• Bit 25 (RX_SHIFT16)—Set this bit to 1 to instruct the MAC

function to align receive frames on 32-bit boundary. For more information on frame alignment, refer to IP Payload

Alignment on page 4-11.

This setting applies only when you turn on the Align packet headers to 32-bit boundary option and in MAC variations

with 32-bit internal FIFO buffers. Otherwise, reading this bit always return a 0.

In MAC variations without internal FIFO buffers, this bit is a read-only bit and takes the value of the Align packet headers to 32-bit boundary option.

• Bits 26 to 31—unused.

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Supplementary Address (Dword Offset 0xC0 – 0xC7)

A software reset has no impact on these registers. MAC supplementary addresses are not available in 10/100 and 1000 Small MAC variations.

Table 6-6: Supplementary Address Registers

Offset

Supplementary Address (Dword Offset 0xC0 – 0xC7)

6-15

HW ResetDescriptionR/WNameDword

smac_0_00xC0

smac_0_10xC1

smac_1_00xC2

smac_1_10xC3

smac_2_00xC4

smac_2_10xC5

smac_3_00xC6

smac_3_10xC7

You can specify up to four 6-byte supplementary addresses:

• smac_0_0/1

• smac_1_0/1

• smac_2_0/1

• smac_3_0/1

Map the supplementary addresses to the respective registers in the same manner as the primary MAC address. Refer to the description of mac_0 and mac_1.

The MAC function uses the supplementary addresses for the following operations:

• to filter unicast frames when the promiscuous mode is disabled (refer to Command_Config Register (Dword

Offset 0x02) on page 6-7 for the description of the

PROMIS_EN bit).

• to replace the source address in transmit frames received from the user application when address insertion is enabled (refer to Command_Config Register (Dword

Offset 0x02) on page 6-7 for the description of the

TX_ADDR_INS and TX_ADDR_SEL bits).

If you do not require the use of supplementary addresses, configure them to the primary address.

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6-16

IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6)

Table 6-7: IEEE 1588v2 MAC Registers

Offset

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HW ResetDescriptionR/WNameDword

RWtx_period0xD0

0x0Clock period for timestamp adjustment on the transmit datapath. The period register is multiplied by the number of stages separating actual timestamp and the GMII bus.

• Bits 0 to 15: Period in fractional nanoseconds

(TX_PERIOD_FNS).

• Bits 16 to 24: Period in nanoseconds (TX_

PERIOD_NS).

• Bits 25 to 31: Not used.

The default value for the period is 0. For 125MHz clock, set this register to 8 ns.

RWtx_adjust_fns0xD1

0x0Static timing adjustment in fractional nanoseconds for outbound timestamps on the transmit datapath.

• Bits 0 to 15: Timing adjustment in fractional

nanoseconds.

• Bits 16 to 31: Not used.

RWtx_adjust_ns0xD2

0x0Static timing adjustment in nanoseconds for outbound timestamps on the transmit datapath.

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• Bits 0 to 15: Timing adjustment in nanosec-

onds.

• Bits 16 to 23: Not used.

RWrx_period0xD3

0x0Clock period for timestamp adjustment on the receive datapath. The period register is multiplied by the number of stages separating actual timestamp and the GMII bus.

• Bits 0 to 15: Period in fractional nanoseconds

(RX_PERIOD_FNS).

• Bits 16 to 24: Period in nanoseconds (RX_

PERIOD_NS).

• Bits 25 to 31: Not used.

The default value for the period is 0. For 125MHz clock, set this register to 8 ns.

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Offset

IEEE 1588v2 Feature PMA Delay

6-17

HW ResetDescriptionR/WNameDword

RWrx_adjust_fns0xD4

nanoseconds for outbound timestamps on the receive datapath.

• Bits 0 to 15: Timing adjustment in fractional

• Bits 16 to 31: Not used.

RWrx_adjust_ns0xD5

outbound timestamps on the receive datapath.

• Bits 0 to 15: Timing adjustment in nanosec-

• Bits 16 to 23: Not used.

IEEE 1588v2 Feature PMA Delay

PMA digital and analog delay of hardware for the IEEE 1588v2 feature and the register timing adjustment. 1 UI is equivalent to 800 ps.

Table 6-8: IEEE 1588v2 Feature PMA Delay—Hardware

DeviceDelay

0x0Static timing adjustment in fractional

nanoseconds.

0x0Static timing adjustment in nanoseconds for

onds.

Timing Adjustment

RX registerTX register

Digital 34 UI52 UIArria V GX, Arria V GT, or Arria V SoC

Analog 1.75 ns-1.1 nsArria V

Table 6-9: IEEE 1588v2 Feature LVDS I/O Delay—Hardware

DeviceDelay

Digital

PMA digital and analog delay of simulation model for the IEEE 1588v2 feature and the register timing adjustment.

26 UI53 UIStratix V or Arria V GZ

44 UI32 UICyclone V GX or Cyclone V SoC

1.75 ns-1.1 nsStratix V

1.75 ns-1.1 nsCyclone V

Timing Adjustment

RX registerTX register

36 UI11 UIStratix V or Arria V GZ

36 UI11 UIArria V GX, Arria V GT, or Arria V SoC

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Altera Triple Speed Ethernet MegaCore Function User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

About This MegaCore Function

About This MegaCore Function

Device Family Support

Features

10/100/1000 Ethernet MAC Versus Small MAC

High-Level Block Diagrams

Example Applications

MegaCore Verification

Optical Platform

Copper Platform

Performance and Resource Utilization

Release Information

Getting Started with Altera IP Cores

Introduction to Altera IP Cores

Installing and Licensing IP Cores

OpenCore Plus IP Evaluation

Upgrading Outdated IP Cores

IP Catalog and Parameter Editor

Using the Parameter Editor

Design Walkthrough

Creating a New Quartus II Project

Specifying IP Core Parameters and Options

Generating a Design Example or Simulation Model

Simulate the System

Compiling the Triple-Speed Ethernet MegaCore Function Design

Programming an FPGA Device

Generated Files

Design Constraint File No Longer Generated

Parameter Settings

Parameter Settings

Core Configuration

Ethernet MAC Options

FIFO Options

Timestamp Options

PCS/Transceiver Options

Functional Description

10/100/1000 Ethernet MAC

MAC Architecture

MAC Interfaces

MAC Transmit Datapath

IP Payload Re-alignment

Address Insertion

Frame Payload Padding

CRC-32 Generation

Interpacket Gap Insertion

Collision Detection in Half-Duplex Mode

MAC Receive Datapath

Preamble Processing

Collision Detection in Half-Duplex Mode

Address Checking

Unicast Address Checking

Multicast Address Resolution

Frame Type Validation

Payload Pad Removal

CRC Checking

Length Checking

Frame Writing

IP Payload Alignment

MAC Transmit and Receive Latencies

FIFO Buffer Thresholds

Receive Thresholds

Transmit Thresholds

Transmit FIFO Buffer Underflow

Congestion and Flow Control

Remote Device Congestion

Receive FIFO Buffer and Local Device Congestion

Magic Packets

Sleep Mode

Magic Packet Detection

MAC Local Loopback

MAC Error Correction Code

MAC Reset

PHY Management (MDIO)

MDIO Connection

MDIO Frame Format