Altera Temperature Sensor User Manual

2015.05.04

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Altera Temperature Sensor IP Core User Guide

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The Altera Temperature Sensor IP core configures the temperature sensing diode (TSD) block to utilize
the temperature measurement feature in the FPGA.

Note: Beginning from the Quartus II software version 14.0, the name of this IP core has been changed

from ALTTEMP_SENSE to Altera Temperature Sensor IP core.

Related Information

Introduction to Altera IP Cores

Provides general information about Altera IP cores.

Altera Temperature Sensor Features

The following table lists the Altera Temperature Sensor IP core features.

Table 1: Altera Temperature Sensor Features

Device Features

Stratix® V, Stratix IV, Arria® V, and Arria
V GZ

• An internal TSD with built-in 8-bit analog-to-digital
converter (ADC) circuitry to monitor die temperature

• A clock divider to reduce the frequency of the clock signal
to 1 MHz or less before clocking the ADC

• An asynchronous clear signal to reset the TSD block

Arria 10

• An internal TSD with built-in 10-bit ADC circuitry
clocked by 1 MHz internal oscillator to monitor die
temperature

• Does not require external clock source

• An asynchronous clear signal to reset the TSD block

Note: The Altera Temperature Sensor IP core does not have simulation model files and cannot be

simulated.

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Altera Temperature Sensor Functional Description

Altera Temperature Sensor Functional Description

Temperature Sensing Operation for Arria 10 Devices

Figure 1: Altera Temperature Sensor IP Core Top-Level Diagram for Arria 10 Devices

The following lists the features for Altera Temperature Sensor IP core for Arria 10 devices:

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• For Arria 10 devices, the Altera Temperature Sensor IP core supports the instantiation of temperature
sensor block in your design from the IP Catalog.

• The Arria 10 temperature sensor block runs at 1 MHz, where the clock signal is coming from the
internal oscillator. Within the block, 10-bit ADC circuitry is included for converting sensor’s reading
to digital output.

• The corectl signal is used as an enable signal. When asserting the corectl signal, the ADC starts the
conversion and 10-bit data is available at tempout after 1,024 clock cycles. The eoc signal goes high for
one clock cycle indicating end of conversion. You can latch the data on tempout at the falling edge of

eoc.

• You can reset the temperature sensor anytime by asserting the reset signal.

Related Information

Transfer Function for Internal TSD

Provides more information on how to calculate the temperature from the tempout[9:0] value.

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Altera Temperature Sensor IP Core User Guide

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ce

tsdcalo[7:0]

clr

tsdcaldone

clk

Altera Temperature Sensor IP Core

TEMPERATURE

SENSOR

adcclk

CLOCK

DIVIDER

ADC

oe

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Temperature Sensing Operation for Arria V, Arria V GZ, Stratix IV, and Stratix V

Temperature Sensing Operation for Arria V, Arria V GZ, Stratix IV, and Stratix V Devices

Figure 2: Altera Temperature Sensor Block Diagram

This figure shows the top-level ports and the basic building blocks of the Altera Temperature Sensor IP
core.

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Devices

The Altera Temperature Sensor IP core runs at the frequency of the clk signal. The clk signal can run at a
frequency of 80 MHz and below. The clock divider divides the clk signal to 1 MHz or less to feed the
ADC. You can set the value of the clock divider using the Altera Temperature Sensor IP core parameter
editor.

The ce signal connects to the output enable (oe) port of the clock divider block. Assert the ce signal to
enable the Altera Temperature Sensor IP core. When you deassert the ce signal, the IP core disables the
ADC, and maintains the previous values of the tsdcalo[7..0] and tsdcaldone signals unless you assert
the clr signal, or reset the device. The clr signal is asynchronous, and you must assert the clr signal at
least one clock cycle of the adcclk signal to clear the output ports.

Enabling the ADC allows you to measure the device temperature only once. To perform another tempera‐
ture measurement, assert the clr signal, or reset the device. The clr signal is asynchronous, and you must
assert the clr signal at least one clock cycle of the ADC clk signal to clear the output ports.

Note:

When you choose not to create the ce port, the IP core connects the ce port to VCC. In this case,
the ADC circuitry is always enabled. Altera recommends that you disable the ADC by deasserting
the ce signal when the ADC is not in use to reduce power consumption.

During device power-up or when you assert the asynchronous clr signal, the Altera Temperature Sensor
IP core sets the tsdcaldone port to 0 and the tsdcalo[7:0] signal to 11010101 or 0xD5. After 10 clock
cycles of the adcclk signal, the Altera Temperature Sensor IP core asserts the tsdcaldone signal to
indicate that the temperature sensing operation is complete and that the value of the tsdcalo[7:0] signal
is valid. The value of the tsdcalo[7:0] signal corresponds to the device temperature range. For more
information about the value of tsdcalo[7:0] signals, refer to the Related Information. To start another
temperature sensing operation, assert the clr signal for at least one clock cycle of the adcclk signal, or
reset the device.

Altera Temperature Sensor IP Core User Guide

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Generating the Altera Temperature Sensor IP

Note: When you choose not to create the clr port , the Altera Temperature Sensor IP core connects the

clr port to GND. In this case, you must reset the device to clear the output signals or start a

temperature sensing operation. Altera recommends that you generate the clr port if you are
planning to run the temperature sensing operation more than once.

If a derived PLL output clock is used to drive the Altera Temperature Sensor IP core, a minimum pulse
violation might occur. When using the Altera Temperature Sensor IP core, you must ensure the clock
applied must be less than or equal to 1 MHz. If you are using a higher frequency clock, the Altera
Temperature Sensor IP core allows you use the 40 or 80 clock divider to reduce the clock frequency to be
less than or equal to 1.0MHz.

Related Information

Altera Temperature Sensor Signals on page 8

Provides more information about the value of tsdcalo[7:0] that corresponds to the device temperature
range.

Generating the Altera Temperature Sensor IP

To generate the Altera Temperature Sensor IP core, follow these steps:

1. Open the alttemp_sense_ex1.zip file and extract alttemp_sense_ex1.qar.

2. In the Quartus II software, open the alttemp_sense_ex1.qar file and restore the archive file into your

working directory.

3. On the IP Catalog window, search and click Altera Temperature Sensor.

4. In the New IP Instance dialog box, type tsd_s4 as your top-level file name.

5. In the Device family field, select Stratix IV.

6. Then, select your FPGA device family from the Device Family pull-down list. Click OK.

7. In the Parameter Editor, set the following parameter settings.

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Table 2: Configuration Settings for the Altera Temperature Sensor IP Core

Option Value

What is the input frequency? 40 MHz
What is the clock divider value? 80 MHz
Create a clock enable port Turned on
Create an asynchronous clear port Turned on

8.

Click Finish. The tsd_s4 module is built.

Compiling the Altera Temperature Sensor IP

To compile the Altera Temperature Sensor IP core in the Quartus II software, follow these steps:

1. Open the top-level file alttemp_sense_ex1.bdf in the Quartus II Block Editor software. This file
contains the input and output assignments and a placeholder for the tsd_s4 module.

2. To insert the tsd_s4 module, double-click on the Block Editor window. The Symbol window appears.

3. Under Name, browse to the tsd_s4.bsf file.

4. Click OK.

5. Place the tsd_s4 module onto the INSERT TSD_S4 BLOCK HERE placeholder so that the module

aligns with the input and output ports.

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Altera Temperature Sensor IP Core User Guide

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