Altera Stratix V GX Edition User Manual

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Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

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MNL-01064-1.1

© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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9001:2008

Registered

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

Chapter 1. Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Chapter 2. Board Components

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Featured Device: Stratix V GX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

MAX II CPLD System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

FPGA Programming over Embedded USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

JTAG Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

FPP Configuration/MAX II Bypass DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

Program Select Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

CPU Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

Dedicated Transceiver Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

General-Purpose Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Embedded USB-Blaster Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

Transceiver Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

SMA Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

Backplane Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29

User-Defined Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29

User-Defined DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31

Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

Transceiver Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

XFP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

SFP+ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39

Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–40

Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–42

Temperature Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–42

Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–43

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

iv ContentsContents

Appendix A. Board Revision History

Engineering Silicon Version Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2

Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

This document describes the hardware features of the Stratix® V GX transceiver signal integrity development board, including the detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board.

General Description

The Transceiver Signal Integrity Development Kit, Stratix V GX Edition, allows you to evaluate the performance the Stratix V GX FPGA which is optimized for high-performance and high-bandwidth applications with integrated transceivers supporting backplane, chip-to-chip, and chip-to-module operation.

f For more information on the following topics, refer to the respective documents:

■ Setting up the development board and using the included software, refer to the

Transceiver Signal Integrity Development Kit, Stratix V GX Edition User Guide.

1. Overview

■ Stratix V device family, refer to the Stratix V Device Handbook.

Board Component Blocks

The Stratix V GX transceiver signal integrity development board provides a hardware platform for evaluating the performance and signal integrity features of the Altera Stratix V GX device. The development board features the following major component blocks:

■ Altera Stratix V GX FPGA (5SGXEA7N2F40C2N) in a 1517-pin FineLine BGA

Package (migratable to Stratix V GT FPGA 5SGTMC7K3F40C2)

■ 622,000 LEs

■ 358,500 adaptive logic modules (ALMs)

■ 50-Mbits embedded memory

■ 512 18x18-bit multipliers

■ 32 transceivers (12.5 Gbps)

■ 174 LVDS transmit channels

■ 28 phase locked loops (PLLs)

■ 696 user I/Os

■ 850-mV core voltage

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

1–2 Chapter 1: Overview

Board Component Blocks

■ FPGA configuration circuitry

■ MAX

II CPLD (EPM2210F256C3N) and flash Fast Passive Parallel (FPP)

configuration

■ MAX

■ JTAG header for external USB-Blaster

■ Flash storage for two configuration images (factory and user)

■ On-board clocking circuitry

■ 625-MHz, 644.53125-MHz, 706.25-MHz, and 875-MHz programmable

II CPLD (EPM570M100C4N) for on-board USB-BlasterTM to use with the

Quartus

II Programmer

oscillators for the high-speed transceiver reference clocks

■ 25/100/125/200 MHz jumper-selectable oscillator to the FPGA

■ 50-MHz general-purpose oscillator to the FPGA

■ One differential SMA clock input to the FPGA

■ Four differential SMA clock input to the transceivers

■ Spread spectrum clock input

■ Four clock trigger outputs

■ Transceiver interfaces

■ Four 28-Gbps TX/RX channels to MMPX connectors (for Stratix V GT FPGA

only)

■ Seven 12.5-Gbps TX/RX channels to SMA connectors

■ One 12.5-Gbps TX/RX channel to SFP+ cage

■ One 12.5-Gbps TX/RX channel to XFP cage

■ Five 12.5-Gbps TX/RX channels to Molex backplane connectors

■ Seven 12.5-Gbps TX/RX channels to Amphenol backplane connectors

■ Seven 12.5-Gbps TX/RX channels to Tyco backplane connectors

■ Memory devices

■ One 1-Gbyte (GB) synchronous flash with a 16-bit data bus

■ Communication ports

■ USB type-B connector

■ Gigabit Ethernet port and RJ-45 jack

■ LCD header

■ General user I/O

■ 8 user LEDs

■ Three configuration status LEDs (factory, user, error)

■ Six Ethernet LEDs

■ One 16-character × 2-line character LCD display

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 1: Overview 1–3

Board Component Blocks

■ Push buttons and DIP switches

■ One CPU reset push button

■ One configuration reset push button

■ Four general user push buttons

■ One 8-position user DIP switch

■ One 6-position MSEL control DIP switch

■ One 4-position frequency select and spread spectrum select DIP switch

■ One 4-position transceiver clock input select DIP switch

■ Two 4-position power sequence enable select DIP switches

■ One 4-position VCCRT_GXB/VCCA_GXB voltage select DIP switch

■ Heat sink and fan

■ 40-mm heat sink and fan combo

■ One over-temperature warning indicator LED

■ Power

■ 14-V – 20-V (laptop) DC input

■ One power-on LED

■ One on/off slide power switch

■ Power monitor and trim capability

■ Power sequence capability

■ System monitoring

■ Temp e ra tu re — FPGA d ie

■ Mechanical

■ 7.5" x 10.5" board dimension

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

1–4 Chapter 1: Overview

LCD

Buttons, Switches, Displays

16 Char × 2 Line LCD

8 User DIP Switch

4 User

Push Buttons

8 User

LEDs

Pwrgood

FPP Configuration

28-Gbps Channels

12.5-Gbps Channels

Clock

Circuitry

Tyco

Connector

1 SFP+

XFP

Amphl/FCI Connector

28 SMA

Connectors

16 MMPX

Connectors

Molex

Connector

1 GB Flash

3 Configuration

Status LEDs

MAX II

EPM2210

CPLD

PGMSEL

Flash

FPP Config

Power Monitor

15-bit ADCs

10-bit IDACs

ADC

2-wire Ch1

Power

Circuitry

2-wire Ch8

Temperature

Dual Temp

Sensor

Temperature Measure

TDIODES

7 TX/RX

1 TX/RX

7 TX/RX

1 TX/RX

5 TX/RX

4-ATT TX/RX

5-V Fan

USB-Blaster

USB

Type-B

Connector

FTDI

745BL

USB PHY

MAX II

EPM570M

CPLD

10/100/1000 Ethernet

RJ45+

Magnetics

Marvell

88E1111

Ethernet PHY

Development Board Block Diagram

Figure 1–1 shows the block diagram of the Stratix V GX transceiver signal integrity

development board.

Figure 1–1. Stratix V GX Transceiver Signal Integrity Development Board Block Diagram

Handling the Board

c Without proper anti-static handling, the board can be damaged. Therefore, use

When handling the board, it is important to observe the following static discharge precaution:

anti-static handling precautions when touching the board.

The Stratix V GX transceiver signal integrity development board must be stored between –40º C and 100º C. The recommended operating temperature is between 0º C and 55º C.

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Introduction

1 A complete set of schematics, a physical layout database, and GERBER files for the

f For information about powering up the board and installing the demo software, refer

2. Board Components

This chapter introduces all the important components on the Stratix V GX transceiver signal integrity development board. Figure 2–1 illustrates major component locations and Table 2–1 provides a brief description of all features of the board.

development board reside in the Stratix V GX development kit documents directory.

to the Transceiver Signal Integrity Development Kit, Stratix V GX Edition User Guide.

This chapter consists of the following sections:

■ “Board Overview”

■ “Featured Device: Stratix V GX” on page 2–6

■ “MAX II CPLD System Controller” on page 2–9

■ “Configuration, Status, and Setup Elements” on page 2–14

■ “Clock Circuitry” on page 2–21

■ “General User Input/Output” on page 2–29

■ “Components and Interfaces” on page 2–33

■ “Flash Memory” on page 2–37

■ “Power Supply” on page 2–39

■ “Statement of China-RoHS Compliance” on page 2–43

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

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2–2 Chapter 2: Board Components

User DIP Switch (SW4)

Stratix V GX FPGA (U29)

VCCRT_GXB/ VCCA_GXB

Voltage Select (SW2)

MSEL Selection/MAX II Bypass (S7)

Clock Trigger Outputs (U32, U33)

Clock Trigger Outputs (U34, U35)

Transceiver Clock Input Select DIP switch (SW6)

Reset Push Buttons (S5, S6)

MAX II

CPLD (U19)

Transceiver Input

Reference Clocks

User Push Buttons (SW1-SW4)

User LEDs (D8-D15)

SFP+ Module (J51)

XFP Module (U25)

Molex Backplane Connector (J34)

Tyco

Connector

(J33)

Amphenol Backplane Connector (J32)

Powe r Switch (SW1)

JTAG Header

(J93)

DC Power

Jack (J1)

Character LCD (J30)

Embedded

USB-Blaster

(CN1)

Power Sequence

Enable/Disable

(SW7, SW3)

10/100 /1000

Ethernet

Port (J29)

Fan Connector (J12)

Fan Jumper (J26)

Fan LED (D6)

GXB Receive SMA

GXB Transmit SMA

FPGA Clock Input Select/

Spread Spectrum Clock Select

(SW5)

External Power

Input Banana Jacks

(J6, J15, J18, J21)

Board Overview

This section provides an overview of the Stratix V GX transceiver signal integrity development board, including an annotated board image and component descriptions. Figure 2–1 provides an overview of the development board features.

Figure 2–1. Overview of the Stratix V GX Transceiver Signal Integrity Development Board Features

Tab le 2– 1 describes the components and lists their corresponding board references.

Table 2–1. Transceiver Signal Integrity Development Kit Components (Part 1 of 4)

Board Reference Type Description

Featured Devices

U29 FPGA Stratix V GX FPGA (5SGXEA7N2F40C2N), 1517-pin BGA.

U19 CPLD MAX II CPLD (EPM2210F256C3N), 256-pin BGA.

Configuration, Status, and Setup Elements

S7 (pin 6-7) MAX II bypass switch

Enables or disables the MAX II CPLD in the JTAG chain. The MAX II CPLD is disabled by default.

Stratix V GX Edition Reference Manual

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation

Chapter 2: Board Components 2–3

Board Overview

Table 2–1. Transceiver Signal Integrity Development Kit Components (Part 2 of 4)

Board Reference Type Description

J28 Program select jumper

SW5

FPP configuration/MAX II bypass DIP switch

Spread spectrum clock settings DIP switch

VCCA_GXB voltage selection

SW2 (pin2-7)

jumper

VCCRT voltage selection

SW2 (pin 1-8)

jumper

Toggles the program LEDs to select which FPGA image to load on power-up; 0 selects factory image and 1 selects user-defined image.

Select the configuration mode from the MAX II CPLD.

DIP switch to set the spread spectrum output clock frequency and down-spread percentages.

Jumper to select V close position, the V position, the V

voltage to the FPGA. When the jumper is set to

CCA

voltage is 3.0 V (default). When set to open

CCA

voltage is 2.5 V.

CCA

voltage to the FPGA. When the jumper is set to

CCRT

voltage is 1.0 V (default). When set to open

CCRT

voltage is 0.85 V.

CCRT

Fan control jumper Jumper to select whether the fan is always on or the FPGA

J26

automatically controls the fan. To set it to its default setting of always on, connect jumper pin 2-3. Connect jumper pin pin 1-2 to set the fan in auto mode.

D7 Fan LED Indicates an over-temperature condition in the FPGA and a fan should

be attached to the FPGA and running.

D8 Load LED Illuminates during embedded USB-Blaster data transfers.

D9 Error LED Illuminates when the FPGA configuration from flash fails.

D3 Power LED Illuminates when 14-V power is present.

D12-D17 Ethernet LEDs Shows the connection speed as well as transmit or receive activity.

Clock Circuitry

Feeds even-numbered REFCLKs on left side of the Stratix V GX device

Y3 Programmable oscillator

and trigger an output at board reference J81. The external input is available at board reference J79 and J80. The default frequency is

644.53125 MHz.

Feeds odd-numbered REFCLKs on left side of the Stratix V GX device

Y4 Programmable oscillator

and trigger an output at board reference J85. The external input is available at board reference J83 and J84. The default frequency is

706.25 MHz.

Feeds even-numbered REFCLKs on right side of the Stratix V GX device

Y5 Programmable oscillator

and trigger an output at board reference J88. The external input is available at board reference J86 and J87. The default frequency is 625 MHz.

Feeds odd-numbered REFCLKs on right side of the Stratix V GX device

Y6 Programmable oscillator

and trigger an output at board reference J91. The external input is available at board reference J89 and J90. The default frequency is 875 MHz.

SW6

Transceiver clock input select DIP switch

DIP switch to select the SMA or oscillator as the clock input.

Y2 50-MHz oscillator 50.000-MHz crystal oscillator for general purpose logic.

X3 25/100/125/200-MHz core

Selects the core clock frequency. The default frequency is 100 MHz.

clock selectable oscillator

SW5 Spread spectrum selection

switch

Select either the core or spread spectrum clock. Pin 1-2 selects S0 and S1 while pin 3-4 selects SS0 and SS1.

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

2–4 Chapter 2: Board Components

Board Overview

Table 2–1. Transceiver Signal Integrity Development Kit Components (Part 3 of 4)

Board Reference Type Description

J70 and J71 External core clock input SMA external input at CLK10 p/n.

J72 and J73 External core clock output SMA external output at FPLL/IO4D.

Transceiver Interfaces

J36, J39, J41,

GXB transmit channel Transceiver GXB transmit channels connected to SMA. J46, J48, J53, J55, J57, J59, J61, J63, J65, J67, J69

J35, J37, J38,

GXB receive channel Transceiver GXB receive channels connected to SMA. J40, J42, J45, J47, J52, J54, J56, J58, J60, J62, J64, J66, J68

J51 Transceiver optical interface Transceiver receive and transmit channel connected to the Small

Form-Factor Pluggable (SFP+) module.

U25 Transceiver optical interface Transceiver receive and transmit channel connected to the XFP

module.

Transceiver Interfaces – Backplane Connectors

J33 10Gbase-KR reference

backplane

J34 10Gbase-KR reference

backplane

J32 10Gbase-KR reference

backplane

7 transceiver-channel pairs, right angle receptacle for Tyco backplane connector.

5 transceiver-channel pairs, right angle receptacle for Molex Impact backplane connector.

7 transceiver-channel pairs, right angle receptacle for Amphenol backplane connector.

Transceiver Interfaces – Stratix V GT

J94, J96, J98,

Advanced transceiver interface Transceiver GTB receive channels connected to the MMPX connectors. J100, J102, J104, J106, J108

J95, J97, J99, J101, J103, J105,

Advanced transceiver interface Transceiver GTB transmit channels connected to the MMPX

connectors.

J107, J109

J110, J111, J112, J113

Transceiver test trace Transceiver GTB receive and transmit channels connected to the

MMPX connectors with an eight inch test trace.

General User Input and Output

D18-D25 User LEDs 8 user LEDs. Illuminates when driven low.

SW4 User DIP switch Octal user DIP switches. When the switch is open, a logic 0 is selected.

Configuration reset push

button

The default reset for the MAX II CPLD System Controller.

S6 CPU reset push button The default reset for the FPGA logic.

S1-S4 General user push buttons Four user push buttons. Driven low when pressed .

J30 Character LCD header

A single 14-pin 0.1" pitch dual-row header which interfaces to the 16 character × 2 line LCD module.

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–5

Board Overview

Table 2–1. Transceiver Signal Integrity Development Kit Components (Part 4 of 4)

Board Reference Type Description

Memory Devices

U21 Flash memory Micron PC28F00AP30BF, 1-GB CFI NOR flash memory.

U17 EEPROM Microchip Technology Inc. 93LC46B/SNG-ND, 64x16 EEPROM SO.

Communication Ports

RJ-45 connector which provides a 10/100/1000 Ethernet connection

J29 Gigabit Ethernet port

through a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed Ethernet MAC MegaCore function in SGMII mode.

JTAG header for connecting an Altera USB-Blaster dongle to program

J93 JTAG header

the FPGA and MAX II CPLD devices. The embedded USB-Blaster is disabled when you connect the USB-Blaster to the JTAG header.

CN1 USB Type-B connector

Connects a type-B USB cable to enable the JTAG embedded USB-Blaster to program the FPGA and MAX II CPLD devices.

Power Supply

J1 DC input jack

14-V – 20-V DC female input power jack. Accepts a 2.5-mm male center-positive barrel from 14-V DC power supply.

SW1 Power switch Switch to power on/off the board.

J6 S5GX_VCC (0.85 V/0.9 V)

banana jack

Banana jack for supplying external V and F2 must be removed prior to supplying external power to this

power to the FPGA. Fuses F1

banana jack.

J12 VCCA_GXB (2.5 V/3.3 V)

banana jack

J9 VCCRT_GXB (0.85 V/1.0 V)

banana jack

J15 VCCR_GTB (1.0 V) banana

jack

J21 VCCL_GTB (1.0 V) banana

jack

J18 VCCT_GTB (1.0 V) banana

jack

Banana jack for supplying external V must be removed prior to supplying external power to this banana jack.

power to the FPGA. Fuse F7

CCA

power to the FPGA. Fuse F6

CCRT_GXB

power to the FPGA. Fuse F3

CCR_GTB

power to the FPGA. Fuse F5

CCL_GTB

power to the FPGA. Fuse F4

CCT_GTB

J3 Ground banana jack Banana jack connected to ground.

U10 and U11 Power monitor devices Linear Technology LTC2978, octal PMBus power supply monitor and

controller.

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

2–6 Chapter 2: Board Components

Featured Device: Stratix V GX

The Stratix V GX development board features the Stratix V GX 5SGXEA7N2F40C2N device (U29) in a 1517-pin FineLine BGA package.

f For more information about the Stratix V device family, refer to the Stratix V Device

Handbook.

Tab le 2– 2 describes the features of the Stratix V GX 5SGXEA7N2F40C2N device.

Table 2–2. Stratix V GX 5SGXEA7N2F40C2N Features

ALMs

358,500 622,000 939,000 2,560 7.16 512 28 36

Equivalent

LEs

Registers

M20K

Blocks

MLAB

Blocks (Mb)

18-bit × 18-bit

Multipliers

PLLs

Transceiver

Channels

(12.5 Gbps)

Package Type

1517-pin

FineLine BGA

Tab le 2– 3 lists the Stratix V GX component reference and manufacturing information.

Table 2–3. Stratix V GX Component Reference and Manufacturing Information

Board

Reference

U29

Description Manufacturer

FPGA, Stratix V GX F1517, 622K LEs, lead-free

Corporation 5SGXEA7N2F40C2N www.altera.com

Altera

Manufacturing

Part Number

Manufacturer

Website

I/O Resources

Tab le 2– 4 summarizes the FPGA I/O usage by function on the Stratix V GX

transceiver signal integrity development board.

Table 2–4. Stratix V GX I/O Usage Summary (Part 1 of 3)

Function I/O Type I/O Count Description

FPGA Transceiver Clocks

Programmable differential clock LVDS input 4 Differential REFCLK input to feed the even-

numbered channels on the left side of the Stratix V GX device.

Programmable differential clock LVDS input 4 Differential REFCLK input to feed the odd-numbered

channels on the left side of the Stratix V GX device.

Programmable differential clock LVDS input 4 Differential REFCLK input to feed the even-

numbered channels on the right side of the Stratix V GX device.

Programmable differential clock LVDS input 4 Differential REFCLK input to feed the odd-numbered

channels on the right side of the Stratix V GX device.

External differential clock inputs LVDS input 4 pairs Differential REFCLK input for one SMA pair per

clock buffer.

FPGA Global Clocks

50-MHz clock 2.5-V CMOS input 1 Global clock input.

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–7

Featured Device: Stratix V GX

Table 2–4. Stratix V GX I/O Usage Summary (Part 2 of 3)

Function I/O Type I/O Count Description

Spread Spectrum clock 2.5-V CMOS input 2 Differential global clock.

SMA differential clock input LVDS input 2 Differential global clock.

Temperature Monitor

Temperature sense diodes Analog 2 Stratix V GX internal sense diode.

Power Monitor Devices

LTC2978 controller 2.5-V CMOS 24 Octal PMBus power supply monitor and controller.

Temperature Measure

MAX1619 interface 2.5V CMOS 4 Die and ambient temperature sense.

Fan

FAN_On 2.5-V CMOS output 1 Fan control

FAN_LED 2.5-V CMOS output 1 Fan LED

USB-Blaster

JTAG USB-Blaster or JTAG header

2.5-V CMOS 4 Built-in USB-Blaster or JTAG 0.1-mm header for debugging

FPP Configuration

FPGA Dclk 2.5-V CMOS input 1 FPP Dclk

FPGA D[15:0] 2.5V CMOS 16 FPP data bus

MSEL [4:0] 2.5V CMOS 5 Dedicated configuration pins

NCONFIG 2.5V CMOS 1 Dedicated configuration pins

NSTATUS 2.5V CMOS 1 Dedicated configuration pins

NCE 2.5V CMOS 1 Dedicated configuration pins

CONFIG_DONE 2.5V CMOS 1 Dedicated configuration pins

Flash Memory

ADDR[26:1] 1.8-V CMOS output 26 Flash address bus

DATA[15:0] 1.8-V CMOS

16 Flash data bus

input/output

FLASH_CEn 1.8-V CMOS output 1 Flash chip enable

FLASH_OEn 1.8-V CMOS output 1 Flash read strobe

FLASH_WEn 1.8-V CMOS output 1 Flash write strobe

FLASH_WAIT 1.8-V CMOS input 1 Flash ready or busy

FLASH_CLK 1.8-V CMOS output 1 Flash clock

FLASH_RSTn 1.8-V CMOS output 1 Flash reset

FLASH_ADVn 1.8-V CMOS output 1 Flash address valid

FLASH_WPn 1.8-V CMOS output 1 Flash write protect

Reset

CPU_RESETn 2.5-V CMOS input 1 Nios

II CPU reset

Switches, Buttons, LEDS

User push buttons 2.5-V CMOS input 4 4 user push buttons

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

2–8 Chapter 2: Board Components

Featured Device: Stratix V GX

Table 2–4. Stratix V GX I/O Usage Summary (Part 3 of 3)

Function I/O Type I/O Count Description

User DIP switches 2.5-V CMOS input 8 8 user DIP switches

User LEDs 2.5-V CMOS output 8 8 user LEDs (green)

LCD

16 Character × 2 Line LCD 5.0-V LVTTL output 11 LCD

Ethernet

TXD[3:0] 2.5-V CMOS output 4 Ethernet transmit RGMII data bus

TXEN 2.5-V CMOS output 1 Ethernet transmit enable

GTXCLK 2.5-V CMOS output 1 Ethernet transmit clock

RXD[3:0] 2.5-V CMOS input 4 Ethernet receive RGMII data bus

RXDV 2.5-V CMOS input 1 Receive data valid

RXCLK 2.5-V CMOS input 1 Receive clock

MDC 2.5-V CMOS input 1 Ethernet MII clock

MDIO 2.5-V CMOS inout 1 Ethernet MII data

ENET_SGMII_TXP/N LVDS output 2 Ethernet SGMII transmit data positive/negative

ENET_SGMII_RXP/N LVDS input 2 Ethernet SGMII receive data positive/negative

Transceivers

28G channels to MMPX 1.4-V PCML 16 Transceiver channel

12.5G channels to Tyco backplane connector

12.5G channels to Amphenol backplane connector

12.5G channels to Molex backplane connector

1.4-V PCML 28

Transceiver channel

12.5G channels to SMA 1.4-V PCML 28 Transceiver channel

12.5G channels to a SFP+ cage 1.4-V PCML 4 Transceiver channel

12.5G channels to XFP cage 1.4-V PCML 4 Transceiver channel

Spares

Spare[7:0] 2.5-V CMOS 8 Spare signals to the MAX II CPLD

Device I/O Total:

304

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–9

MAX1619

Controller

Information

Embedded

USB-Blaster

MAX II CPLD

SLD-HUB

PFL

FSD Bus

Temperature

Measure Results

Virtual-JTAG

S5_VCCA

Measure Results

FPGA

LTC2978

Controller

Flash

GPIO

Decoder

Encoder

JTAG Control

Control

Power Monitor

MAX II CPLD System Controller

The board utilizes the EPM2210F256C3N System Controller, an Altera MAX II CPLD, for the following purposes:

■ FPGA configuration from flash memory

■ Temp e ra tu re m onito ri ng

■ Fan control

■ Virtual JTAG interface for PC-based power and temperature GUI

■ Control registers for clocks

■ Control registers for Remote System Update

■ Register with CPLD design revision and board information (read-only)

Figure 2–2 illustrates the MAX II CPLD System Controller's functionality and external

circuit connections as a block diagram.

Figure 2–2. MAX II CPLD System Controller Block Diagram

Tab le 2– 5 lists the I/O signals present on the MAX II CPLD System Controller. The

signal names and functions are relative to the MAX II device (U19).

Table 2–5. MAX II CPLD System Controller Device Pin-Out (Part 1 of 5)

Schematic Signal

Name

50MHZ_MAXLL_CLK

ALERTn

CONF_DONE

CONFIG_D0

CONFIG_D1

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

MAX II CPLD

Pin Number

H5 — 2.5-V 50 MHz clock input

D2 E8 2.5-V Temperature monitor alert

Stratix V GX

Pin Number

i/O

Standard

T13 AB12 2.5-V Configuration done

T11 AR33 2.5-V Configuration data

T10 AU32 2.5-V Configuration data

Description

Stratix V GX Edition Reference Manual

2–10 Chapter 2: Board Components

MAX II CPLD System Controller

Table 2–5. MAX II CPLD System Controller Device Pin-Out (Part 2 of 5)

Schematic Signal

Name

CONFIG_D2

CONFIG_D3

CONFIG_D4

CONFIG_D5

CONFIG_D6

CONFIG_D7

CONFIG_D8

CONFIG_D9

CONFIG_D10

CONFIG_D11

CONFIG_D12

CONFIG_D13

CONFIG_D14

CONFIG_D15

CONFIG_ERR

DCLK

ENET_RSTn

F_AD1

F_AD2

F_AD3

F_AD4

F_AD5

F_AD6

F_AD7

F_AD8

F_AD9

F_AD10

F_AD11

F_AD12

F_AD13

F_AD14

F_AD15

F_AD16

F_AD17

F_AD18

F_AD19

F_AD20

F_AD21

F_AD22

MAX II CPLD

Pin Number

Stratix V GX

Pin Number

i/O

Standard

P12 AT32 2.5-V Configuration data

P11 AW32 2.5-V Configuration data

R11 AV32 2.5-V Configuration data

R10 AM32 2.5-V Configuration data

N12 AL31 2.5-V Configuration data

P10 AN32 2.5-V Configuration data

H4 AN31 2.5-V Configuration data

J4 AM31 2.5-V Configuration data

J3 AL30 2.5-V Configuration data

K2 AK30 2.5-V Configuration data

K5 AJ30 2.5-V Configuration data

K4 AJ29 2.5-V Configuration data

K3 AJ28 2.5-V Configuration data

L5 AM29 2.5-V Configuration data

R9 — 2.5-V Configuration error

T8 U28 2.5-V Configuration clock

A15 AT6 2.5-V Ethernet LED

M16 AE14 2.5-V Flash address bus

M15 AD14 2.5-V Flash address bus

M14 AC13 2.5-V Flash address bus

N16 AC12 2.5-V Flash address bus

N15 AG14 2.5-V Flash address bus

J16 AF14 2.5-V Flash address bus

N13 AD11 2.5-V Flash address bus

N14 AC11 2.5-V Flash address bus

C14 AF11 2.5-V Flash address bus

B12 AE11 2.5-V Flash address bus

F15 AE13 2.5-V Flash address bus

F16 AE12 2.5-V Flash address bus

D16 AJ14 2.5-V Flash address bus

A11 AH13 2.5-V Flash address bus

A12 AG13 2.5-V Flash address bus

B13 AF13 2.5-V Flash address bus

E15 AJ13 2.5-V Flash address bus

L14 AJ12 2.5-V Flash address bus

J15 AH12 2.5-V Flash address bus

D14 AG11 2.5-V Flash address bus

K14 AK12 2.5-V Flash address bus

D15 AK11 2.5-V Flash address bus

Description

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–11

MAX II CPLD System Controller

Table 2–5. MAX II CPLD System Controller Device Pin-Out (Part 3 of 5)

Schematic Signal

Name

F_AD23

F_AD24

F_AD25

F_AD26

F_ADVn

F_BSYn

F_CEn

F_CLK

F_D0

F_D1

F_D2

F_D3

F_D4

F_D5

F_D6

F_D7

F_D8

F_D9

F_D10

F_D11

F_D12

F_D13

F_D14

F_D15

F_OEn

F_RSTn

F_WEn

F_WPn

FACTORY_IMAGE

FAN_CTRL

FAN_LED

INIT_DONE

JTAG_TCK

JTAG_TMS

MAX_2_MAX_INITDONE

MAX_FPP_TDI

MAX_FPP_TDO

MAX II CPLD

Pin Number

Stratix V GX

Pin Number

i/O

Standard

Description

A13 AL12 2.5-V Flash address bus

B14 AL11 2.5-V Flash address bus

C13 AM13 2.5-V Flash address bus

B16 AL13 2.5-V Flash address bus

P13 AP7 2.5-V Flash address valid

J14 AR7 2.5-V Flash chip busy

P14 AP9 2.5-V Flash chip enable

R16 AN6 2.5-V Flash clock

L15 AN11 2.5-V Flash data bus

L16 AM11 2.5-V Flash data bus

K15 AP12 2.5-V Flash data bus

K16 AN12 2.5-V Flash data bus

H16 AN10 2.5-V Flash data bus

H15 AM10 2.5-V Flash data bus

G16 AR11 2.5-V Flash data bus

G15 AR10 2.5-V Flash data bus

M13 AT12 2.5-V Flash data bus

L13 AU13 2.5-V Flash data bus

J13 AU12 2.5-V Flash data bus

H13 AU11 2.5-V Flash data bus

G13 AT11 2.5-V Flash data bus

F13 AW13 2.5-V Flash data bus

F14 AV13 2.5-V Flash data bus

E14 AW11 2.5-V Flash data bus

P15 AN9 2.5-V Flash output enable

H14 AL8 2.5-V Flash reset

G14 AM8 2.5-V Flash write enable

T12 AP6 2.5-V Flash write protect

R8 — 2.5-V Factory image for configuration

E3 D6 2.5-V Fan control

C3 C6 2.5-V Fan LED

R13 AN33 2.5-V FPGA initialization done.

P3 AV34 2.5-V JTAG chain clock

N4 AU34 2.5-V JTAG chain mode

Control signal between the MAX II System Controller

H2 — 2.5-V

and the MAX II embedded USB-Blaster to indicate that initialization is done.

L6 — 2.5-V Fast Passive Parallel (FPP) programming data in

M5 — 2.5-V FPP programming data out

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

2–12 Chapter 2: Board Components

MAX II CPLD System Controller

Table 2–5. MAX II CPLD System Controller Device Pin-Out (Part 4 of 5)

Schematic Signal

Name

MAXLL_BEN0

MAXLL_BEN1

MAXLL_BEN2

MAXLL_BEN3

MAXLL_CLK

MAXLL_CSn

MAXLL_OEn

MAXLL_WEn

MSEL0

MSEL1

MSEL2

MSEL3

MSEL4

NCONFIG

NSTATUS

OVERTEMPn

PFL_STATUS

PGM0

PGM1

PGM2

PGMSEL

PM1_FAULTB00

PM1_FAULTB01

PM1_FAULTB10

PM1_FAULTB11

PM2_FAULTB00

PM2_FAULTB01

PM2_FAULTB10

PM2_FAULTB11

PM_ALERTB

PM_CNTL0

PM_CNTL1

PM_PWRGD

PM_RSTN

PM_SHARE_CLK

PR_DONE

PR_ERROR

PR_READY

PR_REQUEST

MAX II CPLD

Pin Number

Stratix V GX

Pin Number

i/O

Standard

Description

F5 AN15 2.5-V Flash bus MAX II byte enable 0

F2 AN14 2.5-V Flash bus MAX II byte enable 1

F6 AM14 2.5-V Flash bus MAX II byte enable 2

F1 AR14 2.5-V Flash bus MAX II byte enable 3

G3 AR13 2.5-V Flash bus MAX II clock

G2 AR15 2.5-V Flash bus MAX II chip select

G4 AP15 2.5-V Flash bus MAX II output enable

G1 AT15 2.5-V Flash bus MAX II write enable

D13 W12 2.5-V DIP - FPGA mode select 0

K12 Y11 2.5-V DIP - FPGA mode select 1

K13 AA12 2.5-V DIP - FPGA mode select 2

L11 AA11 2.5-V DIP - FPGA mode select 3

L12 W11 2.5-V DIP - FPGA mode select 4

R14 U26 2.5-V FPGA configuration active LED

R12 AL10 2.5-V FPGA configuration ready status LED

E4 E7 2.5-V Temperature monitor over-temperature indicator LED

P4 — 2.5-V Parallel Flash Loader (PFL) programming status

T6 AW10 2.5-V Flash memory PGM select indicator 0

T5 AV10 2.5-V Flash memory PGM select indicator 1

T4 AR12 2.5-V Flash memory PGM select indicator 2

T7 — 2.5-V Toggles the

PGM_LED[0:2]

sequence

C4 U14 2.5-V Power monitor bus

C6 U13 2.5-V Power monitor bus

B3 R12 2.5-V Power monitor bus

C5 P11 2.5-V Power monitor bus

A2 N13 2.5-V Power monitor bus

D5 N12 2.5-V Power monitor bus

B1 R13 2.5-V Power monitor bus

D4 P13 2.5-V Power monitor bus

B4 L12 2.5-V Power monitor alert

C7 K12 2.5-V Power monitor control bus

A4 K13 2.5-V Power monitor control bus

D6 V12 2.5-V Power monitor power

E6 J13 2.5-V Power monitor reset

B5 M12 2.5-V Power monitor clock

B6 AB29 2.5-V FPGA partial reconfiguration done

D7 AC27 2.5-V FPGA partial reconfiguration error

A5 AD29 2.5-V FPGA partial reconfiguration ready

E7 AE29 2.5-V FPGA partial reconfiguration request

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–13

MAX II CPLD System Controller

Table 2–5. MAX II CPLD System Controller Device Pin-Out (Part 5 of 5)

Schematic Signal

Name

PWR_GOOD

RESETN

S5_RSTN

S5_SMBCLK_TEMP

S5_SMBDATA_TEMP

SCL_OSC

SCL_PM

SDA_OSC

SDA_PM

SPARE0

SPARE1

SPARE2

SPARE3

SPARE4

SPARE5

SPARE6

SPARE7

USB_MAX_D0

USB_MAX_D1

USB_MAX_D2

USB_MAX_D3

USB_MAX_D4

USB_MAX_D5

USB_MAX_D6

USB_MAX_D7

USB_MAX_PWR_ENn

USB_MAX_RDn

USB_MAX_RXFn

USB_MAX_TXEn

USB_MAX_WR

USER_IMAGE

MAX II CPLD

Pin Number

J1 — —

Stratix V GX

Pin Number

i/O

Standard

Description

Power good signal to indicate that all voltage rails have come up to their proper levels.

T2 — 2.5-V FPGA reset LED

T15 AV19 2.5-V FPGA reset

D3 B8 2.5-V Temperature monitor SMB clock

C2 A8 2.5-V Temperature monitor SMB data

D8 — 2.5-V Configuration clock oscillator

C8 L11 2.5-V Configuration clock power monitor

B7 — 2.5-V Configuration data oscillator

A6 M11 2.5-V Configuration data power monitor

A10 AH19 2.5-V Spare signals to the MAX II CPLD

A9 AG19 2.5-V Spare signals to the MAX II CPLD

A8 AJ18 2.5-V Spare signals to the MAX II CPLD

A7 AH18 2.5-V Spare signals to the MAX II CPLD

B11 AN19 2.5-V Spare signals to the MAX II CPLD

B10 AM19 2.5-V Spare signals to the MAX II CPLD

B9 AR19 2.5-V Spare signals to the MAX II CPLD

B8 AP19 2.5-V Spare signals to the MAX II CPLD

M3 — 2.5-V USB configuration data bus

L4 — 2.5-V USB configuration data bus

N1 — 2.5-V USB configuration data bus

L3 — 2.5-V USB configuration data bus

N2 — 2.5-V USB configuration data bus

M4 — 2.5-V USB configuration data bus

N3 — 2.5-V USB configuration data bus

P2 — 2.5-V USB configuration data bus

E1 — 2.5-V USB configuration power enable

D1 — 2.5-V USB configuration read from FIFO

F4 — 2.5-V USB configuration receive enable

E2 — 2.5-V USB configuration transmit enable

F3 — 2.5-V USB configuration write to FIFO

R7 — 2.5-V User image for configuration

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

2–14 Chapter 2: Board Components

Configuration, Status, and Setup Elements

Tab le 2– 6 lists the MAX II CPLD System Controller component reference and

manufacturing information.

Table 2–6. MAX II CPLD EPM2210 System Controller Component Reference and Manufacturing Information

Board Reference Description Manufacturer

U19

MAX II CPLD 256FBGA -3 LF

3.3 V VCCINT

Corporation EPM2210F256C3N www.altera.com

Altera

Configuration, Status, and Setup Elements

This section describes the board's configuration, status, and setup elements.

Configuration

This section describes the FPGA, flash memory, and MAX II CPLD System Controller device programming methods supported by the Stratix V GX transceiver signal integrity development board.

The Stratix V GX transceiver signal integrity development board supports three configuration methods:

■ Embedded USB-Blaster is the default method for configuring the FPGA at any

time using the Quartus II Programmer in JTAG mode with the supplied USB cable.

■ MAX II and flash FPP download for configuring the FPGA using stored images

from the flash on either power-up or pressing the reset push-button (S5).

■ JTAG header (J93) for initial debugging and to bring up the on-board USB-Blaster

circuitry.

Manufacturing

Part Number

Manufacturer

Website

FPGA Programming over Embedded USB-Blaster

Programming the FPGA over embedded USB-Blaster is implemented using a type-B USB connector (CN1), a USB 2.0 PHY device, and an Altera MAX II CPLD EPM2210F256C3N (U19). This allows configuration of the FPGA using a USB cable directly connected between the USB port on the board (CN1) and a USB port of a PC running the Quartus II software. The JTAG chain is normally mastered by the embedded USB-Blaster found in the MAX II CPLD System Controller.

A green USB-Blaster LED (D8) indicates the USB-Blaster activity. The embedded USB-Blaster is automatically disabled when you connect an external USB-Blaster to the JTAG chain at the JTAG header (J93).

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–15

USB

USB CONN (CN1)

FTDI

FT245BL

USB PHY

(U16)

USB FIFO BUS

MAX7064

CPLD (U17)

JTAG

JTAG PROG

HDR (J28)

USB

Stratix IV GX FPGA (U33)

Configuration, Status, and Setup Elements

Figure 2–3 shows the block diagram for the embedded USB-Blaster.

Figure 2–3. Embedded USB-Blaster

MAX II CPLD System Controller

The EPM570M100 MAX II CPLD (U16) is dedicated to the on-board USB-Blaster functionality. The CPLD connects to the FT245BL USB FIFO device on one side and drives the JTAG signals out the other side on the general purpose I/O (GPIO) pins. A 64x16 EEPROM connects to the CPLD device and stores the factory image for USB–JTAG functionality.

FPGA Programming from Flash Memory

On power-up, the MAX II CPLD System Controller’s parallel flash loader (PFL) configures the FPGA from the flash memory. The system controller uses the Altera Parallel Flash Loader (PFL) megafunction to read 16-bit data from the flash memory and converts it to fast passive parallel (FPP) format. This 8-bit data is then written to the FPGA’s dedicated configuration pins during configuration.

The FPP configuration is implemented with an Altera MAX II CPLD together with the Micron PC2800AP30BF 1-Gbit CFI NOR-type flash device (U21). The CPLD shares the flash interface with the FPGA. The configuration program select, PGMSEL jumper (J28) selects between two Programmer Object Files (.pof) files (factory or user) stored in the flash. The configuration mode select signals, MSEL[4:0], are pulled to [ FPP x16 on the board for FPP mode configuration.

There are three configuration status LEDs,

USER_IMAGE

(D9, D10, D11) which indicate the status of the FPP configuration. For

CONFIG_ERR, FACTORY_IMAGE

, and

information on the configuration status LEDs, refer to “Status Elements” on

page 2–18.

Tab le 2– 7 lists the PGMSEL jumper settings.

Table 2–7. PGMSEL Jumper Settings

Jumper PGMSEL Setting File Selection

Not installed (default) 0 Factory image

Installed 1 User image

00100

]

Stratix V GX Edition Reference Manual

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

2–16 Chapter 2: Board Components

MAX II CPLD

System Controller

CONF_D[15:0]

DCLK

CLKxP

F_AD[26:1]

F_D[15:0]

D[15:0]

nSTATUS

nCONFIG

CONF_DONE

MSEL0

MSEL1

MSEL2

MSEL3

nCE

CFI Flash

Green LED (Factory Image)

Green LED (User Image)

Red LED (Error Image)

F_CEn

F_OEn

F_WEn

DEV_CLRn

nCONFIG

CONF_DONE

FSM Bus Interface

PGMSEL

PGM [2:0]

CLKBUF

nSTATUS

CLK

ADVn

CONFIG_ERR, FACTORY_IMAGE, USER_IMAGE LEDs

2.5 V

F_CLK

F_RSTn

RESETn

RY/BYn

WPn

RY/BYn

WPn

50 MHz

MSEL4

MAX_BYPASS

DIP Switch

(S7)

RESETn

F_AD[26:1]

F_D[15:0]

F_CEn

F_OEn

F_WEn

ADVn

F_CLK

Configuration, Status, and Setup Elements

Figure 2–4 shows the MAX II and flash FPP configuration.

Figure 2–4. MAX II and Flash FPP Configuration

f For more information on the flash memory map storage, refer to the Transceiver Signal

Integrity Development Kit, Stratix V GX Edition User Guide.

Flash Programming

Flash programming is possible through a variety of methods using the Stratix V GX device.

The first method is to use the factory design called the Board Update Portal. This design is an embedded webserver, which serves the Board Update Portal web page. The web page allows you to select new FPGA designs including hardware, software, or both in an industry-standard S-Record File (.flash) and write the design to the user hardware page (page 1) of the flash over the network.

The secondary method is to use the pre-built PFL design included in the development kit. The development board implements the Altera PFL megafunction for flash programming. The PFL megafunction is a block of logic that is programmed into an Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for writing to a compatible flash device. This pre-built design contains the PFL megafunction that allows you to write either page 0, page 1, or other areas of flash over the USB interface using the Quartus II software. This method is used to restore the development board to its factory default settings.

Other methods to program the flash can be used as well, including the Nios processor.

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–17

Stratix V GX FPGA

External USB-Blaster Header

Remove jumper to exclude

the MAX CPLD device

from the JTAG chain.

Jumper

Dual Analog Switch

TDI

TMS

TCK

LAST_TDO

S5GX_TDI

S5GX_TDO

JTAG_TMS

JTAG_TCK

MAX CPLD

TDI

TDO

TMS

TCK

IO_TDI

IO_TDO

IO_TMS

IO_TCK

MAX_OEn

JTAG_TMS

JTAG_TCK

MAX_FPP_TDI

MAX_FPP_TDO

MAX II and Flash FPP

JTAG

Header

USB Interface

Configuration, Status, and Setup Elements

f For more information on the Nios II processor, refer to the Nios II Processor page of

the Altera website.

FPGA Programming over External USB-Blaster

The JTAG header provides another method for configuring the FPGA (U29) using an external USB-Blaster device with the Quartus II Programmer running on a PC. The external USB-Blaster is connected to the board through the JTAG header (J93). The JTAG DIP switch (S7) allows the MAX II CPLD device to be removed from the JTAG chain so that the FPGA is the only device on the JTAG chain.

JTAG Header

The JTAG header provides another method for configuring the FPGA using an Altera USB-Blaster dongle with the Quartus II Programmer running on a PC. Figure 2–5 shows the schematic connections for the dedicated JTAG programming header (J93). The program MSEL switch (S7) allows the MAX II CPLD device to be removed from the JTAG chain so that the FPGA is the only device on the JTAG chain.

Figure 2–5. JTAG Header

The MAX II CPLD System Controller must be in the chain to use some of the GUI interfaces. For this setting, set pins 6-7 of the program MSEL switch (S7) to 1.

f For more information on the following topics, refer to the respective documents:

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

■ Board Update Portal and PFL Design, refer to the Transceiver Signal Integrity

Development Kit, Stratix V GX Edition User Guide.

■ PFL megafunction, refer to AN 386: Using the Parallel Flash Loader with the Quartus

II Software.

Stratix V GX Edition Reference Manual

2–18 Chapter 2: Board Components

Configuration, Status, and Setup Elements

Status Elements

The development board includes board-specific status LEDs and switches for enabling and configuring various features on the board, as well as a 16 character × 2 line LCD for displaying board power and temperature measurements. This section describes these status elements.

Status LEDs

Surface mount LEDs indicate the various status of the board. A logic 0 is driven on the I/O port to turn the LED on while a logic 1 is driven to turn the LED off.

Tab le 2– 8 lists the LED board references, names, and functional descriptions.

Table 2–8. Board-Specific LEDs

Board

Reference

D3 POWER — Blue LED. Illuminates when 5-V power is active.

D7 FAN

D8 USB

D9 ERROR

D10 FACTORY

D11 USER

D12 TX

D13 RX

D14 DUPLEX

D15 1000

D16 100

D17 10

LED Name

Schematic Signal

Name

FAN_LED

USB_LED

CONFIG_ERR

FACTORY_IMAGE

USER_IMAGE

ENET_LED_TX

ENET_LED_RX

ENET_LED_DUPLEX

ENET_LED_LINK1000

ENET_LED_LINK100

ENET_LED_LINK10

Description

Amber LED. Illuminates when an over-temperature condition occurs. This occurrence should automatically turn on the fan.

Green LED. Illuminates when the MAX II CPLD System Controller is actively configuring the FPGA using the embedded USB-Blaster.

Red LED. Illuminates when the MAX II CPLD System Controller fails to configure the FPGA. Driven by the MAX II CPLD System Controller.

Green LED. Illuminates when the factory image is successfully loaded into the FPGA. Driven by the MAX II CPLD System Controller.

Green LED. Illuminates when the user image is successfully loaded into the FPGA. Driven by the MAX II CPLD System Controller.

Green LED. Blinks to indicate Ethernet PHY transmit activity. Driven by the Marvell 88E1111 PHY.

Green LED. Blinks to indicate Ethernet PHY receive activity. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet full duplex status.

Green LED. Illuminates to indicate Ethernet linked at 1000 Mbps connection speed. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet linked at 100 Mbps connection speed Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet linked at 10 Mbps connection speed Driven by the Marvell 88E1111 PHY.

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–19

Configuration, Status, and Setup Elements

Tab le 2– 9 lists the board-specific LEDs component references and manufacturing

information.

Table 2–9. Board-Specific LEDs Component References and Manufacturing Information

Board Reference Description Manufacturer

Manufacturer

Part Number

Manufacturer

Website

D8, D10-D17 Green LEDs Lumex Inc. SML-LX1206GC-TR www.lumex.com

D9 Red LED Lumex Inc. SML-LX1206IC-TR www.lumex.com

D3 Blue LED Lumex Inc. SML-LX1206USBC-TR www.lumex.com

D7 Amber LED Lite-On LTST-C150KYKT www.lite-on.com

Setup Elements

The development board includes several different kinds of setup elements. This section describes the following setup elements:

■ FPP configuration/MAX II bypass DIP switch

■ Program select jumper

■ MAX II reset push button

■ CPU reset push button

FPP Configuration/MAX II Bypass DIP Switch

The FPP configuration/MAX II bypass DIP switch (S7) controls the FPP configuration mode and also selects the MAX II CPLD to be in the JTAG chain.

Tab le 2– 10 lists the switch settings and descriptions.

Table 2–10. FPP Configuration/MAX II Bypass DIP Switch Settings

Board

Reference (S7)

1–12

2–11

3–10

4–9

5–8

6–7

Schematic Signal

Name

MSEL0

MSEL1

MSEL2

MSEL3

MSEL4

MAX_BYPASS

ON : Logic 0 is selected for MSEL0

OFF : Logic 1 is selected for MSEL0

ON : Logic 0 is selected for MSEL1

OFF : Logic 1 is selected for MSEL1

ON : Logic 0 is selected for MSEL2

OFF : Logic 1 is selected for MSEL2

ON : Logic 0 is selected for MSEL3

OFF : Logic 1 is selected for MSEL3

ON : Logic 0 is selected for MSEL4

OFF : Logic 1 is selected for MSEL4

ON : MAX II CPLD EPM2210 System Controller in-chain

OFF : Bypass MAX II CPLD EPM2210 System Controller

Description Default

OFF

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

2–20 Chapter 2: Board Components

Configuration, Status, and Setup Elements

Tab le 2– 11 lists the DIP switch component reference and manufacturing information.

Table 2–11. FPP Configuration/MAX II Bypass DIP Switch Component Reference and Manufacturing Information

Board Reference Description Manufacturer

S7 Six-Position slide DIP switch Grayhill 97C06RT www.grayhill.com

Manufacturer

Part Number

Manufacturer Website

Program Select Jumper

The program select jumper, Controller. After a power-on or reset configuration, the MAX II CPLD System Controller configures the FPGA to either factory or user image. For information on the jumper settings, refer to “FPGA Programming from Flash Memory” on page 2–15.

PGMSEL

, (J28) is an input to the MAX II CPLD System

Reset Push Button

The reset push button, push button is the default logic reset for the CPLD logic.

Tab le 2– 12 lists the MAX II reset push button component reference and manufacturing

information.

Table 2–12. MAX II Reset Push Button Component Reference and Manufacturing Information

Board Reference Description Manufacturer

S5 Push Button Panasonic Corporation EVQPAC07K www.panasonic.com

RESETn

, is an input to the MAX II CPLD System Controller. This

Manufacturer

Part Number

Manufacturer

Website

CPU Reset Push Button

The CPU reset push button, FPGA and serves as a reset for the NIOS II when you load the application.

Tab le 2– 13 lists the CPU reset configuration push button component reference and

manufacturing information.

Table 2–13. CPU Reset Configuration Push Button Component Reference and Manufacturing Information

Board Reference Description Manufacturer

S6 Push Button Panasonic Corporation EVQPAC07K www.panasonic.com

CPURSTn

, (S6) is connected to a regular I/O pin of the

Manufacturer

Part Number

Manufacturer

Website

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–21

6-12.5G

Channels

Clock Buffer

6-12.5G

Channels

6-12.5G

Channels

6-12.5G

Channels

2-12.5G

Channels

1-28G

Channel

2-12.5G

Channels

1-28G

Channel

2-12.5G

Channels

1-28G

Channel

2-12.5G

Channels

1-28G

Channel

644.53125 MHz

Trigger

Clock Buffer

706.25 MHz

Trigger

Clock Buffer

625 MHz

Trigger

SMA

REFCLK

Stratix V GX

REFCLK

Clock

Buffer

875 MHz

SMA

Clock Circuitry

This section describes the board's dedicated and general purpose clocks.

Dedicated Transceiver Clocks

Four differential clock sources are provided from the I2C programmable VCO oscillators to the dedicated REFCLK input pins of transceiver blocks on both sides of the FPGA. The default frequencies for these four oscillators at startup are 625 MHz,

644.53125 MHz, 706.25 MHz, and 875 MHz. The default frequencies can be overridden and a different frequency can be programmed into the oscillators to support other protocols. Each oscillator supports a programmable frequency range of 10 MHz–1.4 GHz and provide a trigger output to an SMA connector for scope or other lab equipment triggering purposes.

Figure 2–6 shows the default frequencies of all external clocks going to the Stratix V

GX transceiver signal integrity development board.

Figure 2–6. Transceiver Signal Integrity Development Kit Dedicated Transceiver Clocks

Tab le 2– 14 lists the frequency of these oscillators and the application it supports.

Table 2–14. Transceiver On-Board Oscillators

644.53125 MHz LVDS IDT5T9306

625 MHz LVDS IDT5T9306

Frequency I/O Standard Clock Buffer

706.25 MHz LVDS IDT5T9306

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

875 MHz LVDS IDT5T9306

Stratix V GX Edition Reference Manual

2–22 Chapter 2: Board Components

ICS8304

CLKBUF

MAX II CPLD

(U19)

CLKIN SMA

(J70/J71)

Trigger SMA

ICS557

25/100/125/

200-MHz

Spread Spectrum CLKBUF

Stratix V GX

FPGA

(U29)

50 MHz

25 MHz

XTAL

Clock Circuitry

In addition to the four oscillators, each side has a dedicated differential from a pair of SMA connectors to allow an external clock source.

General-Purpose Clocks

Three general-purpose clocks are provided to the FPGA global clock inputs for general FPGA design. The clocks consist of the following components:

■ A 50-MHz oscillator through an ICS8304 buffer for NIOS II applications at clock

input

CLK2p

. This clock also routes to the MAX II device for FPP configuration and

to the clock inputs

■ A 25-MHz crystal oscillator through an ICS557-03 spread spectrum differential

clock buffer. The available frequencies and down spread percentages available from the spread spectrum buffer is shown in Table 2–15.

■ An external differential clock source from SMA at

Figure 2–7 shows the general purpose clocks going in to the Stratix V GX transceiver

signal integrity development board.

Figure 2–7. Transceiver Signal Integrity Development Kit General Purpose Clocks

CLK12p

and

CLK16p

of banks 7 and 8.

CLK10p/n

(J70/J71).

REFCLK

input

Tab le 2– 15 lists the spread spectrum clock settings and frequencies.

Table 2–15. Spread Spectrum Clock Settings and Frequencies

Spread Spectrum Buffer (inputs)

Output Clock Select Spread (%)

SS1/S1 SS0/S0

0 0 25 MHz (default) Center ±0.25

0 1 100 MHz Down –0.5

1 0 125 MHz Down –0.75

1 1 200 MHz No spraed

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–23

Transceiver Channels

Embedded USB-Blaster Clocks

A separate 6-MHz crystal and 24-MHz oscillator are dedicated for the embedded USB-Blaster circuitry. The 6-MHz crystal is used to clock the FTDI FT245 USB PHY device while the 24-MHz oscillator is used to clock the MAX II CPLD device. Refer to

“FPGA Programming over Embedded USB-Blaster” on page 2–14 for the embedded

USB-Blaster implementation.

Tab le 2– 16 lists the crystal oscillators component references and manufacturing

information.

Table 2–16. Crystal Oscillator Component References and Manufacturing Information

Board

Reference

X1 Crystal oscillator, 6.0 MHz, SMD ESC Inc. ECSX-60-32-5P-TR www.ecsxtal.com

Crystal oscillator, CMOS, 2.5 V,

24.000 MHz, SMT, ±50ppm

Description Manufacturer

Epson

Manufacturer

Part Number

SG-310SDF 24.0000M-B3www.epsontoyocom.co.jp/

Manufacturer Website

english/index.html

Transceiver Channels

The transceiver signal integrity development board dedicates 31 (out of 32) 12.5-Gbps transceiver channels from both the left and right sides of the device to various backplane connectors—SFP+ and XFP cages, and SMA connectors. One 12.5-Gbps channel on the 28 Gbps side of the device is a dedicated CMUclk input from SMA connectors.

1 For the Stratix V GT device migration support, the four 28-Gbps ATT channels

connects to the MMPX connectors.

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

2–24 Chapter 2: Board Components

Six 12.5G

Channels

Two 12.5G

Channels

One 28G

Channel

Six 12.5G

Channels

Two 12.5G

Channels

One 28G

Channel

Six 12.5G

Channels

Two 12.5G

Channels

One 28G

Channel

Six 12.5G

Channels

Two 12.5G

Channels

One 28G

Channel

Tyco BP

Connector

Molex

Connector

XFP Cage

Amphenol Connector

SFP+ Cage

5-TX/RX

Stratix V GX

2-TX/RX (12.5G)

6-TX/RX

7-TX/RX

Channels

28 SMA

Connectors

TX/RX

MMPX

1 CMURX Clock from SMA

TX/RX

5-TX/RX

TX/RX (28G)

Transceiver Channels

Figure 2–8 shows the complete transceiver usage diagram.

Figure 2–8. Transceiver Signal Integrity Development Kit Dedicated Transceiver Channels

Tab le 2– 17 lists the connection requirements for the transceiver channels.

Table 2–17. Transceiver Signal Integrity Development Kit Transceiver Channels (Part 1 of 2)

Signal Group Note

5-12.5-Gbps TX to Tyco backplane connector (left side of transceiver block) Length matched between this TX group

5-12.5-Gbps RX to Tyco backplane connector (left side of transceiver block) Length matched between this RX group

2-12.5-Gbps TX to Tyco backplane connector (right side of transceiver block) Length matched between this TX pair

2-12.5-Gbps RX to Tyco backplane connector (right side of transceiver block) Length matched between this RX pair

5-12.5-Gbps TX to Amphenol/FCI backplane connector (left side of transceiver block)

5-12.5-Gbps RX to Amphenol/FCI backplane connector (left side of transceiver block)

2-12.5-Gbps TX to Amphenol/FCI backplane connector (right side of transceiver block)

2-12.5-Gbps RX to Amphenol/FCI backplane connector (right side of transceiver block)

5-12.5-Gbps TX to Molex connector (left side of transceiver block) Length matched between this TX group

5-12.5-Gbps RX to Molex connector (left side of transceiver block) Length matched between this RX group

7-12.5-Gbps TX to SMAs (left side of transceiver block) Length match between this TX group

Length matched between this TX group

Length matched between this RX group

Length matched between this TX pair

Length matched between this RX pair

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–25

SMA Connectors

Table 2–17. Transceiver Signal Integrity Development Kit Transceiver Channels (Part 2 of 2)

Signal Group Note

7-12.5-Gbps RX to SMAs—can be used as CMUclk inputs (left side of transceiver block)

4-28-Gbps TX to MMPX connector (right side of transceiver block) Length match between this TX group

4-28-Gbps RX to MMPX connector (right side of transceiver block) Length match between this RX group

1-12.5-Gbps TX/RX to SFP+ cage (left side of transceiver block) No matching between TX/RX pairs

1-12.5-Gbps TX/RX to XFP cage (left side of transceiver block) No matching between TX/RX pairs

1-12.5-Gbps RX channel used as CMUclk input from SMA (right side of transceiver block)

Length match between this RX group

Match P/N of RX input

SMA Connectors

The development board includes seven transceiver-channel pairs for the SMA connectors.

Tab le 2– 18 lists the SMA connectors pin assignments, signal names, and functions.

Table 2–18. SMA Connectors Pin Assignments, Signal Names, and Functions

Board

Reference

J35

J38

J40

J45

J47

J52

J54

J56

J58

J60

J62

J64

J66

J68

J36

J39

J41

J46

J48

J53

J55

J57

J59

Schematic Signal Name I/O Standard

GXB_RXLp_11

GXB_RXLn_11

GXB_RXLp_12

GXB_RXLn_12

GXB_RXLp_13

GXB_RXLn_13

GXB_RXLp_14

GXB_RXLn_14

GXB_RXLp_15

GXB_RXLn_15

GXB_RXLp_16

GXB_RXLn_16

GXB_RXLp_17

GXB_RXLn_17

GXB_TXLp_11

GXB_TXLn_11

GXB_TXLp_12

GXB_TXLn_12

GXB_TXLp_13

GXB_TXLn_13

GXB_TXLp_14

GXB_TXLn_14

GXB_TXLp_15

1.4-V PCML AA36 GXB receive

1.4-V PCML AA37 GXB receive

1.4-V PCML Y38 GXB receive

1.4-V PCML Y39 GXB receive

1.4-V PCML V38 GXB receive

1.4-V PCML V39 GXB receive

1.4-V PCML U36 GXB receive

1.4-V PCML U37 GXB receive

1.4-V PCML T38 GXB receive

1.4-V PCML T39 GXB receive

1.4-V PCML P38 GXB receive

1.4-V PCML P39 GXB receive

1.4-V PCML M38 GXB receive

1.4-V PCML M39 GXB receive

1.4-V PCML Y34 GXB transmit

1.4-V PCML Y35 GXB transmit

1.4-V PCML W36 GXB transmit

1.4-V PCML W37 GXB transmit

1.4-V PCML V34 GXB transmit

1.4-V PCML V35 GXB transmit

1.4-V PCML T34 GXB transmit

1.4-V PCML T35 GXB transmit

1.4-V PCML R36 GXB transmit

Stratix V GX Device

Pin Number

Description

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

2–26 Chapter 2: Board Components

Backplane Connectors

Table 2–18. SMA Connectors Pin Assignments, Signal Names, and Functions

Board

Reference

J61

J63

J65

J67

J69

Schematic Signal Name I/O Standard

GXB_TXLn_15

GXB_TXLp_16

GXB_TXLn_16

GXB_TXLp_17

GXB_TXLn_17

1.4-V PCML R37 GXB transmit

1.4-V PCML P34 GXB transmit

1.4-V PCML P35 GXB transmit

1.4-V PCML N36 GXB transmit

1.4-V PCML N37 GXB transmit

Stratix V GX Device

Pin Number

Description

Backplane Connectors

The development board supports three different types of 10Gbase-KR reference backplanes by directly mating with backplanes made from Tyco, Amphenol, and Molex manufacturers.

1 The Tyco Strada Whisper connector is currently not installed on this board. The part

number for this connector is listed at the end of this section.

Tab le 2– 19 lists the Amphenol backplane connector pin assignments.

Table 2–19. Amphenol Backplane Connector Pin Assignments, Signal Names and Functions (Part 1 of 2)

Board

Reference

(J32)

Schematic Signal Name I/O Standard

GXB_TXLN_19

GXB_TXLP_19

GXB_TXLN_20

GXB_TXLP_20

GXB_TXLN_21

GXB_TXLP_21

GXB_TXLN_22

GXB_TXLP_22

GXB_TXLN_23

GXB_TXLP_23

GXB_TXRN_18

GXB_TXRP_18

GXB_TXRN_23

GXB_TXRP_23

GXB_RXLN_19

GXB_RXLP_19

GXB_RXLN_20

GXB_RXLP_20

GXB_RXLN_21

GXB_RXLP_21

1.4-V PCML K35 GXB transmit

1.4-V PCML K34 GXB transmit

1.4-V PCML J37 GXB transmit

1.4-V PCML J36 GXB transmit

1.4-V PCML G37 GXB transmit

1.4-V PCML G36 GXB transmit

1.4-V PCML E37 GXB transmit

1.4-V PCML E36 GXB transmit

1.4-V PCML C37 GXB transmit

1.4-V PCML C36 GXB transmit

1.4-V PCML M5 GXB transmit

1.4-V PCML M6 GXB transmit

1.4-V PCML C3 GXB transmit

1.4-V PCML C4 GXB transmit

1.4-V PCML K39 GXB receive

1.4-V PCML K38 GXB receive

1.4-V PCML H39 GXB receive

1.4-V PCML H38 GXB receive

1.4-V PCML F39 GXB receive

1.4-V PCML F38 GXB receive

Stratix V GX Device

Pin Number

Description

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–27

Backplane Connectors

Table 2–19. Amphenol Backplane Connector Pin Assignments, Signal Names and Functions (Part 2 of 2)

Board

Reference

(J32)

Schematic Signal Name I/O Standard

GXB_RXLN_22

GXB_RXLP_22

GXB_RXLN_23

GXB_RXLP_23

GXB_RXRN_18

GXB_RXRP_18

GXB_RXRN_23

GXB_RXRP_23

1.4-V PCML D39 GXB receive

1.4-V PCML D38 GXB receive

1.4-V PCML B39 GXB receive

1.4-V PCML B38 GXB receive

1.4-V PCML L3 GXB receive

1.4-V PCML L4 GXB receive

1.4-V PCML B1 GXB receive

1.4-V PCML B2 GXB receive

Stratix V GX Device

Pin Number

Description

Tab le 2– 20 lists the Tyco backplane connector pin assignments.

Table 2–20. Tyco Backplane Connector Pin Assignments, Signal Names and Functions (Part 1 of 2)

Board

Reference

(J33)

F11

G11

H11

F14

G14

F12

G12

H12

F15

G15

F18

G18

F17

G17

Schematic Signal Name I/O Standard

GXB_TXLN_0

GXB_TXLN_1

GXB_TXLN_2

GXB_TXLN_3

GXB_TXLN_4

GXB_TXLP_0

GXB_TXLP_1

GXB_TXLP_2

GXB_TXLP_3

GXB_TXLP_4

GXB_TXRN_0

GXB_TXRN_5

GXB_TXRP_0

GXB_TXRP_5

GXB_RXLN_0

GXB_RXLN_1

GXB_RXLN_2

GXB_RXLN_3

GXB_RXLN_4

GXB_RXLP_0

GXB_RXLP_1

GXB_RXLP_2

GXB_RXLP_3

GXB_RXLP_4

1.4-V PCML AU37 GXB transmit

1.4-V PCML AR37 GXB transmit

1.4-V PCML AN37 GXB transmit

1.4-V PCML AL37 GXB transmit

1.4-V PCML AK35 GXB transmit

1.4-V PCML AU36 GXB transmit

1.4-V PCML AR36 GXB transmit

1.4-V PCML AN36 GXB transmit

1.4-V PCML AL36 GXB transmit

1.4-V PCML AK34 GXB transmit

1.4-V PCML AU3 GXB transmit

1.4-V PCML AH5 GXB transmit

1.4-V PCML AU4 GXB transmit

1.4-V PCML AH6 GXB transmit

1.4-V PCML AV39 GXB receive

1.4-V PCML AT39 GXB receive

1.4-V PCML AP39 GXB receive

1.4-V PCML AM39 GXB receive

1.4-V PCML AJ37 GXB receive

1.4-V PCML AV38 GXB receive

1.4-V PCML AT38 GXB receive

1.4-V PCML AP38 GXB receive

1.4-V PCML AM38 GXB receive

1.4-V PCML AJ36 GXB receive

Stratix V GX Device

Pin Number

Description

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

2–28 Chapter 2: Board Components

Backplane Connectors

Table 2–20. Tyco Backplane Connector Pin Assignments, Signal Names and Functions (Part 2 of 2)

Board

Reference

(J33)

Schematic Signal Name I/O Standard

GXB_RXRN_0

GXB_RXRN_5

GXB_RXRP_0

GXB_RXRP_5

1.4-V PCML AV1 GXB receive

1.4-V PCML AJ3 GXB receive

1.4-V PCML AV2 GXB receive

1.4-V PCML AJ4 GXB receive

Stratix V GX Device

Pin Number

Tab le 2– 21 lists the Molex backplane connector pin assignments.

Table 2–21. Molex Backplane Connector Pin Assignments, Signal Names and Functions

Board

Reference

(J34)

H10

E10

G10

D10

Schematic Signal Name I/O Standard

GXB_TXLN_6

GXB_TXLN_7

GXB_TXLN_8

GXB_TXLN_9

GXB_TXLN_10

GXB_TXLP_6

GXB_TXLP_7

GXB_TXLP_8

GXB_TXLP_9

GXB_TXLP_10

GXB_RXLN_6

GXB_RXLN_7

GXB_RXLN_8

GXB_RXLN_9

GXB_RXLN_10

GXB_RXLP_6

GXB_RXLP_7

GXB_RXLP_8

GXB_RXLP_9

GXB_RXLP_10

1.4-V PCML AG37 GXB transmit

1.4-V PCML AF35 GXB transmit

1.4-V PCML AD35 GXB transmit

1.4-V PCML AC37 GXB transmit

1.4-V PCML AB35 GXB transmit

1.4-V PCML AG36 GXB transmit

1.4-V PCML AF34 GXB transmit

1.4-V PCML AD34 GXB transmit

1.4-V PCML AC36 GXB transmit

1.4-V PCML AB34 GXB transmit

1.4-V PCML AH39 GXB receive

1.4-V PCML AE37 GXB receive

1.4-V PCML AF39 GXB receive

1.4-V PCML AD39 GXB receive

1.4-V PCML AB39 GXB receive

1.4-V PCML AH38 GXB receive

1.4-V PCML AE36 GXB receive

1.4-V PCML AF38 GXB receive

1.4-V PCML AD38 GXB receive

1.4-V PCML AB38 GXB receive

Stratix V GX Device

Pin Number

Description

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–29

General User Input/Output

Tab le 2– 22 lists the backplane connector component reference and the manufacturing

information.

Table 2–22. Backplane Connector Component Reference and Manufacturing Information

Board

Reference

J32

J33

J34 Connector, 4-pair, receptacle, Molex Impact Molex 76160-5020 www.molex.com

Connector, 4-pair, 6 position, Amphenol Xcede

Connector, 8-pair, 6-columns, receptacle, Tyco Str ada

Description Manufacturer

Amphenol AX400-00682 www.amphenol.com

Tyco Electronics 2149323-1 www.te.com

Manufacturer

Part Number

General User Input/Output

This section describes the user I/O interface to the FPGA. This section describes the following I/O elements:

■ User-defined push buttons

■ User-defined DIP switch

■ User-defined LEDs

■ Character LCD

User-Defined Push Buttons

The development board includes four user-defined push buttons which allow you to interact with the Stratix V GX device. When the push button is pressed and held down, the device pin is set to logic 0; when the push button is released, the device pin is set to logic 1. There is no board-specific function for these general user push buttons.

Manufacturer

Website

Tab le 2– 23 lists the user-defined push button schematic signal names and their

corresponding Stratix V GX device pin numbers.

Table 2–23. User-Defined Push Button Schematic Signal Names and Functions

Board Reference

Schematic Signal

Name

USER_PB0

USER_PB1

USER_PB2

USER_PB3

I/O Standard

2.5-V H29 Push button

2.5-V G28 Push button

2.5-V K27 Push button

2.5-V J27 Push button

Stratix V GX Device

Pin Number

Description

Tab le 2– 24 lists the user-defined push button component reference and the

manufacturing information.

Table 2–24. User-Defined Push Button Component Reference and Manufacturing Information

Board Reference Description Manufacturer

S1-S4 Push button Panasonic Corporation EVQPAC07K www.panasonic.com

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Manufacturer

Part Number

Stratix V GX Edition Reference Manual

Manufacturer

Website

2–30 Chapter 2: Board Components

General User Input/Output

User-Defined DIP Switch

Board reference SW4 is a 8-pin DIP switch. The switches are user-defined, and are provided for additional FPGA input control. There is no board-specific function for these switches.

Tab le 2– 25 lists the user-defined DIP switch schematic signal names and their

corresponding Stratix V GX pin numbers.

Table 2–25. User-Defined DIP Switch Schematic Signal Names and Functions

Board Reference

(SW4)

Schematic

Signal Name

S5_UNLOCK

USER_DIP6

USER_DIP5

USER_DIP4

USER_DIP3

USER_DIP2

USER_DIP1

USER_DIP0

I/O Standard

2.5-V

2.5-V H34

2.5-V F33

2.5-V G33

2.5-V H32

2.5-V D34

2.5-V E34

2.5-V D33

Stratix V GX Device

(Connected to USB MAX II pin B6)

Pin Number

—

User-defined DIP switch connected to FPGA device. When the switch is in the OPEN or ON position, a logic 1 is selected. When the switch is in the CLOSED or OFF position, a logic 0 is selected.

Tab le 2– 26 lists the user-defined DIP switch component reference and the

manufacturing information.

Table 2–26. User-Defined DIP Switch Component Reference and Manufacturing Information

Board Reference Description Manufacturer

SW4 Eight-Position DIP switch Grayhill 76SB08ST www.grayhill.com

Manufacturer

Part Number

User-Defined LEDs

Description

Manufacturer Website

The development board includes eight user-defined LEDs. Board references D18 through D25 are user LEDs which allow status and debugging signals to be driven to the LEDs from the designs loaded into the Stratix V GX device. The LEDs illuminate when a logic 0 is driven, and turns off when a logic 1 is driven. There is no board-specific function for these LEDs.

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–31

General User Input/Output

Tab le 2– 27 lists the user-defined LED schematic signal names and their corresponding

Stratix V GX pin numbers.

Table 2–27. User-Defined LED Schematic Signal Names and Functions

Board Reference

D18

D19

D20

D21

D22

D23

D24

D25

Schematic

Signal Name

USER_LED_0

USER_LED_1

USER_LED_2

USER_LED_3

USER_LED_4

USER_LED_5

USER_LED_6

USER_LED_7

I/O Standard

2.5-V B32

2.5-V A32

2.5-V B34

2.5-V A34

2.5-V C34

2.5-V C33

2.5-V F32

2.5-V E32

Stratix V GX Device

Pin Number

Tab le 2– 28 lists the user-defined LED component reference and the manufacturing

information.

Table 2–28. User-Defined LED Component Reference and Manufacturing Information

Board Reference Device Description Manufacturer

D18-D25

Green LEDs, 1206, SMT, Clear Lens, 2.1 V

Lumex Inc. SML-LX1206GC-TR www.lumex.com

Manufacturer

Part Number

Character LCD

Description

User-defined LEDs. Driving a logic 0 on the I/O port turns the LED ON. Driving a logic 1 on the I/O port turns the LED OFF.

Manufacturer

Website

The development board contains a single 14-pin 0.1" pitch dual-row header that interfaces to a 16 character × 2 line Lumex LCD display. The LCD has a 14-pin receptacle that mounts directly to the board's 14-pin header, so it can be easily removed for access to components under the display. You can also use the header for debugging or other purposes.

Tab le 2– 29 summarizes the LCD pin assignments. The signal names and directions are

relative to the Stratix V GX device.

Table 2–29. LCD Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)

Board Reference

(J30)

Schematic Signal

Name

LCD_D_Cn

LCD_Wen

LCD_EN

LCD_DATA0

LCD_DATA1

LCD_DATA2

LCD_DATA3

LCD_DATA4

LCD_DATA5

I/O Standard

2.5-V B14 LCD data or command select

2.5-V B13 LCD write enable

2.5-V A14 LCD chip select

2.5-V A13 LCD data bus

2.5-V B16 LCD data bus

2.5-V A16 LCD data bus

2.5-V C15 LCD data bus

2.5-V C14 LCD data bus

2.5-V D15 LCD data bus

Stratix V GX Device

Pin Number

Description

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

2–32 Chapter 2: Board Components

General User Input/Output

Table 2–29. LCD Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)

Board Reference

(J30)

f For more information such as timing, character maps, interface guidelines, and other

Schematic Signal

Name

LCD_DATA6

LCD_DATA7

I/O Standard

2.5-V D16 LCD data bus

2.5-V F14 LCD data bus

Stratix V GX Device

Pin Number

Description

Tab le 2– 30 shows the LCD pin definitions, and is an excerpt from the Lumex data

sheet.

related documentation, visit www.lumex.com.

Table 2–30. LCD Pin Definitions and Functions

Number

Symbol

Level

—

—GND (0 V)

Power supply

Function

5 V

— For LCD drive

4RS H/L

H: Data input

L: Instruction input

5R/W H/L

H: Data read (module to MPU)

L: Data write (MPU to module)

6 E H, H to L Enable

7–14 DB0–DB7 H/L Data bus, software selectable 4-bit or 8-bit mode

Tab le 2– 31 lists the LCD component references and the manufacturing information.

Table 2–31. LCD Component References and Manufacturing Information

Board

Reference

Description Manufacturer

2×7 pin, 100 mil, vertical header Samtec TSM-107-01-G-DV www.samtec.com

J30

2×16 character display, 5×8 dot matrix

Lumex Inc. LCM-S01602DSR/C www.lumex.com

Manufacturer

Part Number

Manufacturer

Website

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–33

MAC

88E1111

Device

Transformer

RJ45

SGMII Interface

S_IN

S_OUT ±

CAT 5 UTP:

- 10BASE-T

- 100BASE-TX

- 1000BASE-T

Components and Interfaces

This section describes the development board's communication ports and interface cards relative to the Stratix V GX device. The development board supports the following components and interfaces:

■ 10/100/1000 Ethernet

■ Transceiver interfaces

■ XFP interface

■ SFP+ interface

10/100/1000 Ethernet

The development board supports a 10/100/1000 BASE-T Ethernet connection using a Marvell 88E1111 PHY device and the Altera Triple-Speed Ethernet MegaCore MAC function. The device is an auto-negotiating Ethernet PHY with an SGMII interface to the FPGA. The Stratix V GX device can communicate with the LVDS interfaces at up to 1.25 Gbps. The MAC function must be provided in the FPGA for typical networking applications. The Marvell 88E1111 PHY uses 2.5-V and 1.2-V power rails and requires a 25-MHz reference clock driven from a dedicated oscillator. It interfaces to an RJ-45 with internal magnetics that can be used for driving copper lines with Ethernet traffic.

Figure 2–9 shows the SGMII interface between the FPGA (MAC) and Marvell 88E1111

PHY.

Figure 2–9. SGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY

Tab le 2– 32 lists the Ethernet PHY interface pin assignments.

Table 2–32. Ethernet PHY Pin Assignments, Signal Names and Functions

Board

Reference

Schematic Signal Name I/O Standard

(U22)

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

ENET_INTN

ENET_LED_DUPLEX

ENET_LED_LINK10

ENET_LED_LINK100

2.5-V AL14 Management bus Interrupt

2.5-V — Duplex LED

2.5-V — 10-Mb link LED

2.5-V — 100-Mb link LED

Stratix V GX Device

Pin Number

Description

Stratix V GX Edition Reference Manual

2–34 Chapter 2: Board Components

Components and Interfaces

Table 2–32. Ethernet PHY Pin Assignments, Signal Names and Functions

Board

Reference

(U22)

Schematic Signal Name I/O Standard

ENET_LED_LINK1000

ENET_LED_RX

ENET_LED_TX

ENET_RSTN

ENET_SGMII_RX_N

ENET_SGMII_RX_P

ENET_SGMII_TX_N

ENET_SGMII_TX_P

ENET_XTAL_25MHZ

GTXCLK

MDC

MDI_N0

MDI_N1

MDI_N2

MDI_N3

MDI_P0

MDI_P1

MDI_P2

MDI_P3

MDIO

RXCLK

RXD0

RXD1

RXD2

RXD3

RXDV

TXD0

TXD1

TXD2

TXD3

TXEN

2.5-V — 1000-Mb link LED

2.5-V — RX data active LED

2.5-V — TX data active LED

2.5-V AT6 Device reset

2.5-V AJ15 SGMII receive

2.5-V AH15 SGMII receive

2.5-V AL15 SGMII transmit

2.5-V AK15 SGMII transmit

2.5-V — 25-MHz clock

2.5-V AE15 Ethernet transmit clock

2.5-V AB16 Management bus data clock

2.5-V — Management bus data

2.5-V AC16 Management bus data input/output

2.5-V AH16 SGMII receive clock

2.5-V AG17 SGMII receive data

2.5-V AD15 SGMII receive data

2.5-V AE16 SGMII receive data

2.5-V AB15 SGMII receive data

2.5-V AF17 SGMII receive data valid

2.5-V AK17 SGMII transmit data

2.5-V AL17 SGMII transmit data

2.5-V AJ16 SGMII transmit data

2.5-V AJ17 SGMII transmit data

2.5-V AF16 SGMII transmit enable

Stratix V GX Device

Pin Number

Description

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–35

Components and Interfaces

Tab le 2– 33 lists the Ethernet PHY interface component reference and manufacturing

information.

Table 2–33. Ethernet PHY Component Reference and Manufacturing Information

Board Reference Description Manufacturer

U22 Ethernet PHY BASE-T device

Marvel Semiconductor

Transceiver Interfaces

The transceiver signal integrity development board incorporates a XFP transceiver module, and a SFP+ transceiver module. Each module has a single duplex channel.

XFP Interface

Tab le 2– 34 lists the XFP connector cage interface pin assignments.

Table 2–34. XFP Interface Pin Assignments, Signal Names and Functions

Board Reference

(U25)

Schematic Signal

Name

GXB_TXLN_5

GXB_TXLP_5

GXB_RXLN_5

GXB_RXLP_5

REFCLK_XFPN

REFCLK_XFPP

XFP_MOD_DESEL

XFP_PDOWN_RST

XFP_T_INTERRUPT

XFP_T_MOD_ABS

XFP_T_SCL

XFP_T_SDA

XFP_TX_DIS

I/O Standard

1.4-V PCML AH35 GXB transmit

1.4-V PCML AH34 GXB transmit

1.4-V PCML AK39 GXB receive

1.4-V PCML AK38 GXB receive

1.8-V — XFP reference clock

1.8-V AV23 Module deselect

1.8-V AW23 Power down reset

1.8-V AV22 Interrupt

1.8-V AW26 Module absent

1.8-V AW25 Two-wire serial interface clock line

1.8-V AV25 Two-wire serial interface data line

1.8-V AW22 Disables transmitter output

Stratix V GX

Device Pin Number

Manufacturing

Part Number

88E1111-B2-CAAIC000 www.marvell.com

Manufacturer

Website

Description

Tab le 2– 35 lists the XFP interface component reference and manufacturing

information.

Table 2–35. XFP Interface Component Reference and Manufacturing Information

Board Reference Description Manufacturer

XFP 30-pin connector, 30UM gold plating, high speed

U25

XFP cage without light pipe, press fit

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Amphenol

Tyco

Amphenol

Tyco

Manufacturing

Part Number

1367500-1

1489951-1

Stratix V GX Edition Reference Manual

Manufacturer

Website

www.amphenol.com

www.te.com

2–36 Chapter 2: Board Components

Components and Interfaces

SFP+ Interface

Tab le 2– 32 lists the pin assignments for the SFP+ interface (SFPA) and their

corresponding schematic signal names and Stratix V GX pin numbers.

Table 2–36. SFP+ Interface Pin Assignments, Signal Names and Functions

Board Reference

(J51)

Schematic Signal Name I/O Standard

GXB_TXLN_18

GXB_TXLP_18

GXB_RXLN_18

GXB_RXLP_18

SFPA_LOS

SFPA_MOD0_PRSNTN

SFPA_MOD1_SCL

SFPA_MOD2_SDA

SFPA_RATESEL0

SFPA_RATESEL1

SFPA_TXDISABLE

SFPA_TXFAULT

1.8-V M35 GXB transmit

1.8-V M34 GXB transmit

1.8-V L37 GXB receive

1.8-V L36 GXB receive

1.8-V B28 Signal loss indicator

1.8-V B26 Module present indicator

1.8-V A26 Two-wire serial interface clock line

1.8-V B25 Two-wire serial interface data line

1.8-V C27

1.8-V C26

1.8-V A28

1.8-V A25 Transmitter fault

Stratix V GX

Device Pin Number

Description

Rate select 0. Controls the SFP+ interface receiver.

Rate select 1. Controls the SFP+ interface receiver.

Turns off and disables the transmitter output

Tab le 2– 35 lists the SFP+ interface component reference and manufacturing

information.

Table 2–37. SFP+ Interface Component Reference and Manufacturing Information

Board Reference Description Manufacturer

Manufacturing

Part Number

SFP+ connector - Mect family

J51

standard SFP right-angle 20-pin SMT

Samtec MECT-110-01-M-D-RA1 www.samtec.com

SFP+ cage Molex 74754-0101 www.molex.com

Manufacturer

Website

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–37

Flash Memory

The development board has a 1-GB CFI-compatible synchronous flash device for nonvolatile storage of FPGA configuration data, board information, test application data, and user code space. The FPGA and MAX II System Controller shares this device.

This 16-bit data memory interface can sustain burst read operations at up to 52 MHz for a throughput of 832 Mbps per device. The write performance is 270 µs for a single word and 310 µs for a 32-word buffer. The erase time is 800 ms for a 128 K parameter block.

Tab le 2– 38 lists the flash pin assignments, signal names, and functions. The signal

names and types are relative to the Stratix V GX device in terms of I/O setting and direction.

Table 2–38. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)

Board

Reference (U21)

Schematic Signal

Name

F_AD1

F_AD2

F_AD3

F_AD4

F_AD5

F_AD6

F_AD7

F_AD8

F_AD9

F_AD10

F_AD11

F_AD12

F_AD13

F_AD14

F_AD15

F_AD16

F_AD17

F_AD18

F_AD19

F_AD20

F_AD21

F_AD22

F_AD23

F_AD24

F_AD25

F_AD26

F_ADVN

F_BSYN

I/O Standard

1.8-V AE14 Address bus

1.8-V AD14 Address bus

1.8-V AC13 Address bus

1.8-V AC12 Address bus

1.8-V AG14 Address bus

1.8-V AF14 Address bus

1.8-V AD11 Address bus

1.8-V AC11 Address bus

1.8-V AF11 Address bus

1.8-V AE11 Address bus

1.8-V AE13 Address bus

1.8-V AE12 Address bus

1.8-V AJ14 Address bus

1.8-V AH13 Address bus

1.8-V AG13 Address bus

1.8-V AF13 Address bus

1.8-V AJ13 Address bus

1.8-V AJ12 Address bus

1.8-V AH12 Address bus

1.8-V AG11 Address bus

1.8-V AK12 Address bus

1.8-V AK11 Address bus

1.8-V AL12 Address bus

1.8-V AL11 Address bus

1.8-V AM13 Address bus

1.8-V AL13 Address bus

1.8-V AP7 Address valid

1.8-V AR7 Ready

Stratix V GX Device

Pin Number

Description

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

2–38 Chapter 2: Board Components

Flash Memory

Table 2–38. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)

Board

Reference (U21)

Schematic Signal

Name

F_CEN

F_CLK

F_D0

F_D1

F_D2

F_D3

F_D4

F_D5

F_D6

F_D7

F_D8

F_D9

F_D10

F_D11

F_D12

F_D13

F_D14

F_D15

F_OEN

F_RSTN

F_WEN

F_WPN

I/O Standard

Stratix V GX Device

Pin Number

1.8-V AP9 Chip enable

1.8-V AN6 Clock

1.8-V AN11 Data bus

1.8-V AM11 Data bus

1.8-V AP12 Data bus

1.8-V AN12 Data bus

1.8-V AN10 Data bus

1.8-V AM10 Data bus

1.8-V AR11 Data bus

1.8-V AR10 Data bus

1.8-V AT12 Data bus

1.8-V AU13 Data bus

1.8-V AU12 Data bus

1.8-V AU11 Data bus

1.8-V AT11 Data bus

1.8-V AW13 Data bus

1.8-V AV13 Data bus

1.8-V AW11 Data bus

1.8-V AN9 Output enable

1.8-V AL8 Reset

1.8-V AM8 Write enable

1.8-V AP6 Write protect

Description

Tab le 2– 39 lists the flash memory component reference and manufacturing

information.

Table 2–39. Flash Memory Component Reference and Manufacturing Information

Board Reference Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

U21 1-GB synchronous flash Micron PC28F00AP30BF www.micron.com

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–39

Power Supply

A laptop style DC power input provides power to the development board. The input voltage must be in the range of 14 V to 20 V. The DC voltage is then stepped down to the various power rails used by the components on the board.

An on-board multi-channel power monitor device (LTC2978) measures both the voltage and current for several specific board rails. This device has the capability to trim voltage outputs ±10%.

Tab le 2– 40 lists the power requirements for each major component on the board.

Table 2–40. Power Requirements

Device Voltage Name Voltage (V) Note

VCC

FPGA

MAX II (for FPP configuration)

Flash

MAX II (for USB-Blaster)

EEPROM

USB PHY

Power monitor

Temperature sense ADC

S5GX_VCC

2p5V

2p5V_FLTR

1p5V

VCCBAT

VCCR_GTB (28G channels)

VCCT_GTB (28G channels)

VCCL_GTB (28G channels)

VCCRT_GXB

VCCA_GXB

VCCH_GXB

2p5V

XFP_1p8V

2p5V

USBVCC

2p5V_USB

3p3V

0.9

2.5

1.5

1.5 BT1 socket

1.0 LDO

0.9 or 1.0 Low noise switcher

2.5 or 3.0 Low noise switcher

1.5

2.5 —

2.5 Core

1.8 I/O

2.5 Core or I/O

5.0 —

5.0 Core

2.5 I/O

5.0 —

3.3 —

VCCHIP

VCCHSSI

VCCIO

VCCPD

VCCREF

VCCPGM

VCCBAT

VCC_CLKIN

Ferrite fitered from VCCA_PLL, and VCCAUX

VCCPT

VCCH_GXB

VCCD_FPLL

1p5V

Tied to switcher)

(low noise

2p5V

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

2–40 Chapter 2: Board Components

Power Supply

Table 2–40. Power Requirements

Device Voltage Name Voltage (V) Note

ICS557-03 spread spectrum clock buffer (x1)

ICS8304 clock buffer

IDT5T9306 transceiver REFCLK clock buffers (x4)

T85A23157 dual analog switch

Character LCD

LEDs (x13)

Board power LED

3p3V

3p3V/2p5V

2p5V

3.3

3.3/2.5 50-MHz clock outputs

2.5 Programmable clock outputs

5.0 —

2.5 —

5.0 —

25-MHz clock output to the FPGA

Power Measurement

There are 6 voltage rails tied to two LTC2978 power monitor devices. These devices are capable of measuring the voltage and current for each voltage rail. The device can also provide power sequencing. A sense resistor at each voltage rail is in place for these measurements. These devices are also capable of trimming the output voltage ±10%. An I

C bus connects to the MAX II CPLD and FPGA devices for control.

Tab le 2– 41 lists the voltage rails. Each voltage is identified by its schematic net name.

Table 2–41. Voltage Rails

Schematic Net Name Voltage (V) Description

S5GX_VCC

VCCR_GTB

VCCT_GTB

VCCL_GTB

VCCRT_GXB

VCCA_GXB

VCCH_GXB

VCCD_FPLL

VCCPT

Note to Table 2–41:

(1) This value is based on a C1 or C2 speed grade. Voltage level for a C3 speed grade is 0.85 V.

(1)

0.9

VCC, VCCHIP, VCCHSSI FPGA core power.

1.0 Transceiver receiver power for 28G channels.

1.0 Transceiver transmit power for 28G channels.

1.0 Transceiver clocking power for 28G channels.

0.9 or 1.0 Shared VCCR_GXB and VCCT_GXB transceiver power for 12.5G channels.

2.5 or 3.0 Transceiver analog clock power

1.5 Transceiver TX buffer voltage

1.5 FPGA core D PPL voltage

1.5 FPGA programmable power technology

The LTC2978 power monitor devices installed on this board are programmed with a project file that sets up each voltage rail according to a sequence. Each voltage rail adjusts to its voltage level to within a certain tolerance. These two voltage rails can be adjusted through switch SW2.

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–41

Power Supply

Tab le 2– 42 lists the

VCCRT_GXB

and

VCCA_GXB

voltage rails and their voltage level

depending on the switch position.

Table 2–42. Voltage Level Setting

Switch (Position 1 and 2) Schematic Net Name Voltage (V)

Close (Default)

Open

VCCRT_GXB

VCCA_GXB

VCCRT_GXB

VCCA_GXB

1.0

3.0

0.9

2.5

1 If the board is powered off and powered on again with SW2 in the open position, the

voltages for

VCCRT_GXB

and

VCCA_GXB

voltage rails read 0.90 V and 2.5 V respectively and will not come up to the proper levels. This is due to the LTC2978 device trying to adjust these rails to their programed values, which it cannot due to the switch position of SW2. The work around to this issue is to set switch SW2 in the close position at power up.

Tab le 2– 43 lists the power monitor devices component reference and manufacturing

information.

Table 2–43. Power Measurement ADC Component References and Manufacturing Information

Board Reference Description Manufacturer

U10, U11

IC, power supply monitor w/EPROM, octal PMBUS

Linear Technology LTC2978CUP#PBF www.linear.com

Manufacturing

Part Number

Manufacturer

Website

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

2–42 Chapter 2: Board Components

Power Supply

Power Distribution System

Figure 2–10 shows the power distribution system on the development board. The

VCCR_GTB, VCCT_GTB

but are combined on the 12.5G transceivers.

Figure 2–10. Power Distribution System

14 V - 20 V

DC Input

, and

VCCL_GTB

power rails are separated on the 28G transceivers

LTC3855 Switching Regulator

LTC3855

Switching Regulator

0.90 V

2.5 V

5 V

LEGEND

Stratix V GX Power

VCC

VCCHIP

VCCHSSI

LTM4615

Dual Switcher

1 LDO (1.5 A)

LTM4608 Switcher

LCD, Fan

(4 A)

(8 A)

3.3 V

0.90 V / 1.0 V

2.5 V / 3.0 V

1.5 V

VCCIO

VCCPD

VCCPGM

VCCBAT

2.5 V Devices

3.3 V Devices

LTC3026

LDO (1.5 A)

LTC3026

LDO (1.5 A)

LTC3026

LDO (1.5 A)

LTC3026

LDO (1.5 A)

1.8 V

Bead

VCCA_PLL

VCCAUX

SFP+

XFP

VCCRT_GXB

VCCA_GXB

VCCH_GXB

VCCD_PLL

VCCPT

VCCR_GTB

VCCT_GXB

VCCL_GTB

Other Power

LTC3026

LDO (1.5 A)

Ethernet

Temperature Sense

The Stratix V GX die uses a MAX1619 temperature sense device for temperature monitoring. The device connects to the MAX II CPLD EPM2210 System Controller and the Stratix V GX device by a 2-wire SMB interface. The MAX1619 device is located at slave address 0011000b (18h).

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Chapter 2: Board Components 2–43

Statement of China-RoHS Compliance

The

OVERTEMPn

sense device based on a programmable threshold temperature. The

and

TSENSE_ALERTn

signals are driven by the MAX1619 temperature

OVERTEMPn

signal is driven to the MAX II System Controller. An over-temperature warning LED (D7) indicates the temperature fault condition.

Tab le 2– 44 lists the temperature sense interface pin assignments, signal names, and

functions.

Table 2–44. Temperature Sense Pin Assignments, Schematic Signal Names, and Functions

Board

Reference

(U12)

Schematic Signal

Name

SMBCLK_TEMP

SMBDATA_TEMP

ALERTn

OVERTEMPn

TEMPDIODE_P

TEMPDIODE_N

I/O

Standard

3.3-V

MAX II CPLD

System Controller

Pin Number

Stratix V GX

Device

Pin Number

D3 B8 SMB clock

C2 A8 SMB data

D2 E8 Programmable alert

E4 E7 Fan enable

—V11

— U11 Remote diode input

Tab le 2– 45 lists the temperature sense component reference and manufacturing

information.

Table 2–45. Temperature Sense Component Reference and Manufacturing Information

Board Reference Description Manufacturer

U12

Temperature sense, remote and local, programmable alert.

Maxim MAX1619MEE+T www.maxim-ic.com

Manufacturing

Part Number

Description

Current source and remote diode input

Manufacturer

Website

Statement of China-RoHS Compliance

Tab le 2– 46 lists hazardous substances included with the kit.

Table 2–46. Table of Hazardous Substances’ Name and Concentration Notes

Hexavalent

Chromium

(Cr6+)

Part Name

Stratix V GX transceiver signal integrity development board

Lead

(Pb)

Cadmium

(Cd)

X* 0 0 0 0 0

14 V power supply 0 0 0 0 0 0

Type A-B USB cable 0 0 0 0 0 0

User guide 0 0 0 0 0 0

Notes to Table 2–46:

(1) 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the

SJ/T11363-2006 standard.

(2) X* indicates that the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant

threshold of the SJ/T11363-2006 standard, but it is exempted by EU RoHS.

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

(1), (2)

Mercury

(Hg)

Polybrominated biphenyls (PBB)

Stratix V GX Edition Reference Manual

Polybrominated diphenyl Ethers

(PBDE)

2–44 Chapter 2: Board Components

Statement of China-RoHS Compliance

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

This appendix catalogs revisions to the Stratix V GX transceiver signal integrity development board.

Tab le A– 1 lists the versions of all releases of the Stratix V GX transceiver signal

integrity development board.

Table A–1. Transceiver Signal Integrity Development Kit Revision History

Version Release Date Description

■ New production device part number.

Production silicon July 2012

■ New voltage levels for production silicon.

■ Updated printed circuit board (PCB) for two revisions; rev-C, rev-D.

Engineering silicon September 2011 Initial release.

A. Board Revision History

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

A–2 Appendix A: Board Revision History

Engineering Silicon Version Differences

The engineering silicon version of the Stratix V GX transceiver signal integrity development board is the initial release of the board. This section describes the differences between the engineering silicon and production silicon versions of the board.

Power Supply

Tab le A– 2 lists information for the targeted power rails whose voltage values on the

engineering silicon board differ from the production silicon board. Table 2–40 on

page 2–39 shows the production silicon voltage values.

Table A–2. Power Requirements (Engineering Silicon)

Device Voltage Name Voltage (V) Note

VCC

FPGA

MAX V (for FPP configuration)

Flash

MAX II (for USB-Blaster)

EEPROM

USB PHY

Power monitor

S5GX_VCC

2p5V

2p5V_FLTR

1p5V

VCCBAT

VCCR_GTB (28G channels)

VCCT_GTB (28G channels)

VCCL_GTB (28G channels)

VCCRT_GXB

VCCA_GXB

VCCH_GXB

2p5V

XFP_1p8V

2p5V

USBVCC

2p5V_USB

0.85

2.5

1.5

1.5 BT1 socket

0.85 or 1.0 LDO

0.85 or 1.0 Low noise switcher

2.5 or 3 Low noise switcher

1.5 Tied to

2.5 —

2.5 Core

1.8 I/O

3.3 Core or I/O

5.0 —

5.0 Core

2.5 I/O

5.0 —

VCCHIP

VCCHSSI

VCCIO

VCCPD

VCCREF

VCCPGM

VCCBAT

VCC_CLKIN

Ferrite fitered from VCCA_PLL, and VCCAUX

VCCPT

VCCH_GXB

VCCD_FPLL

1p5V

(low noise switcher)

2p5V

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Appendix A: Board Revision History A–3

Engineering Silicon Version Differences

Table A–2. Power Requirements (Engineering Silicon)

Device Voltage Name Voltage (V) Note

Temperature sense ADC

ICS557-03 spread spectrum clock buffer (x1)

ICS8304 clock buffer

IDT5T9306 transceiver REFCLK clock buffers (x4)

T85A23157 dual analog switch

Character LCD

LEDs (x13)

Board power LED

3p3V

3p3V/2p5V

2p5V

3.3 —

3.3 25-MHz clock output to the FPGA

3.3/2.5 50-MHz clock outputs

2.5 Programmable clock outputs

5.0 —

2.5 —

5.0 —

Power Measurement

Tab le A– 3 lists information for the voltage rails whose values on the engineering

silicon board differ from the production silicon board. Table 2–41 on page 2–40 shows the production silicon voltage values.

Table A–3. Voltage Rails (Engineering Silicon)

Schematic Net Name Voltage (V) Description

S5GX_VCC

VCCR_GTB

VCCT_GTB

VCCL_GTB

VCCRT_GXB

VCCA_GXB

VCCH_GXB

VCCD_PLL

VCCPT

0.9 VCC, VCCHIP, VCCHSSI FPGA core power.

1.1 Transceiver receiver power for 28G channels.

1.1 Transceiver transmit power for 28G channels.

1.1 Transceiver clocking power for 28G channels.

1.0 or 1.2 Shared VCCR_GXB and VCCT_GXB transceiver power for 12.5G channels.

2.5 or 3.3 Transceiver analog clock power

1.6 Transceiver TX buffer voltage

1.6 FPGA core D PPL voltage

1.6 FPGA programmable power technology

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

A–4 Appendix A: Board Revision History

Engineering Silicon Version Differences

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

This chapter provides additional information about the document and Altera.

Document Revision History

The following table shows the revision history for this document.

Date Version Changes

■ Updated the production device part number.

■ Added pin information for SMA connectors.

■ Updated the schematic signal names for all GXB receive pins in Table 2–19 and

July 2012 1.1

September 2011 1.0 Initial release.

Table 2–20.

■ Updated the board reference numbers in Table 2–21.

■ Added information on startup issue for VCCRT / VCCA voltage rails.

■ Converted document to new frame template and made textual and style changes.

Additional Information

How to Contact Altera

To locate the most up-to-date information about Altera products, refer to the following table.

Contact

Technical support Website www.altera.com/support

Technical training

Product literature Website www.altera.com/literature

Nontechnical support (general) Email nacomp@altera.com

(software licensing) Email authorization@altera.com

Note to Table:

(1) You can also contact your local Altera sales office or sales representative.

(1)

Contact Method Address

Website www.altera.com/training

Email custrain@altera.com

July 2012 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GX Edition Reference Manual

1–2 Additional InformationAdditional Information

Typographic Conventions

The following table shows the typographic conventions this document uses.

Visual Cue Meaning

Bold Type with Initial Capital Letters

bold type

Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.

italic type

Initial Capital Letters

“Subheading Title”

Courier type

r An angled arrow instructs you to press the Enter key.

1., 2., 3., and a., b., c., and so on

■ ■ ■ Bullets indicate a list of items when the sequence of the items is not important.

1 The hand points to information that requires special attention. h The question mark directs you to a software help system with related information. f The feet direct you to another document or website with related information. m The multimedia icon directs you to a related multimedia presentation.

Indicate command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI.

Indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \qdesigns directory, D: drive, and chiptrip.gdf file.

Indicates variables. For example, n + 1.

Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file.

Indicate keyboard keys and menu names. For example, the Delete key and the Options menu.

Quotation marks indicate references to sections in a document and titles of Quartus II Help topics. For example, “Typographic Conventions.”

Indicates signal, port, register, bit, block, and primitive names. For example,

tdi

, and

input

. The suffix n denotes an active-low signal. For example,

data1

resetn

Indicates command line commands and anything that must be typed exactly as it appears. For example,

c:\qdesigns\tutorial\chiptrip.gdf

Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword

TRI

example,

SUBDESIGN

), and logic function names (for

Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure.

A caution calls attention to a condition or possible situation that can damage or destroy the product or your work.

A warning calls attention to a condition or possible situation that can cause you injury.

The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents.

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation Stratix V GX Edition Reference Manual

Altera Stratix V GX Edition User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

General Description

1. Overview

Board Component Blocks

Development Board Block Diagram

Handling the Board

Introduction

2. Board Components

Board Overview

Featured Device: Stratix V GX

I/O Resources

MAX II CPLD System Controller

Configuration, Status, and Setup Elements

Configuration

FPGA Programming over Embedded USB-Blaster

FPGA Programming from Flash Memory

FPGA Programming over External USB-Blaster

JTAG Header

Status Elements

Status LEDs

Setup Elements

FPP Configuration/MAX II Bypass DIP Switch

Program Select Jumper

Reset Push Button

CPU Reset Push Button

Clock Circuitry

Dedicated Transceiver Clocks

General-Purpose Clocks

Transceiver Channels

Embedded USB-Blaster Clocks

SMA Connectors

Backplane Connectors

General User Input/Output

User-Defined Push Buttons

User-Defined DIP Switch

User-Defined LEDs

Character LCD

Components and Interfaces

10/100/1000 Ethernet

Transceiver Interfaces

XFP Interface

SFP+ Interface

Flash Memory

Power Supply

Power Measurement

Power Distribution System

Temperature Sense

Statement of China-RoHS Compliance

A. Board Revision History

Engineering Silicon Version Differences

Power Supply

Power Measurement

Document Revision History

Additional Information

How to Contact Altera

Typographic Conventions