Altera Stratix V GT Edition User Manual

Transceiver Signal Integrity Development Kit

Stratix V GT Edition Reference Manual

101 Innovation Drive San Jose, CA 95134

www.altera.com

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© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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May 2014 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GT Edition Reference Manual

Chapter 1. Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Chapter 2. Board Components

Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Featured Device: Stratix V GT FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

MAX II CPLD System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

FPGA Programming over Embedded USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

JTAG Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

FPP Configuration/MAX II Bypass DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

Program Select Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

CPU Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

Dedicated Transceiver Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

General-Purpose Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Embedded USB-Blaster Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

Transceiver Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

Backplane Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

User-Defined Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

User-Defined DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29

User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29

Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32

10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32

Transceiver Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34

XFP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34

SFP+ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39

Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–40

Temperature Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–41

Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–42

Additional Information

May 2014 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GT Edition Reference Manual

iv ContentsContents

Board Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Transceiver Signal Integrity Development Kit May 2014 Altera Corporation Stratix V GT Edition Reference Manual

This document describes the hardware features of the Stratix® V GT transceiver signal integrity development board, including the detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board.

General Description

The Transceiver Signal Integrity Development Kit, Stratix V GT Edition, allows you to evaluate the performance of the Stratix V GT FPGA which is optimized for high-performance and high-bandwidth applications with integrated transceivers supporting backplane, chip-to-chip, and chip-to-module operation.

f For more information on the following topics, refer to the respective documents:

■ Setting up the development board and using the included software, refer to the

Transceiver Signal Integrity Development Kit, Stratix V GT Edition User Guide.

1. Overview

■ Stratix V device family, refer to the Stratix V Device Handbook.

Board Component Blocks

The Stratix V GT transceiver signal integrity development board provides a hardware platform for evaluating the performance and signal integrity features of the Altera Stratix V GT device. The development board features the following major component blocks:

■ Altera Stratix V GT FPGA (5SGTMC7K2F40C2) in a 1517-pin FineLine BGA

package

■ 622,000 LEs

■ 234,720 adaptive logic modules (ALMs)

■ 50-Mbits (Mb) embedded memory

■ 512 18x18-bit multipliers

■ 36 transceivers (32 channels with 12.5 Gbps and four channels with 28 Gbps)

■ 174 LVDS transmit channels

■ 28 phase locked loops (PLLs)

■ 696 user I/Os

■ 850-mV core voltage

May 2014 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GT Edition Reference Manual

1–2 Chapter 1: Overview

Board Component Blocks

■ FPGA configuration circuitry

■ MAX

II CPLD (EPM2210F256C3N) and flash Fast Passive Parallel (FPP)

configuration

■ MAX

■ JTAG header for external USB-Blaster

■ Flash storage for two configuration images (factory and user)

■ On-Board clocking circuitry

■ 625-MHz, 644.53125-MHz, 706.25-MHz, and 875-MHz programmable

II CPLD (EPM570M100C4N) for on-board USB-BlasterTM to use with the

Quartus

II Programmer

oscillators for the high-speed transceiver reference clocks

■ 25/100/125/200 MHz jumper-selectable oscillator to the FPGA

■ 50-MHz general-purpose oscillator to the FPGA

■ One differential SMA clock input to the FPGA

■ Four differential SMA clock input to the transceivers

■ Spread spectrum clock input

■ Four clock trigger outputs

■ Transceiver interfaces

■ Four 28-Gbps TX/RX channels to MMPX connectors (for Stratix V GT FPGA

only)

■ Seven 12.5-Gbps TX/RX channels to SMA connectors

■ One 12.5-Gbps TX/RX channel to SFP+ cage

■ One 12.5-Gbps TX/RX channel to XFP cage

■ Seven 12.5-Gbps TX/RX channels to Molex backplane connectors

■ Seven 12.5-Gbps TX/RX channels to Amphenol backplane connectors

■ Seven 12.5-Gbps TX/RX channels to Tyco backplane connectors

■ Memory devices

■ One 1-Gbit (Gb) synchronous flash with a 16-bit data bus

■ Communication ports

■ USB type-B connector

■ Gigabit Ethernet port and RJ-45 jack

■ LCD header

■ General user I/O

■ Eight user LEDs

■ Three configuration status LEDs (factory, user, error)

■ Six Ethernet LEDs

■ One 16-character × 2-line character LCD display

Transceiver Signal Integrity Development Kit May 2014 Altera Corporation Stratix V GT Edition Reference Manual

Chapter 1: Overview 1–3

Board Component Blocks

■ Push button and DIP switches

■ One CPU reset push button

■ One configuration reset push button

■ Four general user push buttons

■ One 8-position user DIP switch

■ One 6-position MSEL control DIP switch

■ One 4-position frequency select and spread spectrum select DIP switch

■ One 4-position transceiver clock input select DIP switch

■ Two 4-position power sequence enable select DIP switches

■ One 4-position VCCRT_GXB/VCCA_GXB voltage select DIP switch

■ Heat sink and fan

■ 40-mm heat sink and fan combo

■ One over-temperature warning indicator LED

■ Power

■ 14-V – 20-V (laptop) DC input

■ One power-on LED

■ One on/off power slide switch

■ Power monitor and trim capability

■ Power sequence capability

■ System Monitoring

■ Temp e ratu r e —FPG A die

■ Mechanical

■ 7.5" x 10.5" board dimension

May 2014 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GT Edition Reference Manual

1–4 Chapter 1: Overview

LCD

Buttons, Switches, Displays

16 Char × 2 Line LCD

8 User DIP Switch

4 User

Push Buttons

8 User

LEDs

Pwrgood

FPP Configuration

28-Gbps Channels

12.5-Gbps Channels

Clock

Circuitry

Tyco

Connector

1 SFP+

XFP

Amphl/FCI Connector

28 SMA

Connectors

16 MMPX

Connectors

Molex

Connector

1 Gb

Flash

3 Configuration

Status LEDs

MAX II

EPM2210

CPLD

PGMSEL

Flash

FPP Config

Power Monitor

15-bit ADCs

10-bit IDACs

ADC

2-wire Ch1

Power

Circuitry

2-wire Ch8

Temperature

Dual Temp

Sensor

Temperature Measure

TDIODES

7 TX/RX

1 TX/RX

7 TX/RX

1 TX/RX

7 TX/RX

4-ATT TX/RX

5-V Fan

USB-Blaster

USB

Type-B

Connector

FTDI

745BL

USB PHY

MAX II

EPM570M

CPLD

10/100/1000 Ethernet

RJ45+

Magnetics

Marvell

88E1111

Ethernet PHY

Development Board Block Diagram

Figure 1–1 shows the block diagram of the Stratix V GT transceiver signal integrity

development board.

Figure 1–1. Stratix V GT Transceiver Signal Integrity Development Board Block Diagram

Handling the Board

When handling the board, it is important to observe the following static discharge precaution:

c Without proper anti-static handling, the board can be damaged. Therefore, use

anti-static handling precautions when touching the board.

The Stratix V GT transceiver signal integrity development board must be stored between –40º C and 100º C. The recommended operating temperature is between 0º C and 55º C.

Transceiver Signal Integrity Development Kit May 2014 Altera Corporation Stratix V GT Edition Reference Manual

2. Board Components

This chapter introduces all the important components on the Stratix V GT transceiver signal integrity development board. Figure 2–1 illustrates major component locations and Table 2–1 provides a brief description of all features of the board.

1 A complete set of schematics, a physical layout database, and GERBER files for the

development board reside in the Stratix V GT development kit documents directory.

f For information about powering up the board and installing the demo software, refer

to the Transceiver Signal Integrity Development Kit, Stratix V GT Edition User Guide.

This chapter consists of the following sections:

■ “Board Overview”

■ “Featured Device: Stratix V GT FPGA” on page 2–6

■ “MAX II CPLD System Controller” on page 2–9

■ “Configuration, Status, and Setup Elements” on page 2–14

■ “Clock Circuitry” on page 2–21

■ “General User Input/Output” on page 2–28

■ “Components and Interfaces” on page 2–32

■ “Flash Memory” on page 2–36

■ “Power Supply” on page 2–37

■ “Statement of China-RoHS Compliance” on page 2–42

May 2014 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GT Edition Reference Manual

2–2 Chapter 2: Board Components

User DIP Switch (SW4)

Stratix V GT FPGA (U29)

VCCRT_GXB/ VCCA_GXB

Voltage Select (SW2)

MSEL Selection/MAX II Bypass (S7)

Clock Trigger Outputs (U32, U33)

Clock Trigger Outputs (U34, U35)

Transceiver Clock Input Select DIP switch (SW6)

Reset Push Buttons (S5, S6)

MAX II

CPLD (U19)

MMPX

Connectors

Transceiver Input

Reference Clocks

User Push Buttons (SW1-SW4)

User LEDs (D8-D15)

SFP+ Module (J51)

XFP Module (U25)

Molex Backplane Connector (J34)

Tyco

Connector

(J33)

Amphenol Backplane Connector (J32)

Powe r Switch (SW1)

JTAG Header

(J93)

DC Power

Jack (J1)

Character LCD (J30)

Embedded

USB-Blaster

(CN1)

Power Sequence

Enable/Disable

(SW7, SW3)

10/100 /1000

Ethernet

Port (J29)

Fan Connector (J12)

Fan Jumper (J26)

Fan LED (D6)

GXB Receive SMA

GXB Transmit SMA

FPGA Clock Input Select/

Spread Spectrum Clock Select

(SW5)

External Power

Input Banana Jacks

(J6, J15, J18, J21)

Board Overview

This section provides an overview of the Stratix V GT transceiver signal integrity development board, including an annotated board image and component descriptions. Figure 2–1 provides an overview of the development board features.

Figure 2–1. Overview of the Stratix V GT Transceiver Signal Integrity Development Board Features

Tab le 2– 1 describes the components and lists their corresponding board references.

Table 2–1. Transceiver Signal Integrity Development Kit Components (Part 1 of 4)

Board Reference Type Description

Featured Devices

U29 FPGA Stratix V GT FPGA (5SGTMC7K2F40C2), 1517-pin BGA.

U19 CPLD MAX II CPLD (EPM2210F256C3N), 256-pin BGA.

Configuration, Status, and Setup Elements

S7 (pin 6-7) MAX II bypass switch

Enables or disables the MAX II CPLD in the JTAG chain. The MAX II CPLD is disabled by default.

Transceiver Signal Integrity Development Kit May 2014 Altera Corporation Stratix V GT Edition Reference Manual

Chapter 2: Board Components 2–3

Board Overview

Table 2–1. Transceiver Signal Integrity Development Kit Components (Part 2 of 4)

Board Reference Type Description

J28 Program select jumper

SW5

FPP configuration/MAX II bypass DIP switch

Spread spectrum clock settings DIP switch

VCCA_GXB voltage selection

SW2 (pin2-7)

jumper

VCCRT voltage selection

SW2 (pin 1-8)

jumper

Toggles the program LEDs to select which FPGA image to load on power-up; 0 selects factory image and 1 selects user-defined image.

Select the configuration mode from the MAX II CPLD.

Sets the spread spectrum output clock frequency and down-spread percentages.

Selects V position, the V the V

voltage to the FPGA. When the jumper is set to close

CCA

voltage is 3.0 V (default). When set to open position,

CCA

voltage is 2.5 V.

CCA

voltage to the FPGA. When the jumper is set to close

CCRT

voltage is 0.85 V.

CCRT

voltage is 1.0 V (default). When set to open position,

CCRT

Fan control jumper Selects whether the fan is always on or the FPGA automatically

J26

controls the fan. To set it to its default setting of always on, connect jumper pin 2-3. Connect jumper pin 1-2 to set the fan in auto mode.

D7 Fan LED Indicates an over-temperature condition in the FPGA and a fan should

be attached to the FPGA and running.

D8 Load LED Illuminates during embedded USB-Blaster data transfers.

D9 Error LED Illuminates when the FPGA configuration from flash fails.

D3 Power LED Illuminates when 14-V power is present.

D12-D17 Ethernet LEDs Indicates the connection speed as well as transmit or receive activity.

Clock Circuitry

Feeds even-numbered REFCLKs on left side of the Stratix V GT device

Y3 Programmable oscillator

and trigger an output at board reference J81. The external input is available at board reference J79 and J80. The default frequency is

644.53125 MHz.

Feeds odd-numbered REFCLKs on left side of the Stratix V GT device

Y4 Programmable oscillator

and trigger an output at board reference J85. The external input is available at board reference J83 and J84. The default frequency is

706.25 MHz.

Feeds even-numbered REFCLKs on right side of the Stratix V GT device

Y5 Programmable oscillator

and trigger an output at board reference J88. The external input is available at board reference J86 and J87. The default frequency is 625 MHz.

Feeds odd-numbered REFCLKs on right side of the Stratix V GT device

Y6 Programmable oscillator

and trigger an output at board reference J91. The external input is available at board reference J89 and J90. The default frequency is 875 MHz.

SW6

Transceiver clock input select DIP switch

Selects the SMA or oscillator as the clock input.

Y2 50-MHz oscillator 50.000-MHz crystal oscillator for general purpose logic.

X3 25/100/125/200-MHz core

Selects the core clock frequency. The default frequency is 100 MHz.

clock selectable oscillator

SW5 Spread spectrum selection

switch

Select either the core or spread spectrum clock. Pin 1-2 selects S0 and S1 while pin 3-4 selects SS0 and SS1.

J70 and J71 External core clock input SMA external input at CLK10 p/n.

May 2014 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GT Edition Reference Manual

2–4 Chapter 2: Board Components

Board Overview

Table 2–1. Transceiver Signal Integrity Development Kit Components (Part 3 of 4)

Board Reference Type Description

J72 and J73 External core clock output SMA external output at FPLL/IO4D.

Transceiver Interfaces

J36, J39, J41,

GXB transmit channel Transceiver GXB transmit channels connected to SMA. J46, J48, J53, J55, J57, J59, J61, J63, J65, J67, J69

J35, J37, J38,

GXB receive channel Transceiver GXB receive channels connected to SMA. J40, J42, J45, J47, J52, J54, J56, J58, J60, J62, J64, J66, J68

J51 Transceiver optical interface Transceiver receive and transmit channel connected to the SFP+

module.

U25 Transceiver optical interface Transceiver receive and transmit channel connected to the XFP

module.

Transceiver Interfaces – Backplane Connectors

J33 10Gbase-KR reference

backplane

J34 10Gbase-KR reference

backplane

J32 10Gbase-KR reference

backplane

7 transceiver-channel pairs, right angle receptacle for Tyco backplane connector.

7 transceiver-channel pairs, right angle receptacle for Molex Impact backplane connector.

7 transceiver-channel pairs, right angle receptacle for Amphenol backplane connector.

Transceiver Interfaces – Stratix V GT

J94, J96, J98,

Advanced transceiver interface Transceiver GTB receive channels connected to the MMPX connectors. J100, J102, J104, J106, J108

J95, J97, J99, J101, J103, J105,

Advanced transceiver interface Transceiver GTB transmit channels connected to the MMPX

connectors.

J107, J109

J110, J111, J112, J113

Transceiver test trace Transceiver GTB receive and transmit channels connected to the

MMPX connectors with an eight inch test trace.

General User Input and Output

D18-D25 User LEDs 8 user LEDs. Illuminates when driven low.

SW4 User DIP switch

Configuration reset push

button

Octal user DIP switch. When the switch is in the open position, a logic 0 is selected.

The default reset for the MAX II CPLD System Controller.

S6 CPU reset push button The default reset for the FPGA logic.

S1-S4 General user push buttons Four user push buttons. Driven low when pressed.

J30 Character LCD header

A single 14-pin 0.1" pitch dual-row header which interfaces to the 16 character × 2 line LCD module.

Transceiver Signal Integrity Development Kit May 2014 Altera Corporation Stratix V GT Edition Reference Manual

Chapter 2: Board Components 2–5

Board Overview

Table 2–1. Transceiver Signal Integrity Development Kit Components (Part 4 of 4)

Board Reference Type Description

Memory Devices

U21 Flash memory Micron PC28F00AP30BF, 1-Gb CFI NOR flash memory.

U17 EEPROM Microchip Technology Inc. 93LC46B/SNG-ND, 64x16 EEPROM SO.

Communication Ports

RJ-45 connector which provides a 10/100/1000 Ethernet connection

J29 Gigabit Ethernet port

through a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed Ethernet MAC MegaCore function in SGMII mode.

Connects an Altera USB-Blaster dongle to program the FPGA and

J93 JTAG header

MAX II CPLD devices. The embedded USB-Blaster is disabled when you connect the USB-Blaster to the JTAG header.

CN1 USB Type-B connector

Connects a type-B USB cable to enable the JTAG embedded USB-Blaster to program the FPGA and MAX II CPLD devices.

Power Supply

J1 DC input jack

14-V – 20-V DC female input power jack. Accepts a 2.5-mm male center-positive barrel from 14-V DC power supply.

SW1 Power switch Switch to power on/off the board.

J6 S5GX_VCC (0.85 V/0.9 V)

banana jack

Banana jack for supplying external V and F2 must be removed prior to supplying external power to this

power to the FPGA. Fuses F1

banana jack.

J12 VCCA_GXB (2.5 V/3.3 V)

banana jack

J9 VCCRT_GXB (0.85 V/1.0 V)

banana jack

J15 VCCR_GTB (1.0 V) banana

jack

J21 VCCL_GTB (1.0 V) banana

jack

J18 VCCT_GTB (1.0 V) banana

jack

Banana jack for supplying external V must be removed prior to supplying external power to this banana jack.

power to the FPGA. Fuse F7

CCA

power to the FPGA. Fuse F6

CCRT_GXB

power to the FPGA. Fuse F3

CCR_GTB

power to the FPGA. Fuse F5

CCL_GTB

power to the FPGA. Fuse F4

CCT_GTB

J3 Ground banana jack Banana jack connected to ground.

U10 and U11 Power monitor devices Linear Technology LTC2978, octal PMBus power supply monitor and

controller.

May 2014 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GT Edition Reference Manual

2–6 Chapter 2: Board Components

Featured Device: Stratix V GT FPGA

The development board features the Stratix V GT 5SGTMC7K2F40C2 device (U29) in a 1517-pin FineLine BGA package.

f For more information about the Stratix V device family, refer to the Stratix V Device

Handbook.

Tab le 2– 2 describes the features of the Stratix V GT 5SGTMC7K2F40C2 device.

Table 2–2. Stratix V GT Device Features

ALMs

234,720 622,000 939,000 2,560 7.16 512 28 36

Equivalent

LEs

Registers

M20K

Blocks

MLAB

Blocks (Mb)

18-bit × 18-bit

Multipliers

PLLs

Transceiver

Channels

(12.5 Gbps)

Package Type

1517-pin

FineLine BGA

Tab le 2– 3 lists the Stratix V GT component reference and manufacturing information.

Table 2–3. Stratix V GT Component Reference and Manufacturing Information

Board

Reference

U29

Description Manufacturer

FPGA, Stratix V GT F1517, 622K LEs, lead-free

Corporation 5SGTMC7K2F40C2 www.altera.com

Altera

Manufacturing

Part Number

Manufacturer

Website

I/O Resources

Tab le 2– 4 summarizes the FPGA I/O usage by function on the Stratix V GT

transceiver signal integrity development board.

Table 2–4. Stratix V GT I/O Usage Summary (Part 1 of 3)

Function I/O Type I/O Count Description

FPGA Transceiver Clocks

Programmable differential clock LVDS input 4 Differential REFCLK input to feed the even-numbered

channels on the left side of the Stratix V GT device.

Programmable differential clock LVDS input 4 Differential REFCLK input to feed the odd-numbered

channels on the left side of the Stratix V GT device.

Programmable differential clock LVDS input 4 Differential REFCLK input to feed the even-numbered

channels on the right side of the Stratix V GT device.

Programmable differential clock LVDS input 4 Differential REFCLK input to feed the odd-numbered

channels on the right side of the Stratix V GT device.

External differential clock inputs LVDS input 4 pairs Differential REFCLK input for one SMA pair per clock

buffer.

FPGA Global Clocks

50-MHz clock 2.5-V CMOS input 1 Global clock input.

Spread Spectrum clock 2.5-V CMOS input 2 Differential global clock.

SMA differential clock input LVDS input 2 Differential global clock.

Transceiver Signal Integrity Development Kit May 2014 Altera Corporation Stratix V GT Edition Reference Manual

Chapter 2: Board Components 2–7

Featured Device: Stratix V GT FPGA

Table 2–4. Stratix V GT I/O Usage Summary (Part 2 of 3)

Function I/O Type I/O Count Description

Temperature Monitor

Temperature sense diodes Analog 2 Stratix V GT internal sense diode.

Power Monitor Devices

LTC2978 controller 2.5-V CMOS 24 Octal PMBus power supply monitor and controller.

Temperature Measure

MAX1619 interface 2.5V CMOS 4 Die and ambient temperature sense.

Fan

FAN_On 2.5-V CMOS output 1 Fan control

FAN_LED 2.5-V CMOS output 1 Fan LED

USB-Blaster

JTAG USB-Blaster or JTAG header

2.5-V CMOS 4 Built-in USB-Blaster or JTAG 0.1-mm header for debugging

FPP Configuration

FPGA Dclk 2.5-V CMOS input 1 FPP Dclk

FPGA D[15:0] 2.5V CMOS 16 FPP data bus

MSEL [4:0] 2.5V CMOS 5 Dedicated configuration pins

NCONFIG 2.5V CMOS 1 Dedicated configuration pins

NSTATUS 2.5V CMOS 1 Dedicated configuration pins

NCE 2.5V CMOS 1 Dedicated configuration pins

CONFIG_DONE 2.5V CMOS 1 Dedicated configuration pins

Flash Memory

ADDR[26:1] 1.8-V CMOS output 26 Flash address bus

DATA[15:0] 1.8-V CMOS

16 Flash data bus

input/output

FLASH_CEn 1.8-V CMOS output 1 Flash chip enable

FLASH_OEn 1.8-V CMOS output 1 Flash read strobe

FLASH_WEn 1.8-V CMOS output 1 Flash write strobe

FLASH_WAIT 1.8-V CMOS input 1 Flash ready or busy

FLASH_CLK 1.8-V CMOS output 1 Flash clock

FLASH_RSTn 1.8-V CMOS output 1 Flash reset

FLASH_ADVn 1.8-V CMOS output 1 Flash address valid

FLASH_WPn 1.8-V CMOS output 1 Flash write protect

Reset

CPU_RESETn 2.5-V CMOS input 1 Nios

II CPU reset

Switches, Buttons, LEDS

User push buttons 2.5-V CMOS input 4 4 user push buttons

User DIP switches 2.5-V CMOS input 8 8 user DIP switches

User LEDs 2.5-V CMOS output 8 8 user LEDs (green)

May 2014 Altera Corporation Transceiver Signal Integrity Development Kit

Stratix V GT Edition Reference Manual

2–8 Chapter 2: Board Components

Featured Device: Stratix V GT FPGA

Table 2–4. Stratix V GT I/O Usage Summary (Part 3 of 3)

Function I/O Type I/O Count Description

LCD

16 Character × 2 Line LCD 5.0-V LVTTL output 11 LCD

Ethernet

TXD[3:0] 2.5-V CMOS output 4 Ethernet transmit RGMII data bus

TXEN 2.5-V CMOS output 1 Ethernet transmit enable

GTXCLK 2.5-V CMOS output 1 Ethernet transmit clock

RXD[3:0] 2.5-V CMOS input 4 Ethernet receive RGMII data bus

RXDV 2.5-V CMOS input 1 Receive data valid

RXCLK 2.5-V CMOS input 1 Receive clock

MDC 2.5-V CMOS input 1 Ethernet MII clock

MDIO 2.5-V CMOS inout 1 Ethernet MII data

ENET_SGMII_TXP/N LVDS output 2 Ethernet SGMII transmit data positive/negative

ENET_SGMII_RXP/N LVDS input 2 Ethernet SGMII receive data positive/negative

Transceivers

28G channels to MMPX 1.4-V PCML 16 Transceiver channel

12.5G channels to Tyco backplane connector

12.5G channels to Amphenol backplane connector

12.5G channels to Molex backplane connector

1.4-V PCML 28

Transceiver channel

12.5G channels to SMA 1.4-V PCML 28 Transceiver channel

12.5G channels to a SFP+ cage 1.4-V PCML 4 Transceiver channel

12.5G channels to XFP cage 1.4-V PCML 4 Transceiver channel

Spares

Spare[7:0] 2.5-V CMOS 8 Spare signals to the MAX II CPLD

Device I/O Total:

304

Transceiver Signal Integrity Development Kit May 2014 Altera Corporation Stratix V GT Edition Reference Manual

+ 36 hidden pages

Altera Stratix V GT Edition User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

General Description

1. Overview

Board Component Blocks

Development Board Block Diagram

Handling the Board

2. Board Components

Board Overview

Featured Device: Stratix V GT FPGA

I/O Resources