Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual

Stratix V Avalon-MM Interface for PCIe Solutions

User Guide

Last updated for Altera Complete Design Suite: 14.1

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Bridge

PCIe Hard IP

Block

PIPE

Interface

PHY IP Core

for PCIe

(PCS/PMA)

Serial Data

Transmission

Application

Layer

(User Logic)

Avalon-MM

Interface

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Stratix V Avalon-MM Interface for PCIe Datasheet

Altera® Stratix® V FPGAs include a configurable, hardened protocol stack for PCI Express compliant with PCI Express Base Specification 2.1 or 3.0.

The Hard IP for PCI Express IP core using the Avalon ® Memory-Mapped (Avalon-MM) interface removes some of the complexities associated with the PCIe protocol. For example, it handles all of the Transaction Layer Protocol (TLP) encoding and decoding. Consequently, you can complete your design more quickly. The Avalon-MM interface is implemented as a bridge in soft logic. It is available in Qsys.

Figure 1-1: Stratix V PCIe Variant with Avalon-MM Interface

The following figure shows the high-level modules and connecting interfaces for this variant.

that is

Table 1-1: PCI Express Data Throughput

The following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for 1, 2, 4, and 8 lanes. The protocol specifies 2.5 giga-transfers per second for Gen1, 5.0 giga-transfers per second for Gen2, and 8.0 giga-transfers per second for Gen3. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead. In contrast, Gen3 uses 128b/130b encoding which reduces the data throughput lost to encoding to less than 1%.

PCI Express Gen1 (2.5 Gbps)

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Link Width in Gigabits Per Second (Gbps)

x1 x2 x4 x8

2 4 8 16

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1-2

Features

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Link Width in Gigabits Per Second (Gbps)

x1 x2 x4 x8

PCI Express Gen2 (5.0 Gbps)

PCI Express Gen3 (8.0 Gbps)

Refer to the PCI Express Reference Design for Stratix V Devices for more information about calculating bandwidth for the hard IP implementation of PCI Express in many Altera FPGAs, including the Stratix V Hard IP for PCI Express IP core.

Related Information

• PCI Express Base Specification 2.1 or 3.0

• PCI Express DMA Reference Design for Stratix V Devices

• Creating a System with Qsys

Features

New features in the Quartus® II 14.1 software release:

• Reduced Quartus II compilation warnings by 50%. The Stratix V Hard IP for PCI Express with the Avalon-MM interface supports the following features:

4 8 16 32

7.87 15.75 31.51 63

• Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as hard IP.

• Support for ×1, ×2, ×4, and ×8 configurations with Gen1, Gen2, or Gen3 lane rates for Root Ports and Endpoints.

• Dedicated 16 KByte receive buffer.

• Optional hard reset controller for Gen2.

• Optional support for Configuration via Protocol (CvP) using the PCIe link allowing the I/O and core bitstreams to be stored separately.

• Support for 32- or 64-bit addressing for the Avalon-MM interface to the Application Layer.

• Qsys example designs demonstrating parameterization, design modules, and connectivity.

• Extended credit allocation settings to better optimize the RX buffer space based on application type.

• Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error reporting (AER) for high reliability applications.

• Support for Configuration Space Bypass Mode, allowing you to design a custom Configuration Space and support multiple functions.

• Support for Gen3 PIPE simulation.

• Easy to use:

• Flexible configuration.

• No license requirement.

• Example designs to get started.

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Table 1-2: Feature Comparison for all Hard IP for PCI Express IP Cores

The table compares the features of the four Hard IP for PCI Express IP Cores.

Features

1-3

Feature Avalon‑ST Interface Avalon‑MM

Interface

Avalon‑MM DMA Avalon‑ST Interface with SR-

IP Core License Free Free Free Free

Native

Supported Supported Supported Supported

Endpoint

Legacy Endpoint

(1)

Supported Not Supported Not Supported Not Supported

Root port Supported Supported Not Supported Not Supported

Gen1 ×1, ×2, ×4, ×8 ×1, ×2, ×4, ×8 Not Supported

Gen2 ×1, ×2, ×4, ×8 ×1, ×2, ×4, ×8 ×4, ×8

Gen3 ×1, ×2, ×4, ×8 ×1, ×2, ×4 ×4, ×8

64-bit Applica‐

Supported Supported Not supported Not supported

×8

×4, ×8

×2, ×4, ×8

tion Layer interface

IOV

128-bit

Supported Supported Supported Supported Application Layer interface

256-bit

Supported Not Supported Supported Supported Application Layer interface

(1)

Not recommended for new designs.

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Features

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Feature Avalon‑ST Interface Avalon‑MM

Interface

Transaction Layer Packet type (TLP)

• Memory Read Request

• Memory Read RequestLocked

• Memory Write Request

• I/O Read Request

• I/O Write Request

• Configuration Read Request (Root Port)

• Configuration Write Request (Root Port)

• Message Request

• Message Request with Data Payload

• Completion Message

• Completion with Data

• Memory Read Request

• Memory Write Request

• I/O Read Request—Root Port only

• I/O Write Request—Root Port only

• Configuration Read Request (Root Port)

• Configuration Write Request (Root Port)

• Completion Message

• Completion with Data

• Memory Read Request (single dword)

• Memory Write Request (single dword)

• Completion for Locked Read without Data

Avalon‑MM DMA Avalon‑ST Interface with SR-

IOV

• Memory Read Request

• Memory Write Request

• Completion Message

• Completion with Data

• Memory Read Request

• Memory Write Request

• Configuration Read Request (from Root Port)

• Configuration Write Request (from Root Port)

• Message Request

• Completion Message

• Completion with Data

Payload size

Number of tags supported for non-posted requests

62.5 MHz clock Supported Supported Not Supported Not Supported

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128–2048 bytes 128–256 bytes 128, 256, 512 bytes 128–256 bytes

256 8 16 256

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Features

1-5

Feature Avalon‑ST Interface Avalon‑MM

Interface

Out-of-order

Not supported Supported Supported Not supported completions (transparent to the Application Layer)

Requests that

Not supported Supported Supported Supported cross 4 KByte address boundary (transparent to the Application Layer)

Polarity

Supported Supported Supported Supported Inversion of PIPE interface signals

Avalon‑MM DMA Avalon‑ST Interface with SR-

IOV

ECRC

Supported Not supported Not supported Not supported forwarding on RX and TX

Number of MSI requests

1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 (for

Physical Functions)

MSI-X Supported Supported Supported Supported

Legacy

Supported Supported Supported Supported interrupts

Expansion

Supported Not supported Not supported Not supported ROM

The Stratix VAvalon-MM Interface for PCIe Solutions User Guide explains how to use this IP core and not the PCI Express protocol. Although there is inevitable overlap between these two purposes, use this document only in conjunction with an understanding of the PCI Express Base Specification.

Note:

This release provides separate user guides for the different variants. The Related Information provides links to all versions.

Related Information

Datasheet

• Stratix V Avalon-MM Interface for PCIe Solutions User Guide

• Stratix V Avalon-ST Interface for PCIe Solutions User Guide

• Stratix V Avalon-ST Interface with SR-IOV for PCIe Solutions User Guide

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Release Information

• V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

Release Information

Table 1-3: Hard IP for PCI Express Release Information

Item Description

Version 14.1

Release Date December 2014

Ordering Codes No ordering code is required

Product IDs There are no encrypted files for the Stratix V Hard

IP for PCI Express. The Product ID and Vendor ID

Vendor ID

are not required because this IP core does not require a license.

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Device Family Support

Table 1-4: Device Family Support

Device Family Support

Stratix V Final. The IP core is verified with final timing

models. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

Other device families Refer to the Related Information below for other

device families:

Related Information

• Arria V Avalon-MM Interface for PCIe Solutions User Guide

• Arria V Avalon-ST Interface for PCIe Solutions User Guide

• Arria V GZ Avalon-MM Interface for PCIe Solutions User Guide

• Arria V GZ Avalon-ST Interface for PCIe Solutions User Guide

• Arria 10 Avalon-MM Interface for PCIe Solutions User Guide

• Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide

• Arria 10 Avalon-ST Interface for PCIe Solutions User Guide

• Cyclone V Avalon-MM Interface for PCIe Solutions User Guide

• Cyclone V Avalon-ST Interface for PCIe Solutions User Guide

• IP Compiler for PCI Express User Guide

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User Application

Logic

PCIe

Hard IP

PCIe

Hard IP

User Application

Logic

PCI Express Link

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Configurations

The Avalon-MM Stratix V Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stack comprising the following layers:

• Physical (PHY), including:

• Media Access Control (MAC)

• Data Link Layer (DL)

• Transaction Layer (TL) When configured as an Endpoint, the Stratix V Hard IP for PCI Express using the Avalon-MM supports

memory read and write requests and completions with or without data.

Figure 1-2: PCI Express Application with a Single Root Port and Endpoint

The following figure shows a PCI Express link between two Stratix V FPGAs.

• Physical Media Attachment (PMA)

• Physical Coding Sublayer (PCS)

Configurations

1-7

Datasheet

Figure 1-3: PCI Express Application Using Configuration via Protocol

The Stratix V design below includes the following components:

• A Root Port that connects directly to a second FPGA that includes an Endpoint.

• Two Endpoints that connect to a PCIe switch.

• A host CPU that implements CvP using the PCI Express link connects through the switch. For more

information about configuration over a PCI Express link, refer to Configuration via Protocol (CvP) on page 13-1.

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PCIe Link

PCIe Hard IP

Switch

PCIe

Hard IP

User Application

Logic

PCIe Hard IP

PCIe Link

User Application

Logic

Altera FPGA Hard IP for PCI Express

Altera FPGA with Hard IP for PCI Express

Active Serial or

Active Quad

Device Configuration

Configuration via Protocol (CvP)

using the PCI Express Link

Serial or

Quad Flash

USB

Download

cable

PCIe

Hard IP

User

Application

Logic

Altera FPGA with Hard IP for PCI Express

Config Control

CVP

USB

Host CPU

PCIe

1-8

Example Designs

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Related Information

Configuration via Protocol (CvP)Implementation in Altera FPGAs User Guide

Example Designs

The following Qsys example designs are available for the Avalon-MM Stratix V Hard IP for PCI Express IP Core. You can download them from the <install_dir>/ip/altera/altera_pcie/altera_pcie_<dev>__hip_avmm/

example_designs directory:

• ep_g1x1.qsys

• ep_g1x4.qsys

• ep_g1x8.qsys

• ep_g2x1.qsys

• ep_g2x4.qsys

• ep_g2x8.qsys

Related Information

Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express on page 2-1

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Debug Features

Debug features allow observation and control of the Hard IP for faster debugging of system-level problems.

Related Information

Debugging on page 14-1

IP Core Verification

To ensure compliance with the PCI Express specification, Altera performs extensive verification. The simulation environment uses multiple testbenches that consist of industry-standard bus functional models (BFMs) driving the PCI Express link interface. Altera performs the following tests in the simulation environment:

• Directed and pseudorandom stimuli are applied to test the Application Layer interface, Configuration Space, and all types and sizes of TLPs

• Error injection tests that inject errors in the link, TLPs, and Data Link Layer Packets (DLLPs), and check for the proper responses

• PCI-SIG® Compliance Checklist tests that specifically test the items in the checklist

• Random tests that test a wide range of traffic patterns

Debug Features

1-9

Altera provides the following two example designs that you can leverage to test your PCBs and complete compliance base board testing (CBB testing) at PCI-SIG.

Related Information

• PCI SIG Gen3 x8 Merged Design - Stratix V

• PCI SIG Gen2 x8 Merged Design - Stratix V

Compatibility Testing Environment

Altera has performed significant hardware testing to ensure a reliable solution. In addition, Altera internally tests every release with motherboards and PCI Express switches from a variety of manufac‐ turers. All PCI-SIG compliance tests are run with each IP core release.

Performance and Resource Utilization

Because the PCIe protocol stack is implemented in hardened logic, it uses less than 1% of device resources.

The Avalon-MM soft logic bridge functions as a front end to the hardened protocol stack. The following table shows the typical device resource utilization for selected configurations using the current version of the Quartus II software. With the exception of M20K memory blocks, the numbers of ALMs and logic registers are rounded up to the nearest 50.

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Recommended Speed Grades

Table 1-5: Performance and Resource Utilization Avalon-MM Hard IP for PCI Express

Interface Width ALMs M20K Memory Blocks Logic Registers

Avalon-MM Bridge

64 1100 17 1500

128 1900 25 2900

Avalon-MM Interface–Completer Only

64 650 8 1000

128 1400 12 2400

Avalon-MM–Completer Only Single Dword

64 250 0 350

Note: Soft calibration of the transceiver module requires additional logic. The amount of logic required

depends upon the configuration.

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Related Information

Fitter Resources Reports

Recommended Speed Grades

Table 1-6: Stratix V Recommended Speed Grades for All Avalon-MM Widths and Frequencies

Lane Rate Link Width Interface Width Application Clock

Frequency (MHz)

Gen1 ×8 128 Bits 125 –1, –2, –3, –4

×4 128 bits 125 –1, –2, –3, –4

Gen2

×8 128 bits 250 –1, –2, –3

×2 128 bits 125 –1, –2, –3

Gen3

×4 128 bits 250 –1, –2, –3

Recommended Speed Grades

(2)

The -4 speed grade is also possible for this configuration; however, it requires significant effort by the end user to close timing.

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×8 256 bits 250 –1, –2, –3

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Related Information

• Area and Timing Optimization

• Altera Software Installation and Licensing Manual

• Setting up and Running Analysis and Synthesis

Steps in Creating a Design for PCI Express

Before you begin

Select the PCIe variant that best meets your design requirements.

• Is your design an Endpoint or Root Port?

• What Generation do you intend to implement?

• What link width do you intend to implement?

• What bandwidth does your application require?

• Does your design require CvP?

1. Select parameters for that variant.

2. Simulate using an Altera-provided example design. All of Altera's PCI Express example designs are

available under <install_dir>/ip/altera/altera_pcie/. Alternatively, create a simulation model and use your own custom or third-party BFM. The Qsys Generate menu generates simulation models. Altera supports ModelSim-Altera for all IP. The PCIe cores support the Aldec RivieraPro, Cadence NCsim, Mentor Graphics ModelSim, and Synopsys VCS and VCS-MX simulators.

3. Compile your design using the Quartus II software. If the versions of your design and the Quartus II software you are running do not match, regenerate your PCIe design.

4. Download your design to an Altera development board or your own PCB. Click on the All Develop‐ ment Kits link below for a list of Altera's development boards.

5. Test the hardware. You can use Altera's SignalTap® II Logic Analyzer or a third-party protocol analyzer to observe behavior.

6. Substitute your Application Layer logic for the Application Layer logic in Altera's testbench. Then repeat Steps 3–6. In Altera's testbenches, the PCIe core is typically called the DUT (device under test). The Application Layer logic is typically called APPS.

Steps in Creating a Design for PCI Express

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Datasheet

Related Information

• Parameter Settings on page 3-1

• Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express on page 2-1

• All Development Kits

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Getting Started with the Avalon‑MM Stratix V

Transaction,

Data Link,

and PHY

Layers

O n-C hip

Memory

DMA

Qsys System Design for PCI Express

PCI Express

Link

PCI

Express

Avalon-MM

Bridge

Interconnect

Avalon-MM Hard IP for PCI Express

Transceiver

Reconfiguration

Controller

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You can download a design example for the Avalon-MM Stratix V Hard IP for PCI Express from the

<install_dir>/ip/altera/altera_pcie/altera_pcie-<dev>_hip_avmm/example_designs directory. This walkthrough

uses a Gen2 x4 Endpoint, ep_g2x4.qsys. The design examples contain the following components:

• Avalon-MM Stratix V Hard IP for PCI Express IP core

• On-Chip memory

• DMA controller

• Transceiver Reconfiguration Controller

• Two Avalon-MM pipeline bridges

Figure 2-1: Qsys Generated Endpoint

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Running Qsys

The design example transfers data between an on-chip memory buffer located on the Avalon-MM side and a PCI Express memory buffer located on the root complex side. The data transfer uses the DMA component which is programmed by the PCI Express software application running on the Root Complex processor.

The example design also includes the Transceiver Reconfiguration Controller which allows you to dynamically reconfigure transceiver settings. This component is necessary for high performance transceiver designs.

Related Information

• Generating the Example Design on page 2-3

• Creating a System with Qsys

This document provides an introduction to Qsys.

Running Qsys

1. Choose Programs > Altera > Quartus II><version_number> (Windows Start menu) to run the

Quartus II software. Alternatively, you can also use the Quartus II Web Edition software.

2. On the File menu, select New, then Qsys System File.

3. Open the ep_g2x4.qsys example design.

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The following figure shows a Qsys system that includes the Transceiver Reconfiguration Controller and the Altera PCIe Reconfig Driver IP Cores. The Transceiver Reconfiguration Controller performs dynamic reconfiguration of the analog transceiver settings to optimize signal quality. You must include these components to the Qsys system to run successfully in hardware.

Figure 2-2: Qsys Avalon-MM Design for PCIe with Transceiver Reconfiguration Components

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Refer to Creating a System with Qsys in volume 1 of the Quartus II Handbook for more information about how to use Qsys. For an explanation of each Qsys menu item, refer to About Qsys in Quartus II Help.

Related Information

• Creating a System with Qsys

• About Qsys

Generating the Example Design

1. On the Generate menu, select Generate Testbench System. The Generation dialog box appears.

2. Under Testbench System, set the following options: a. For Create testbench Qsys system, select Standard, BFMs for standard Qsys interfaces.

b. For Create testbench simulation model, select Verilog.

3. You can retain the default values for all other parameters.

4. Click Generate.

5. After Qsys reports Generation Completed, click Close.

6. On the File menu, click Save.

The following table lists the testbench and simulation directories Qsys generates.

Generating the Example Design

2-3

Table 2-1: Qsys System Generated Directories

Directory Location

Qsys system

Testbench

Simulation Model

The design example simulation includes the following components and software:

• The Qsys system

• A testbench. You can view this testbench in Qsys by opening <project_dir>/ep_g2x4/testbench/ep_g2x4_

tb.qsys.

• The ModelSim software

Note:

You can also use any other supported third-party simulator to simulate your design.

Complete the following steps to run the Qsys testbench:

1. In a terminal window, change to the <project_dir>/ep_g2x4/testbench/mentor directory.

2. Start the ModelSim® simulator.

3. Type the following commands in a terminal window:

<project_dir>/ep_g2x4

<project_dir>/ep_g2x4/testbench/<cad_vendor>

<project_dir>/ep_g2x4/testbench/ep_g2x4_tb/

simulation/

a. do msim_setup.tcl b. ld_debug c. run 140000 ns

Getting Started with the Avalon‑MM Stratix V Hard IP for PCI Express

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Generating the Example Design

The driver performs the following transactions with status of the transactions displayed in the ModelSim simulation message window:

1. Various configuration accesses to the Avalon-MM Stratix V Hard IP for PCI Express in your system after the link is initialized

2. Setup of the Address Translation Table for requests that are coming from the DMA component

3. Setup of the DMA controller to read 512 Bytes of data from the Transaction Layer Direct BFM shared

memory

4. Setup of the DMA controller to write the same data back to the Transaction Layer Direct BFM shared memory

5. Data comparison and report of any mismatch

The following example shows the transcript from a successful simulation run.

Example 2-1: Transcript from ModelSim Simulation of Gen2 x4 Endpoint

# 464 ns Completed initial configuration of Root Port. # INFO: 2657 ns EP LTSSM State: DETECT.ACTIVE # INFO: 3661 ns RP LTSSM State: DETECT.ACTIVE # INFO: 6049 ns EP LTSSM State: POLLING.ACTIVE # INFO: 6909 ns RP LTSSM State: POLLING.ACTIVE # INFO: 9037 ns RP LTSSM State: POLLING.CONFIG # INFO: 9441 ns EP LTSSM State: POLLING.CONFIG # INFO: 10657 ns EP LTSSM State:CONFIG.LINKWIDTH.START # INFO: 10829 ns RP LTSSM State: CONFIG.LINKWIDTH.START # INFO: 11713 ns EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT # INFO: 12253 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT # INFO: 12573 ns RP LTSSM State: CONFIG.LANENUM.WAIT # INFO: 13505 ns EP LTSSM State: CONFIG.LANENUM.WAIT # INFO: 13825 ns EP LTSSM State: CONFIG.LANENUM.ACCEPT # INFO: 13853 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT # INFO: 14173 ns RP LTSSM State: CONFIG.COMPLETE # INFO: 14721 ns EP LTSSM State: CONFIG.COMPLETE # INFO: 16001 ns EP LTSSM State: CONFIG.IDLE # INFO: 16093 ns RP LTSSM State: CONFIG.IDLE # INFO: 16285 ns RP LTSSM State: L0 # INFO: 16545 ns EP LTSSM State: L0 # INFO: 19112 ns Configuring Bus 001, Device 001, Function 00 # INFO: 19112 ns EP Read Only Configuration Registers: # INFO: 19112 ns Vendor ID: 0000 # INFO: 19112 ns Device ID: 0001 # INFO: 19112 ns Revision ID: 01 # INFO: 19112 ns Class Code: 000000 # INFO: 19112 ns Subsystem Vendor ID: 0000 # INFO: 19112 ns Subsystem ID: 0000 # INFO: 19112 ns Interrupt Pin: INTA used # INFO: 20584 ns PCI MSI Capability Register: # INFO: 20584 ns 64-Bit Address Capable: Supported # INFO: 20584 ns Messages Requested: 4 # INFO: 28136 ns EP PCI Express Link Status Register (1041): # INFO: 28136 ns Negotiated Link Width: x4 # INFO: 28136 ns Slot Clock Config: System Reference Clock Used # INFO: 29685 ns RP LTSSM State: RECOVERY.RCVRLOCK # INFO: 30561 ns EP LTSSM State: RECOVERY.RCVRLOCK # INFO: 31297 ns EP LTSSM State: RECOVERY.RCVRCFG # INFO: 31381 ns RP LTSSM State: RECOVERY.RCVRCFG # INFO: 32661 ns RP LTSSM State: RECOVERY.IDLE # INFO: 32961 ns EP LTSSM State: RECOVERY.IDLE # INFO: 33153 ns EP LTSSM State: L0 # INFO: 33237 ns RP LTSSM State: L0 # INFO: 34696 ns Current Link Speed: 2.5GT/s INFO: 34696 ns

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Generating the Example Design

# INFO: 36168 ns EP PCI Express Link Control Register (0040): # INFO: 36168 ns Common Clock Config: System Reference Clock Used # INFO: 37960 ns EP PCI Express Capabilities Register (0002): # INFO: 37960 ns Capability Version: 2 # INFO: 37960 ns Port Type: Native Endpoint # INFO: 37960 ns EP PCI Express Device Capabilities Register(00008020): # INFO: 37960 ns Max Payload Supported: 128 Bytes # INFO: 37960 ns Extended Tag: Supported # INFO: 37960 ns Acceptable L0s Latency: Less Than 64 ns # INFO: 37960 ns Acceptable L1 Latency: Less Than 1 us # INFO: 37960 ns Attention Button: Not Present # INFO: 37960 ns Attention Indicator: Not Present # INFO: 37960 ns Power Indicator: Not Present # INFO: 37960 ns EP PCI Express Link Capabilities Register (01406041): # INFO: 37960 ns Maximum Link Width: x4 # INFO: 37960 ns Supported Link Speed: 2.5GT/s # INFO: 37960 ns L0s Entry: Not Supported # INFO: 37960 ns L1 Entry: Not Supported # INFO: 37960 ns L0s Exit Latency: 2 us to 4 us # INFO: 37960 ns L1 Exit Latency: Less Than 1 us # INFO: 37960 ns Port Number: 01 # INFO: 37960 ns Surprise Dwn Err Report: Not Supported # INFO: 37960 ns DLL Link Active Report: Not Supported # INFO: 37960 ns EP PCI Express Device Capabilities 2 Register (0000001F): # INFO: 37960 ns Completion Timeout Rnge: ABCD (50us to 64s) # INFO: 39512 ns EP PCI Express Device Control Register (0110): # INFO: 39512 ns Error Reporting Enables: 0 # INFO: 39512 ns Relaxed Ordering: Enabled # INFO: 39512 ns Error Reporting Enables: 0 # INFO: 39512 ns Relaxed Ordering: Enabled # INFO: 39512 ns Max Payload: 128 Bytes # INFO: 39512 ns Extended Tag: Enabled # INFO: 39512 ns Max Read Request: 128 Bytes # INFO: 39512 ns EP PCI Express Device Status Register (0000): # INFO: 41016 ns EP PCI Express Virtual Channel Capability: # INFO: 41016 ns Virtual Channel: 1 # INFO: 41016 ns Low Priority VC: 0 # INFO: 46456 ns BAR Address Assignments: # INFO: 46456 ns BAR Size Assigned Address Type # INFO: 46456 ns BAR1:0 4 MBytes 00000001 00000000 Prefetchable # INFO: 46456 ns BAR2 32 KBytes 00200000 Non-Prefetchable # INFO: 46456 ns BAR3 Disabled # INFO: 46456 ns BAR4 Disabled # INFO: 46456 ns BAR5 Disabled # INFO: 46456 ns ExpROM Disabled # INFO: 48408 ns Completed configuration of Endpoint BAR # INFO: 50008 ns Starting Target Write/Read Test. # INFO: 50008 ns Target BAR = 0 # INFO: 50008 ns Length = 000512, Start Offset = 000000 # INFO: 54368 ns Target Write and Read compared okay! # INFO: 54368 ns Starting DMA Read/Write Test. # INFO: 54368 ns Setup BAR = 2 # INFO: 54368 ns Length = 000512, Start Offset = 000000 # INFO: 60609 ns Interrupt Monitor: Interrupt INTA Asserted # INFO: 60609 ns Clear Interrupt INTA # INFO: 62225 ns Interrupt Monitor: Interrupt INTA Deasserted # INFO: 69361 ns MSI recieved! # INFO: 69361ns DMA Read and Write compared okay! # SUCCESS: Simulation stopped due to successful completion! # Break at .ep_g1x4_tb/simulation/submodules//altpcietb_bfm_log.v line 78

2-5

Related Information

Simulating Altera Designs

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2-6

Understanding Simulation Log File Generation

Starting with the Quartus II 14.0 software release, simulation automatically creates a log file, altpcie_

monitor_<dev>_dlhip_tlp_file_log.log in your simulation directory.

Table 2-2: Sample Simulation Log File Entries

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Time TLP Type Payload

(Bytes)

17989 RX CfgRd0 0004 04000001_0000000F_01080008 17989 RX MRd 0000 00000000_00000000_01080000 18021 RX CfgRd0 0004 04000001_0000010F_0108002C 18053 RX CfgRd0 0004 04000001_0000030F_0108003C 18085 RX MRd 0000 00000000_00000000_0108000C

Running A Gate-Level Simulation

The PCI Express testbenches run simulations at the register transfer level (RTL). However, it is possible to create you own gate-level simulations. Contact your Altera Sales Representative for instructions and an example that illustrate how to create a gate-level simulation from the RTL testbench.

Simulating the Single DWord Design

You can use the same testbench to simulate the Completer-Only Single Dword IP core by changing the settings in the driver file.

TLP Header

1. In a terminal window, change to the <project_dir>/<variant>/testbench/<variant>_tb/simulation/submodules

2. Open altpcietb_bfm_driver_avmm.v in your text editor.

3. To enable target memory tests and specify the completer-only single dword variant, specify the

4. Change to the <project_dir>/variant/testbench/mentor directory.

5. Start the ModelSim simulator.

6. To run the simulation, type the following commands in a terminal window:

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directory.

following parameters:

a. parameter RUN_TGT_MEM_TST = 1; b. parameter RUN_DMA_MEM_TST = 0; c. parameter AVALON_MM_LITE = 1;

a. do msim_setup.tcl b. ld_debug (The debug suffix stops optimizations, improving visibility in the ModelSim waveforms.) c. run 140000 ns

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Generating Quartus II Synthesis Files

1. On the Generate menu, select Generate HDL.

2. For Create HDL design files for synthesis, select Verilog.

You can leave the default settings for all other items.

3. Click Generate to generate files for Quartus II synthesis.

4. Click Finish when the generation completes.

Creating a Quartus II Project

You can create a new Quartus II project with the New Project Wizard, which helps you specify the working directory for the project, assign the project name, and designate the name of the top-level design entity.

1. On the Quartus II File menu, click then New Project Wizard, then Next.

2. Click Next in the New Project Wizard: Introduction (The introduction does not appear if you

previously turned it off.)

3. On the Directory, Name, Top-Level Entity page, enter the following information:

Generating Quartus II Synthesis Files

2-7

a. For What is the working directory for this project, browse to <project_dir>/ep_g2x4/synthesis/. b. For What is the name of this project, select ep_g2x4.v from the synthesis directory.

4. Click Next.

5. On the Add Files page, add<project_dir>/ep_g2x4/synthesis/ep_g2_x4.qip to your Quartus II project. This

file lists all necessary files for Quartus II compilation.

6. Click Next to display the Family & Device Settings page.

7. On the Device page, choose the following target device family and options: a. In the Family list, select Stratix V (GS/GT/GX/E).

b. In the Devices list, select Stratix V GX PCIe. c. In the Available devices list, select 5SGXEA7K2F40C2.

8. Click Next to close this page and display the EDA Tool Settings page.

9. From the Simulation list, select ModelSim. From the Format list, select the HDL language you intend

to use for simulation.

10.Click Next to display the Summary page.

11.Check the Summary page to ensure that you have entered all the information correctly.

Compiling the Design

1. Before compiling, you need to make a few changes to your top-level Verilog HDL file to create a design that you can successfully download to a PCB.

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Programming a Device

a. In the <project_dir>/ep_g2x4_avmm128/synth/, open ep_g2x4_avmm128.v. b. Comment out the declaration for pcie_a10_hip_0_hip_ctrl_test_in. c. Add a wire [31:0] pcie_a10_hip_0_hip_ctrl_test_in declaration to the same the same file. d. Assign pcie_a10_hip_0_hip_ctrl_test_in = 0x000000A8. e. Connect pcie_a10_hip_0_hip_ctrl_test_in to the test_in port on the Stratix V Hard IP for

PCI Express instance.

2. On the Quartus II Processing menu, click Start Compilation.

3. After compilation, expand the TimeQuest Timing Analyzer folder in the Compilation Report. Note

whether the timing constraints are achieved in the Compilation Report.

If your design does not initially meet the timing constraints, you can find the optimal Fitter settings for your design by using the Design Space Explorer. To use the Design Space Explorer, click Launch Design Space Explorer on the Tools menu.

Programming a Device

After you compile your design, you can program your targeted Altera device and verify your design in hardware.

For more information about programming Altera FPGAs, refer to Quartus II Programmer.

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Related Information

Quartus II Programmer

Understanding Channel Placement Guidelines

Stratix V transceivers are organized in banks of six channels. The transceiver bank boundaries are important for clocking resources, bonding channels, and fitting. Refer to the channel placement figures following Serial Interface Signals for illustrations of channel placement for x1, x2, x4, and x8 variants.

Related Information

Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices on page 4-29

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Parameter Settings

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Stratix V and Arria V GZ Avalon-MM System Settings

Table 3-1: System Settings for PCI Express

Parameter Value Description

Number of Lanes x1, x2, x4, x8 Specifies the maximum number of lanes supported.

Lane Rate Gen1 (2.5 Gbps)

Gen2 (2.5/5.0 Gbps)

Gen3 (2.5/5.0/8.0

Gbps)

Port type Native Endpoint

Root Port

Specifies the maximum data rate at which the link can operate.

Specifies the port type. Altera recommends Native Endpoint for all new Endpoint designs. Select Legacy Endpoint only when you require I/O transaction support for compatibility.

The Endpoint stores parameters in the Type 0 Configuration Space. The Root Port stores parameters in the Type 1 Configu‐ ration Space.

RX Buffer credit allocation performance for received requests

Minimum

Low

Balanced

Determines the allocation of posted header credits, posted data credits, non-posted header credits, completion header credits, and completion data credits in the 16 KByte RX buffer. The 5 settings allow you to adjust the credit allocation to optimize your system. The credit allocation for the selected setting displays in the message pane.

Refer to the Throughput Optimization chapter for more information about optimizing performance. The Flow Control chapter explains how the RX credit allocation and the

Maximum payload RX Buffer credit allocation and the Maximum payload size that you choose affect the allocation

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Stratix V and Arria V GZ Avalon-MM System Settings

Parameter Value Description

of flow control credits. You can set the Maximum payload size parameter on the Device tab.

The Message window dynamically updates the number of credits for Posted, Non-Posted Headers and Data, and Completion Headers and Data as you change this selection.

• Minimum—configures the minimum PCIe specification

allowed for non-posted and posted request credits, leaving most of the RX Buffer space for received completion header and data. Select this option for variations where application logic generates many read requests and only infrequently receives single requests from the PCIe link.

• Low—configures a slightly larger amount of RX Buffer

space for non-posted and posted request credits, but still dedicates most of the space for received completion header and data. Select this option for variations where application logic generates many read requests and infrequently receives small bursts of requests from the PCIe link. This option is recommended for typical endpoint applications where most of the PCIe traffic is generated by a DMA engine that is located in the endpoint application layer logic.

• Balanced—configures approximately half the RX Buffer

space to received requests and the other half of the RX Buffer space to received completions. Select this option for variations where the received requests and received completions are roughly equal.

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Reference clock frequency

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100 MHz 125 MHz

The PCI Express Base Specification 3.0 requires a 100 MHz ±300 ppm reference clock. The 125 MHz reference clock is provided as a convenience for systems that include a 125 MHz clock source. For more information about Gen3 operation, refer to 4.3.8 Refclk Specifications for 8.0 GT/sin the specification.

For Gen3, Altera recommends using a common reference clock (0 ppm) because when using separate reference clocks (non 0 ppm), the PCS occasionally must insert SKP symbols, potentially causes the PCIe link to go to recovery. Stratix V PCIe Hard IP in Gen1 or Gen2 modes are not affected by this issue. Systems using the common reference clock (0 ppm) are not affected by this issue. The primary repercussion of this is a slight decrease in bandwidth. On Gen3 x8 systems, this bandwidth impact is negligible. If non 0 ppm mode is required, so that separate reference clocks are being used, please contact Altera for further information and guidance.

Parameter Settings

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Base Address Register (BAR) Settings

Parameter Value Description

3-3

Use 62.5 MHz

On/Off This mode is only available only for Gen1 ×1.

application clock

Enable configu‐ ration via PCI Express (CvP)

On/Off When On, the Quartus II software places the Endpoint in the

location required for configuration via protocol (CvP). For more information about CvP, click the Configuration via Protocol (CvP) link below.

Use ATX PLL On/Off When enabled, the Hard IP for PCI Express uses the ATX PLL

instead of the CMU PLL. For other configurations, using the ATX PLL instead of the CMU PLL reduces the number of transceiver channels that are necessary. This option requires the use of the soft reset controller and does not support the CvP flow.

Enable Hard IP reset pulse at power-up when using the soft reset controller

On/Off

When On, the soft reset controller generates a pulse at power up to reset the Hard IP. This pulse ensures that the Hard IP is reset after programming the device, regardless of the behavior of the dedicated PCI Express reset pin, perstn. This option is available for Gen2 and Gen3 designs that use a soft reset controller.

Related Information

PCI Express Base Specification 2.1 or 3.0

Base Address Register (BAR) Settings

You can configure up to six 32-bit BARs or three 64-bit BARs.

Table 3-2: BAR Registers

Parameter Value Description

Type

64-bit prefetchable memory

32-bit non-prefetchable memory

32-bit prefetchable memory

Parameter Settings

Disabled

I/O address space

Defining memory as prefetchable allows data in the region to be fetched ahead anticipating that the requestor may require more data from the same region than was originally requested. If you specify that a memory is prefetchable, it must have the following 2 attributes:

• Reads do not have side effects

• Write merging is allowed The 32-bit prefetchable memory and I/O address

space BARs are only available for the Legacy Endpoint.

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Device Identification Registers

Parameter Value Description

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Size

Not configurable

Specifies the memory size calculated from other parameters you enter.

Device Identification Registers

Table 3-3: Device ID Registers

The following table lists the default values of the read-only Device ID registers. You can use the parameter editor to change the values of these registers. Refer to Type 0 Configuration Space Registers for the layout of the Device Identification registers.

Vendor ID 16 bits 0x00000000 Sets the read-only value of the Vendor ID register. This

parameter cannot be set to 0xFFFF, per the PCI Express Specification.

Address offset: 0x000.

Device ID 16 bits 0x00000001 Sets the read-only value of the Device ID register. This

Address offset: 0x000.

Revision ID 8 bits 0x00000001 Sets the read-only value of the Revision ID register.

Address offset: 0x008.

Class code 24 bits 0x00000000 Sets the read-only value of the Class Code register.

Address offset: 0x008.

Subsystem Vendor ID

16 bits 0x00000000 Sets the read-only value of the Subsystem Vendor ID

register in the PCI Type 0 Configuration Space. This parameter cannot be set to 0xFFFF per the PCI Express Base Specification. This value is assigned by PCI-SIG to the device manufacturer. This register is only valid in the Type 0 (Endpoint) Configuration Space.

Address offset: 0x02C.

Subsystem Device ID

16 bits 0x00000000 Sets the read-only value of the Subsystem Device ID

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Parameter Settings

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Related Information

PCI Express Base Specification 2.1 or 3.0

PCI Express and PCI Capabilities Parameters

This group of parameters defines various capability properties of the IP core. Some of these parameters are stored in the PCI Configuration Space - PCI Compatible Configuration Space. The byte offset indicates the parameter address.

Device Capabilities

Table 3-4: Capabilities Registers

Parameter Possible Values Default Value Description

PCI Express and PCI Capabilities Parameters

3-5

Maximum payload size

Completion timeout range

128 bytes 256 bytes

ABCD

BCD ABC

None

128 bytes Specifies the maximum payload size supported. This

parameter sets the read-only value of the max payload size supported field of the Device Capabilities register (0x084[2:0]). Address: 0x084.

ABCD Indicates device function support for the optional

completion timeout programmability mechanism. This mechanism allows the system software to modify the completion timeout value. This field is applicable only to Root Ports and Endpoints that issue requests on their own behalf. Completion timeouts are specified and enabled in the Device Control 2 register (0x0A8) of the PCI Express Capability Structure Version. For all other functions this field is reserved and must be hardwired to 0x0000b. Four time value ranges are defined:

• Range A: 50 us to 10 ms

• Range B: 10 ms to 250 ms

• Range C: 250 ms to 4 s

• Range D: 4 s to 64 s Bits are set to show timeout value ranges supported. The

function must implement a timeout value in the range 50 sto 50 ms. The following values specify the range:

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• None—Completion timeout programming is not supported

• 0001 Range A

• 0010 Range B

• 0011 Ranges A and B

• 0110 Ranges B and C

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3-6

Error Reporting

Parameter Possible Values Default Value Description

• 0111 Ranges A, B, and C

• 1110 Ranges B, C and D

• 1111 Ranges A, B, C, and D

All other values are reserved. Altera recommends that the completion timeout mechanism expire in no less than 10 ms.

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Implement completion timeout disable

On/Off On For Endpoints using PCI Express version 2.1 or 3.0, this

option must be On. The timeout range is selectable. When On, the core supports the completion timeout disable mechanism via the PCI Express Device

Control Register 2. The Application Layer logic must

implement the actual completion timeout mechanism for the required ranges.

Error Reporting

Table 3-5: Error Reporting

Parameter Value Default Value Description

Advanced error reporting (AER)

Enable ECRC checking

On/Off Off When On, enables the Advanced Error Reporting (AER)

capability.

On/Off Off When On, enables ECRC checking. Sets the read-only

value of the ECRC check capable bit in the Advanced

Error Capabilities and Control Register. This

parameter requires you to enable the AER capability.

Enable ECRC generation

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On/Off Off

When On, enables ECRC generation capability. Sets the read-only value of the ECRC generation capable bit in the Advanced Error Capabilities and Control

AER capability.

Parameter Settings

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Parameter Value Default Value Description

Link Capabilities

3-7

Enable ECRC forwarding on the Avalon-ST interface

On/Off Off When On, enables ECRC forwarding to the Application

Layer. On the Avalon-ST RX path, the incoming TLP contains the ECRC dword

(1)

and the TD bit is set if an ECRC exists. On the transmit the TLP from the Applica‐ tion Layer must contain the ECRC dword and have the

TD bit set.

Not applicable for Avalon-MM or Avalon-MM DMA interfaces.

Track RX completion buffer overflow on the AvalonST interface

On/Off Off When On, the core includes the rxfx_cplbuf_ovf

output status signal to track the RX posted completion buffer overflow status.

Not applicable for Avalon-MM or Avalon-MM DMA interfaces.

Note:

1. Throughout this user guide, the terms word, dword and qword have the same meaning that they have

in the PCI Express Base Specification. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.

Related Information

PCI Express Base Specification Revision 2.1 or 3.0

Link Capabilities

Table 3-6: Link Capabilities

Parameter Value Description

Link port number

Slot clock configuration

0x01 Sets the read-only value of the port number field in the Link

Capabilities Register.

On/Off When On, indicates that the Endpoint or Root Port uses the

same physical reference clock that the system provides on the connector. When Off, the IP core uses an independent clock regardless of the presence of a reference clock on the connector.

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MSI and MSI-X Capabilities

Table 3-7: MSI and MSI-X Capabilities

Parameter Value Description

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MSI messages requested

1, 2, 4, 8, 16 Specifies the number of messages the Application Layer can

request. Sets the value of the Multiple Message Capable field of the Message Control register, 0x050[31:16].

MSI-X Capabilities

Implement MSI-X On/Off When On, enables the MSI-X functionality.

Bit Range

Table size [10:0] System software reads this field to determine the MSI-X Table

size <n>, which is encoded as <n–1>. For example, a returned value of 2047 indicates a table size of 2048. This field is readonly. Legal range is 0–2047 (211).

Address offset: 0x068[26:16]

Table Offset [31:0] Points to the base of the MSI-X Table. The lower 3 bits of the

table BAR indicator (BIR) are set to zero by software to form a 32-bit qword-aligned offset. This field is read-only.

Table BAR Indicator

[2:0] Specifies which one of a function’s BARs, located beginning at

0x10 in Configuration Space, is used to map the MSI-X table into memory space. This field is read-only. Legal range is 0–5.

Pending Bit Array (PBA) Offset

PBA BAR Indicator

Related Information

PCI Express Base Specification Revision 2.1 or 3.0

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[31:0] Used as an offset from the address contained in one of the

function’s Base Address registers to point to the base of the MSI-X PBA. The lower 3 bits of the PBA BIR are set to zero by software to form a 32-bit qword-aligned offset. This field is read-only.

[2:0] Specifies the function Base Address registers, located

beginning at 0x10 in Configuration Space, that maps the MSIX PBA into memory space. This field is read-only. Legal range is 0–5.

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Power Management

Table 3-8: Power Management Parameters

Parameter Value Description

Power Management

3-9

Endpoint L0s acceptable latency

Endpoint L1 acceptable latency

Maximum of 64 ns Maximum of 128 ns Maximum of 256 ns Maximum of 512 ns Maximum of 1 us Maximum of 2 us Maximum of 4 us No limit

Maximum of 1 us Maximum of 2 us Maximum of 4 us Maximum of 8 us Maximum of 16 us Maximum of 32 us No limit

This design parameter specifies the maximum acceptable latency that the device can tolerate to exit the L0s state for any links between the device and the root complex. It sets the read-only value of the Endpoint L0s acceptable latency field of the Device Capabilities Register (0x084).

This Endpoint does not support the L0s or L1 states. However, in a switched system there may be links connected to switches that have L0s and L1 enabled. This parameter is set to allow system configuration software to read the acceptable latencies for all devices in the system and the exit latencies for each link to determine which links can enable Active State Power Management (ASPM). This setting is disabled for Root Ports.

The default value of this parameter is 64 ns. This is the safest setting for most designs.

This value indicates the acceptable latency that an Endpoint can withstand in the transition from the L1 to L0 state. It is an indirect measure of the Endpoint’s internal buffering. It sets the read-only value of the Endpoint L1 acceptable latency field of the Device Capabilities Register.

This Endpoint does not support the L0s or L1 states. However, a switched system may include links connected to switches that have L0s and L1 enabled. This parameter is set to allow system configuration software to read the acceptable latencies for all devices in the system and the exit latencies for each link to determine which links can enable Active State Power Management (ASPM). This setting is disabled for Root Ports.

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The default value of this parameter is 1 µs. This is the safest setting for most designs.

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3-10

Avalon Memory‑Mapped System Settings

Table 3-9: Avalon Memory-Mapped System Settings

Parameter Value Description

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Avalon-MM data width

Avalon-MM address width

Peripheral mode

64-bit

128-bit

32-bit 64-bit

Requester/ Completer

Completer-Only

Specifies the data width for the Application Layer to Transaction Layer interface. Refer to Application

Layer Clock Frequencies for All Combinations of Link Width, Data Rate and Application Layer Interface Widths for all legal combinations of data width,

number of lanes, Application Layer clock frequency, and data rate.

Specifies the address width for Avalon-MM RX master ports that access Avalon-MM slaves in the Avalon address domain. When you select 32-bit addresses, the PCI Express Avalon-MM Bridge performs address translation. When you specify 64bits addresses, no address translation is performed in either direction. The destination address specified is forwarded to the Avalon-MM interface without any changes.

For the Avalon-MM interface with DMA, this value must be set to 64.

Specifies whether the Avalon-MM Stratix V Hard IP for PCI Express is capable of sending requests to the upstream PCI Express devices, and whether the incoming requests are pipelined.

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Requester/Completer—In this mode, the Hard IP can send request packets on the PCI Express TX link and receive request packets on the PCI Express RX link.

Completer-Only—In this mode, the Hard IP can receive requests, but cannot initiate upstream requests. However, it can transmit completion packets on the PCI Express TX link. This mode removes the Avalon-MM TX slave port and thereby reduces logic utilization.

Parameter Settings

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Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Datasheet

Stratix V Avalon-MM Interface for PCIe Datasheet

Features

Release Information

Device Family Support

Configurations

Example Designs

Debug Features

IP Core Verification

Compatibility Testing Environment

Performance and Resource Utilization

Recommended Speed Grades

Steps in Creating a Design for PCI Express

Running Qsys

Generating the Example Design

Understanding Simulation Log File Generation

Running A Gate-Level Simulation

Simulating the Single DWord Design

Generating Quartus II Synthesis Files

Creating a Quartus II Project

Compiling the Design

Programming a Device

Understanding Channel Placement Guidelines

Parameter Settings

Stratix V and Arria V GZ Avalon-MM System Settings

Base Address Register (BAR) Settings

Device Identification Registers

PCI Express and PCI Capabilities Parameters

Device Capabilities

Error Reporting

Link Capabilities

MSI and MSI-X Capabilities

Power Management

Avalon Memory‑Mapped System Settings