Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual

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Stratix V Avalon-MM Interface for PCIe Solutions

User Guide

Last updated for Altera Complete Design Suite: 14.1

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Bridge

PCIe Hard IP

Block

PIPE

Interface

PHY IP Core

for PCIe

(PCS/PMA)

Serial Data

Transmission

Application

Layer

(User Logic)

Avalon-MM

Interface

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Stratix V Avalon-MM Interface for PCIe Datasheet

Altera® Stratix® V FPGAs include a configurable, hardened protocol stack for PCI Express compliant with PCI Express Base Specification 2.1 or 3.0.

The Hard IP for PCI Express IP core using the Avalon ® Memory-Mapped (Avalon-MM) interface removes some of the complexities associated with the PCIe protocol. For example, it handles all of the Transaction Layer Protocol (TLP) encoding and decoding. Consequently, you can complete your design more quickly. The Avalon-MM interface is implemented as a bridge in soft logic. It is available in Qsys.

Figure 1-1: Stratix V PCIe Variant with Avalon-MM Interface

The following figure shows the high-level modules and connecting interfaces for this variant.

that is

Table 1-1: PCI Express Data Throughput

The following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for 1, 2, 4, and 8 lanes. The protocol specifies 2.5 giga-transfers per second for Gen1, 5.0 giga-transfers per second for Gen2, and 8.0 giga-transfers per second for Gen3. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead. In contrast, Gen3 uses 128b/130b encoding which reduces the data throughput lost to encoding to less than 1%.

PCI Express Gen1 (2.5 Gbps)

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Link Width in Gigabits Per Second (Gbps)

x1 x2 x4 x8

2 4 8 16

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1-2

Features

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Link Width in Gigabits Per Second (Gbps)

x1 x2 x4 x8

PCI Express Gen2 (5.0 Gbps)

PCI Express Gen3 (8.0 Gbps)

Refer to the PCI Express Reference Design for Stratix V Devices for more information about calculating bandwidth for the hard IP implementation of PCI Express in many Altera FPGAs, including the Stratix V Hard IP for PCI Express IP core.

Related Information

• PCI Express Base Specification 2.1 or 3.0

• PCI Express DMA Reference Design for Stratix V Devices

• Creating a System with Qsys

Features

New features in the Quartus® II 14.1 software release:

• Reduced Quartus II compilation warnings by 50%. The Stratix V Hard IP for PCI Express with the Avalon-MM interface supports the following features:

4 8 16 32

7.87 15.75 31.51 63

• Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as hard IP.

• Support for ×1, ×2, ×4, and ×8 configurations with Gen1, Gen2, or Gen3 lane rates for Root Ports and Endpoints.

• Dedicated 16 KByte receive buffer.

• Optional hard reset controller for Gen2.

• Optional support for Configuration via Protocol (CvP) using the PCIe link allowing the I/O and core bitstreams to be stored separately.

• Support for 32- or 64-bit addressing for the Avalon-MM interface to the Application Layer.

• Qsys example designs demonstrating parameterization, design modules, and connectivity.

• Extended credit allocation settings to better optimize the RX buffer space based on application type.

• Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error reporting (AER) for high reliability applications.

• Support for Configuration Space Bypass Mode, allowing you to design a custom Configuration Space and support multiple functions.

• Support for Gen3 PIPE simulation.

• Easy to use:

• Flexible configuration.

• No license requirement.

• Example designs to get started.

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Table 1-2: Feature Comparison for all Hard IP for PCI Express IP Cores

The table compares the features of the four Hard IP for PCI Express IP Cores.

Features

1-3

Feature Avalon‑ST Interface Avalon‑MM

Interface

Avalon‑MM DMA Avalon‑ST Interface with SR-

IP Core License Free Free Free Free

Native

Supported Supported Supported Supported

Endpoint

Legacy Endpoint

(1)

Supported Not Supported Not Supported Not Supported

Root port Supported Supported Not Supported Not Supported

Gen1 ×1, ×2, ×4, ×8 ×1, ×2, ×4, ×8 Not Supported

Gen2 ×1, ×2, ×4, ×8 ×1, ×2, ×4, ×8 ×4, ×8

Gen3 ×1, ×2, ×4, ×8 ×1, ×2, ×4 ×4, ×8

64-bit Applica‐

Supported Supported Not supported Not supported

×8

×4, ×8

×2, ×4, ×8

tion Layer interface

IOV

128-bit

Supported Supported Supported Supported Application Layer interface

256-bit

Supported Not Supported Supported Supported Application Layer interface

(1)

Not recommended for new designs.

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Features

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Feature Avalon‑ST Interface Avalon‑MM

Interface

Transaction Layer Packet type (TLP)

• Memory Read Request

• Memory Read RequestLocked

• Memory Write Request

• I/O Read Request

• I/O Write Request

• Configuration Read Request (Root Port)

• Configuration Write Request (Root Port)

• Message Request

• Message Request with Data Payload

• Completion Message

• Completion with Data

• Memory Read Request

• Memory Write Request

• I/O Read Request—Root Port only

• I/O Write Request—Root Port only

• Configuration Read Request (Root Port)

• Configuration Write Request (Root Port)

• Completion Message

• Completion with Data

• Memory Read Request (single dword)

• Memory Write Request (single dword)

• Completion for Locked Read without Data

Avalon‑MM DMA Avalon‑ST Interface with SR-

IOV

• Memory Read Request

• Memory Write Request

• Completion Message

• Completion with Data

• Memory Read Request

• Memory Write Request

• Configuration Read Request (from Root Port)

• Configuration Write Request (from Root Port)

• Message Request

• Completion Message

• Completion with Data

Payload size

Number of tags supported for non-posted requests

62.5 MHz clock Supported Supported Not Supported Not Supported

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128–2048 bytes 128–256 bytes 128, 256, 512 bytes 128–256 bytes

256 8 16 256

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Features

1-5

Feature Avalon‑ST Interface Avalon‑MM

Interface

Out-of-order

Not supported Supported Supported Not supported completions (transparent to the Application Layer)

Requests that

Not supported Supported Supported Supported cross 4 KByte address boundary (transparent to the Application Layer)

Polarity

Supported Supported Supported Supported Inversion of PIPE interface signals

Avalon‑MM DMA Avalon‑ST Interface with SR-

IOV

ECRC

Supported Not supported Not supported Not supported forwarding on RX and TX

Number of MSI requests

1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 (for

Physical Functions)

MSI-X Supported Supported Supported Supported

Legacy

Supported Supported Supported Supported interrupts

Expansion

Supported Not supported Not supported Not supported ROM

The Stratix VAvalon-MM Interface for PCIe Solutions User Guide explains how to use this IP core and not the PCI Express protocol. Although there is inevitable overlap between these two purposes, use this document only in conjunction with an understanding of the PCI Express Base Specification.

Note:

This release provides separate user guides for the different variants. The Related Information provides links to all versions.

Related Information

Datasheet

• Stratix V Avalon-MM Interface for PCIe Solutions User Guide

• Stratix V Avalon-ST Interface for PCIe Solutions User Guide

• Stratix V Avalon-ST Interface with SR-IOV for PCIe Solutions User Guide

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Release Information

• V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

Release Information

Table 1-3: Hard IP for PCI Express Release Information

Item Description

Version 14.1

Release Date December 2014

Ordering Codes No ordering code is required

Product IDs There are no encrypted files for the Stratix V Hard

IP for PCI Express. The Product ID and Vendor ID

Vendor ID

are not required because this IP core does not require a license.

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Device Family Support

Table 1-4: Device Family Support

Device Family Support

Stratix V Final. The IP core is verified with final timing

models. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

Other device families Refer to the Related Information below for other

device families:

Related Information

• Arria V Avalon-MM Interface for PCIe Solutions User Guide

• Arria V Avalon-ST Interface for PCIe Solutions User Guide

• Arria V GZ Avalon-MM Interface for PCIe Solutions User Guide

• Arria V GZ Avalon-ST Interface for PCIe Solutions User Guide

• Arria 10 Avalon-MM Interface for PCIe Solutions User Guide

• Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide

• Arria 10 Avalon-ST Interface for PCIe Solutions User Guide

• Cyclone V Avalon-MM Interface for PCIe Solutions User Guide

• Cyclone V Avalon-ST Interface for PCIe Solutions User Guide

• IP Compiler for PCI Express User Guide

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Altera FPGA

User Application

Logic

PCIe

Hard IP

PCIe

Hard IP

User Application

Logic

PCI Express Link

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Configurations

The Avalon-MM Stratix V Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stack comprising the following layers:

• Physical (PHY), including:

• Media Access Control (MAC)

• Data Link Layer (DL)

• Transaction Layer (TL) When configured as an Endpoint, the Stratix V Hard IP for PCI Express using the Avalon-MM supports

memory read and write requests and completions with or without data.

Figure 1-2: PCI Express Application with a Single Root Port and Endpoint

The following figure shows a PCI Express link between two Stratix V FPGAs.

• Physical Media Attachment (PMA)

• Physical Coding Sublayer (PCS)

Configurations

1-7

Datasheet

Figure 1-3: PCI Express Application Using Configuration via Protocol

The Stratix V design below includes the following components:

• A Root Port that connects directly to a second FPGA that includes an Endpoint.

• Two Endpoints that connect to a PCIe switch.

• A host CPU that implements CvP using the PCI Express link connects through the switch. For more

information about configuration over a PCI Express link, refer to Configuration via Protocol (CvP) on page 13-1.

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PCIe Link

PCIe Hard IP

Switch

PCIe

Hard IP

User Application

Logic

PCIe Hard IP

PCIe Link

User Application

Logic

Altera FPGA Hard IP for PCI Express

Altera FPGA with Hard IP for PCI Express

Active Serial or

Active Quad

Device Configuration

Configuration via Protocol (CvP)

using the PCI Express Link

Serial or

Quad Flash

USB

Download

cable

PCIe

Hard IP

User

Application

Logic

Altera FPGA with Hard IP for PCI Express

Config Control

CVP

USB

Host CPU

PCIe

1-8

Example Designs

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Related Information

Configuration via Protocol (CvP)Implementation in Altera FPGAs User Guide

Example Designs

The following Qsys example designs are available for the Avalon-MM Stratix V Hard IP for PCI Express IP Core. You can download them from the <install_dir>/ip/altera/altera_pcie/altera_pcie_<dev>__hip_avmm/

example_designs directory:

• ep_g1x1.qsys

• ep_g1x4.qsys

• ep_g1x8.qsys

• ep_g2x1.qsys

• ep_g2x4.qsys

• ep_g2x8.qsys

Related Information

Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express on page 2-1

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Debug Features

Debug features allow observation and control of the Hard IP for faster debugging of system-level problems.

Related Information

Debugging on page 14-1

IP Core Verification

To ensure compliance with the PCI Express specification, Altera performs extensive verification. The simulation environment uses multiple testbenches that consist of industry-standard bus functional models (BFMs) driving the PCI Express link interface. Altera performs the following tests in the simulation environment:

• Directed and pseudorandom stimuli are applied to test the Application Layer interface, Configuration Space, and all types and sizes of TLPs

• Error injection tests that inject errors in the link, TLPs, and Data Link Layer Packets (DLLPs), and check for the proper responses

• PCI-SIG® Compliance Checklist tests that specifically test the items in the checklist

• Random tests that test a wide range of traffic patterns

Debug Features

1-9

Altera provides the following two example designs that you can leverage to test your PCBs and complete compliance base board testing (CBB testing) at PCI-SIG.

Related Information

• PCI SIG Gen3 x8 Merged Design - Stratix V

• PCI SIG Gen2 x8 Merged Design - Stratix V

Compatibility Testing Environment

Altera has performed significant hardware testing to ensure a reliable solution. In addition, Altera internally tests every release with motherboards and PCI Express switches from a variety of manufac‐ turers. All PCI-SIG compliance tests are run with each IP core release.

Performance and Resource Utilization

Because the PCIe protocol stack is implemented in hardened logic, it uses less than 1% of device resources.

The Avalon-MM soft logic bridge functions as a front end to the hardened protocol stack. The following table shows the typical device resource utilization for selected configurations using the current version of the Quartus II software. With the exception of M20K memory blocks, the numbers of ALMs and logic registers are rounded up to the nearest 50.

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Recommended Speed Grades

Table 1-5: Performance and Resource Utilization Avalon-MM Hard IP for PCI Express

Interface Width ALMs M20K Memory Blocks Logic Registers

Avalon-MM Bridge

64 1100 17 1500

128 1900 25 2900

Avalon-MM Interface–Completer Only

64 650 8 1000

128 1400 12 2400

Avalon-MM–Completer Only Single Dword

64 250 0 350

Note: Soft calibration of the transceiver module requires additional logic. The amount of logic required

depends upon the configuration.

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Related Information

Fitter Resources Reports

Recommended Speed Grades

Table 1-6: Stratix V Recommended Speed Grades for All Avalon-MM Widths and Frequencies

Lane Rate Link Width Interface Width Application Clock

Frequency (MHz)

Gen1 ×8 128 Bits 125 –1, –2, –3, –4

×4 128 bits 125 –1, –2, –3, –4

Gen2

×8 128 bits 250 –1, –2, –3

×2 128 bits 125 –1, –2, –3

Gen3

×4 128 bits 250 –1, –2, –3

Recommended Speed Grades

(2)

The -4 speed grade is also possible for this configuration; however, it requires significant effort by the end user to close timing.

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×8 256 bits 250 –1, –2, –3

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Related Information

• Area and Timing Optimization

• Altera Software Installation and Licensing Manual

• Setting up and Running Analysis and Synthesis

Steps in Creating a Design for PCI Express

Before you begin

Select the PCIe variant that best meets your design requirements.

• Is your design an Endpoint or Root Port?

• What Generation do you intend to implement?

• What link width do you intend to implement?

• What bandwidth does your application require?

• Does your design require CvP?

1. Select parameters for that variant.

2. Simulate using an Altera-provided example design. All of Altera's PCI Express example designs are

available under <install_dir>/ip/altera/altera_pcie/. Alternatively, create a simulation model and use your own custom or third-party BFM. The Qsys Generate menu generates simulation models. Altera supports ModelSim-Altera for all IP. The PCIe cores support the Aldec RivieraPro, Cadence NCsim, Mentor Graphics ModelSim, and Synopsys VCS and VCS-MX simulators.

3. Compile your design using the Quartus II software. If the versions of your design and the Quartus II software you are running do not match, regenerate your PCIe design.

4. Download your design to an Altera development board or your own PCB. Click on the All Develop‐ ment Kits link below for a list of Altera's development boards.

5. Test the hardware. You can use Altera's SignalTap® II Logic Analyzer or a third-party protocol analyzer to observe behavior.

6. Substitute your Application Layer logic for the Application Layer logic in Altera's testbench. Then repeat Steps 3–6. In Altera's testbenches, the PCIe core is typically called the DUT (device under test). The Application Layer logic is typically called APPS.

Steps in Creating a Design for PCI Express

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Datasheet

Related Information

• Parameter Settings on page 3-1

• Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express on page 2-1

• All Development Kits

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Getting Started with the Avalon‑MM Stratix V

Transaction,

Data Link,

and PHY

Layers

O n-C hip

Memory

DMA

Qsys System Design for PCI Express

PCI Express

Link

PCI

Express

Avalon-MM

Bridge

Interconnect

Avalon-MM Hard IP for PCI Express

Transceiver

Reconfiguration

Controller

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Hard IP for PCI Express

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You can download a design example for the Avalon-MM Stratix V Hard IP for PCI Express from the

<install_dir>/ip/altera/altera_pcie/altera_pcie-<dev>_hip_avmm/example_designs directory. This walkthrough

uses a Gen2 x4 Endpoint, ep_g2x4.qsys. The design examples contain the following components:

• Avalon-MM Stratix V Hard IP for PCI Express IP core

• On-Chip memory

• DMA controller

• Transceiver Reconfiguration Controller

• Two Avalon-MM pipeline bridges

Figure 2-1: Qsys Generated Endpoint

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ISO 9001:2008 Registered

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Running Qsys

The design example transfers data between an on-chip memory buffer located on the Avalon-MM side and a PCI Express memory buffer located on the root complex side. The data transfer uses the DMA component which is programmed by the PCI Express software application running on the Root Complex processor.

The example design also includes the Transceiver Reconfiguration Controller which allows you to dynamically reconfigure transceiver settings. This component is necessary for high performance transceiver designs.

Related Information

• Generating the Example Design on page 2-3

• Creating a System with Qsys

This document provides an introduction to Qsys.

Running Qsys

1. Choose Programs > Altera > Quartus II><version_number> (Windows Start menu) to run the

Quartus II software. Alternatively, you can also use the Quartus II Web Edition software.

2. On the File menu, select New, then Qsys System File.

3. Open the ep_g2x4.qsys example design.

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The following figure shows a Qsys system that includes the Transceiver Reconfiguration Controller and the Altera PCIe Reconfig Driver IP Cores. The Transceiver Reconfiguration Controller performs dynamic reconfiguration of the analog transceiver settings to optimize signal quality. You must include these components to the Qsys system to run successfully in hardware.

Figure 2-2: Qsys Avalon-MM Design for PCIe with Transceiver Reconfiguration Components

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Refer to Creating a System with Qsys in volume 1 of the Quartus II Handbook for more information about how to use Qsys. For an explanation of each Qsys menu item, refer to About Qsys in Quartus II Help.

Related Information

• Creating a System with Qsys

• About Qsys

Generating the Example Design

1. On the Generate menu, select Generate Testbench System. The Generation dialog box appears.

2. Under Testbench System, set the following options: a. For Create testbench Qsys system, select Standard, BFMs for standard Qsys interfaces.

b. For Create testbench simulation model, select Verilog.

3. You can retain the default values for all other parameters.

4. Click Generate.

5. After Qsys reports Generation Completed, click Close.

6. On the File menu, click Save.

The following table lists the testbench and simulation directories Qsys generates.

Generating the Example Design

2-3

Table 2-1: Qsys System Generated Directories

Directory Location

Qsys system

Testbench

Simulation Model

The design example simulation includes the following components and software:

• The Qsys system

• A testbench. You can view this testbench in Qsys by opening <project_dir>/ep_g2x4/testbench/ep_g2x4_

tb.qsys.

• The ModelSim software

Note:

You can also use any other supported third-party simulator to simulate your design.

Complete the following steps to run the Qsys testbench:

1. In a terminal window, change to the <project_dir>/ep_g2x4/testbench/mentor directory.

2. Start the ModelSim® simulator.

3. Type the following commands in a terminal window:

<project_dir>/ep_g2x4

<project_dir>/ep_g2x4/testbench/<cad_vendor>

<project_dir>/ep_g2x4/testbench/ep_g2x4_tb/

simulation/

a. do msim_setup.tcl b. ld_debug c. run 140000 ns

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Generating the Example Design

The driver performs the following transactions with status of the transactions displayed in the ModelSim simulation message window:

1. Various configuration accesses to the Avalon-MM Stratix V Hard IP for PCI Express in your system after the link is initialized

2. Setup of the Address Translation Table for requests that are coming from the DMA component

3. Setup of the DMA controller to read 512 Bytes of data from the Transaction Layer Direct BFM shared

memory

4. Setup of the DMA controller to write the same data back to the Transaction Layer Direct BFM shared memory

5. Data comparison and report of any mismatch

The following example shows the transcript from a successful simulation run.

Example 2-1: Transcript from ModelSim Simulation of Gen2 x4 Endpoint

# 464 ns Completed initial configuration of Root Port. # INFO: 2657 ns EP LTSSM State: DETECT.ACTIVE # INFO: 3661 ns RP LTSSM State: DETECT.ACTIVE # INFO: 6049 ns EP LTSSM State: POLLING.ACTIVE # INFO: 6909 ns RP LTSSM State: POLLING.ACTIVE # INFO: 9037 ns RP LTSSM State: POLLING.CONFIG # INFO: 9441 ns EP LTSSM State: POLLING.CONFIG # INFO: 10657 ns EP LTSSM State:CONFIG.LINKWIDTH.START # INFO: 10829 ns RP LTSSM State: CONFIG.LINKWIDTH.START # INFO: 11713 ns EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT # INFO: 12253 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT # INFO: 12573 ns RP LTSSM State: CONFIG.LANENUM.WAIT # INFO: 13505 ns EP LTSSM State: CONFIG.LANENUM.WAIT # INFO: 13825 ns EP LTSSM State: CONFIG.LANENUM.ACCEPT # INFO: 13853 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT # INFO: 14173 ns RP LTSSM State: CONFIG.COMPLETE # INFO: 14721 ns EP LTSSM State: CONFIG.COMPLETE # INFO: 16001 ns EP LTSSM State: CONFIG.IDLE # INFO: 16093 ns RP LTSSM State: CONFIG.IDLE # INFO: 16285 ns RP LTSSM State: L0 # INFO: 16545 ns EP LTSSM State: L0 # INFO: 19112 ns Configuring Bus 001, Device 001, Function 00 # INFO: 19112 ns EP Read Only Configuration Registers: # INFO: 19112 ns Vendor ID: 0000 # INFO: 19112 ns Device ID: 0001 # INFO: 19112 ns Revision ID: 01 # INFO: 19112 ns Class Code: 000000 # INFO: 19112 ns Subsystem Vendor ID: 0000 # INFO: 19112 ns Subsystem ID: 0000 # INFO: 19112 ns Interrupt Pin: INTA used # INFO: 20584 ns PCI MSI Capability Register: # INFO: 20584 ns 64-Bit Address Capable: Supported # INFO: 20584 ns Messages Requested: 4 # INFO: 28136 ns EP PCI Express Link Status Register (1041): # INFO: 28136 ns Negotiated Link Width: x4 # INFO: 28136 ns Slot Clock Config: System Reference Clock Used # INFO: 29685 ns RP LTSSM State: RECOVERY.RCVRLOCK # INFO: 30561 ns EP LTSSM State: RECOVERY.RCVRLOCK # INFO: 31297 ns EP LTSSM State: RECOVERY.RCVRCFG # INFO: 31381 ns RP LTSSM State: RECOVERY.RCVRCFG # INFO: 32661 ns RP LTSSM State: RECOVERY.IDLE # INFO: 32961 ns EP LTSSM State: RECOVERY.IDLE # INFO: 33153 ns EP LTSSM State: L0 # INFO: 33237 ns RP LTSSM State: L0 # INFO: 34696 ns Current Link Speed: 2.5GT/s INFO: 34696 ns

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Generating the Example Design

# INFO: 36168 ns EP PCI Express Link Control Register (0040): # INFO: 36168 ns Common Clock Config: System Reference Clock Used # INFO: 37960 ns EP PCI Express Capabilities Register (0002): # INFO: 37960 ns Capability Version: 2 # INFO: 37960 ns Port Type: Native Endpoint # INFO: 37960 ns EP PCI Express Device Capabilities Register(00008020): # INFO: 37960 ns Max Payload Supported: 128 Bytes # INFO: 37960 ns Extended Tag: Supported # INFO: 37960 ns Acceptable L0s Latency: Less Than 64 ns # INFO: 37960 ns Acceptable L1 Latency: Less Than 1 us # INFO: 37960 ns Attention Button: Not Present # INFO: 37960 ns Attention Indicator: Not Present # INFO: 37960 ns Power Indicator: Not Present # INFO: 37960 ns EP PCI Express Link Capabilities Register (01406041): # INFO: 37960 ns Maximum Link Width: x4 # INFO: 37960 ns Supported Link Speed: 2.5GT/s # INFO: 37960 ns L0s Entry: Not Supported # INFO: 37960 ns L1 Entry: Not Supported # INFO: 37960 ns L0s Exit Latency: 2 us to 4 us # INFO: 37960 ns L1 Exit Latency: Less Than 1 us # INFO: 37960 ns Port Number: 01 # INFO: 37960 ns Surprise Dwn Err Report: Not Supported # INFO: 37960 ns DLL Link Active Report: Not Supported # INFO: 37960 ns EP PCI Express Device Capabilities 2 Register (0000001F): # INFO: 37960 ns Completion Timeout Rnge: ABCD (50us to 64s) # INFO: 39512 ns EP PCI Express Device Control Register (0110): # INFO: 39512 ns Error Reporting Enables: 0 # INFO: 39512 ns Relaxed Ordering: Enabled # INFO: 39512 ns Error Reporting Enables: 0 # INFO: 39512 ns Relaxed Ordering: Enabled # INFO: 39512 ns Max Payload: 128 Bytes # INFO: 39512 ns Extended Tag: Enabled # INFO: 39512 ns Max Read Request: 128 Bytes # INFO: 39512 ns EP PCI Express Device Status Register (0000): # INFO: 41016 ns EP PCI Express Virtual Channel Capability: # INFO: 41016 ns Virtual Channel: 1 # INFO: 41016 ns Low Priority VC: 0 # INFO: 46456 ns BAR Address Assignments: # INFO: 46456 ns BAR Size Assigned Address Type # INFO: 46456 ns BAR1:0 4 MBytes 00000001 00000000 Prefetchable # INFO: 46456 ns BAR2 32 KBytes 00200000 Non-Prefetchable # INFO: 46456 ns BAR3 Disabled # INFO: 46456 ns BAR4 Disabled # INFO: 46456 ns BAR5 Disabled # INFO: 46456 ns ExpROM Disabled # INFO: 48408 ns Completed configuration of Endpoint BAR # INFO: 50008 ns Starting Target Write/Read Test. # INFO: 50008 ns Target BAR = 0 # INFO: 50008 ns Length = 000512, Start Offset = 000000 # INFO: 54368 ns Target Write and Read compared okay! # INFO: 54368 ns Starting DMA Read/Write Test. # INFO: 54368 ns Setup BAR = 2 # INFO: 54368 ns Length = 000512, Start Offset = 000000 # INFO: 60609 ns Interrupt Monitor: Interrupt INTA Asserted # INFO: 60609 ns Clear Interrupt INTA # INFO: 62225 ns Interrupt Monitor: Interrupt INTA Deasserted # INFO: 69361 ns MSI recieved! # INFO: 69361ns DMA Read and Write compared okay! # SUCCESS: Simulation stopped due to successful completion! # Break at .ep_g1x4_tb/simulation/submodules//altpcietb_bfm_log.v line 78

2-5

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Simulating Altera Designs

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2-6

Understanding Simulation Log File Generation

Starting with the Quartus II 14.0 software release, simulation automatically creates a log file, altpcie_

monitor_<dev>_dlhip_tlp_file_log.log in your simulation directory.

Table 2-2: Sample Simulation Log File Entries

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Time TLP Type Payload

(Bytes)

17989 RX CfgRd0 0004 04000001_0000000F_01080008 17989 RX MRd 0000 00000000_00000000_01080000 18021 RX CfgRd0 0004 04000001_0000010F_0108002C 18053 RX CfgRd0 0004 04000001_0000030F_0108003C 18085 RX MRd 0000 00000000_00000000_0108000C

Running A Gate-Level Simulation

The PCI Express testbenches run simulations at the register transfer level (RTL). However, it is possible to create you own gate-level simulations. Contact your Altera Sales Representative for instructions and an example that illustrate how to create a gate-level simulation from the RTL testbench.

Simulating the Single DWord Design

You can use the same testbench to simulate the Completer-Only Single Dword IP core by changing the settings in the driver file.

TLP Header

1. In a terminal window, change to the <project_dir>/<variant>/testbench/<variant>_tb/simulation/submodules

2. Open altpcietb_bfm_driver_avmm.v in your text editor.

3. To enable target memory tests and specify the completer-only single dword variant, specify the

4. Change to the <project_dir>/variant/testbench/mentor directory.

5. Start the ModelSim simulator.

6. To run the simulation, type the following commands in a terminal window:

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directory.

following parameters:

a. parameter RUN_TGT_MEM_TST = 1; b. parameter RUN_DMA_MEM_TST = 0; c. parameter AVALON_MM_LITE = 1;

a. do msim_setup.tcl b. ld_debug (The debug suffix stops optimizations, improving visibility in the ModelSim waveforms.) c. run 140000 ns

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Generating Quartus II Synthesis Files

1. On the Generate menu, select Generate HDL.

2. For Create HDL design files for synthesis, select Verilog.

You can leave the default settings for all other items.

3. Click Generate to generate files for Quartus II synthesis.

4. Click Finish when the generation completes.

Creating a Quartus II Project

You can create a new Quartus II project with the New Project Wizard, which helps you specify the working directory for the project, assign the project name, and designate the name of the top-level design entity.

1. On the Quartus II File menu, click then New Project Wizard, then Next.

2. Click Next in the New Project Wizard: Introduction (The introduction does not appear if you

previously turned it off.)

3. On the Directory, Name, Top-Level Entity page, enter the following information:

Generating Quartus II Synthesis Files

2-7

a. For What is the working directory for this project, browse to <project_dir>/ep_g2x4/synthesis/. b. For What is the name of this project, select ep_g2x4.v from the synthesis directory.

4. Click Next.

5. On the Add Files page, add<project_dir>/ep_g2x4/synthesis/ep_g2_x4.qip to your Quartus II project. This

file lists all necessary files for Quartus II compilation.

6. Click Next to display the Family & Device Settings page.

7. On the Device page, choose the following target device family and options: a. In the Family list, select Stratix V (GS/GT/GX/E).

b. In the Devices list, select Stratix V GX PCIe. c. In the Available devices list, select 5SGXEA7K2F40C2.

8. Click Next to close this page and display the EDA Tool Settings page.

9. From the Simulation list, select ModelSim. From the Format list, select the HDL language you intend

to use for simulation.

10.Click Next to display the Summary page.

11.Check the Summary page to ensure that you have entered all the information correctly.

Compiling the Design

1. Before compiling, you need to make a few changes to your top-level Verilog HDL file to create a design that you can successfully download to a PCB.

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Programming a Device

a. In the <project_dir>/ep_g2x4_avmm128/synth/, open ep_g2x4_avmm128.v. b. Comment out the declaration for pcie_a10_hip_0_hip_ctrl_test_in. c. Add a wire [31:0] pcie_a10_hip_0_hip_ctrl_test_in declaration to the same the same file. d. Assign pcie_a10_hip_0_hip_ctrl_test_in = 0x000000A8. e. Connect pcie_a10_hip_0_hip_ctrl_test_in to the test_in port on the Stratix V Hard IP for

PCI Express instance.

2. On the Quartus II Processing menu, click Start Compilation.

3. After compilation, expand the TimeQuest Timing Analyzer folder in the Compilation Report. Note

whether the timing constraints are achieved in the Compilation Report.

If your design does not initially meet the timing constraints, you can find the optimal Fitter settings for your design by using the Design Space Explorer. To use the Design Space Explorer, click Launch Design Space Explorer on the Tools menu.

Programming a Device

After you compile your design, you can program your targeted Altera device and verify your design in hardware.

For more information about programming Altera FPGAs, refer to Quartus II Programmer.

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Related Information

Quartus II Programmer

Understanding Channel Placement Guidelines

Stratix V transceivers are organized in banks of six channels. The transceiver bank boundaries are important for clocking resources, bonding channels, and fitting. Refer to the channel placement figures following Serial Interface Signals for illustrations of channel placement for x1, x2, x4, and x8 variants.

Related Information

Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices on page 4-29

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Parameter Settings

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Stratix V and Arria V GZ Avalon-MM System Settings

Table 3-1: System Settings for PCI Express

Parameter Value Description

Number of Lanes x1, x2, x4, x8 Specifies the maximum number of lanes supported.

Lane Rate Gen1 (2.5 Gbps)

Gen2 (2.5/5.0 Gbps)

Gen3 (2.5/5.0/8.0

Gbps)

Port type Native Endpoint

Root Port

Specifies the maximum data rate at which the link can operate.

Specifies the port type. Altera recommends Native Endpoint for all new Endpoint designs. Select Legacy Endpoint only when you require I/O transaction support for compatibility.

The Endpoint stores parameters in the Type 0 Configuration Space. The Root Port stores parameters in the Type 1 Configu‐ ration Space.

RX Buffer credit allocation performance for received requests

Minimum

Low

Balanced

Determines the allocation of posted header credits, posted data credits, non-posted header credits, completion header credits, and completion data credits in the 16 KByte RX buffer. The 5 settings allow you to adjust the credit allocation to optimize your system. The credit allocation for the selected setting displays in the message pane.

Refer to the Throughput Optimization chapter for more information about optimizing performance. The Flow Control chapter explains how the RX credit allocation and the

Maximum payload RX Buffer credit allocation and the Maximum payload size that you choose affect the allocation

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Stratix V and Arria V GZ Avalon-MM System Settings

Parameter Value Description

of flow control credits. You can set the Maximum payload size parameter on the Device tab.

The Message window dynamically updates the number of credits for Posted, Non-Posted Headers and Data, and Completion Headers and Data as you change this selection.

• Minimum—configures the minimum PCIe specification

allowed for non-posted and posted request credits, leaving most of the RX Buffer space for received completion header and data. Select this option for variations where application logic generates many read requests and only infrequently receives single requests from the PCIe link.

• Low—configures a slightly larger amount of RX Buffer

space for non-posted and posted request credits, but still dedicates most of the space for received completion header and data. Select this option for variations where application logic generates many read requests and infrequently receives small bursts of requests from the PCIe link. This option is recommended for typical endpoint applications where most of the PCIe traffic is generated by a DMA engine that is located in the endpoint application layer logic.

• Balanced—configures approximately half the RX Buffer

space to received requests and the other half of the RX Buffer space to received completions. Select this option for variations where the received requests and received completions are roughly equal.

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Reference clock frequency

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100 MHz 125 MHz

The PCI Express Base Specification 3.0 requires a 100 MHz ±300 ppm reference clock. The 125 MHz reference clock is provided as a convenience for systems that include a 125 MHz clock source. For more information about Gen3 operation, refer to 4.3.8 Refclk Specifications for 8.0 GT/sin the specification.

For Gen3, Altera recommends using a common reference clock (0 ppm) because when using separate reference clocks (non 0 ppm), the PCS occasionally must insert SKP symbols, potentially causes the PCIe link to go to recovery. Stratix V PCIe Hard IP in Gen1 or Gen2 modes are not affected by this issue. Systems using the common reference clock (0 ppm) are not affected by this issue. The primary repercussion of this is a slight decrease in bandwidth. On Gen3 x8 systems, this bandwidth impact is negligible. If non 0 ppm mode is required, so that separate reference clocks are being used, please contact Altera for further information and guidance.

Parameter Settings

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Base Address Register (BAR) Settings

Parameter Value Description

3-3

Use 62.5 MHz

On/Off This mode is only available only for Gen1 ×1.

application clock

Enable configu‐ ration via PCI Express (CvP)

On/Off When On, the Quartus II software places the Endpoint in the

location required for configuration via protocol (CvP). For more information about CvP, click the Configuration via Protocol (CvP) link below.

Use ATX PLL On/Off When enabled, the Hard IP for PCI Express uses the ATX PLL

instead of the CMU PLL. For other configurations, using the ATX PLL instead of the CMU PLL reduces the number of transceiver channels that are necessary. This option requires the use of the soft reset controller and does not support the CvP flow.

Enable Hard IP reset pulse at power-up when using the soft reset controller

On/Off

When On, the soft reset controller generates a pulse at power up to reset the Hard IP. This pulse ensures that the Hard IP is reset after programming the device, regardless of the behavior of the dedicated PCI Express reset pin, perstn. This option is available for Gen2 and Gen3 designs that use a soft reset controller.

Related Information

PCI Express Base Specification 2.1 or 3.0

Base Address Register (BAR) Settings

You can configure up to six 32-bit BARs or three 64-bit BARs.

Table 3-2: BAR Registers

Parameter Value Description

Type

64-bit prefetchable memory

32-bit non-prefetchable memory

32-bit prefetchable memory

Parameter Settings

Disabled

I/O address space

Defining memory as prefetchable allows data in the region to be fetched ahead anticipating that the requestor may require more data from the same region than was originally requested. If you specify that a memory is prefetchable, it must have the following 2 attributes:

• Reads do not have side effects

• Write merging is allowed The 32-bit prefetchable memory and I/O address

space BARs are only available for the Legacy Endpoint.

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Device Identification Registers

Parameter Value Description

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Size

Not configurable

Specifies the memory size calculated from other parameters you enter.

Device Identification Registers

Table 3-3: Device ID Registers

The following table lists the default values of the read-only Device ID registers. You can use the parameter editor to change the values of these registers. Refer to Type 0 Configuration Space Registers for the layout of the Device Identification registers.

Vendor ID 16 bits 0x00000000 Sets the read-only value of the Vendor ID register. This

parameter cannot be set to 0xFFFF, per the PCI Express Specification.

Address offset: 0x000.

Device ID 16 bits 0x00000001 Sets the read-only value of the Device ID register. This

Address offset: 0x000.

Revision ID 8 bits 0x00000001 Sets the read-only value of the Revision ID register.

Address offset: 0x008.

Class code 24 bits 0x00000000 Sets the read-only value of the Class Code register.

Address offset: 0x008.

Subsystem Vendor ID

16 bits 0x00000000 Sets the read-only value of the Subsystem Vendor ID

register in the PCI Type 0 Configuration Space. This parameter cannot be set to 0xFFFF per the PCI Express Base Specification. This value is assigned by PCI-SIG to the device manufacturer. This register is only valid in the Type 0 (Endpoint) Configuration Space.

Address offset: 0x02C.

Subsystem Device ID

16 bits 0x00000000 Sets the read-only value of the Subsystem Device ID

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Parameter Settings

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Related Information

PCI Express Base Specification 2.1 or 3.0

PCI Express and PCI Capabilities Parameters

This group of parameters defines various capability properties of the IP core. Some of these parameters are stored in the PCI Configuration Space - PCI Compatible Configuration Space. The byte offset indicates the parameter address.

Device Capabilities

Table 3-4: Capabilities Registers

Parameter Possible Values Default Value Description

PCI Express and PCI Capabilities Parameters

3-5

Maximum payload size

Completion timeout range

128 bytes 256 bytes

ABCD

BCD ABC

None

128 bytes Specifies the maximum payload size supported. This

parameter sets the read-only value of the max payload size supported field of the Device Capabilities register (0x084[2:0]). Address: 0x084.

ABCD Indicates device function support for the optional

completion timeout programmability mechanism. This mechanism allows the system software to modify the completion timeout value. This field is applicable only to Root Ports and Endpoints that issue requests on their own behalf. Completion timeouts are specified and enabled in the Device Control 2 register (0x0A8) of the PCI Express Capability Structure Version. For all other functions this field is reserved and must be hardwired to 0x0000b. Four time value ranges are defined:

• Range A: 50 us to 10 ms

• Range B: 10 ms to 250 ms

• Range C: 250 ms to 4 s

• Range D: 4 s to 64 s Bits are set to show timeout value ranges supported. The

function must implement a timeout value in the range 50 sto 50 ms. The following values specify the range:

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• None—Completion timeout programming is not supported

• 0001 Range A

• 0010 Range B

• 0011 Ranges A and B

• 0110 Ranges B and C

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3-6

Error Reporting

Parameter Possible Values Default Value Description

• 0111 Ranges A, B, and C

• 1110 Ranges B, C and D

• 1111 Ranges A, B, C, and D

All other values are reserved. Altera recommends that the completion timeout mechanism expire in no less than 10 ms.

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Implement completion timeout disable

On/Off On For Endpoints using PCI Express version 2.1 or 3.0, this

option must be On. The timeout range is selectable. When On, the core supports the completion timeout disable mechanism via the PCI Express Device

Control Register 2. The Application Layer logic must

implement the actual completion timeout mechanism for the required ranges.

Error Reporting

Table 3-5: Error Reporting

Parameter Value Default Value Description

Advanced error reporting (AER)

Enable ECRC checking

On/Off Off When On, enables the Advanced Error Reporting (AER)

capability.

On/Off Off When On, enables ECRC checking. Sets the read-only

value of the ECRC check capable bit in the Advanced

Error Capabilities and Control Register. This

parameter requires you to enable the AER capability.

Enable ECRC generation

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On/Off Off

When On, enables ECRC generation capability. Sets the read-only value of the ECRC generation capable bit in the Advanced Error Capabilities and Control

AER capability.

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Parameter Value Default Value Description

Link Capabilities

3-7

Enable ECRC forwarding on the Avalon-ST interface

On/Off Off When On, enables ECRC forwarding to the Application

Layer. On the Avalon-ST RX path, the incoming TLP contains the ECRC dword

(1)

and the TD bit is set if an ECRC exists. On the transmit the TLP from the Applica‐ tion Layer must contain the ECRC dword and have the

TD bit set.

Not applicable for Avalon-MM or Avalon-MM DMA interfaces.

Track RX completion buffer overflow on the AvalonST interface

On/Off Off When On, the core includes the rxfx_cplbuf_ovf

output status signal to track the RX posted completion buffer overflow status.

Not applicable for Avalon-MM or Avalon-MM DMA interfaces.

Note:

1. Throughout this user guide, the terms word, dword and qword have the same meaning that they have

in the PCI Express Base Specification. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.

Related Information

PCI Express Base Specification Revision 2.1 or 3.0

Link Capabilities

Table 3-6: Link Capabilities

Parameter Value Description

Link port number

Slot clock configuration

0x01 Sets the read-only value of the port number field in the Link

Capabilities Register.

On/Off When On, indicates that the Endpoint or Root Port uses the

same physical reference clock that the system provides on the connector. When Off, the IP core uses an independent clock regardless of the presence of a reference clock on the connector.

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MSI and MSI-X Capabilities

Table 3-7: MSI and MSI-X Capabilities

Parameter Value Description

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MSI messages requested

1, 2, 4, 8, 16 Specifies the number of messages the Application Layer can

request. Sets the value of the Multiple Message Capable field of the Message Control register, 0x050[31:16].

MSI-X Capabilities

Implement MSI-X On/Off When On, enables the MSI-X functionality.

Bit Range

Table size [10:0] System software reads this field to determine the MSI-X Table

size <n>, which is encoded as <n–1>. For example, a returned value of 2047 indicates a table size of 2048. This field is readonly. Legal range is 0–2047 (211).

Address offset: 0x068[26:16]

Table Offset [31:0] Points to the base of the MSI-X Table. The lower 3 bits of the

table BAR indicator (BIR) are set to zero by software to form a 32-bit qword-aligned offset. This field is read-only.

Table BAR Indicator

[2:0] Specifies which one of a function’s BARs, located beginning at

0x10 in Configuration Space, is used to map the MSI-X table into memory space. This field is read-only. Legal range is 0–5.

Pending Bit Array (PBA) Offset

PBA BAR Indicator

Related Information

PCI Express Base Specification Revision 2.1 or 3.0

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[31:0] Used as an offset from the address contained in one of the

function’s Base Address registers to point to the base of the MSI-X PBA. The lower 3 bits of the PBA BIR are set to zero by software to form a 32-bit qword-aligned offset. This field is read-only.

[2:0] Specifies the function Base Address registers, located

beginning at 0x10 in Configuration Space, that maps the MSIX PBA into memory space. This field is read-only. Legal range is 0–5.

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Power Management

Table 3-8: Power Management Parameters

Parameter Value Description

Power Management

3-9

Endpoint L0s acceptable latency

Endpoint L1 acceptable latency

Maximum of 64 ns Maximum of 128 ns Maximum of 256 ns Maximum of 512 ns Maximum of 1 us Maximum of 2 us Maximum of 4 us No limit

Maximum of 1 us Maximum of 2 us Maximum of 4 us Maximum of 8 us Maximum of 16 us Maximum of 32 us No limit

This design parameter specifies the maximum acceptable latency that the device can tolerate to exit the L0s state for any links between the device and the root complex. It sets the read-only value of the Endpoint L0s acceptable latency field of the Device Capabilities Register (0x084).

This Endpoint does not support the L0s or L1 states. However, in a switched system there may be links connected to switches that have L0s and L1 enabled. This parameter is set to allow system configuration software to read the acceptable latencies for all devices in the system and the exit latencies for each link to determine which links can enable Active State Power Management (ASPM). This setting is disabled for Root Ports.

The default value of this parameter is 64 ns. This is the safest setting for most designs.

This value indicates the acceptable latency that an Endpoint can withstand in the transition from the L1 to L0 state. It is an indirect measure of the Endpoint’s internal buffering. It sets the read-only value of the Endpoint L1 acceptable latency field of the Device Capabilities Register.

This Endpoint does not support the L0s or L1 states. However, a switched system may include links connected to switches that have L0s and L1 enabled. This parameter is set to allow system configuration software to read the acceptable latencies for all devices in the system and the exit latencies for each link to determine which links can enable Active State Power Management (ASPM). This setting is disabled for Root Ports.

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The default value of this parameter is 1 µs. This is the safest setting for most designs.

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3-10

Avalon Memory‑Mapped System Settings

Table 3-9: Avalon Memory-Mapped System Settings

Parameter Value Description

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Avalon-MM data width

Avalon-MM address width

Peripheral mode

64-bit

128-bit

32-bit 64-bit

Requester/ Completer

Completer-Only

Specifies the data width for the Application Layer to Transaction Layer interface. Refer to Application

Layer Clock Frequencies for All Combinations of Link Width, Data Rate and Application Layer Interface Widths for all legal combinations of data width,

number of lanes, Application Layer clock frequency, and data rate.

Specifies the address width for Avalon-MM RX master ports that access Avalon-MM slaves in the Avalon address domain. When you select 32-bit addresses, the PCI Express Avalon-MM Bridge performs address translation. When you specify 64bits addresses, no address translation is performed in either direction. The destination address specified is forwarded to the Avalon-MM interface without any changes.

For the Avalon-MM interface with DMA, this value must be set to 64.

Specifies whether the Avalon-MM Stratix V Hard IP for PCI Express is capable of sending requests to the upstream PCI Express devices, and whether the incoming requests are pipelined.

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Requester/Completer—In this mode, the Hard IP can send request packets on the PCI Express TX link and receive request packets on the PCI Express RX link.

Completer-Only—In this mode, the Hard IP can receive requests, but cannot initiate upstream requests. However, it can transmit completion packets on the PCI Express TX link. This mode removes the Avalon-MM TX slave port and thereby reduces logic utilization.

Parameter Settings

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Avalon Memory‑Mapped System Settings

Parameter Value Description

3-11

Single DW Completer On/Off

Control register access

On/Off (CRA) Avalon-MM slave port

Enable multiple MSI/MSI-X

On/Off support

This is a non-pipelined version of Completer Only mode. At any time, only a single request can be outstanding. Single dword completer uses fewer resources than Completer Only. This variant is targeted for systems that require simple read and write register accesses from a host CPU. If you select this option, the width of the data for RXM BAR masters is always 32 bits, regardless of the Avalon- MM width.

For the Avalon-MM interface with DMA, this value must be Off .

Allows read and write access to bridge registers from the interconnect fabric using a specialized slave port. This option is required for Requester/Completer variants and optional for Completer Only variants. Enabling this option allows read and write access to bridge registers, except in the Completer-Only single dword variations.

When you turn this option On, the core exports top-level MSI and MSI-X interfaces that you can use to implement a Customer Interrupt Handler for MSI and MSI-X interrupts. For more information about the Custom Interrupt Handler, refer to Interrupts for

End Points Using the Avalon-MM Interface with

Multiple MSI/MSI

X Support. If you turn this option

Off, the core handles interrupts internally.

Auto enabled PCIe interrupt (enabled at power-on)

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On/Off

Turning on this option enables the Avalon-MM Stratix V Hard IP for PCI Express interrupt register at power-up. Turning off this option disables the interrupt register at power-up. The setting does not affect run-time configuration of the interrupt enable register.

For the Avalon-MM interface with DMA, this value must be Off.

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3-12

Avalon Memory‑Mapped System Settings

Parameter Value Description

Enable hard IP status bus On/Off When you turn this option on, your top-level variant

includes the signals necessary to connect to the Transceiver Reconfiguration Controller IP Core, your variant, including:

• Link status signals

• ECC error signals

• TX and RX parity error signals

• Completion header and data signals, indicating the total number of Completion TLPs currently stored in the RX buffer

Altera recommends that you include the Transceiver Reconfiguration Controller IP Core in your design to improve signal quality.

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Enable hard IP status

On/Off When you turn this option on, your top-level variant

extension bus

Avalon to PCIe Address Translation Settings

Number of address pages 1, 2, 4, 8, 16, 32,

64, 128, 256, 512

includes signals that are useful for debugging, including link training and status, error, and the Transaction Layer Configuration Space signals. The top-level variant also includes signals showing the start and end of packets, error, ready, and BAR signals for the native Avalon-ST interface that connects to the Transaction Layer. The following signals are included in the top-level variant:

• Link status signals

• ECC error signals

• Transaction Layer Configuration Space signals

• Avalon-ST packet, error, ready, and BAR signals

Specifies the number of pages required to translate Avalon-MM addresses to PCI Express addresses before a request packet is sent to the Transaction Layer. Each of the 512 possible entries corresponds to a base address of the PCI Express memory segment of a specific size. This parameter is only necessary when you select 32-bit addressing.

Size of address pages 4 KBytes–4

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GBytes

Specifies the size of each memory segment. Each memory segment must be the same size. Refer to

Avalon-MM-to-PCI Express Address Translation Algorithm for 32-Bit Bridge for more information

about address translation. This parameter is only necessary when you select 32-bit addressing.

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Related Information

Clock Domains on page 6-5

Avalon Memory‑Mapped System Settings

3-13

Parameter Settings

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Application Layer

2014.12.15

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This chapter describes the top-level signals of the Stratix V Hard IP for PCI Express using the AvalonMM interface to the Application Layer. The Avalon-MM bridge translates PCI Express read, write and completion TLPs into standard Avalon-MM read and write commands for the Avalon-MM RX Master Port interface. For the Avalon-MM TX Slave Port interface, the bridge translates Avalon-MM reads and writes into PCI Express TLPs. The Avalon-MM read and write commands are the same as those used by master and slave interfaces to access memories and registers. Consequently, you do not need a detailed understanding of the PCI Express TLPs to use this Avalon-MM variant.

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ISO 9001:2008 Registered

tx_out0[<n>:0]

rx_in0[<n>:0]

1-Bit Serial

cra_readdata[31:0] cra_waitrequest

cra_byteenable[3:0] cra_chipselect

cra_address[11:0]

cra_read cra_write cra_writedata[31:0]

txs_writedata[<w>-1:0] txs_busrtcount[6:0]

txs_chipselect txs_read txs_write

txs_address[<w>-1:0] txs_byteenable[7:0] txs_readdatavalid txs_readdata[<w>-1:0] txs_waitrequest

32-Bit

Avalon-MM

CRA

Slave Port

(Optional,

Not available for

Completer-Only

Single Dword)

64- or 128-Bit

Avalon-MM TX

Slave Port

(Not used for

Completer-Only)

Test Interface

test_in[31:0]

simu_mode_pipe

rxm_bar0_write_<n> rxm_bar0_address_<n>[31:0] rxm_bar0_writedata_<n>[63:0] or [31:0] rxm_bar0_byteenable_<n>[7:0] rxm_bar0_burstcount_<n>[6:0] rxm_bar0_waitrequest_<n> rxm_bar0_read_<n> rxm_bar0_readdata_<n>[63:0] rxm_bar0_readdatavalid rxm_irq[<m>:0], <m> < 16

reconfig_from_xcvr[<n>46-1:0]

MsiIntfc_o[81:0]

MsiControl_o[15:0]

MsixIntfc_o[15:0]

IntxReq_i

IntxAck_o

reconfig_to_xcvr[<n>70-1:0]

Transceiver

Multiple MSI/MSI-X

Hard IP Status Extension

Reconfiguration

Clocks

npor nreset_status pin_perst

cfg_par_err derr_cor_ext_rcv derr_ext_rpl derr_rpl dlup dlup_exit ev128ns ev1us hotrst_exit int_status[3:0] ko_cpl_spc_data[11:0] ko_cpl_spc_header[7:0] l2_ext lane_act[3:0] ltssmstate[4:0] rx_par_err tx_par_err

Reset &

Lock Status

refclk coreclkout

cra_irq_irq

txdata0[7:0]

txdatak0

txblkst0

rxdata0[7:0]

rxdatak0

rxblkst0

txdetectrx0

txelecidle0

txcompl0

rxpolarity0

powerdown0[1:0]

currentcoeff0[17:0]

currentrxpreset0[2:0]

txmargin[2:0]

txswing

txsynchd0[1:0]

rxsyncd[1:0]

rxvalid0 phystatus0 rxelecidle0

rxstatus0[2:0]

simu_mode_pipe

sim_pipe_rate[1:0]

sim_pipe_pclk_in

sim_pipe_pclk_out sim_pipe_clk250_out sim_pipe_clk500_out

sim_ltssmstate[4:0]

rxfreqlocked0

rxdataskip0

eidleinfersel0[2:0]

txdeemph0

Transmit Data Interface Signals

Receive Data Interface Signals

Command Interface Signals

Status Interface Signals

64- or 128-Bit Avalon-MM Intearface to

Application Layer

PIPE

Interface for Simulation and Hardware

Debug Using

dl_ltssm[4:0]

SignalTap,

Gen3 version

pld_clk_inuse

pme_to_sr

rx_st_bar[7:0]

rx_st_data[127:0]

rx_st_eop

rx_st_err

rx_st_sop

rx_st_valid

serr_out

tl_cfg_add[3:0]

tx_cfg_sts[52:0]

tx_st_ready

Hard IP Reset, Status and Link Training

64-Bit

Avalon-MM RX

BAR Master Port

4-2

64- or 128-Bit Avalon-MM Interface to the Application Layer

Figure 4-1: 64- or 128-Bit Avalon-MM Interface to the Application Layer

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Note: Signals listed for BAR0 are the same as those for BAR1–BAR5 when those BARs are enabled in the

Variations using the Avalon-MM interface implement the Avalon-MM protocol described in the Avalon Interface Specifications. Refer to this specification for information about the Avalon-MM protocol, including timing diagrams.

Related Information

Avalon Interface Specifications

parameter editor.

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32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals

The optional CRA port for the full-featured IP core allows upstream PCI Express devices and external Avalon-MM masters to access internal control and status registers.

Table 4-1: Avalon-MM CRA Slave Interface Signals

4-3

Signal Name Directio

CraIrq_o

CraReadData_o[31:0]

CraWaitRequest_o

CraAddress_i[13:0]

CraByteEnable_i[3:0]

CraChipSelect_i

CraRead_i

CraWrite_i

Description

Output Interrupt request. A port request for an Avalon-MM interrupt.

Output Read data lines

Output Wait request to hold off more requests

Input An address space of 16,384 bytes is allocated for the control

registers. Avalon-MM slave addresses provide address resolution down to the width of the slave data bus. Because all addresses are byte addresses, this address logically goes down to bit 2. Bits 1 and 0 are 0.

Input Byte enable

Input Chip select signal to this slave

Input Read enable

Input Write request

CraWriteData_i[31:0]

Input Write data

RX Avalon-MM Master Signals

This Avalon-MM master port propagates PCI Express requests to the Qsys interconnect fabric. For the full-feature IP core it propagates requests as bursting reads or writes. A separate Avalon-MM master port corresponds to each BAR.

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RX Avalon-MM Master Signals

Table 4-2: Avalon-MM RX Master Interface Signals

Signals that include Bar number 0 also exist for BAR1–BAR5 when additional BARs are enabled.

Signal Name Direction Description

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RxmWrite<n>

RxmAddress_<n>_o[31:0]

RxmWriteData_<n>_o[<w>-1:0]

RxmByteEnable_<n>_o[<w>-1:0]

RXMBurstCount_<n>_o[6 or 5:0]

RXMWaitRequest_<n>_o

RXMRead_<n>_o

RXMReadData_<n>_o[<w>-1:0]

Output Asserted by the core to request a write to an Avalon-

MM slave.

Output The address of the Avalon-MM slave being accessed.

Output RX data being written to slave. <w> = 64 or 128 for the

full-featured IP core. <w> = 32 for the completer-only IP core.

Output Byte enable for write data.

Output The burst count, measured in qwords, of the RX write or

read request. The width indicates the maximum data that can be requested. The maximum data in a burst is 512 bytes.

Input Asserted by the external Avalon-MM slave to hold data

transfer.

Output Asserted by the core to request a read.

Input Read data returned from Avalon-MM slave in response

to a read request. This data is sent to the IP core through the TX interface. <w> = 64 or 128 for the full-featured IP core. <w> = 32 for the completer-only IP core.

RXMReadDataValid_<n>_i

RxmIrq_<n>[<m>:0], <m>< 16

The following figure illustrates the RX master port propagating requests to the Application Layer and also shows simultaneous, DMA read and write activity

Altera Corporation

Input Asserted by the system interconnect fabric to indicate

that the read data on is valid.

Input Indicates an interrupt request asserted from the system

interconnect fabric. This signal is only available when the CRA port is enabled. Qsys-generated variations have as many as 16 individual interrupt signals (<m>≤15). If

rxm_irq_<n>[<m>:0] is asserted on consecutive cycles

without the deassertion of all interrupt inputs, no MSI message is sent for subsequent interrupts. To avoid losing interrupts, software must ensure that all interrupt sources are cleared for each MSI message received.

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RxmRead_o

RxmReadDataValid_i

RxmReadData_i[63:0]

RxmResetRequest_o

RxmAddress_o[31:0]

RxmWaitRequest_i

RxmWrite_o

RxmBurstCount_o[9:0]

RxmByteEnable_o[7:0]

RxmWriteData_o[63:0]

RxmIrq_i

TxsWrite_i

TxsWriteData_i[63:0]

TxsBurstCount_i[9:0]

TxsByteEnable_i[7:0]

TxsAddress_i[17:0]

TxsWaitRequest_o

TxsRead_i

TxsReadDataValid_o

TxsReadData_o[63:0]

TxsChipSelect_i

.. . . .

80000100 80000180

010

FF FF

. .

000000000002080F

. . . . . . .

001 080

04000 04080 04000

00000 . . 0 .

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Figure 4-2: Simultaneous DMA Read, DMA Write, and Target Access

64- or 128-Bit Bursting TX Avalon-MM Slave Signals

4-5

64- or 128-Bit Bursting TX Avalon-MM Slave Signals

This optional Avalon-MM bursting slave port propagates requests from the interconnect fabric to the fullfeatured Avalon-MM Stratix V Hard IP for PCI Express. Requests from the interconnect fabric are translated into PCI Express request packets. Incoming requests can be up to 512 bytes. For better performance, Altera recommends using smaller read request size (a maximum of 512 bytes).

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64- or 128-Bit Bursting TX Avalon-MM Slave Signals

Table 4-3: Avalon-MM TX Slave Interface Signals

Signal Name Direction Description

UG-01097_avmm

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TxsChipSelect_i

TxsRead_i

TxsWrite_i

TxsWriteData[127 or 63:0]

TxsBurstCount[6 or 5:0]

TxsAddress_i[<w>-1:0]

Input The system interconnect fabric asserts this signal to

select the TX slave port.

Input Read request asserted by the system interconnect fabric

to request a read.

Input Write request asserted by the system interconnect fabric

to request a write.

Input Write data sent by the external Avalon-MM master to

the TX slave port.

Input Asserted by the system interconnect fabric indicating

the amount of data requested. The count unit is the amount of data that is transferred in a single cycle, that is, the width of the bus. The burst count is limited to 512 bytes.

Input Address of the read or write request from the external

Avalon-MM master. This address translates to 64-bit or 32-bit PCI Express addresses based on the translation table. The <w> value is determined when the system is created.

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64- or 128-Bit Bursting TX Avalon-MM Slave Signals

Signal Name Direction Description

4-7

TxsByteEnable_i[<w>-1:0]

Input Write byte enable for data. A burst must be continuous.

Therefore all intermediate data phases of a burst must have a byte enable value of 0xFF. The first and final data phases of a burst can have other valid values.

For the 128-bit interface, the following restrictions apply:

• All bytes of a single dword must either be enabled or disabled

• If more than 1 dword is enabled, the enabled dwords must be contiguous. The following patterns are legal:

• 16'bF000

• 16'b0F00

• 16'b00F0

• 16'b000F

• 16'bFF00

• 16'b0FF0

• 16'b00FF

• 16'bFFF0

• 16'b0FFF

• 16'bFFFF

TxsReadDataValid_o

TxsReadData_o[127 or 63:0]

TxsWaitrequest_o

Output Asserted by the bridge to indicate that read data is valid.

Output The bridge returns the read data on this bus when the

RX read completions for the read have been received and stored in the internal buffer.

Output Asserted by the bridge to hold off read or write data

when running out of buffer space. If this signal is asserted during an operation, the master should maintain the TxsRead_i signal (or TxsWrite_i signal and TxsWriteData) stable until after TxsWaitrequest_

o is deasserted. txs_Read must be deasserted when TxsWaitrequest_o is deasserted.

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4-8

Clock Signals

Table 4-4: Clock Signals

Signal Direction Description

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refclk

coreclkout

Input Reference clock for the IP core. It must have the frequency

specified under the System Settings heading in the parameter editor. This is a dedicated free running input clock to the dedicated REFCLK pin.

If your design meets the following criteria:

• Enables CvP

• Includes an additional transceiver PHY connected to the same Transceiver Reconfiguration Controller

then you must connect refclk to the mgmt_clk_clk signal of the Transceiver Reconfiguration Controller and the additional transceiver PHY. In addition, if your design includes more than one Transceiver Reconfiguration Controller on the same side of the FPGA, they all must share the mgmt_clk_clk signal.

Output This is a fixed frequency clock used by the Data Link and

Transaction Layers. To meet PCI Express link bandwidth constraints, this clock has minimum frequency requirements as listed in Application Layer Clock Frequency for All Combination

of Link Width, Data Rate and Application Layer Interface Width in the Reset and Clocks chapter .

Related Information

Clocks on page 6-5

Reset

Refer to Reset and Clocks for more information about the reset sequence and a block diagram of the reset logic.

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Table 4-5: Reset Signals

Signal Direction Description

Reset

4-9

npor

nreset_status

pin_perst

Input Active low reset signal. In the Altera hardware example designs,

npor is the OR of pin_perst and local_rstn coming from the

software Application Layer. If you do not drive a soft reset signal from the Application Layer, this signal must be derived from

pin_perst. You cannot disable this signal. Resets the entire IP

Core and transceiver. Asynchronous. In systems that use the hard reset controller, this signal is edge,

not level sensitive; consequently, you cannot use a low value on this signal to hold custom logic in reset. For more information about the hard and soft reset controllers, refer to Reset.

Output

Active low reset signal. It is derived from npor or pin_perstn. You can use this signal to reset the Application Layer.

Input Active low reset from the PCIe reset pin of the device. pin_perst

resets the datapath and control registers. Configuration via Protocol (CvP) requires this signal. For more information about CvP refer to Configuration via Protocol (CvP).

Stratix V devices can have up to 4 instances of the Hard IP for PCI Express. Each instance has its own pin_perst signal. You

must connect the pin_perst of each Hard IP instance to the corresponding nPERST pin of the device. These pins have the

following locations:

• NPERSTL0: bottom left Hard IP and CvP blocks

• NPERSTL1: top left Hard IP block

• NPERSTR0: bottom right Hard IP block

• NPERSTR1: top right Hard IP block

For example, if you are using the Hard IP instance in the bottom left corner of the device, you must connect pin_perst to

NPERSL0.

For maximum use of the Stratix V device, Altera recommends that you use the bottom left Hard IP first. This is the only location that supports CvP over a PCIe link. If your design does not require CvP, you may select other Hard IP blocks.

Refer to the appropriate device pinout for correct pin assignment for more detailed information about these pins. The PCI Express Card Electromechanical Specification 2.0 specifies this pin requires 3.3 V. You can drive this 3.3V signal to the nPERST*

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npor

IO_POF_Load

PCIe_LinkTraining_Enumeration

dl_ltssm[4:0]

detect

detect.active polling.active

4-10

Reset

Signal Direction Description

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even if the V

VCCPGM

of the bank is not 3.3V if the following 2

conditions are met:

• The input signal meets the VIH and VIL specification for LVTTL.

• The input signal meets the overshoot specification for 100°C operation as specified by the “Maximum Allowed Overshoot and Undershoot Voltage” section in volume 3 of the Stratix V Device Handbook.

Figure 4-3: Reset and Link Training Timing Relationships

The following figure illustrates the timing relationship between npor and the LTSSM L0 state.

Note: To meet the 100 ms system configuration time, you must use the fast passive parallel configuration

scheme with CvP and a 32-bit data width (FPP x32) or use the CvP in autonomous mode.

Table 4-6: Status and Link Training Signals

Signal Direction Description

cfg_par_err

Output Indicates that a parity error in a TLP routed to the internal

Configuration Space. This error is also logged in the Vendor Specific Extended Capability internal error register. You must reset the Hard IP if this error occurs.

derr_cor_ext_rcv Output Indicates a corrected error in the RX buffer. This signal is for

debug only. It is not valid until the RX buffer is filled with data. This is a pulse, not a level, signal. Internally, the pulse is generated with the 500 MHz clock. A pulse extender extends the signal so that the FPGA fabric running at 250 MHz can capture it. Because the error was corrected by the IP core, no Application Layer intervention is required.

(3)

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derr_cor_ext_rpl Output Indicates a corrected ECC error in the retry buffer. This signal is

Signal Direction Description

for debug only. Because the error was corrected by the IP core, no Application Layer intervention is required.

(3)

Reset

4-11

derr_rpl Output Indicates an uncorrectable error in the retry buffer. This signal is

for debug only.

dlup

Output When asserted, indicates that the Hard IP block is in the Data

(3)

Link Control and Management State Machine (DLCMSM) DL_ Up state.

dlup_exit

Output This signal is asserted low for one pld_clk cycle when the IP

core exits the DLCMSM DL_Up state, indicating that the Data Link Layer has lost communication with the other end of the PCIe link and left the Up state. When this pulse is asserted, the Application Layer should generate an internal reset signal that is asserted for at least 32 cycles.

ev128ns

ev1us

hotrst_exit

Output Asserted every 128 ns to create a time base aligned activity.

Output Asserted every 1µs to create a time base aligned activity.

Output Hot reset exit. This signal is asserted for 1 clock cycle when the

LTSSM exits the hot reset state. This signal should cause the Application Layer to be reset. This signal is active low. When this pulse is asserted, the Application Layer should generate an internal reset signal that is asserted for at least 32 cycles.

int_status[3:0]

Output These signals drive legacy interrupts to the Application Layer as

follows:

• int_status[0]: interrupt signal A

• int_status[1]: interrupt signal B

• int_status[2]: interrupt signal C

• int_status[3]: interrupt signal D

ko_cpl_spc_data[11:0]

Output The Application Layer can use this signal to build circuitry to

prevent RX buffer overflow for completion data. Endpoints must advertise infinite space for completion data; however, RX buffer space is finite. ko_cpl_spc_data is a static signal that reflects the total number of 16 byte completion data units that can be stored in the completion RX buffer.

(3)

Altera does not rigorously test or verify debug signals. Only use debug signals to observe behavior. Do not use debug signals to drive custom logic.

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Reset

Signal Direction Description

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ko_cpl_spc_ header[7:0]

Output The Application Layer can use this signal to build circuitry to

prevent RX buffer overflow for completion headers. Endpoints must advertise infinite space for completion headers; however, RX buffer space is finite. ko_cpl_spc_header is a static signal that indicates the total number of completion headers that can be stored in the RX buffer.

l2_exit

Output L2 exit. This signal is active low and otherwise remains high. It is

asserted for one cycle (changing value from 1 to 0 and back to 1) after the LTSSM transitions from l2.idle to detect. When this pulse is asserted, the Application Layer should generate an internal reset signal that is asserted for at least 32 cycles.

lane_act[3:0] Output Lane Active Mode: This signal indicates the number of lanes that

configured during link training. The following encodings are defined:

• 4’b0001: 1 lane

• 4’b0010: 2 lanes

• 4’b0100: 4 lanes

• 4’b1000: 8 lanes

ltssmstate[4:0]

Output LTSSM state: The LTSSM state machine encoding defines the

following states:

• 00000: Detect.Quiet

• 00001: Detect.Active

• 00010: Polling.Active

• 00011: Polling.Compliance

• 00100: Polling.Configuration

• 00101: Polling.Speed

• 00110: config.Linkwidthstart

• 00111: Config.Linkaccept

• 01000: Config.Lanenumaccept

• 01001: Config.Lanenumwait

• 01010: Config.Complete

• 01011: Config.Idle

• 01100: Recovery.Rcvlock

• 01101: Recovery.Rcvconfig

• 01110: Recovery.Idle

• 01111: L0

• 10000: Disable

• 10001: Loopback.Entry

• 10010: Loopback.Active

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Signal Direction Description

• 10011: Loopback.Exit

• 10100: Hot.Reset

• 10101: L0s

• 11001: L2.transmit.Wake

• 11010: Speed.Recovery

• 11011: Recovery.Equalization, Phase 0

• 11100: Recovery.Equalization, Phase 1

• 11101: Recovery.Equalization, Phase 2

• 11110: recovery.Equalization, Phase 3

Reset

4-13

rx_par_err

tx_par_err[1:0]

Output When asserted for a single cycle, indicates that a parity error was

detected in a TLP at the input of the RX buffer. This error is logged as an uncorrectable internal error in the VSEC registers. For more information, refer to Uncorrectable Internal Error Status Register. You must reset the Hard IP if this error occurs because parity errors can leave the Hard IP in an unknown state.

Output When asserted for a single cycle, indicates a parity error during

TX TLP transmission. These errors are logged in the VSEC register. The following encodings are defined:

• 2’b10: A parity error was detected by the TX Transaction Layer. The TLP is nullified and logged as an uncorrectable internal error in the VSEC registers. For more information, refer to Uncorrectable Internal Error Status Register.

• 2’b01: Some time later, the parity error is detected by the TX Data Link Layer which drives 2’b01 to indicate the error. Reset the IP core when this error is detected. Contact Altera technical support if resetting becomes unworkable.

Note that not all simulation models assert the Transaction Layer error bit in conjunction with the Data Link Layer error bit.

Related Information

• PCI Express Card Electromechanical Specification 2.0

• Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide

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Interrupts for Endpoints when Multiple MSI/MSI‑X Support Is Enabled

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Interrupts for Endpoints when Multiple MSI/MSI‑X Support Is Enabled

Table 4-7: Exported Interrupt Signals for Endpoints when Multiple MSI/MSI‑X Support is Enabled

The following table describes the IP core’s exported interrupt signals when you turn on Enable multiple MSI/ MSI-X support under the Avalon-MM System Settings banner in the parameter editor.

Signal Direction Description

2014.12.15

MsiIntfc_o[81:0]

MsiControl_o[15:0]

MsixIntfc_o[15:0]

Output This bus provides the following MSI address, data, and enabled

signals:

• MsiIntf_o[81]: Master enable

• MsiIntf_o[80}: MSI enable

• MsiIntf_o[79:64]: MSI data

• MsiIntf_o[63:0]: MSI address

Output Provides for system software control of MSI as defined in Section

6.8.1.3 Message Control for MSI in the PCI Local Bus Specifica‐

tion, Rev. 3.0. The following fields are defined:

• MsiControl_o[15:9]: Reserved

• MsiControl_o[8]: Per-vector masking capable

• MsiControl_o[7]: 64-bit address capable

• MsiControl_o[6:4]: Multiple Message Enable

• MsiControl_o[3:1]: MSI Message Capable

• MsiControl_o[0]: MSI Enable.

Output Provides for system software control of MSI-X as defined in

Section 6.8.2.3 Message Control for MSI-X in the PCI Local Bus Specification, Rev. 3.0. The following fields are defined:

IntxReq_i

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Input

• MsixIntfc_o[15]: Enable

• MsixIntfc_o[14]: Mask

• MsixIntfc_o[13:11]: Reserved

• MsixIntfc_o[10:0]: Table size

When asserted, the Endpoint is requesting attention from the interrupt service routine unless MSI or MSI-X interrupts are enabled. Remains asserted until the device driver clears the pending request.

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clk

IntxReq_i

IntAck_o

clk

IntxReq_i

IntAck_o

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Physical Layer Interface Signals

Signal Direction Description

4-15

IntxAck_o

Output This signal is the acknowledge for IntxReq_i. It is asserted for at

least one cycle either when either of the following events occur:

• The Assert_INTA message TLP has been transmitted in response to the assertion of the IntxReq_i.

• The Deassert_INTA message TLP has been transmitted in response to the deassertion of the IntxReq_i signal.

Refer to the timing diagrams below.

The following figure illustrates interrupt timing for the legacy interface. In this figure the assertion of

IntxReq_i instructs the Hard IP for PCI Express to send an Assert_INTA message TLP.

Figure 4-4: Legacy Interrupt Assertion

The following figure illustrates the timing for deassertion of legacy interrupts. The assertion of IntxReq_i instructs the Hard IP for PCI Express to send a Deassert_INTA message.

Figure 4-5: Legacy Interrupt Deassertion

Physical Layer Interface Signals

Altera provides an integrated solution with the Transaction, Data Link and Physical Layers. The IP Parameter Editor generates a SERDES variation file, <variation>_serdes.v or .vhd , in addition to the Hard IP variation file, <variation>.v or .vhd. The SERDES entity is included in the library files for PCI Express.

Transceiver Reconfiguration

Dynamic reconfiguration compensates for variations due to process, voltage and temperature (PVT). Among the analog settings that you can reconfigure are VOD, pre-emphasis, and equalization.

You can use the Altera Transceiver Reconfiguration Controller to dynamically reconfigure analog settings. For more information about instantiating the Altera Transceiver Reconfiguration Controller IP core refer to Hard IP Reconfiguration .

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Transceiver Reconfiguration

Table 4-8: Transceiver Control Signals

In this table, <n> is the number of interfaces required.

Signal Name Direction Description

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reconfig_from_ xcvr[(<n>46)-1:0]

reconfig_to_xcvr[(<n>

70)-1:0]

Output Reconfiguration signals to the Transceiver Reconfiguration

Controller.

Input Reconfiguration signals from the Transceiver Reconfiguration

Controller.

The following table shows the number of logical reconfiguration and physical interfaces required for various configurations. The Quartus II Fitter merges logical interfaces to minimize the number of physical interfaces configured in the hardware. Typically, one logical interface is required for each channel and one for each PLL. The ×8 variants require an extra channel for PCS clock routing and control. The ×8 variants use channel 4 for clocking.

Table 4-9: Number of Logical and Physical Reconfiguration Interfaces

Variant Logical Interfaces

Gen1 and Gen2 ×1 2

Gen1 and Gen2 ×2 3

Gen1 and Gen2 ×4 5

Gen1 and Gen2 ×8 10

Gen3 ×1 3

Gen3 ×2 4

Gen3 ×4 6

Gen3 ×8 11

For more information about the Transceiver Reconfiguration Controller, refer to the Transceiver Reconfi‐ guration Controller chapter in the Altera Transceiver PHY IP Core User Guide .

Related Information

Altera Transceiver PHY IP Core User Guide

Altera Corporation

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Hard IP Status Extension

Table 4-10: Hard IP Status Extension Signals

This optional bus adds signals that are useful for debugging to the top-level variant, including:

• The most important native Avalon-ST RX signals

• The Configuration Space signals

• The BAR

• The ECC error

• The signal indicating that the pld_clk is in use

Signal Direction Description

Hard IP Status Extension

4-17

pld_clk_inuse

pme_to_sr

Output When asserted, indicates that the Hard IP Transaction Layer is

using the pld_clk as its clock and is ready for operation with the Application Layer. For reliable operation, hold the Application Layer in reset until pld_clk_inuse is asserted.

Output Power management turn off status register.

Root Port—This signal is asserted for 1 clock cycle when the Root Port receives the pme_turn_off acknowledge message.

Endpoint—This signal is asserted for 1 cycle when the Endpoint receives the PME_turn_off message from the Root Port.

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Hard IP Status Extension

Signal Direction Description

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rx_st_bar[7:0]

Output The decoded BAR bits for the TLP. Valid for MRd, MWr, IOWR, and

IORD TLPs. Ignored for the completion or message TLPs. Valid

during the cycle in which rx_st_sop is asserted. The following encodings are defined for Endpoints:

• Bit 0: BAR 0

• Bit 1: BAR 1

• Bit 2: Bar 2

• Bit 3: Bar 3

• Bit 4: Bar 4

• Bit 5: Bar 5

• Bit 6: Reserved

• Bit 7: Reserved

The following encodings are defined for Root Ports:

• Bit 0: BAR 0

• Bit 1: BAR 1

• Bit 2: Primary Bus number

• Bit 3: Secondary Bus number

• Bit 4: Secondary Bus number to Subordinate Bus number window

• Bit 5: I/O window

• Bit 6: Non-Prefetchable window

• Bit 7: Prefetchable window

rx_st_data[

rx_st_eop Output Indicates that this is the last cycle of the TLP when rx_st_valid

rx_st_err

Altera Corporation

<n>-1:0]

Output Receive data bus. Note that the position of the first payload

dword depends on whether the TLP address is qword aligned. The mapping of message TLPs is the same as the mapping of TLPs with 4-dword headers.

is asserted.

Output Indicates that there is an ECC error in the internal RX buffer.

Active when ECC is enabled. ECC is automatically enabled by the Quartus II assembler. ECC corrects single-bit errors and detects double-bit errors on a per byte basis.

When an uncorrectable ECC error is detected, rx_st_err is asserted for at least 1 cycle while rx_st_valid is asserted.

Altera recommends resetting the Stratix V Hard IP for PCI Express when an uncorrectable double-bit ECC error is detected.

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Hard IP Status Extension

Signal Direction Description

4-19

rx_st_sop

Output Indicates that this is the first cycle of the TLP when rx_st_valid

is asserted.

rx_st_valid Output Clocks rx_st_data into the Application Layer. Deasserts within

2 clocks of rx_st_ready deassertion and reasserts within 2 clocks of rx_st_ready assertion if more data is available to send.

serr_out

Output System Error: This signal only applies to Root Port designs that

report each system error detected, assuming the proper enabling bits are asserted in the Root Control and Device Control registers. If enabled, serr_out is asserted for a single clock cycle when a system error occurs. System errors are described in the PCI Express Base Specification 2.1 or 3.0 in the Root Control register.

tl_cfg_add[3:0]

Output Address of the register that has been updated. This signal is an

index indicating which Configuration Space register information is being driven onto tl_cfg_ctl.

tl_cfg_sts[52:0]

Output Configuration status bits. This information updates every pld_

clk cycle. The following table provides detailed descriptions of

the status bits.

tx_st_ready Output Indicates that the Transaction Layer is ready to accept data for

transmission. The core deasserts this signal to throttle the data stream. tx_st_ready may be asserted during reset. The Applica‐ tion Layer should wait at least 2 clock cycles after the reset is released before issuing packets on the Avalon-ST TX interface. The reset_status signal can also be used to monitor when the IP core has come out of reset.

If asserted by the Transaction Layer on cycle <n>tx_st_ready , then <n + readyLatency> is a ready cycle, during which the Application Layer may assert tx_st_valid and transfer data.

When tx_st_ready, tx_st_valid and tx_st_data are registered (the typical case), Altera recommends a readyLatency of 2 cycles to facilitate timing closure; however, a readyLatency of 1 cycle is possible. If no other delays are added to the read-valid latency, the resulting delay corresponds to a readyLa-

tency of 2.

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4-20

Hard IP Status Extension

Table 4-11: Mapping Between tl_cfg_sts and Configuration Space Registers

tl_cfg_sts Configuration Space Register Description

[52:49] Device Status Register[3:0] Records the following errors:

• Bit 3: unsupported request detected

• Bit 2: fatal error detected

• Bit 1: non-fatal error detected

• Bit 0: correctable error detected

[48] Slot Status Register[8] Data Link Layer state changed

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[47]

Slot Status Register[4] Command completed. (The hot plug

controller completed a command.) Note: For Root Ports, you enable the

Slot register by turning on Use Slot Power Register in the parameter editor. When enabled, access to Command Completed Interrupt Enable bit of the Slot Control register remains Read/ Write. This bit should be hardwired to 1b'0. You should not write this bit.

[46:31] Link Status Register[15:0] Records the following link status informa‐

tion:

• Bit 15: link autonomous bandwidth status

• Bit 14: link bandwidth management status

• Bit 13: Data Link Layer link active

• Bit 12: Slot clock configuration

• Bit 11: Link Training

• Bit 10: Undefined

• Bits[9:4]: Negotiated Link Width

• Bits[3:0] Link Speed

[30]

Altera Corporation

Link Status 2 Register[0] Current de-emphasis level.

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tl_cfg_sts Configuration Space Register Description

[29:25] Status Register[15:11] Records the following 5 primary command

[24] Secondary Status Register[8] Master data parity error

[23:6] Root Status Register[17:0] Records the following PME status informa‐

Configuration Space Register Access

status errors:

• Bit 15: detected parity error

• Bit 14: signaled system error

• Bit 13: received master abort

• Bit 12: received target abort

• Bit 11: signalled target abort

tion:

• Bit 17: PME pending

• Bit 16: PME status

• Bits[15:0]: PME request ID[15:0]

4-21

[5:1] Secondary Status Register[15:11] Records the following 5 secondary command

status errors:

• Bit 15: detected parity error

• Bit 14: received system error

• Bit 13: received master abort

• Bit 12: received target abort

• Bit 11: signalled target abort

[0] Secondary Status Register[8] Master Data Parity Error

Related Information

PCI Express Card Electromechanical Specification 2.0

Configuration Space Register Access

The tl_cfg_ctl signal is a multiplexed bus that contains the contents of Configuration Space registers as shown in the figure below. Information stored in the Configuration Space is accessed in round robin order where tl_cfg_add indicates which register is being accessed. The following table shows the layout of configuration information that is multiplexed on tl_cfg_ctl.

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cfg_dev_ctrl[15:0]

2 3 4 5 6 7 8

9 A B C D

cfg_dev_ctrl2[15:0]

cfg_link_ctrl[15:0] cfg_link_ctrl2[15:0]

cfg_dev_ctrl[14:12] =

Max Read Req Size

16’h0000 cfg_slot_ctrl[15:0]

8’h00 cfg_root_ctrl[7:0]

cfg_secbus[7:0] cfg_subbus[7:0]cfg_sec_ctrl[15:0]

cfg_msi_addr[11:0] cfg_io_bas[19:0]

cfg_dev_ctrl[7:5] =

Max Payload

cfg_pgm_cmd[15:0]

cfg_msi_addr[43:32] cfg_io_lim[19:0]

8’h00 cfg_np_bas[11:0] cfg_np_lim[11:0]

cfg_msi_addr[31:12] cfg_pr_bas[43:32]

cfg_pr_bas[31:0]

cfg_msi_addr[63:44] cfg_pr_lim[43:32]

cfg_pr_lim[31:0]

cfg_msixcsr[15:09] cfg_msicsr[15:0]

cfg_pmcsr[31:0]

6’h00, tx_ecrcgen[25],

rx_ecrccheck[24]

cfg_tcvcmap[23:0]

cfg_msi_data[15:0] 3’b00 0

cfg_busdev[12:0]

4-22

Configuration Space Register Access

Figure 4-6: Multiplexed Configuration Register Information Available on tl_cfg_ctl

Fields in blue are available only for Root Ports.

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Table 4-12: Configuration Space Register Descriptions

Altera Corporation

cfg_dev_ctrl

cfg_dev_ctrl2

cfg_slot_ctrl

16 Output cfg_devctrl[15:0] is Device Control for the PCI

16 Output cfg_dev2ctrl[15:0] is Device Control 2 for the

16 Output cfg_slot_ctrl[15:0] is the Slot Status of the PCI

Express capability structure.

PCI Express capability structure.

Express capability structure. This register is only available in Root Port mode.

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Configuration Space Register Access

4-23

cfg_link_ctrl

cfg_link_ctrl2

16 Output cfg_link_ctrl[15:0]is the primary Link Control

of the PCI Express capability structure. For Gen2 or Gen3 operation, you must write a 1’b1

to the Retrain Link bit (Bit[5] of the cfg_link_

ctrl) of the Root Port to initiate retraining to a

higher data rate after the initial link training to Gen1 L0 state. Retraining directs the Link Training and Status State Machine (LTSSM) to the Recovery state. Retraining to a higher data rate is not automatic for the Stratix V Hard IP for PCI Express IP Core even if both devices on the link are capable of a higher data rate.

16 Output cfg_link_ctrl2[31:16] is the secondary Link

Control register of the PCI Express capability structure for Gen2 operation.

When tl_cfg_addr=4'b0010, tl_cfg_ctl returns the primary and secondary Link Control registers,

{ {cfg_link_ctrl[15:0], cfg_link_ ctrl2[15:0]}. The primary Link Status register

contents are available on tl_cfg_sts[46:31].

cfg_prm_cmd

cfg_root_ctrl

cfg_sec_ctrl

cfg_secbus

cfg_subbus

For Gen1 variants, the link bandwidth notification bit is always set to 0. For Gen2 variants, this bit is set to 1.

16 Output Base/Primary Command register for the PCI

Configuration Space.

8 Output Root control and status register of the PCI Express

capability. This register is only available in Root Port mode.

16 Output Secondary bus Control and Status register of the

PCI Express capability. This register is available only in Root Port mode.

8 Output Secondary bus number. This register is available

only in Root Port mode.

8 Output Subordinate bus number. This register is available

only in Root Port mode.

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4-24

Configuration Space Register Access

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cfg_msi_addr

cfg_io_bas

cfg_io_lim

cfg_np_bas

cfg_np_lim

cfg_pr_bas

64 Output cfg_msi_add[63:32] is the message signaled

interrupt (MSI) upper message address. cfg_msi_

add[31:0] is the MSI message address.

20 Output The upper 20 bits of the I/O limit registers of the

Type1 Configuration Space. This register is only available in Root Port mode.

20 Output The upper 20 bits of the IO limit registers of the

Type1 Configuration Space. This register is only available in Root Port mode.

12 Output The upper 12 bits of the memory base register of the

Type1 Configuration Space. This register is only available in Root Port mode.

12 Output The upper 12 bits of the memory limit register of

the Type1 Configuration Space. This register is only available in Root Port mode.

44 Output The upper 44 bits of the prefetchable base registers

of the Type1 Configuration Space. This register is only available in Root Port mode.

cfg_pr_lim

cfg_pmcsr

cfg_msixcsr

cfg_msicsr

44 Output The upper 44 bits of the prefetchable limit registers

of the Type1 Configuration Space. Available in Root Port mode.

32 Output cfg_pmcsr[31:16] is Power Management Control

and cfg_pmcsr[15:0]is the Power Management Status register.

16 Output MSI-X message control.

16 Output MSI message control. Refer to the following table

for the fields of this register.

Altera Corporation

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Field and Bit Map

0134678951

reserved

mask

capability

64-bit

address

capability

multiple message enable multiple message capable

MSI

enable

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Configuration Space Register Access

4-25

cfg_tcvcmap

24 Output Configuration traffic class (TC)/virtual channel

(VC) mapping. The Application Layer uses this signal to generate a TLP mapped to the appropriate channel based on the traffic class of the packet.

• cfg_tcvcmap[2:0]: Mapping for TC0 (always 0)

• cfg_tcvcmap[5:3]: Mapping for TC1.

• cfg_tcvcmap[8:6]: Mapping for TC2.

• cfg_tcvcmap[11:9]: Mapping for TC3.

• cfg_tcvcmap[14:12]: Mapping for TC4.

• cfg_tcvcmap[17:15]: Mapping for TC5.

• cfg_tcvcmap[20:18]: Mapping for TC6.

• cfg_tcvcmap[23:21]: Mapping for TC7.

cfg_msi_data

cfg_busdev

16 Output cfg_msi_data[15:0] is message data for MSI.

13 Output Bus/Device Number captured by or programmed in

the Hard IP.

Figure 4-7: Configuration MSI Control Status Register

Table 4-13: Configuration MSI Control Status Register Field Descriptions

Bit(s) Field Description

[15:9] Reserved N/A

[8] mask capability Per-vector masking capable. This bit is hardwired to 0 because the

[7] 64-bit address

capability

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function does not support the optional MSI per-vector masking using the Mask_Bits and Pending_Bits registers defined in the PCI Local Bus Specification. Per-vector masking can be implemented using Application Layer registers.

64-bit address capable.

• 1: function capable of sending a 64-bit message address

• 0: function not capable of sending a 64-bit message address

Altera Corporation

pld_clk

tl_cfg_add[3:0]

tl_cfg_ctl[31:0]

2 3 4 5 6 7 8 9 A B 8 9 A B C D E

00... 00... 00... 7F...

00000000 00000000

00... 00...

4-26

Configuration Space Register Access Timing

Bit(s) Field Description

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[6:4] multiple message

enable

[3:1]

multiple message capable

This field indicates permitted values for MSI signals. For example, if “100” is written to this field 16 MSI signals are allocated.

• 3’b000: 1 MSI allocated

• 3’b001: 2 MSI allocated

• 3’b010: 4 MSI allocated

• 3’b011: 8 MSI allocated

• 3’b100: 16 MSI allocated

• 3’b101: 32 MSI allocated

• 3’b110: Reserved

• 3’b111: Reserved

This field is read by system software to determine the number of requested MSI messages.

• 3’b000: 1 MSI requested

• 3’b001: 2 MSI requested

• 3’b010: 4 MSI requested

• 3’b011: 8 MSI requested

• 3’b100: 16 MSI requested

• 3’b101: 32 MSI requested

• 3’b110: Reserved

[0] MSI Enable If set to 0, this component is not permitted to use MSI.

Related Information

• PCI Express Base Specification 2.1 or 3.0

• PCI Local Bus Specification, Rev. 3.0

Configuration Space Register Access Timing

Figure 4-8: tl_cfg_ctl Timing

The following figure shows typical traffic on the tl_cfg_ctl bus. The tl_cfg_add index increments on the rising edge of the pld_clk. The address specifies which Configuration Space register data value is being driven onto tl_cfg_ctl.

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Serial Data Signals

Table 4-14: 1-Bit Interface Signals

Signal Direction Description

Serial Data Signals

4-27

(1)

Output Transmit output. These signals are the serial outputs of lanes 7–0.

Input Receive input. These signals are the serial inputs of lanes 7–0.

tx_out[7:0]

rx_in[7:0]

Note:

1. The x1 IP core only has lane 0. The x2 IP core only has lanes 1–0. The x4 IP core only has lanes 3–0.

Refer to

Pin-out Files for Altera Devices for pin-out tables for all Altera devices in .pdf, .txt, and .xls

formats. Transceiver channels are arranged in groups of six. For GX devices, the lowest six channels on the left side

of the device are labeled GXB_L0, the next group is GXB_L1, and so on. Channels on the right side of the device are labeled GXB_R0, GXB_R1, and so on. Be sure to connect the Hard IP for PCI Express on the left side of the device to appropriate channels on the left side of the device, as specified in the Pin-out Files for Altera Devices.

Related Information

Pin-out Files for Altera Devices

Physical Layout of Hard IP in Stratix V GX/GT/GS Devices

Stratix V devices include one, two, or four Hard IP for PCI Express IP cores. The following figures illustrate the placement of the PCIe IP cores, transceiver banks, and channels for the largest Stratix V devices. Note that the bottom left hard IP block includes the CvP functionality for flip chip packages. For other package types, the CvP functionality is in the bottom right block. All other Hard IP blocks do not include the CvP functionality.

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3 Ch

6 Ch

3 Ch

6 Ch

PCIe Hard

IOBANK_B5R

IOBANK_B4R

IOBANK_B3R

IOBANK_B2R

IOBANK_B1R

IOBANK_B0R

IOBANK_B5L

IOBANK_B4L

IOBANK_B3L

IOBANK_B2L

IOBANK_B1L

IOBANK_B0L

Number of Channels

Per Bank

Transceiver

Bank Names

Number of Channels

Per Bank

Transceiver

Bank Names

Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 0

PCIe Hard

with

CvP

4-28

Physical Layout of Hard IP in Stratix V GX/GT/GS Devices

Figure 4-9: Stratix V GX/GT/GS Devices with Four PCIe Hard IP Blocks

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Altera Corporation

Smaller devices include the following PCIe Hard IP Cores:

• One Hard IP for PCIe IP core - bottom left IP core with CvP, located at GX banks L0 and L1

• Two Hard IP for PCIe IP cores - bottom left IP core with CvP and bottom right IP Core, located at banks L0 and L1, and banks R0 and R1

Refer to Stratix V GX/GT Channel and PCIe Hard IP (HIP) Layout for comprehensive information on the number of Hard IP for PCIe IP cores available in various Stratix V packages.

Related Information

• Transceiver Architecture in Stratix V Devices

• Pin-Out Files for Altera Devices

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Ch5

Ch3 Ch2

Ch1 Ch0

ATX PLL0

CMU PLLATX PLL1

PCIe Hard IP

Ch0

Ch1

Ch5

Ch3 Ch2 Ch1 Ch0

ATX PLL0

CMU PLL

PCIe Hard IP

ATX PLL1

Ch0

Ch1

Ch2

Ch3

Ch5

Ch3 Ch2 Ch1 Ch0

ATX PLL0

CMU PLL

ATX PLL1

Ch0

Ch1

Ch2

Ch3

Ch11

Ch9

Ch8 Ch7 Ch6

Ch10

PCIe Hard IP

Ch5

Ch6

Ch7

Ch4

Ch5

Ch3 Ch2

CMU PLL

Ch0

ATX PLL0

Ch4ATX PLL1

PCIe Hard IP

Ch0

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Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices

Figure 4-10: Arria V GZ and Stratix V GX/GT/GS Gen1 and Gen2 Channel Placement Using the CMU PLL

In the following figures the channels shaded in blue provide the transmit CMU PLL generating the highspeed serial clock.

4-29

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Ch5

Ch3 Ch2

CMU PLL

Ch0

ATX PLL0 Gen3

Ch4

PCIe Hard IP

Ch0

Ch5

Ch3 Ch2

PCIe Hard IP

Ch0

Ch1

Ch0

Ch5

Ch3 Ch2

Ch1

Ch1 Ch0

PCIe Hard IP

Ch0

Ch1

Ch2

Ch3

ATX PLL1 Gen3

ATX PLL0

ATX PLL1 Gen3

ATX PLL0

Ch5

Ch3 Ch2 Ch1 Ch0 Ch0

Ch1

Ch2

Ch3

Ch11

Ch9

Ch8 Ch7 Ch6

Ch10

PCIe Hard IP

Ch5

Ch6

Ch7

Ch4

ATX PLL0

ATX PLL1 Gen3

ATX PLL0

CMU PLL

ATX PLL1

CMU PLL

ATX PLL1

4-30

Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices

Figure 4-11: Arria V GZ and Stratix V GX/GT/GS Gen3 Channel Placement Using the CMU and ATX PLLs

Gen3 requires two PLLs to facilitate rate switching between the Gen1, Gen2, and Gen3 data rates. Channels shaded in blue provide the transmit CMU PLL generating the high-speed serial clock. The ATX PLL shaded in blue is the ATX PLL used in these configurations.

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ATX PLL0

Ch5

Ch3 Ch2 Ch1

Ch0

ATX PLL0

Ch4

PCIe Hard IP

ATX PLL1

Ch0

Ch5

Ch3 Ch2

Ch1 Ch0

ATX PLL0

Ch4ATX PLL1

PCIe Hard IP

Ch0

Ch1

Ch5

Ch3 Ch2 Ch1 Ch0

ATX PLL0

Ch4

PCIe Hard IP

ATX PLL1

Ch0

Ch1

Ch2

Ch3

Ch5

Ch3 Ch2 Ch1 Ch0

ATX PLL0

ATX PLL1 Ch4

ATX PLL1

Ch0

Ch1

Ch2

Ch3

Ch11

Ch9

Ch8 Ch7 Ch6

Ch10

PCIe Hard IP

Ch5

Ch6

Ch7

Ch4

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Figure 4-12: Arria V GZ and Stratix V GX/GT/GS Gen1 and Gen2 Channel Placement Using the ATX PLL

PIPE Interface Signals

Selecting the ATX PLL has the following advantages over selecting the CMU PLL:

• The ATX PLL saves one channel in Gen1 and Gen2 ×1, ×2, and ×4 configurations.

• The ATX PLL has better jitter performance than the CMU PLL.

Note: You must use the soft reset controller when you select the ATX PLL and you cannot use CvP.

4-31

PIPE Interface Signals

These PIPE signals are available for Gen1, Gen2, and Gen3 variants so that you can simulate using either the serial or the PIPE interface. Simulation is much faster using the PIPE interface because the PIPE simulation bypasses the SERDES model . By default, the PIPE interface is 8 bits for Gen1 and Gen2 and 32 bits for Gen3. You can use the PIPE interface for simulation even though your actual design includes a serial interface to the internal transceivers. However, it is not possible to use the Hard IP PIPE interface in hardware, including probing these signals using SignalTap® II Embedded Logic Analyzer.

Note:

The Altera Root Port BFM bypasses Gen3 Phase 2 and Phase 3 Equalization. However, Gen3 variants can perform Phase 2 and Phase 3 equalization if instructed by a third-party BFM.

In the following table, signals that include lane number 0 also exist for lanes 1-7.

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4-32

PIPE Interface Signals

Table 4-15: PIPE Interface Signals

Signal Direction Description

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txdata0[7:0]

txdatak0

Output Transmit data <n>. This bus transmits data on lane <n>.

Output Transmit data control <n>. This signal serves as the control bit

for txdata <n>.

txblkst0

Output For Gen3 operation, indicates the start of a block in the transmit

direction.

txdataskip0 Output For Gen3 operation. Allows the MAC to instruct the TX interface

to ignore the TX data interface for one clock cycle. The following encodings are defined:

• 1’b0: TX data is invalid

• 1’b1: TX data is valid

tx_deemph0

Output Transmit de-emphasis selection. The Stratix V Hard IP for PCI

Express sets the value for this signal based on the indication received from the other end of the link during the Training Sequences (TS). You do not need to change this value.

(2)

Input Receive data <n>. This bus receives data on lane <n>.

Input Receive data <n>. This bus receives data on lane <n>. Bit 0

rxdata0[7:0]

rxdatak0

corresponds to the lowest-order byte of rxdata, and so on. A value of 0 indicates a data byte. A value of 1 indicates a control byte. For Gen1 and Gen2 only.

rxblkst0 Input For Gen3 operation, indicates the start of a block in the receive

txdetectrx0 Output Transmit detect receive <n>. This signal tells the PHY layer to

txelecidle Output Transmit electrical idle <n>. This signal forces the TX output to

txcompl0 Output Transmit compliance <n>. This signal forces the running

rxpolarity0 Output Receive polarity <n>. This signal instructs the PHY layer to

Altera Corporation

direction.

start a receive detection operation or to begin loopback.

electrical idle.

disparity to negative in Compliance Mode (negative COM character).

invert the polarity of the 8B/10B receiver decoding block.

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powerdown0[1:0] Output Power down <n>. This signal requests the PHY to change its

Signal Direction Description

power state to the specified state (P0, P0s, P1, or P2).

PIPE Interface Signals

4-33

currentcoeff0[17:0]

Output For Gen3, specifies the coefficients to be used by the transmitter.

The 18 bits specify the following coefficients:

• [5:0]: C

• [11:6]: C

• [17:12]: C

currentrxpreset0[2:0]

tx_margin[2:0] Output Transmit V

Output For Gen3 designs, specifies the current preset.

-1 0

margin selection. The value for this signal is based

on the value from the Link Control 2 Register. Available for simulation only.

txswing

Output When asserted, indicates full swing for the transmitter voltage.

When deasserted indicates half swing.

txsynchd0[1:0] Output For Gen3 operation, specifies the transmit block type. The

following encodings are defined:

• 2'b01: Ordered Set Block

• 2'b10: Data Block

rxsynchd0[1:0] Input For Gen3 operation, specifies the receive block type. The

following encodings are defined:

• 2'b01: Ordered Set Block

• 2'b10: Data Block

rxvalid0

(1)

Input Receive valid <n>. This signal indicates symbol lock and valid

data on rxdata<n> and rxdatak <n>.

phystatus0

(1)

Input PHY status <n>. This signal communicates completion of several

PHY requests.

rxelecidle0

(1)

Input Receive electrical idle <n>. When asserted, indicates detection of

an electrical idle.

rxstatus0[2:0]

(1)

Input Receive status <n>. This signal encodes receive status, including

error codes for the receive data stream and receiver detection.

simu_mode_pipe Input When set to 1, the PIPE interface is in simulation mode.

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PIPE Interface Signals

Signal Direction Description

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sim_pipe_rate[1:0]

sim_pipe_pclk_in

sim_pipe_pclk_out

sim_pipe_clk250_out

sim_pipe_clk500_out

sim_pipe_ ltssmstate0[4:0]

Output The 2-bit encodings have the following meanings:

• 2’b00: Gen1 rate (2.5 Gbps)

• 2’b01: Gen2 rate (5.0 Gbps)

• 2’b1X: Gen3 rate (8.0 Gbps)

Input This clock is used for PIPE simulation only, and is derived from

the refclk. It is the PIPE interface clock used for PIPE mode simulation.

Output TX datapath clock to the BFM PHY. pclk_out is derived from

refclk and provides the source synchronous clock for TX data from the PHY.

Output Used to generate pclk.

Input and

Output

LTSSM state: The LTSSM state machine encoding defines the following states:

• 5’b00000: Detect.Quiet

• 5’b 00001: Detect.Active

• 5’b00010: Polling.Active

• 5’b 00011: Polling.Compliance

• 5’b 00100: Polling.Configuration

• 5’b00101: Polling.Speed

• 5’b00110: config.LinkwidthsStart

• 5’b 00111: Config.Linkaccept

• 5’b 01000: Config.Lanenumaccept

• 5’b01001: Config.Lanenumwait

• 5’b01010: Config.Complete

• 5’b 01011: Config.Idle

• 5’b01100: Recovery.Rcvlock

• 5’b01101: Recovery.Rcvconfig

• 5’b01110: Recovery.Idle

• 5’b 01111: L0

• 5’b10000: Disable

• 5’b10001: Loopback.Entry

• 5’b10010: Loopback.Active

• 5’b10011: Loopback.Exit

• 5’b10100: Hot.Reset

• 5’b10101: L0s

• 5’b11001: L2.transmit.Wake

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Signal Direction Description

• 5’b11010: Speed.Recovery

• 5’b11011: Recovery.Equalization, Phase 0

• 5’b11100: Recovery.Equalization, Phase 1

• 5’b11101: Recovery.Equalization, Phase 2

• 5’b11110: Recovery.Equalization, Phase 3

• 5’b11111: Recovery.Equalization, Done

PIPE Interface Signals

4-35

rxfreqlocked0

(1)

Input When asserted indicates that the pclk_in used for PIPE

simulation is valid.

rxdataskip0 Output For Gen3 operation. Allows the PCS to instruct the RX interface

to ignore the RX data interface for one clock cycle. The following encodings are defined:

• 1’b0: RX data is invalid

• 1’b1: RX data is valid

eidleinfersel0[2:0]

Output Electrical idle entry inference mechanism selection. The

following encodings are defined:

• 3'b0xx: Electrical Idle Inference not required in current LTSSM state

• 3'b100: Absence of COM/SKP Ordered Set in the 128 us window for Gen1 or Gen2

• 3'b101: Absence of TS1/TS2 Ordered Set in a 1280 UI interval for Gen1 or Gen2

• 3'b110: Absence of Electrical Idle Exit in 2000 UI interval for Gen1 and 16000 UI interval for Gen2

• 3'b111: Absence of Electrical idle exit in 128 us window for Gen1

Notes:

1. These signals are for simulation only. For Quartus II software compilation, these pipe signals can be

left floating.

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Test Signals

Table 4-16: Test Interface Signals

The test_in bus provides run-time control and monitoring of the internal state of the IP core.

Signal Direction Description

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test_in[31:0]

Input The bits of the test_in bus have the following definitions:

• [0]: Simulation mode. This signal can be set to 1 to accelerate initialization by reducing the value of many initialization counters.

• [1]: Reserved. Must be set to 1’b0

• [2]: Descramble mode disable. This signal must be set to 1 during initialization in order to disable data scrambling. You can use this bit in simulation for both Endpoints and Root Ports to observe descrambled data on the link. Descrambled data cannot be used in open systems because the link partner typically scrambles the data.

• [4:3]: Reserved. Must be set to 4’b01.

• [5]: Compliance test mode. Disable/force compliance mode. When set, prevents the LTSSM from entering compliance mode. Toggling this bit controls the entry and exit from the compliance state, enabling the transmission of Gen1, Gen2 and Gen3 compliance patterns.

• [6]: Forces entry to compliance mode when a timeout is reached in the polling.active state and not all lanes have detected their exit condition.

• [7]: Disable low power state negotiation. Altera recommends setting thist bit.

• [31:8]: Reserved. Set to all 0s.

Related Information

How can I observe the Hard IP for PCI Express PIPE interface signals for Arria V GZ and Stratix V devices?

Altera Corporation

For more information about using the test_in to debug, refer to the Knowledge Base Solution How can I observe the Hard IP for

PCI Express PIPE interface signals for Arria V GZ and Stratix V devices? in the Related Links below.

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101 Innovation Drive, San Jose, CA 95134

Registers

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Correspondence between Configuration Space Registers and the PCIe Specification

Table 5-1: Correspondence between Configuration Space Capability Structures and PCIe Base Specification Description

For the Type 0 and Type 1 Configuration Space Headers, the first line of each entry lists Type 0 values and the second line lists Type 1 values when the values differ.

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification

0x000:0x03C PCI Header Type 0 Configuration Registers Type 0 Configuration Space Header

0x000:0x03C PCI Header Type 1 Configuration Registers Type 1 Configuration Space Header

0x040:0x04C Reserved N/A

0x050:0x05C MSI Capability Structure MSI Capability Structure

0x068:0x070 MSI-X Capability Structure MSI-X Capability Structure

0x070:0x074 Reserved N/A

0x078:0x07C Power Management Capability Structure PCI Power Management Capability

Structure

0x080:0x0B8 PCI Express Capability Structure PCI Express Capability Structure

0x0B8:0x0FC Reserved N/A

0x094:0x0FF Root Port N/A

0x100:0x16C Virtual Channel Capability Structure

Virtual Channel Capability

(Reserved)

ISO 9001:2008 Registered

5-2

Correspondence between Configuration Space Registers and the PCIe Specification

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification

0x170:0x17C Reserved N/A

0x180:0x1FC Virtual channel arbitration table (Reserved) VC Arbitration Table

0x200:0x23C Port VC0 arbitration table (Reserved) Port Arbitration Table

0x240:0x27C Port VC1 arbitration table (Reserved) Port Arbitration Table

0x280:0x2BC Port VC2 arbitration table (Reserved) Port Arbitration Table

0x2C0:0x2FC Port VC3 arbitration table (Reserved) Port Arbitration Table

0x300:0x33C Port VC4 arbitration table (Reserved) Port Arbitration Table

0x340:0x37C Port VC5 arbitration table (Reserved) Port Arbitration Table

0x380:0x3BC Port VC6 arbitration table (Reserved) Port Arbitration Table

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0x3C0:0x3FC Port VC7 arbitration table (Reserved) Port Arbitration Table

0x400:0x7FC Reserved PCIe spec corresponding section name

0x800:0x834 Advanced Error Reporting AER (optional) Advanced Error Reporting Capability

0x838:0xFFF Reserved N/A

0x000 Device ID, Vendor ID Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x004 Status, Command Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x008 Class Code, Revision ID Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x00C BIST, Header Type, Primary Latency Timer,

Cache Line Size

Type 0 Configuration Space Header Type 1 Configuration Space Header

0x010 Base Address 0 Base Address Registers

0x014 Base Address 1 Base Address Registers

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Registers

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Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification

Correspondence between Configuration Space Registers and the PCIe Specification

5-3

0x018 Base Address 2

Secondary Latency Timer, Subordinate Bus Number, Secondary Bus Number, Primary Bus Number

0x01C Base Address 3

Secondary Status, I/O Limit, I/O Base

0x020 Base Address 4

Memory Limit, Memory Base

0x024 Base Address 5

Prefetchable Memory Limit, Prefetchable Memory Base

0x028 Reserved

Prefetchable Base Upper 32 Bits

0x02C Subsystem ID, Subsystem Vendor ID

Base Address Registers Secondary Latency Timer, Type 1

Configuration Space Header, Primary Bus Number

Base Address Registers Secondary Status Register ,Type 1

Configuration Space Header

Base Address Registers Type 1 Configuration Space Header

Base Address Registers Prefetchable Memory Limit, Prefetchable

Memory Base

N/A Type 1 Configuration Space Header

Type 0 Configuration Space Header

Prefetchable Limit Upper 32 Bits

0x030 I/O Limit Upper 16 Bits, I/O Base Upper 16

Bits

Type 1 Configuration Space Header

Type 0 Configuration Space Header Type 1 Configuration Space Header

0x034 Reserved, Capabilities PTR Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x038 Reserved N/A

0x03C Interrupt Pin, Interrupt Line

Bridge Control, Interrupt Pin, Interrupt Line

0x050 MSI-Message Control Next Cap Ptr

Type 0 Configuration Space Header Type 1 Configuration Space Header

MSI and MSI-X Capability Structures

Capability ID

0x054 Message Address MSI and MSI-X Capability Structures

0x058 Message Upper Address MSI and MSI-X Capability Structures

0x05C Reserved Message Data MSI and MSI-X Capability Structures

Registers

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Correspondence between Configuration Space Registers and the PCIe Specification

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification

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0x068 MSI-X Message Control Next Cap Ptr

MSI and MSI-X Capability Structures

Capability ID

0x06C MSI-X Table Offset BIR MSI and MSI-X Capability Structures

0x070 Pending Bit Array (PBA) Offset BIR MSI and MSI-X Capability Structures

0x078 Capabilities Register Next Cap PTR Cap ID PCI Power Management Capability

Structure

0x07C Data PM Control/Status Bridge Extensions

Power Management Status & Control

PCI Power Management Capability Structure

0x800 PCI Express Enhanced Capability Header Advanced Error Reporting Enhanced

Capability Header

0x804 Uncorrectable Error Status Register Uncorrectable Error Status Register

0x808 Uncorrectable Error Mask Register Uncorrectable Error Mask Register

0x80C Uncorrectable Error Severity Register Uncorrectable Error Severity Register

0x810 Correctable Error Status Register Correctable Error Status Register

0x814 Correctable Error Mask Register Correctable Error Mask Register

0x818 Advanced Error Capabilities and Control

Advanced Error Capabilities and Control Register

0x81C Header Log Register Header Log Register

0x82C Root Error Command Root Error Command Register

0x830 Root Error Status Root Error Status Register

0x834 Error Source Identification Register Correct‐

Error Source Identification Register

able Error Source ID Register

Related Information

PCI Express Base Specification 2.1 or 3.0

Altera Corporation

Registers

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0x000 0x004 0x008 0x00C 0x010

0x014

0x018

0x01C

0x020 0x024 0x028

0x02C

0x030 0x034 0x038

0x03C

Device ID Vendor ID

Status

Command

Class Code Revision ID

0x00 Header Type 0x00 Cache Line Size

BAR Registers BAR Registers BAR Registers BAR Registers BAR Registers

BAR Registers

Reserved

Subsystem Device ID Subsystem Vendor ID

Expansion ROM Base Address

Reserved

Capabilities Pointer

0x00 Interrupt Pin Interrupt Line

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Type 0 Configuration Space Registers

Figure 5-1: Type 0 Configuration Space Registers - Byte Address Offsets and Layout

Endpoints store configuration data in the Type 0 Configuration Space. The Correspondence between

Configuration Space Registers and the PCIe Specification on page 5-1 lists the appropriate section of

the PCI Express Base Specification that describes these registers.

Type 0 Configuration Space Registers

5-5

Registers

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0x0000

0x004

Device ID

0x008

0x00C

0x010 0x014 0x018

0x01C

0x020 0x024 0x028

0x02C

0x030 0x034 0x038

0x03C

Vendor ID

BIST Header Type Primary Latency Timer Cache Line Size

Status Command

Class Code Revision ID

BAR Registers BAR Registers

Secondary Latency Timer Subordinate Bus Number Secondary Bus Number Primary Bus Number

Secondary Status I/O Limit I/O Base

Memory Limit Memory Base

Prefetchable Base Upper 32 Bits

Prefetchable Limit Upper 32 Bits

I/O Limit Upper 16 Bits I/O Base Upper 16 Bits

Reserved Capabilities Pointer

Expansion ROM Base Address

Bridge Control Interrupt Pin Interrupt Line

Prefetchable Memory Limit Prefetchable Memory Base

0x050

0x054 0x058

Message Control

Configuration MSI Control Status

Next Cap Ptr

Message Address

Message Upper Address

Reserved Message Data

0x05C

Capability ID

5-6

Type 1 Configuration Space Registers

Figure 5-2: Type 1 Configuration Space Registers (Root Ports)

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PCI Express Capability Structures

Figure 5-3: MSI Capability Structure

Registers

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0x068

0x06C

0x070

Message Control Next Cap Ptr

MSI-X Table Offset

MSI-X Pending Bit Array (PBA) Offset

31 24 23 16 15 8 7 0

Capability ID

3 2

MSI-X

Table BAR

Indicator

MSI-X

Pending

Bit Array

- BAR

Indicator

0x078

0x07C

Capabilities Register Next Cap Ptr

Data

31 24 23 16 15 8 7 0

Capability ID

Power Management Status and Control

PM Control/Status Bridge Extensions

Byte Offs et 31:24 23:16 15:8 7:0

0x800 0x804 Uncorrectable Error Status Register

PCI Express Enhanced Capability Register

Uncorrectable Error Severity Register

Uncorrectable Error Mask Register0x808 0x80C 0x810 0x814 0x818 0x81C 0x82C 0x830 0x834

Correctable Error Status Register

Correctable Error Mask Register

Advanced Error Capabilities and Control Register

Header Log Register

Root Error Command Register

Root Error Status Register

Error Source Identification Register Correctable Error Source Identification Register

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Figure 5-4: MSI-X Capability Structure

Figure 5-5: Power Management Capability Structure - Byte Address Offsets and Layout

PCI Express Capability Structures

5-7

Figure 5-6: PCI Express AER Extended Capability Structure

Registers

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0x080 0x084

0x088

0x08C

0x090

0x094

0x098 0x09C 0x0A0

0x0A4 0x0A8

0x0AC

0x0B0 0x0B4

0x0B8

PCI Express Capabilities Register Next Cap Pointer

Device Capabilities

Device Status Device Control

Slot Capabilities

Root Status

Device Compatibilities 2

Link Capabilities 2

Link Status 2

Link Control 2

Slot Capabilities 2

Slot Status 2

Slot Control 2

PCI Express

Capabilities ID

Link Capabilities

Link Status Link Control

Slot Status

Slot Control

Device Status 2 Device Control 2

Root Capabilities

Root Control

5-8

PCI Express Capability Structures

Figure 5-7: PCI Express Capability Structure - Byte Address Offsets and Layout

In the following table showing the PCI Express Capability Structure, registers that are not applicable to a device are reserved.

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Registers

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0x200

0x204

Next Capability Offset Version

VSEC Length

Altera-Defined VSEC Capability Header

VSEC ID

Altera-Defined, Vendor-Specific Header

VSEC

Revision

Altera Marker

0x208

JTAG Silicon ID DW0 JTAG Silicon ID0x20C JTAG Silicon ID DW1 JTAG Silicon ID

0x210

JTAG Silicon ID DW2 JTAG Silicon ID

0x214

JTAG Silicon ID DW3 JTAG Silicon ID

0x218

CvP Status0x21C

CvP Mode Control0x220

CvP Data2 Register0x224

CvP Data Register0x228

CvP Programming Control Register

0x22C

Reserved

0x230

Uncorrectable Internal Error Status Register0x234

Uncorrectable Internal Error Mask Register0x238

Correctable Internal Error Status Register0x23C

User Device or Board Type ID

Correctable Internal Error Mask Register0x240

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Altera-Defined VSEC Registers

Figure 5-8: VSEC Registers

This extended capability structure supports Configuration via Protocol (CvP) programming and detailed internal error reporting.

Altera-Defined VSEC Registers

5-9

Table 5-2: Altera‑Defined VSEC Capability Register, 0x200

The Altera-Defined Vendor Specific Extended Capability. This extended capability structure supports Configuration via Protocol (CvP) programming and detailed internal error reporting.

Bits Register Description Value Access

[15:0] PCI Express Extended Capability ID. Altera-defined value for

[19:16] Version. Altera-defined value for VSEC version. 0x1 RO

VSEC Capability ID.

[31:20] Next Capability Offset. Starting address of the next Capability

Structure implemented, if any.

Registers

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0x000B RO

Variable RO

Altera Corporation

5-10

CvP Registers

Table 5-3: Altera‑Defined Vendor Specific Header

You can specify these values when you instantiate the Hard IP. These registers are read-only at run-time.

Bits Register Description Value Access

[15:0] VSEC ID. A user configurable VSEC ID. User entered RO

[19:16] VSEC Revision. A user configurable VSEC revision. Variable RO

[31:20] VSEC Length. Total length of this structure in bytes. 0x044 RO

Table 5-4: Altera Marker Register

Bits Register Description Value Access

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[31:0] Altera Marker. This read only register is an additional marker. If

you use the standard Altera Programmer software to configure

A Device

Value the device with CvP, this marker provides a value that the programming software reads to ensure that it is operating with the correct VSEC.

Table 5-5: JTAG Silicon ID Register

Bits Register Description Value Access

[127:96]

JTAG Silicon ID DW3

Application

Specific

[95:64]

JTAG Silicon ID DW2

Application

Specific

[63:32]

JTAG Silicon ID DW1

Application

Specific

[31:0] JTAG Silicon ID DW0. This is the JTAG Silicon ID that CvP

programming software reads to determine that the correct SRAM

Application

Specific

object file (.sof) is being used.

Table 5-6: User Device or Board Type ID Register

Bits Register Description Value Access

[15:0] Configurable device or board type ID to specify to CvP the

correct .sof.

CvP Registers

Altera Corporation

Variable RO

Registers

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Table 5-7: CvP Status

The CvP Status register allows software to monitor the CvP status signals.

Bits Register Description Reset Value Access

[31:26] Reserved 0x00 RO

CvP Registers

5-11

[25] PLD_CORE_READY. From FPGA fabric. This status bit is

Variable RO

provided for debug.

[24] PLD_CLK_IN_USE. From clock switch module to fabric. This

Variable RO

status bit is provided for debug.

[23] CVP_CONFIG_DONE. Indicates that the FPGA control block has

Variable RO

completed the device configuration via CvP and there were

no errors. [22] Reserved Variable RO [21] USERMODE. Indicates if the configurable FPGA fabric is in user

Variable RO

mode. [20] CVP_EN. Indicates if the FPGA control block has enabled CvP

Variable RO

mode. [19] CVP_CONFIG_ERROR. Reflects the value of this signal from the

Variable RO FPGA control block, checked by software to determine if there was an error during configuration.

[18] CVP_CONFIG_READY. Reflects the value of this signal from the

Variable RO FPGA control block, checked by software during programming algorithm.

[17:0] Reserved Variable RO

Table 5-8: CvP Mode Control

The CvP Mode Control register provides global control of the CvP operation.

Bits Register Description Reset Value Access

[31:16] Reserved. 0x0000 RO

[15:8] CVP_NUMCLKS.

0x00 RW

This is the number of clocks to send for every CvP data write. Set this field to one of the values below depending on your configura‐ tion image:

• 0x01 for uncompressed and unencrypted images

• 0x04 for uncompressed and encrypted images

• 0x08 for all compressed images

[7:3] Reserved. 0x0 RO

[2] CVP_FULLCONFIG. Request that the FPGA control block

1’b0 RW reconfigure the entire FPGA including the Stratix V Hard IP for PCI Express, bring the PCIe link down.

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CvP Registers

Bits Register Description Reset Value Access

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[1] HIP_CLK_SEL. Selects between PMA and fabric clock when USER_

MODE = 1 and PLD_CORE_READY = 1. The following encodings are

defined:

• 1: Selects internal clock from PMA which is required for CVP_

MODE.

• 0: Selects the clock from soft logic fabric. This setting should

only be used when the fabric is configured in USER_MODE with a configuration file that connects the correct clock.

To ensure that there is no clock switching during CvP, you should only change this value when the Hard IP for PCI Express has been idle for 10 µs and wait 10 µs after changing this value before resuming activity.

[0] CVP_MODE. Controls whether the IP core is in CVP_MODE or normal

mode. The following encodings are defined:

• 1:CVP_MODE is active. Signals to the FPGA control block active

and all TLPs are routed to the Configuration Space. This CVP_

MODE cannot be enabled if CVP_EN = 0.

• 0: The IP core is in normal mode and TLPs are routed to the

FPGA fabric.

Table 5-9: CvP Data Registers

1’b0 RW

The following table defines the CvP Data registers. For 64-bit data, the optional CvP Data2 stores the upper 32 bits of data. Programming software should write the configuration data to these registers. If you Every write to these register sets the data output to the FPGA control block and generates <n> clock cycles to the FPGA control block as specified by the CVP_NUM_CLKS field in the CvP Mode Control register. Software must ensure that all bytes in the memory write dword are enabled. You can access this register using configuration writes, alternatively, when in CvP mode, these registers can also be written by a memory write to any address defined by a memory space BAR for this device. Using memory writes should allow for higher throughput than configuration writes.

Bits Register Description Reset Value Access

[31:0] Upper 32 bits of configuration data to be transferred to the FPGA

0x00000000 RW control block to configure the device. You can choose 32- or 64bit data.

[31:0] Lower 32 bits of configuration data to be transferred to the FPGA

0x00000000 RW control block to configure the device.

Table 5-10: CvP Programming Control Register

This register is written by the programming software to control CvP programming.

Bits Register Description Reset Value Access

[31:2] Reserved. 0x0000 RO

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Transaction,

Data Link,

and PHY

Qsys Generated Endpoint (Altera FPGA)

PCI Express Avalon-MM Bridge

Interconnect

Avalon-MM Hard IP for PCI Express

Control and Status Registers

Control Register Access (CRA)

PCIe TLP Address

RX PCIe Link

0x0000-0x0FFF: PCIe processors

0x1000-0x1FFF: Addr translation

0x2000-0x2FFF: Root Port TLP Data

0x3000-0x3FFF: Avalon-MM processors

Host CPU

Avalon-MM

32-Bit Byte Address

Avalon-MM Slave

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64- or 128-Bit Avalon-MM Bridge Register Descriptions

Bits Register Description Reset Value Access

5-13

[1] START_XFER. Sets the CvP output to the FPGA control block

indicating the start of a transfer.

[0] CVP_CONFIG. When asserted, instructs that the FPGA control

block begin a transfer via CvP.

64- or 128-Bit Avalon-MM Bridge Register Descriptions

The CRA Avalon-MM slave module provides access control and status registers in the PCI Express Avalon-MM bridge. In addition, it provides access to selected Configuration Space registers and link status registers in read-only mode. This module is optional. However, you must include it to access the registers.

The control and status register address space is 16 KBytes. Each 4-KByte sub-region contains a set of functions, which may be specific to accesses from the PCI Express Root Complex only, from Avalon-MM processors only, or from both types of processors. Because all accesses come across the interconnect fabric —requests from the Avalon-MM Stratix V Hard IP for PCI Express are routed through the interconnect fabric—hardware does not enforce restrictions to limit individual processor access to specific regions. However, the regions are designed to enable straight-forward enforcement by processor software. The following figure illustrates accesses to the Avalon-MM control and status registers from the Host CPU and PCI Express link.

1’b0 RW

Figure 5-9: Accesses to the Avalon-MM Bridge Control and Status Register

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64- or 128-Bit Avalon-MM Bridge Register Descriptions

The following table describes the four subregions.

Table 5-11: Avalon-MM Control and Status Register Address Spaces

AddressRange Address Space Usage

0x0000-0x0FFF Registers typically intended for access by PCI Express link partner only. This includes

PCI Express interrupt enable controls, write access to the PCI Express Avalon-MM bridge mailbox registers, and read access to Avalon-MM-to-PCI Express mailbox registers.

0x1000-0x1FFF Avalon-MM-to-PCI Express address translation tables. Depending on the system

design these may be accessed by the PCI Express link partner, Avalon-MM processors, or both.

0x2000-0x2FFF Root Port request registers. An embedded processor, such as the Nios II processor,

programs these registers to send the data for Configuration TLPs, I/O TLPs, single dword Memory Read and Write requests, and receive interrupts from an Endpoint.

0x3000-0x3FFF Registers typically intended for access by Avalon-MM processors only. Provides host

access to selected Configuration Space and status registers.

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Note: The data returned for a read issued to any undefined address in this range is unpredictable. The following table lists the complete address map for the PCI Express Avalon-MM bridge registers.

Note:

In the following table the text in green are links to the detailed register description

Table 5-12: PCI Express Avalon-MM Bridge Register Map

Address Range Register

0x0040 Avalon-MM to PCI Express Interrupt Status Register

0x0050 Avalon-MM to PCI Express Interrupt Status Enable Register

0x0800–0x081F PCI Express-to-Avalon-MM Mailbox Registers

0x0900–x091F Avalon-MM to PCI Express Mailbox Registers

0x1000–0x1FFF Avalon-MM to PCI Express Address Translation Table

0x2000–0x2FFF Root Port TLP Data Registers

0x3060 Avalon-MM to PCI Express Interrupt Status Registers for Root Ports

0x3060 PCI Express to Avalon-MM Interrupt Status Register for Endpoints

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Address Range Register

0x3070 INT-X Interrupt Enable Register for Root Ports

0x3070 INT-X Interrupt Enable Register for Endpoints

0x3A00-0x3A1F Avalon-MM to PCI Express Mailbox Registers

0x3B00-0x3B1F PCI Express to Avalon-MM Mailbox Registers

Avalon-MM to PCI Express Interrupt Registers

5-15

0x3C00-0x3C6C

Host (Avalon-MM master) access to selected Configuration Space and status registers.

Avalon-MM to PCI Express Interrupt Registers

Avalon-MM to PCI Express Interrupt Status Registers

These registers contain the status of various signals in the PCI Express Avalon-MM bridge logic and allow PCI Express interrupts to be asserted when enabled. Only Root Complexes should access these registers; however, hardware does not prevent other Avalon-MM masters from accessing them.

Table 5-13: Avalon-MM to PCI Express Interrupt Status Register, 0x0040

Bit Name Access Description

[31:24] Reserved N/A N/A

[23]

[22]

[21]

A2P_MAILBOX_INT7

A2P_MAILBOX_INT6

A2P_MAILBOX_INT5

RW1C 1 when the A2P_MAILBOX7 is written to

RW1C 1 when the A2P_MAILBOX6 is written to

RW1C 1 when the A2P_MAILBOX5 is written to

Registers

[20]

[19]

[18]

[17]

[16]

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A2P_MAILBOX_INT4

A2P_MAILBOX_INT3

A2P_MAILBOX_INT2

A2P_MAILBOX_INT1

A2P_MAILBOX_INT0

RW1C 1 when the A2P_MAILBOX4 is written to

RW1C 1 when the A2P_MAILBOX3 is written to

RW1C 1 when the A2P_MAILBOX2 is written to

RW1C 1 when the A2P_MAILBOX1 is written to

RW1C 1 when the A2P_MAILBOX0 is written to

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5-16

Avalon-MM to PCI Express Interrupt Enable Registers

Bit Name Access Description

[15:0] AVL_IRQ_ASSERTED[15:0] RO Current value of the Avalon-MM interrupt

(IRQ) input ports to the Avalon-MM RX master port:

• 0—Avalon-MM IRQ is not being signaled.

• 1—Avalon-MM IRQ is being signaled.

A Qsys-generated IP Compiler for PCI Express has as many as 16 distinct IRQ input ports. Each AVL_IRQ_ASSERTED[] bit reflects the value on the corresponding IRQ input port.

Avalon-MM to PCI Express Interrupt Enable Registers

A PCI Express interrupt can be asserted for any of the conditions registered in the Avalon-MM to PCI

Express Interrupt Status register by setting the corresponding bits in the Avalon-MM-to-PCI Express Interrupt Enable register. Either MSI or legacy interrupts can be generated as explained in the section

Enabling MSI or Legacy Interrupts

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Table 5-14: Avalon-MM to PCI Express Interrupt Enable Register, 0x0050

Bits Name Access Description

[31:24] Reserved N/A N/A

[23:16]

A2P_MB_IRQ

RW Enables generation of PCI Express

interrupts when a specified mailbox is written to by an external Avalon-MM master.

[4:0]

AVL_IRQ[15:0]

RW Enables generation of PCI Express

interrupts when a specified Avalon-MM interrupt signal is asserted. Your Qsys system may have as many as 16 individual input interrupt signals.

Table 5-15: Avalon-MM Interrupt Vector Register - 0x0060

Bits Name Access Description

[31:5] Reserved N/A N/A

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Bits Name Access Description

PCI Express Mailbox Registers

5-17

[15:0]

AVL_IRQ_Vector

RO Stores the interrupt vector of the system

interconnect fabric. The host software should read this register after being interrupted and determine the servicing priority.

PCI Express Mailbox Registers

The PCI Express Root Complex typically requires write access to a set of PCI Express-to-Avalon-MM mailbox registers and read-only access to a set of Avalon-MM-to-PCI Express mailbox registers. Eight mailbox registers are available.

The PCI Express-to-Avalon-MM Mailbox registers are writable at the addresses shown in the following table. Writing to one of these registers causes the corresponding bit in the Avalon-MM Interrupt

Status register to be set to a one.

Table 5-16: PCI Express-to-Avalon-MM Mailbox Registers, 0x0800–0x081F

Address Name Access Description

0x0800

0x0804

P2A_MAILBOX0

P2A_MAILBOX1

RW PCI Express-to-Avalon-MM Mailbox 0

RW PCI Express-to-Avalon-MM Mailbox 1

0x0808

0x080C

0x0810

0x0814

0x0818

0x081C

P2A_MAILBOX2

P2A_MAILBOX3

P2A_MAILBOX4

P2A_MAILBOX5

P2A_MAILBOX6

P2A_MAILBOX7

RW PCI Express-to-Avalon-MM Mailbox 2

RW PCI Express-to-Avalon-MM Mailbox 3

RW PCI Express-to-Avalon-MM Mailbox 4

RW PCI Express-to-Avalon-MM Mailbox 5

RW PCI Express-to-Avalon-MM Mailbox 6

RW PCI Express-to-Avalon-MM Mailbox 7

The Avalon-MM-to-PCI Express Mailbox registers are read at the addresses shown in the following table. The PCI Express Root Complex should use these addresses to read the mailbox information after being signaled by the corresponding bits in the Avalon MM to PCI Express Interrupt Status register.

Table 5-17: Avalon-MM-to-PCI Express Mailbox Registers, 0x0900–0x091F

Address Name Access Description

0x0900 A2P_MAILBOX0 RO Avalon-MM-to-PCI Express Mailbox 0

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Avalon-MM-to-PCI Express Address Translation Table

Address Name Access Description

0x0904 A2P_MAILBOX1 RO Avalon-MM-to-PCI Express Mailbox 1

0x0908 A2P_MAILBOX2 RO Avalon-MM-to-PCI Express Mailbox 2

0x090C A2P_MAILBOX3 RO Avalon-MM-to-PCI Express Mailbox 3

0x0910 A2P_MAILBOX4 RO Avalon-MM-to-PCI Express Mailbox 4

0x0914 A2P_MAILBOX5 RO Avalon-MM-to-PCI Express Mailbox 5

0x0918 A2P_MAILBOX6 RO Avalon-MM-to-PCI Express Mailbox 6

0x091C A2P_MAILBOX7 RO Avalon-MM-to-PCI Express Mailbox 7

Avalon-MM-to-PCI Express Address Translation Table

The Avalon-MM-to-PCI Express address translation table is writable using the CRA slave port. Each entry in the PCI Express address translation table is 8 bytes wide, regardless of the value in the current PCI Express address width parameter. Therefore, register addresses are always the same width, regardless of PCI Express address width.

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These table entries are repeated for each address specified in the Number of address pages parameter. If Number of address pages is set to the maximum of 512, 0x1FF8 contains A2P_ADDR_MAP_LO511 and

0x1FFC contains A2P_ADDR_MAP_HI511.

Table 5-18: Avalon-MM-to-PCI Express Address Translation Table, 0x1000–0x1FFF

Address Bits Name Access Description

[1:0]

A2P_ADDR_ SPACE0

RW Address space indication for entry 0. Refer to Table 9–

31 for the definition of these bits.

0x1000

[31:2]

0x1004 [31:0]

A2P_ADDR_ MAP_LO0

A2P_ADDR_ MAP_HI0

RW Lower bits of Avalon-MM-to-PCI Express address map

entry 0.

RW Upper bits of Avalon-MM-to-PCI Express address map

entry 0.

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Address Bits Name Access Description

PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints

5-19

[1:0]

0x1008

[31:2]

0x100C [31:0]

A2P_ADDR_ SPACE1

A2P_ADDR_ MAP_LO1

A2P_ADDR_ MAP_HI1

RW Address space indication for entry 1. Refer to the

following encodings are defined:

• 2’b00:. Memory Space, 32-bit PCI Express address. 32-bit header is generated. Address bits 63:32 of the translation table entries are ignored.

• 2’b01: Memory space, 64-bit PCI Express address. 64-bit address header is generated.

• 2’b10: Reserved

• 2’b11: Reserved

RW Lower bits of Avalon-MM-to-PCI Express address map

entry 1. This entry is only implemented if the number of

address translation table entries is greater than 1.

RW Upper bits of Avalon-MM-to-PCI Express address map

entry 1. This entry is only implemented if the number of

address translation table entries is greater than 1.

PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints

The registers in this section contain status of various signals in the PCI Express Avalon-MM bridge logic and allow Avalon interrupts to be asserted when enabled. A processor local to the interconnect fabric that processes the Avalon-MM interrupts can access these registers.

Note:

The following table describes the Interrupt Status register when you configure the core as an Endpoint. It records the status of all conditions that can cause an Avalon-MM interrupt to be asserted.

Table 5-19: PCI Express to Avalon-MM Interrupt Status Register for Endpoints, 0x3060

Bits Name Access Description

These registers must not be accessed by the PCI Express Avalon-MM bridge master ports; however, there is nothing in the hardware that prevents a PCI Express Avalon-MM bridge master port from accessing these registers.

ERR_PCI_WRITE_FAILURE

RW1C When set to 1, indicates a PCI Express

write failure. This bit can also be cleared by writing a 1 to the same bit in the

Avalon MM to PCI Express Interrupt Status register.

Registers

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PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints

Bits Name Access Description

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ERR_PCI_READ_FAILURE

RW1C When set to 1, indicates the failure of a

PCI Express read. This bit can also be cleared by writing a 1 to the same bit in the Avalon MM to PCI Express

Interrupt Status register.

[15:2] Reserved — —

[16]

[17]

[18]

[19]

[20]

[21]

[22]

P2A_MAILBOX_INT0

P2A_MAILBOX_INT1

P2A_MAILBOX_INT2

P2A_MAILBOX_INT3

P2A_MAILBOX_INT4

P2A_MAILBOX_INT5

P2A_MAILBOX_INT6

RW1C 1 when the P2A_MAILBOX0 is written

RW1C 1 when the P2A_MAILBOX1 is written

RW1C 1 when the P2A_MAILBOX2 is written

RW1C 1 when the P2A_MAILBOX3 is written

RW1C 1 when the P2A_MAILBOX4 is written

RW1C 1 when the P2A_MAILBOX5 is written

RW1C 1 when the P2A_MAILBOX6 is written

[23]

P2A_MAILBOX_INT7

RW1C 1 when the P2A_MAILBOX7 is written

[31:24] Reserved — —

An Avalon-MM interrupt can be asserted for any of the conditions noted in the Avalon-MM Interrupt

Status register by setting the corresponding bits in the PCI Express to Avalon-MM Interrupt Enable

that only one of the Avalon-MM or PCI Express interrupts can be enabled for any given bit. Typically, a single process in either the PCI Express or Avalon-MM domain handles the condition reported by the interrupt.

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Table 5-20: INT‑X Interrupt Enable Register for Endpoints, 0x3070

Bits Name Access Description

Avalon-MM Mailbox Registers

5-21

[31:0]

PCI Express to Avalon-MM Interrupt Enable

Avalon-MM Mailbox Registers

A processor local to the interconnect fabric typically requires write access to a set of Avalon-MM-to-PCI

Express Mailbox registers and read-only access to a set of PCI Express-to-Avalon-MM Mailbox

registers. Eight mailbox registers are available. The Avalon-MM-to-PCI Express Mailbox registers are writable at the addresses shown in the following

table. When the Avalon-MM processor writes to one of these registers the corresponding bit in the

Avalon MM to PCI Express Interrupt Status register is set to 1.

RW When set to 1, enables the interrupt for

the corresponding bit in the PCI

Express to Avalon MM Interrupt Status register to cause the Avalon

Interrupt signal (cra_Irq_o) to be asserted.

Only bits implemented in the PCI

Express to Avalon MM Interrupt Status register are implemented in the

Enable register. Reserved bits cannot be set to a 1.

Table 5-21: Avalon-MM to PCI Express Mailbox Registers, 0x3A00–0x3A1F

Address Name Access Description

0x3A00

0x3A04

0x3A08

0x3A0C

0x3A10

0x3A14

0x3A18

0x3A1C

A2P_MAILBOX0

A2P_MAILBOX1

A2P _MAILBOX2

A2P _MAILBOX3

A2P _MAILBOX4

A2P _MAILBOX5

A2P _MAILBOX6

A2P_MAILBOX7

RW Avalon-MM-to-PCI Express mailbox 0

RW Avalon-MM-to-PCI Express mailbox 1

RW Avalon-MM-to-PCI Express mailbox 2

RW Avalon-MM-to-PCI Express mailbox 3

RW Avalon-MM-to-PCI Express mailbox 4

RW Avalon-MM-to-PCI Express mailbox 5

RW Avalon-MM-to-PCI Express mailbox 6

RW Avalon-MM-to-PCI Express mailbox 7

Registers

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Control Register Access (CRA) Avalon-MM Slave Port

The PCI Express-to-Avalon-MM Mailbox registers are read-only at the addresses shown in the following table. The Avalon-MM processor reads these registers when the corresponding bit in the PCI

Express to Avalon-MM Interrupt Status register is set to 1.

Table 5-22: PCI Express to Avalon-MM Mailbox Registers, 0x3B00–0x3B1F

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Address Name Access

0x3B00

0x3B04

0x3B08

0x3B0C

0x3B10

0x3B14

0x3B18

0x3B1C

P2A_MAILBOX0

P2A_MAILBOX1

P2A_MAILBOX2

P2A_MAILBOX3

P2A_MAILBOX4

P2A_MAILBOX5

P2A_MAILBOX6

P2A_MAILBOX7

Control Register Access (CRA) Avalon-MM Slave Port

Description

Mode

RO PCI Express-to-Avalon-MM mailbox 0

RO PCI Express-to-Avalon-MM mailbox 1

RO PCI Express-to-Avalon-MM mailbox 2

RO PCI Express-to-Avalon-MM mailbox 3

RO PCI Express-to-Avalon-MM mailbox 4

RO PCI Express-to-Avalon-MM mailbox 5

RO PCI Express-to-Avalon-MM mailbox 6

RO PCI Express-to-Avalon-MM mailbox 7

Table 5-23: Configuration Space Register Descriptions

For registers that are less than 32 bits, the upper bits are unused.

Byte Offset

14'h3C00 cfg_dev_ctrl[15:0]

O cfg_devctrl[15:0] is device control for the PCI

Express capability structure.

14'h3C04 cfg_dev_ctrl2[15:0]

O cfg_dev2ctrl[15:0] is device control 2 for the

PCI Express capability structure.

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Control Register Access (CRA) Avalon-MM Slave Port

5-23

Byte Offset

14'h3C08 cfg_link_ctrl[15:0]

14'h3C0C cfg_link_ctrl2[15:0]

O cfg_link_ctrl[15:0]is the primary Link Control

of the PCI Express capability structure. For Gen2 or Gen3 operation, you must write a 1’b1

to Retrain Link bit (Bit[5] of the cfg_link_ctrl) of the Root Port to initiate retraining to a higher data rate after the initial link training to Gen1 L0 state. Retraining directs the LTSSM to the Recovery state. Retraining to a higher data rate is not automatic for the Stratix V Hard IP for PCI Express IP Core even if both devices on the link are capable of a higher data rate.

O cfg_link_ctrl2[31:16] is the secondary Link

Control register of the PCI Express capability structure for Gen2 operation.

When tl_cfg_addr=2, tl_cfg_ctl returns the primary and secondary Link Control registers,

{cfg_link_ctrl[15:0], cfg_link_ ctrl2[15:0]}, the primary Link Status register

contents is available on tl_cfg_sts[46:31].

14'h3C10 cfg_prm_cmd[15:0]

14'h3C14 cfg_root_ctrl[7:0]

14'h3C18 cfg_sec_ctrl[15:0]

14'h3C1C cfg_secbus[7:0]

14'h3C20 cfg_subbus[7:0]

14'h3C24 cfg_msi_addr_low[31:0]

For Gen1 variants, the link bandwidth notification bit is always set to 0. For Gen2 variants, this bit is set to 1.

O Base/Primary Command register for the PCI

Configuration Space.

O Root control and status register of the PCI-Express

capability. This register is only available in Root Port mode.

O Secondary bus Control and Status register of the

PCI-Express capability. This register is only available in Root Port mode.

O Secondary bus number. Available in Root Port

mode.

O Subordinate bus number. Available in Root Port

mode.

O cfg_msi_add[31:0] is the MSI message address.

Registers

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Control Register Access (CRA) Avalon-MM Slave Port

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Byte Offset

14'h3C28 cfg_msi_addr_hi[63:32]

14'h3C2C cfg_io_bas[19:0]

14'h3C30 cfg_io_lim[19:0]

14'h3C34 cfg_np_bas[11:0]

14'h3C38 cfg_np_lim[11:0]

14'h3C3C cfg_pr_bas_low[31:0]

O cfg_msi_add[63:32] is the MSI upper message

address.

O The IO base register of the Type1 Configuration

Space. This register is only available in Root Port mode.

O The IO limit register of the Type1 Configuration

Space. This register is only available in Root Port mode.

O The non-prefetchable memory base register of the

Type1 Configuration Space. This register is only available in Root Port mode.

O The non-prefetchable memory limit register of the

Type1 Configuration Space. This register is only available in Root Port mode.

O The lower 32 bits of the prefetchable base register of

the Type1 Configuration Space. This register is only available in Root Port mode.

14'h3C40 cfg_pr_bas_hi[43:32]

14'h3C44 cfg_pr_lim_low[31:0]

14'h3C48 cfg_pr_lim_hi[43:32]

14'h3C4C cfg_pmcsr[31:0]

14'h3C50 cfg_msixcsr[15:0]

14'h3C54 cfg_msicsr[15:0]

O The upper 12 bits of the prefetchable base registers

of the Type1 Configuration Space. This register is only available in Root Port mode.

O The lower 32 bits of the prefetchable limit registers

of the Type1 Configuration Space. Available in Root Port mode.

O The upper 12 bits of the prefetchable limit registers

of the Type1 Configuration Space. Available in Root Port mode.

O cfg_pmcsr[31:16] is Power Management Control

and cfg_pmcsr[15:0]is the Power Management Status register.

O MSI-X message control register.

O MSI message control.

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Control Register Access (CRA) Avalon-MM Slave Port

5-25

Byte Offset

14'h3C58 cfg_tcvcmap[23:0]

14'h3C5C cfg_msi_data[15:0]

14'h3C60 cfg_busdev[12:0]

O Configuration traffic class (TC)/virtual channel

(VC) mapping. The Application Layer uses this signal to generate a TLP mapped to the appropriate channel based on the traffic class of the packet.

The following encodings are defined:

• cfg_tcvcmap[2:0]: Mapping for TC0 (always 0) .

• cfg_tcvcmap[5:3]: Mapping for TC1.

• cfg_tcvcmap[8:6]: Mapping for TC2.

• cfg_tcvcmap[11:9]: Mapping for TC3.

• cfg_tcvcmap[14:12]: Mapping for TC4.

• cfg_tcvcmap[17:15]: Mapping for TC5.

• cfg_tcvcmap[20:18]: Mapping for TC6.

• cfg_tcvcmap[23:21]: Mapping for TC7.

O cfg_msi_data[15:0] is message data for MSI.

O Bus/Device Number captured by or programmed in

the Hard IP.

14'h3C64 ltssm_reg[4:0]

Specifies the current LTSSM state. The LTSSM state machine encoding defines the following states:

• 00000: Detect.Quiet

• 00001: Detect.Active

• 00010: Polling.Active

• 00011: Polling.Compliance

• 00100: Polling.Configuration

• 00101: Polling.Speed

• 00110: config.Linkwidthstart

• 00111: Config.Linkaccept

• 01000: Config.Lanenumaccept

• 01001: Config.Lanenumwait

• 01010: Config.Complete

• 01011: Config.Idle

• 01100: Recovery.Rcvlock

• 01101: Recovery.Rcvconfig

• 01110: Recovery.Idle

• 01111: L0

• 10000: Disable

• 10001: Loopback.Entry

• 10010: Loopback.Active

Registers

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Programming Model for Avalon‑MM Root Port

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Byte Offset

14'h3C68 current_speed_reg[1:0]

14'h3C6C lane_act_reg[3:0]

• 10011: Loopback.Exit

• 10100: Hot.Reset

• 10101: LOs

• 11001: L2.transmit.Wake

• 11010: Speed.Recovery

• 11011: Recovery.Equalization, Phase 0

• 11100: Recovery.Equalization, Phase 1

• 11101: Recovery.Equalization, Phase 2

• 11110: recovery.Equalization, Phase 3

O Indicates the current speed of the PCIe link. The

following encodings are defined:

• 2b’00: Undefined

• 2b’01: Gen1

• 2b’10: Gen2

• 2b’11: Gen3

O Lane Active Mode: This signal indicates the number

of lanes that configured during link training. The following encodings are defined:

• 4’b0001: 1 lane

• 4’b0010: 2 lanes

• 4’b0100: 4 lanes

• 4’b1000: 8 lanes

Related Information

• PCI Express Base Specification 2.1 or 3.0

• PCI Local Bus Specification, Rev. 3.0

Programming Model for Avalon‑MM Root Port

The Application Layer writes the Root Port TLP TX Data registers with TLP formatted data for Configu‐ ration Read and Write Requests, Message TLPs, I/O Read and Write Requests, or single dword Memory Read and Write Requests. Software should check the Root Port Link Status register (offset 0x92) to ensure the Data Link Layer Link Active bit is set to 1'b1 before issuing a Configuration request to downstream ports.

The Application Layer data must be in the appropriate TLP format with the data payload aligned to the TLP address. Aligning the payload data to the TLP address may result in the payload data being either aligned or unaligned to the qword. The following figure illustrates three dword TLPs with data that is aligned and unaligned to the qword.

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Header 1 [63:32]

Cycle 1

Data Unaligned to

QWord Boundary

Data Aligned to

QWord Boundary

Cycle 2

Header 0 [31:0]

Data [63:32]

Header 2 [31:0]

Header 1 [63:32]

Cycle 1

Header 0 [31:0]

Cycle 2

Header 2 [31:0]

Cycle 3

Data [31:0]

Unused, but must

be written

Unused, but must

be written

Header 1 [63:32]

Cycle 1

Data Unaligned to

QWord Boundary

Data Aligned to

QWord Boundary

Cycle 2

Header 0 [31:0]

Header 3[63:32]

Header 2 [31:0]

Data [63:32]

Header 1 [63:32]

Header 0 [31:0]

Header 2 [31:0]

Cycle 1

Cycle 2

Cycle 3

Data [31:0]

Unused, but must

be written

Unused, but must

be written

Header 3[63:32]

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Figure 5-10: Layout of Data with 3 Dword Headers

Programming Model for Avalon‑MM Root Port

5-27

The following figure illustrates four dword TLPs with data that are aligned and unaligned to the qword.

Figure 5-11: Layout of Data with 4 Dword Headers

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Sending a Write TLP

The TX TLP programming model scales with the data width. The Application Layer performs the same writes for both the 64- and 128-bit interfaces. The Application Layer can only have one outstanding nonposted request at a time. The Application Layer must use tags 16–31 to identify non-posted requests.

Note: For Root Ports, the Avalon-MM bridge does not filter Type 0 Configuration Requests by device

number. Application Layer software should filter out all requests to Avalon-MM Root Port registers that are not for device 0. Application Layer software should return an Unsupported Request Completion Status.

Sending a Write TLP

The Application Layer performs the following sequence of Avalon-MM accesses to the CRA slave port to send a Memory Write Request:

1. Write the first 32 bits of the TX TLP to RP_TX_REG0.

2. Write the next 32 bits of the TX TLP to RP_TX_REG1.

3. Write the RP_TX_CNTRL.SOP to 1’b1 to push the first two dwords of the TLP into the Root Port TX

FIFO.

4. Repeat Steps 1 and 2. The second write to RP_TX_REG1 is required, even for three dword TLPs with

aligned data.

5. If the packet is complete, write RP_TX_CNTRL to 2’b10 to indicate the end of the packet. If the packet is

not complete, write 2’b00 to RP_TX_CNTRL.

6. Repeat this sequence to program a complete TLP.

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When the programming of the TX TLP is complete, the Avalon-MM bridge schedules the TLP with higher priority than TX TLPs coming from the TX slave port.

Sending a Read TLP or Receiving a Non-Posted Completion TLP

The TLPs associated with the Non-Posted TX requests are stored in the RP_RX_CPL FIFO buffer and subsequently loaded into RP_RXCPL registers. The Application Layer performs the following sequence to retrieve the TLP.

1. Polls the RP_RXCPL_STA TUS.SOP to determine when it is set to 1’b1.

2. Then RP_RXCPL_STATUS.SOP = 1’b’1, reads RP_RXCPL_REG0 and RP_RXCPL_REG1 to retrieve dword 0

and dword 1 of the TLP.

3. Read the RP_RXCPL_STATUS.EOP.

• If RP_RXCPL_STATUS.EOP = 1’b0, read RP_RXCPL_REG0 and RP_RXCPL_REG1 to retrieve dword 2 and dword 3 of the TLP, then repeat step 3.

• If RP_RXCPL_STATUS.EOP = 1’b1, read RP_RXCPL_REG0 and RP_RXCPL_REG1 to retrieve final dwords of TLP.

PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports

The Root Port supports MSI, MSI-X and legacy (INTx) interrupts. MSI and MSI-X interrupts are memory writes from the Endpoint to the Root Port. MSI and MSI-X requests are forwarded to the interconnect without asserting CraIrq_o.

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PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports

Table 5-24: Avalon‑MM Interrupt Status Registers for Root Ports, 0x3060

5-29

Bits Name Access

Mode

[31:5] Reserved — —

[4]

RPRX_CPL_RECEIVED

RW1C Set to 1’b1 when the Root Port has

received a Completion TLP for an outstanding Non-Posted request from the TLP Direct channel.

[3]

INTD_RECEIVED

RW1C The Root Port has received INTD from

the Endpoint.

[2]

INTC_RECEIVED

RW1C The Root Port has received INTC from

the Endpoint.

[1]

INTB_RECEIVED

RW1C The Root Port has received INTB from

the Endpoint.

[0]

INTA_RECEIVED

RW1C The Root Port has received INTA from

the Endpoint.

Description

Table 5-25: INT‑X Interrupt Enable Register for Root Ports, 0x3070

Bit Name Access

Mode

[31:5] Reserved — —

[4]

[3]

RPRX_CPL_RECEIVED

INTD_RECEIVED_ENA

RW When set to 1’b1, enables the assertion

Description

of CraIrq_o when the Root Port Interrupt Status register RPRX_CPL_

RECEIVED bit indicates it has received a

Completion for a Non-Posted request from the TLP Direct channel.

of CraIrq_o when the Root Port Interrupt Status register INTD_

RECEIVED bit indicates it has received

INTD.

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5-30

Root Port TLP Data Registers

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2014.12.15

Bit Name Access

[2]

[1]

[0]

INTC_RECEIVED_ENA

INTB_RECEIVED_ENA

INTA_RECEIVED_ENA

Root Port TLP Data Registers

Description

Mode

RW When set to 1’b1, enables the assertion

of CraIrq_o when the Root Port Interrupt Status register INTC_

RECEIVED bit indicates it has received

INTC.

RW When set to 1’b1, enables the assertion

of CraIrq_o when the Root Port Interrupt Status register INTB_

RECEIVED bit indicates it has received

INTB.

RW When set to 1’b1, enables the assertion

of CraIrq_o when the Root Port Interrupt Status register INTA_

RECEIVED bit indicates it has received

INTA.

The TLP data registers provide a mechanism for the Application Layer to specify data that the Root Port uses to construct Configuration TLPs, I/O TLPs, and single dword Memory Reads and Write requests. The Root Port then drives the TLPs on the TLP Direct Channel to access the Configuration Space, I/O space, or Endpoint memory.

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RX_TX_CNTL

RP_RXCPL_ REG0

RP_RXCPL_ REG

RP_RXCPL_ STATUS

Control

Access

Slave

Avalon-MM

Master

IRQ

RP TX

CTRL

RP_TX_FIFO

RP CPL

CTRL

RP_RXCPL_FIFO

TLP Direct Channel

to Hard IP for PCIe

Root-Port TLP Data Registers Avalon-MM Bridge -

RX_TX_Reg1

RP_TX_Reg0

UG-01097_avmm

2014.12.15

Figure 5-12: Root Port TLP Data Registers

Root Port TLP Data Registers

5-31

Note: The high performance TLPs implemented by Avalon-MM ports in the Avalon-MM Bridge are also

available for Root Ports. For more information about these TLPs, refer to Avalon-MM Bridge TLPs.

Table 5-26: Root Port TLP Data Registers, 0x2000–0x2FFF

Address Bits Name Access Description

0x2000 [31:0]

0x2004 [31:0]

0x2008

Registers

Root-Port Request Registers Address Range: 0x2800-0x2018

RP_TX_REG0

RP_TX_REG1

[31:2] Reserved — —

[1]

[0]

RP_TX_CNTRL.EOP

RP_TX_CNTRL.SOP

W Lower 32 bits of the TX TLP.

W Upper 32 bits of the TX TLP.

W Write 1’b1 to specify the of end a packet.

Writing this bit frees the corresponding entry in the FIFO.

W Write 1’b1 to specify the start of a packet.

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Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Datasheet

Stratix V Avalon-MM Interface for PCIe Datasheet

Features

Release Information

Device Family Support

Configurations

Example Designs

Debug Features

IP Core Verification

Compatibility Testing Environment

Performance and Resource Utilization

Recommended Speed Grades

Steps in Creating a Design for PCI Express

Running Qsys

Generating the Example Design

Understanding Simulation Log File Generation

Running A Gate-Level Simulation

Simulating the Single DWord Design

Generating Quartus II Synthesis Files

Creating a Quartus II Project

Compiling the Design

Programming a Device

Understanding Channel Placement Guidelines

Parameter Settings

Stratix V and Arria V GZ Avalon-MM System Settings

Base Address Register (BAR) Settings

Device Identification Registers

PCI Express and PCI Capabilities Parameters

Device Capabilities

Error Reporting

Link Capabilities

MSI and MSI-X Capabilities

Power Management

Avalon Memory‑Mapped System Settings

32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals

RX Avalon-MM Master Signals

64- or 128-Bit Bursting TX Avalon-MM Slave Signals

Clock Signals

Reset

Interrupts for Endpoints when Multiple MSI/MSI‑X Support Is Enabled

Physical Layer Interface Signals

Transceiver Reconfiguration

Hard IP Status Extension

Configuration Space Register Access

Configuration Space Register Access Timing

Serial Data Signals

Physical Layout of Hard IP in Stratix V GX/GT/GS Devices

Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices

PIPE Interface Signals

Test Signals

Registers

Correspondence between Configuration Space Registers and the PCIe Specification

Type 0 Configuration Space Registers

Type 1 Configuration Space Registers

PCI Express Capability Structures

Altera-Defined VSEC Registers

CvP Registers

64- or 128-Bit Avalon-MM Bridge Register Descriptions

Avalon-MM to PCI Express Interrupt Registers

Avalon-MM to PCI Express Interrupt Status Registers

Avalon-MM to PCI Express Interrupt Enable Registers

PCI Express Mailbox Registers

Avalon-MM-to-PCI Express Address Translation Table

PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints

Avalon-MM Mailbox Registers

Control Register Access (CRA) Avalon-MM Slave Port

Programming Model for Avalon‑MM Root Port

Sending a Write TLP

Sending a Read TLP or Receiving a Non-Posted Completion TLP

PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports

Root Port TLP Data Registers