Altera Stratix V Advanced Systems Development Board User Manual
Stratix V Advanced Systems Development Board
Reference Manual
101 Innovation Drive
San Jose, CA 95134
www.altera.com
MNL-01071-1.1
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January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
Contents
Chapter 1. Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Development Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Dual FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
FPGA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
FPGA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Chapter 2. Board Components
Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Featured Device: Stratix V GX FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
MAX V CPLD System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
FPGA Programming over On-Board USB-Blaster II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
FPGA Programming from CFI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
FPGA Programming from Serial Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19
Board Settings DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
JTAG Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
PCI Express Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
MAX V Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
Program Load Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
Program Select Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
CPU Reset Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
On-Board Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
Off-Board Clock Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
User-Defined Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
User-Defined DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
General User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
FMC User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29
HSMC User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29
Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30
PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30
FMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33
HSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–42
DDR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–42
QDRII+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–54
MoSys MSR576 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–58
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
iv ContentsContents
Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–63
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–65
Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–65
Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–67
Temperature Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–68
Chapter 3. Board Components Reference
Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Additional Information
Board Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2
Stratix V Advanced Systems Development Board January 2014 Altera Corporation
Reference Manual
This document describes the hardware features of the Stratix® V Advanced Systems
development board, including the detailed pin-out and component reference
information required to create custom FPGA designs that interface with all
components of the board.
General Description
The development board comes with two Stratix V GX FPGA devices to provide a
hardware platform for developing and prototyping high-performance and highbandwidth application designs. The board includes a wide range of peripherals and
memory interfaces to facilitate the development of Stratix V GX FPGA designs.
One FPGA Mezzanine Card (FMC) and one High-Speed Mezzanine Card (HSMC)
connector is available to add additional functionality via a variety of FMC and HSMC
cards available from both Altera and various partners.
Design advancements and innovations, such as the PCI Express hard IP
implementation, partial reconfiguration, and programmable power technology
ensure that designs implemented in the Stratix V GX FPGAs operate faster, with
lower power than in previous FPGA families.
1. Overview
f For more information on the following topics, refer to the respective documents or
page:
■ Stratix V device family, refer to the Stratix V Device Handbook.
■ PCI Express hard IP implementation, refer to the Stratix V Hard IP for PCI Express
User Guide.
■ List of the latest daughter cards available, refer to the Development Board
Daughtercards page of the Altera website.
■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
1–2 Chapter 1: Overview
Development Board Component Blocks
Development Board Component Blocks
The board features the following major component blocks:
■ Two Altera Stratix V FPGA (5SGXEA7N2F45C2N) in the 1932-pin FineLine BGA
package
■ MAX
■ FPGA Configuration Circuitry
■ On-Board Clocking Circuitry
®
V CPLD (5M2210ZF256C4N) System Controller in the 256-pin FineLine
BGA package and Flash Fast Passive Parallel (FPP) configuration
■ 1-Gbit (Gb) serial flash
■ MAX V CPLD (5M2210ZF256C4N) and FPP configuration.
■ On-Board USB-Blaster
TM
II for use with the Quartus® II Programmer, Nios®II
Software Build Tools, and System Console.
■ EPCQ for x4 Active Serial (AS) configuration.
■ 50-MHz, 100-MHz, and 125-MHz fully programmable oscillators
■ SMA connector for clock input (LVDS)
■ General user input/output (I/O)
■ One eight-position dual in-line package (DIP) switch for each FPGA
■ 16 user LEDs for each FPGA
■ Three user push buttons for each FPGA
■ Communication interfaces
■ One PCI Express x16 edge connector to PLX PE8747 Gen3 Switch
■ One PCI Express Gen3 x8 branch to each FPGA
■ One FMC connector (FPGA1)
■ One HSMC port (FPGA2)
■ One USB 2.0 on-board USB-Blaster II cable
■ Power
■ 12-16 V (laptop) DC input
■ PCI Express edge connector
■ 2x4 PCI Express ATX connector
■ System Monitoring
■ Power—voltage, current, wattage
■ Temperature—FPGA die, local board
■ Mechanical
■ PCI Express full-length form factor
■ PCI Express chassis or bench-top operation
Stratix V Advanced Systems Development Board January 2014 Altera Corporation
Reference Manual
Chapter 1: Overview 1–3
Development Board Component Blocks
Dual FPGA
The development board includes two Stratix V GX FPGA devices that connect to
other components on the board to provide a better transceiver and bandwidth design
solution.
FPGA1
The first Stratix V GX FPGA device (FPGA1) connects to the following components:
■ Communication interfaces
■ One Gen3 PCI Express x8 edge connector to PLX PEX8747 switch
■ One FPGA Mezzanine Card (FMC) port
■ Memory interfaces
■ DDR3 SDRAM
■ Two 1024-MByte (MB) interfaces with 64-bit data bus
■ Two 512-MB interfaces with 32-bit data bus
■ Four 4.5-MB QDRII+ SRAM with 18-bit data bus
■ One 72-MB MoSys Bandwidth Engine IC SRAM with 16-bit data bus
(16x10.3125 G XCVR)
■ One 32-MB serial flash
■ General user I/O
■ LEDs
■ 16 user LEDs
■ Five PCI Express LEDs
■ Two FMC interface LEDs transmit/receive (TX/RX)
■ Push buttons and DIP switches
■ One CPU reset push button
■ Three general user push buttons
■ Eight general user DIP switches
FPGA2
The second Stratix V GX FPGA device (FPGA2) connects to the following
components:
■ Communication ports
■ One Gen3 PCI Express x8 edge connector to PLX PEX8747 switch
■ One universal HSMC port
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
1–4 Chapter 1: Overview
Development Board Component Blocks
■ Memory interfaces
■ DDR3 SDRAM
■ Two 1024-MB interfaces with 64-bit data bus
■ Two 512-MB interfaces with 32-bit data bus
■ Four 4.5-MB QDRII+ SRAM with 18-bit data bus
■ One 72-MB MoSys Bandwidth Engine IC SRAM with 16-bit data bus
(16x10.3125 G XCVR)
■ One 32-MB serial flash
■ General user I/O
■ LEDs
■ 16 user LEDs
■ Two HSMC interface LEDs transmit/receive (TX/RX)
■ One PCI Express LEDs
■ Push buttons and DIP switches
■ One CPU reset push button
■ Three general user push buttons
■ Eight general user DIP switches
Stratix V Advanced Systems Development Board January 2014 Altera Corporation
Reference Manual
Chapter 1: Overview 1–5
5SGXEA7N2F45C2N 5SGXEA7N2F45C2N
On-Board
USB-Blaster II
and USB Interface
JTAG Chain
XVCR x8
Micro-USB
2.0
x19 USB Interface
LVDS/Single-Ended
FMC
MoSys
72-MB
1-T SRAM
XVCR x8
XVCR x16
MoSys
72-MB
1-T SRAM
XVCR x16
CLKOUT x3
x80
CLKIN x3
XVCR x8
CLKOUT x3
x80
CLKIN x3
512-MB
DDR3 (x32)
x32
JTAG Chain
512-MB
DDR3 (x32)
x32
1024-MB
DDR3 (x64)
x64
1024-MB
DDR3 (x64)
x64
4.5-MB
QDRII+
x18
4.5-MB
QDRII+
x18
x16
4.5-MB
QDRII+
x18
4.5-MB
QDRII+
x18
EPCQ
x4
512-MB
DDR3 (x32)
x32
1024-MB
DDR3 (x64)
x64
4.5-MB
QDRII+
x18
4.5-MB
QDRII+
x18
EPCQ
x4
x14
Push buttons
LEDs
x8
x3
x16
DIP Switches
512-MB
DDR3 (x32)
x32
1024-MB
DDR3 (x64)
x64
4.5-MB
QDRII+
x18
4.5-MB
QDRII+
x18
Push buttons
LEDs
x8
x3
x16
DIP Switches
Programmable
Oscillators
50 M, 125 M
x13
Programmable
Oscillators
50 M, 125 M
x8 Edge
x16 Edge
XVCR x8
x8 Edge
XVCR x8
CPLD
1-Gb
Flash
PLX PEX 8747
PCI Express Switch
x1 (LVDS)
x1 (LVDS)
XVCR x8
SMA Clock
Input
x8 Config
x8 Config
XVCR x8
LVDS x2, CMOS x12
CPLD
Development Board Block Diagram
Development Board Block Diagram
Figure 1–1 shows the block diagram of the Stratix V Advanced Systems development
board.
Figure 1–1. Stratix V Advanced Systems Development Board Block Diagram
Handling the Board
When handling the board, it is important to observe the following static discharge
precaution:
c Without proper anti-static handling, the board can be damaged. Therefore, use
anti-static handling precautions when touching the board.
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
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1–6 Chapter 1: Overview
Handling the Board
Stratix V Advanced Systems Development Board January 2014 Altera Corporation
Reference Manual
2. Board Components
This chapter introduces all the important components on the Stratix V Advanced
Systems development board. Figure 2–1 illustrates major component locations and
Tab le 2– 1 provides a brief description of all features of the board.
1 A complete set of schematics, a physical layout database, and ODB++ files for the
development board reside in the Stratix V Advanced Systems development kit
board_design_files directory.
f For information about powering up the board and installing the demo software, refer
to the Stratix V Advanced Systems Development Kit User Guide.
This chapter consists of the following sections:
■ “Board Overview”
■ “Featured Device: Stratix V GX FPGA” on page 2–5
■ “MAX V CPLD System Controller” on page 2–7
■ “Configuration, Status, and Setup Elements” on page 2–12
■ “Clock Circuitry” on page 2–22
■ “General User Input/Output” on page 2–26
■ “Components and Interfaces” on page 2–30
■ “Memory” on page 2–42
■ “Power Supply” on page 2–65
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
2–2 Chapter 2: Board Components
HSMC Port (J1) MoSys (U14)
MoSys (U4)
Powe r
Switch
(SW2)
12V-15 V
DC Input
Jack (J7)
QDRII+ x18
(U5)
QDRII+ x18
(U40)
QDRII+ x18
(U5)
QDRII+ x18
(U22)
DDR3 Memory x16
(U17, U24, U33)
DDR3 Memory x16
(U32, U39, U43)
DDR3 Memory x16
(U36, U21, U27)
DDR3 Memory x16
(U19, U30, U34)
AT X
Header (J9)
JTAG Header
(J11)
SMA Clock Input
Connector (J4, J5)
CPU Reset
Push Button
(S11)
CPU Reset
Push Button
(S7)
PCI Express
Edge Connector
(J13)
Fan Power
Header (J2)
On-Board
USB-Blaster II
Connector (J6)
Program Load,
Program Select
Push Button (S1, S2)
MAX V Reset
Push Button (S3)
Stratix V GX
FPGA (U29)
Stratix V GX
FPGA (U35)
General User
Push Button
(S8, S9, S10)
General User
Push Button
(S4, S5, S6)
User DIP Switch (SW3)
User DIP Switch
(SW1)
FMC (J8)
Board Overview
Board Overview
This section provides an overview of the Stratix V Advanced Systems development
board, including an annotated board image and component descriptions. Figure 2–1
provides an overview of the development board features.
Figure 2–1. Overview of the Stratix V Advanced Systems Development Board Features
Tab le 2– 1 describes the components and lists their corresponding board references.
Table 2–1. Stratix V Advanced Systems Development Board Components (Part 1 of 4)
Board Reference Type Description
Featured Devices
U29, U35 FPGA 5SGXEA7N2F45C2N, 1932-pin BGA.
U73 CPLD 5M2210ZF256C4, 256-pin BGA.
Configuration, Status, and Setup Elements
J11 JTAG header
J6 On-Board USB-Blaster II Mini-USB 2.0 connector for programming and debugging the FPGA.
SW7 JTAG DIP switch
SW5
SW6
FPGA1 mode select DIP
switch
FPGA2 mode select DIP
switch
Provides access to the JTAG chain by using an external USB-Blaster
cable (disables the on-board USB-Blaster II).
Enables and disables devices in the JTAG chain. This switch is located
on the back of the board.
Sets the Stratix V (U29)
the board.
Sets the Stratix V (U35)
the board.
MSEL[2:0]
MSEL[2:0]
pins. FPGA1
pins. FPGA2
MSEL[4:3]
MSEL[4:3]
= 10 on
= 10 on
Controls the MAX V CPLD System Controller functions such as clock
SW4 Board settings DIP switch
select, clock enable, and FPP configuration control. This switch is
located at the bottom of the board.
Stratix V Advanced Systems Development Board January 2014 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–3
Board Overview
Table 2–1. Stratix V Advanced Systems Development Board Components (Part 2 of 4)
Board Reference Type Description
SW8 PCI Express DIP switch
Controls the PCI Express lane width by connecting the
together on the PCI Express edge connector. This switch is located at
prsnt
pins
the back of the board.
S1 Program select push button
S2
Program configuration push
button
Toggles the program LEDs, which selects the program image that
loads from flash memory to the FPGAs.
Configures the FPGAs from flash memory image based on the program
LEDs.
Illuminates to show the LED sequence that determines which flash
D1, D2, D3 Program LEDs
memory image loads to the FPGA when you press the program select
push button.
D12 Load LED Illuminates during FPGA configuration.
D13 Configuration done LED Illuminates when the FPGA is configured.
D14 Error LED Illuminates when the FPGA configuration from flash fails.
D27 Power LED Illuminates when 5-V power is present.
Indicate the transmit or receive activity of the System Console USB
D4, D5 System Console TX/RX LEDs
interface. The TX and RX LEDs would flicker if the link is in use and
active. The LEDs are either off when not in use or on when in use but
idle.
Indicate the transmit or receive activity of the JTAG chain. The TX and
D15, D16 JTAG TX/RX LEDs
RX LEDs would flicker if the link is in use and active. The LEDs are
either off when not in use or on when in use but idle.
D10, D11 HSMC TX/RX LEDs
You can configure these LEDs to indicate transmit or receive activity on
the HSMC interface.
D21 HSMC Present LED Illuminates when you plug a daughtercard into the HSMC connector.
D36 FMC Present LED Illuminates when you plug a daughtercard into the FMC connector.
D42, D43 PCI Express Gen2/Gen3 LED
D38, D39, D40,
D41
PCI Express Link LEDs
You can configure these LEDs to illuminate when PCI Express is in
Gen2 or Gen3 mode.
You can configure these LEDs to display the PCI Express link width
(x1, x4, x8, x16).
Clock Circuitry
X1 125 M oscillator
X2 50 M oscillator
U53 Quad-output oscillator
U82 Quad-output oscillator
U95 Quad-output oscillator
U100 Quad-output oscillator
X91 Quad-output oscillator
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
125.000-MHz crystal oscillator for general purpose logic. A buffered
copy of this clock is available on FPGA1 and FPGA2.
50.000-MHz crystal oscillator for general purpose logic. A buffered
copy of this clock is available on FPGA1, FPGA2, and MAX V CPLD.
Programmable oscillator with default LVDS frequencies of 625 MHz,
206.25 MHz, 625 MHz, and 206.25 MHz.
Programmable oscillator with default frequencies of 100 MHz (LVDS),
100 MHz (LVDS), 100 MHz (1.8-V CMOS), and 100 MHz (LVDS).
Programmable oscillator with default LVDS frequencies of 100 MHz,
706.25 MHz, 206.25 MHz, and 206.25 MHz.
Programmable oscillator with default frequencies of 100 MHz (LVDS),
100 MHz (LVDS), 100 MHz (1.8-V CMOS), and 100 MHz (LVDS).
Programmable oscillator with default LVDS frequencies of 100 MHz,
644.53125 MHz, 644.53125 MHz, and 100 MHz.
Reference Manual
2–4 Chapter 2: Board Components
Board Overview
Table 2–1. Stratix V Advanced Systems Development Board Components (Part 3 of 4)
Board Reference Type Description
X3 100 M oscillator 100-MHz crystal oscillator for the MAX V CPLD System Controller.
J4, J5 Clock input SMAs Drives LVDS-compatible clock inputs into the clock multiplexer buffer.
General User Input and Output
D6-D9, D17-D20,
D22-D31
D22-D25,
D28-D31
FPGA1 user LEDs
FPGA2 user LEDs
SW1 FPGA1 user DIP switch
SW3 FPGA2 user DIP switch
Two sets of eight bi-color LEDs (green and red) for 16 user LEDs for
FPGA1. Illuminates when driven low.
Two sets of eight bi-color LEDs (green and red) for 16 user LEDs for
FPGA2. Illuminates when driven low.
Octal user DIP switch for FPGA1. When the switch is ON, a logic 0 is
selected.
Octal user DIP switch for FPGA2. When the switch is ON, a logic 0 is
selected.
S3 MAX V reset push button The default reset for the MAX V CPLD System Controller.
S7 FPGA1 CPU reset push button The default reset for the FPGA1 logic.
S11 FPGA2 CPU reset push button The default reset for the FPGA2 logic.
S4-S6
S8-S10
FPGA1 general user push
button
FPGA2 general user push
button
Three user push buttons for FPGA1. Driven low when pressed.
Three user push buttons for FPGA2. Driven low when pressed.
Memory Devices
U19, U57 DDR3A x32
U30, U34, U72,
U80
DDR3B x64
U36, U81 DDR3C x32
U21, U27, U58,
U68
DDR3D x64
U32, U75, DDR3E x32
U39, U43, U88,
U92
DDR3F x64
U33, U78 DDR3G x32
U17, U24, U55,
U64
U12, U52, U41,
U90
U22, U61, U40,
U89
DDR3H x64
QDRII+ x18 (interfaces A to D)
QDRII+ x18 (interfaces E to H)
U4 MoSys x16
512-MB DDR3 x64-bit data bus interfacing to FPGA1, consisting of
two x16-bit devices with a single address and command bus.
1024-MB DDR3 x64-bit data bus interfacing to FPGA1, consisting of
four x16-bit devices with a single address and command bus.
512-MB DDR3 x64-bit data bus interfacing to FPGA1, consisting of
two x16-bit devices with a single address and command bus.
1024-MB DDR3 x64-bit data bus interfacing to FPGA1, consisting of
four x16-bit devices with a single address and command bus.
512-MB DDR3 x64-bit data bus interfacing to FPGA2, consisting of
two x16-bit devices with a single address and command bus.
1024-MB DDR3 x64-bit data bus interfacing to FPGA2, consisting of
four x16-bit devices with a single address and command bus.
512-MB DDR3 x64-bit data bus interfacing to FPGA2, consisting of
two x16-bit devices with a single address and command bus.
1024-MB DDR3 x64-bit data bus interfacing to FPGA2, consisting of
four x16-bit devices with a single address and command bus.
Four 4.5-MB QDRII+ SRAM interfaces with a 18-bit data bus for
FPGA1. The device has a separate 18-bit read and 18-bit write port with
DDR signalling at up to 533 MHz.
Four 4.5-MB QDRII+ SRAM interfaces with a 18-bit data bus for
FPGA2. The device has a separate 18-bit read and 18-bit write port with
DDR signalling at up to 533 MHz.
A 72-MB MoSys Bandwidth Engine IC SRAM with a 16-bit transceiver
data bus for FPGA1.
Stratix V Advanced Systems Development Board January 2014 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–5
Featured Device: Stratix V GX FPGA
Table 2–1. Stratix V Advanced Systems Development Board Components (Part 4 of 4)
Board Reference Type Description
U14 MoSys x16
U86 Flash x16
U93, U48 EPCQ x4
U76, U83 EEPROM
Communication Ports
J13 PCI Express edge connector
U47 PLX PCI Express switch
J8 FMC port Provides 10 transceiver channels and 74 CMOS or 17 LVDS channels.
J1 HSMC port
A 72-MB MoSys Bandwidth Engine IC SRAM with a 16-bit transceiver
data bus for FPGA2.
A 1-Gb synchronous flash device with a 16-bit data bus for non-volatile
memory. Only accessible from the MAX V System Controller, intended
for FPGA configuration.
A 32-MB serial flash is available for each FPGA to use during active
serial (AS) configuration.
A single 8-Kbit serial EEPROM is available for each FPGA to store
board information.
Made of gold-plated edge fingers for up to ×16 signaling in either
Gen1, Gen2, or Gen3 mode.
Switch x16 PCI Express data between FPGA1 x8 and FPGA2 x8 via the
PEX8747 PCIe switch.
Provides eight transceiver channels and 84 CMOS or 17 LVDS
channels.
Power Supply
J13 PCI Express edge connector
J10 PCI Express 2x4 ATX power
J7 DC input jack Accepts a 12- to 15-V DC power supply.
SW2 Power switch
Interfaces to a PCI Express root port such as an appropriate PC
motherboard.
PCI Express compliant 2x4 auxiliary power connector. This can supply
an additional 150 W to the board.
Switch to power on or off the board when power is supplied from the
DC input jack.
Featured Device: Stratix V GX FPGA
The Stratix V Advanced Systems development board features two Stratix V GX FPGA
5SGXEA7N2F45C2N devices (U29, U35) in a 1932-pin FineLine BGA package.
f For more information about the Stratix V device family, refer to the Stratix V Device
Handbook.
Tab le 2– 2 describes the features of the Stratix V GX FPGA 5SGXEA7N2F45C2N
device.
Table 2–2. Stratix V GX FPGA 5SGXEA7N2F45C2N Features
ALMs
358,500 622,000 939,000 50 512 28 48
Equivalent
LEs
Registers
M20K
Memory (Mb)
18-bit × 18-bit
Multipliers
Fractional
PLLs
Transceiver Channels
(12.5 Gbps)
Package Type
1932-pin
FineLine BGA
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
2–6 Chapter 2: Board Components
Featured Device: Stratix V GX FPGA
I/O Resources
Tab le 2– 3 lists the Stratix V GX FPGA device pin count and usage by function on the
development board.
Table 2–3. Stratix V GX FPGA Pin Count and Usage (Part 1 of 2)
Function I/O Standard I/O Count Special Pins
FPGA1
DDR3 1.5-V SSTL 368 4 differential, 24 differential DQS
QDRII+ 1.5-V SSTL 260 4 differential DQS
EEPROM 2.5-V CMOS 2
FMC Adjustable 80 36 differential, 2 reference clocks
Switches 1.5-V CMOS 8
LEDs 1.5-V/2.5-V CMOS 19
Push buttons 1.5-V/2.5-V CMOS 4
Chip-to-chip 2.5-V CMOS + LVDS 20 4 differential
MAX V Interface 1.5-V/2.5-V CMOS 4
MoSys 1.5-V CMOS 10
PCI Express/PLX 1.5-V/2.5-V CMOS 10
Clocks or Oscillators 1.5-V CMOS + LVDS 26 5 differential clock, 7 differential reference clocks
On-board USB-Blaster II 1.5-V CMOS 19
Total I/O Used: 830
Transceiver Pairs
Chip-to-chip 8
FMC 10
MoSys 16
PCI Express/PLX 8
Total Transceivers Used: 42
FPGA2
DDR3 1.5-V SSTL 368 4 differential, 24 differential DQS
QDRII+ 1.5-V SSTL 260 4 differential DQS
EEPROM 2.5-V CMOS 2
HSMC 2.5-V CMOS + LVDS 84 38 differential, 3 clocks
Switches 1.5-V CMOS 8
LEDs 1.5-V CMOS 19
Push-buttons 1.5-V/2.5-V CMOS 4
Chip-to-chip 2.5-V CMOS + LVDS 20 4 differential
MAX V Interface 1.5-V/2.5-V CMOS 4
MoSys 1.5-V CMOS 10
PCI Express/PLX 1.5-V/2.5-V CMOS 6
Clocks or Oscillators 1.5-V CMOS + LVDS 24 5 differential clock, 6 differential reference clocks
Total I/O Used: 809
Stratix V Advanced Systems Development Board January 2014 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–7
Information
Register
On-Board
USB-Blaster II
Si5538
Controller
Si570
Controller
SLD-HUB
PFL
MAX V System Controller
Power
Measurement
Results
Virtual-JTAG
PC
Temperature
Measurement
Results
FPGA1
LTC2418
Controller
MAX1619
Controller
FPGA2
Decoder
Encoder
GPIO
JTAG Control
Flash
Control
Register
Si570
Programmable
Oscillator
Si5338
Programmable
Oscillator
Si5338
Programmable
Oscillator
Si5338
Programmable
Oscillator
Si5338
Programmable
Oscillator
MAX V CPLD System Controller
Table 2–3. Stratix V GX FPGA Pin Count and Usage (Part 2 of 2)
Function I/O Standard I/O Count Special Pins
Transceiver Pairs
Chip-to-chip 8
HSMC 8
MoSys 16
PCI Express/PLX 8
Total Transceivers Used: 40
MAX V CPLD System Controller
The board utilizes the 5M2210ZF256C4 System Controller, an Altera MAX V CPLD,
for the following purposes:
■ FPGA configuration from flash memory
■ Power consumption monitoring
■ Temp e ra tu re m onito ri ng
■ Fan control
■ Control registers for clocks
■ Control registers for remote system update
Figure 2–2 illustrates the MAX V CPLD System Controller's functionality and external
circuit connections as a block diagram.
Figure 2–2. MAX V CPLD System Controller Block Diagram
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
2–8 Chapter 2: Board Components
MAX V CPLD System Controller
Tab le 2– 4 lists the I/O signals present on the MAX V CPLD System Controller. The
signal names and functions are relative to the MAX V device (U73).
Table 2–4. MAX V CPLD System Controller Device Pin-Out (Part 1 of 5)
Schematic Signal Name
CLK125_EN
CLK50_EN
CLK_CONFIG
CLK_ENABLE
CLK_SEL
CLOCK_SCL
CLOCK_SDA
FACTORY_LOAD
FACTORY_REQUEST
FACTORY_STATUS
FLASH_ADVN
FLASH_CEN
FLASH_CLK
FLASH_OEN
FLASH_RDYBSYN
FLASH_RESETN
FLASH_WEN
FLASH_WPN
FLASH_A1
FLASH_A2
FLASH_A3
FLASH_A4
FLASH_A5
FLASH_A6
FLASH_A7
FLASH_A8
FLASH_A9
FLASH_A10
FLASH_A11
FLASH_A12
FLASH_A13
FLASH_A14
FLASH_A15
FLASH_A16
FLASH_A17
FLASH_A18
MAX V CPLD
Pin Number
I/O
Standard
Description
A2 2.5-V 125 MHz oscillator enable
E9 2.5-V 50 MHz oscillator enable
J5 2.5-V 100 MHz configuration clock input
C13 2.5-V DIP switch for clock oscillator enable
D11 2.5-V DIP switch for clock select SMA or oscillator
M2 2.5-V Programmable oscillator I2C clock
M3 2.5-V Programmable oscillator I2C data
B13 2.5-V DIP switch to load factory image from flash at power-up
R14 1.5-V On-Board USB-Blaster II request to send factory command
N12 1.5-V On-Board USB-Blaster II factory command status
K12 1.8-V FM bus flash memory address valid
D13 1.8-V FM bus flash memory chip enable
F12 1.8-V FM bus flash memory clock
D14 1.8-V FM bus flash memory output enable
F11 1.8-V FM bus flash memory chip ready 0
P14 1.8-V FM bus flash memory reset
K13 1.8-V FM bus flash memory write enable
M14 1.8-V FM bus flash memory write protect
C14 1.8-V FM address bus
C15 1.8-V FM address bus
E13 1.8-V FM address bus
E12 1.8-V FM address bus
D15 1.8-V FM address bus
F14 1.8-V FM address bus
D16 1.8-V FM address bus
F13 1.8-V FM address bus
E15 1.8-V FM address bus
E16 1.8-V FM address bus
F15 1.8-V FM address bus
G14 1.8-V FM address bus
F16 1.8-V FM address bus
G13 1.8-V FM address bus
N16 1.8-V FM address bus
G12 1.8-V FM address bus
G16 1.8-V FM address bus
H14 1.8-V FM address bus
Stratix V Advanced Systems Development Board January 2014 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–9
MAX V CPLD System Controller
Table 2–4. MAX V CPLD System Controller Device Pin-Out (Part 2 of 5)
Schematic Signal Name
FLASH_A19
FLASH_A20
FLASH_A21
FLASH_A22
FLASH_A23
FLASH_A24
FLASH_A25
FLASH_A26
FLASH_D0
FLASH_D1
FLASH_D2
FLASH_D3
FLASH_D4
FLASH_D5
FLASH_D6
FLASH_D7
FLASH_D8
FLASH_D9
FLASH_D10
FLASH_D11
FLASH_D12
FLASH_D13
FLASH_D14
FLASH_D15
FMC_C2M_PG
FPGA1_CONF_DONE
FPGA1_CPU_RESETN
FPGA1_CVP_CONFDONE
FPGA1_DCLK
FPGA1_FPP
FPGA1_MSEL0
FPGA1_MSEL1
FPGA1_MSEL2
FPGA1_MSEL3
FPGA1_MSEL4
FPGA1_NCE
FPGA1_NCEO
FPGA1_NCONFIG
FPGA1_NSTATUS
MAX V CPLD
Pin Number
I/O
Standard
Description
H15 1.8-V FM address bus
H13 1.8-V FM address bus
H16 1.8-V FM address bus
J13 1.8-V FM address bus
J16 1.8-V FM address bus
G15 1.8-V FM address bus
L16 1.8-V FM address bus
E14 1.8-V FM address bus
J14 1.8-V FM data bus
J15 1.8-V FM data bus
K16 1.8-V FM data bus
N15 1.8-V FM data bus
K15 1.8-V FM data bus
N14 1.8-V FM data bus
L14 1.8-V FM data bus
L11 1.8-V FM data bus
L15 1.8-V FM data bus
L12 1.8-V FM data bus
M16 1.8-V FM data bus
L13 1.8-V FM data bus
M15 1.8-V FM data bus
M13 1.8-V FM data bus
K14 1.8-V FM data bus
P15 1.8-V FM data bus
E3 2.5-V FMC carrier card to mezzanine module power good
A13 2.5-V FPGA1 configuration done
B1 2.5-V FPGA1 reset
N10 1.5-V FPGA1 configuration via protocol done
J3 2.5-V FPGA1 configuration clock
A15 2.5-V Configure FPGA1 via FPP at power up
A7 2.5-V DIP switch for FPGA1 mode select 0
E1 2.5-V DIP switch for FPGA1 mode select 1
A6 2.5-V DIP switch for FPGA1 mode select 2
A12 2.5-V FPGA1 mode select 3
A5 2.5-V FPGA1 mode select 4
B3 2.5-V FPGA1 chip enable
F1 2.5-V FPGA1 chip enable output
K2 2.5-V FPGA1 configuration active
J4 2.5-V FPGA1 configuration ready status
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
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2–10 Chapter 2: Board Components
MAX V CPLD System Controller
Table 2–4. MAX V CPLD System Controller Device Pin-Out (Part 3 of 5)
Schematic Signal Name
FPGA1_OVERTEMP
FPGA1_OVERTEMPN
FPGA1_PR_DONE
FPGA1_PR_ERROR
FPGA1_PR_READY
FPGA1_PR_REQUEST
FPGA2_CONF_DONE
FPGA2_CPU_RESETN
FPGA2_CVP_CONFDONE
FPGA2_DCLK
FPGA2_FPP
FPGA2_MSEL0
FPGA2_MSEL1
FPGA2_MSEL2
FPGA2_MSEL3
FPGA2_MSEL4
FPGA2_NCE
FPGA2_NCEO
FPGA2_NCONFIG
FPGA2_NSTATUS
FPGA2_OVERTEMP
FPGA2_OVERTEMPN
FPGA2_PR_DONE
FPGA2_PR_ERROR
FPGA2_PR_READY
FPGA2_PR_REQUEST
FPGA_CONFIG_D0
FPGA_CONFIG_D1
FPGA_CONFIG_D2
FPGA_CONFIG_D3
FPGA_CONFIG_D4
FPGA_CONFIG_D5
FPGA_CONFIG_D6
FPGA_CONFIG_D7
HSMC_PRSNTN
JTAG_5M2210_TDI
JTAG_5M2210_TDO
JTAG_TCK
JTAG_TMS
MAX V CPLD
Pin Number
I/O
Standard
Description
A11 2.5-V FPGA1 temperature monitor fan enable
D7 2.5-V FPGA1 temperature monitor over-temperature indicator LED
N9 1.5-V FPGA1 partial reconfiguration done
M10 1.5-V FPGA1 partial reconfiguration error
M8 1.5-V FPGA1 partial reconfiguration ready
R3 1.5-V FPGA1 partial reconfiguration request
P2 2.5-V FPGA2 configuration done
N3 2.5-V FPGA2 reset
T2 2.5-V FPGA2 configuration via protocol done
K5 2.5-V FPGA2 configuration clock
B14 2.5-V Configure FPGA2 via FPP at power up
G1 2.5-V DIP switch for FPGA2 mode select 0
L1 2.5-V DIP switch for FPGA2 mode select 1
J1 2.5-V DIP switch for FPGA2 mode select 2
N1 2.5-V FPGA2 mode select 3
M1 2.5-V FPGA2 mode select 4
K1 2.5-V FPGA2 chip enable
M4 2.5-V FPGA2 chip enable output
L5 2.5-V FPGA2 configuration active
H1 2.5-V FPGA2 configuration ready status
D10 2.5-V FPGA2 temperature monitor fan enable
E10 2.5-V FPGA2 temperature monitor over-temperature indicator LED
R6 1.5-V FPGA2 partial reconfiguration done
R1 1.5-V FPGA2 partial reconfiguration error
T5 1.5-V FPGA2 partial reconfiguration ready
R5 1.5-V FPGA2 partial reconfiguration request
D3 2.5-V FPGA configuration data
C2 2.5-V FPGA configuration data
C3 2.5-V FPGA configuration data
D1 2.5-V FPGA configuration data
D2 2.5-V FPGA configuration data
E4 2.5-V FPGA configuration data
D4 2.5-V FPGA configuration data
E5 2.5-V FPGA configuration data
B8 2.5-V HSMC port present
L6 2.5-V MAX V JTAG data in
M5 2.5-V MAX V JTAG data out
P3 2.5-V MAX V JTAG clock
N4 2.5-V MAX V JTAG TMS
Stratix V Advanced Systems Development Board January 2014 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–11
MAX V CPLD System Controller
Table 2–4. MAX V CPLD System Controller Device Pin-Out (Part 4 of 5)
Schematic Signal Name
M570_CLOCK
M570_PCIE_JTAG_EN
MAX5_CLK
MAX5_DATA
MAX_CONF_DONE
MAX_ERROR
MAX_LOAD
MAX_RESETN
MV_CLK_50
PGM_CONFIG
PGM_LED0
PGM_LED1
PGM_LED2
PGM_SEL
SENSE_CS0N
SENSE_SCK
SENSE_SDI
SENSE_SDO
SENSE_SMB_CLK
SENSE_SMB_DATA
SI53154_SCLK
SI53154_SDATA
TSENSE_ALERTN_1
TSENSE_ALERTN_2
USB_CFG0
USB_CFG1
USB_CFG2
USB_CFG3
USB_CFG4
USB_CFG5
USB_CFG6
USB_CFG7
USB_CFG8
USB_CFG9
USB_CFG10
USB_CFG11
USB_CFG12
USB_CFG13
MAX V CPLD
Pin Number
I/O
Standard
Description
P11 1.5-V 25-MHz clock to on-board USB-Blaster II
E11 2.5-V Reserved
T11 1.5-V MAX V clock
P5 1.5-V MAX V data
C11 2.5-V FPGA configuration done LED
A9 2.5-V FPGA configuration error LED
B12 2.5-V FPGA configuration active LED
M9 1.5-V MAX V reset push button
J12 1.8-V 50-MHz clock input
D9 2.5-V Loads the flash memory image identified by the PGM LEDs
B9 2.5-V Flash memory PGM select indicator 0
C10 2.5-V Flash memory PGM select indicator 1
D12 2.5-V Flash memory PGM select indicator 2
C9 2.5-V Toggles the
PGM_LED[0:2]
sequence
C12 2.5-V Power monitor chip select
B6 2.5-V Power monitor SPI clock
B11 2.5-V Power monitor SPI data in
B10 2.5-V Power monitor SPI data out
E7 2.5-V Temperature monitor SMB clock
E6 2.5-V Temperature monitor SMB data
C8 2.5-V Si53154 serial clock
A10 2.5-V Si53154 serial data
D8 2.5-V FPGA1 temperature monitor alert
B5 2.5-V FPGA2 temperature monitor alert
P8 1.5-V On-board USB Blaster II configuration
N6 1.5-V On-board USB Blaster II configuration
M6 1.5-V On-board USB Blaster II configuration
M7 1.5-V On-board USB Blaster II configuration
N8 1.5-V On-board USB Blaster II configuration
N7 1.5-V On-board USB Blaster II configuration
P9 1.5-V On-board USB Blaster II configuration
N11 1.5-V On-board USB Blaster II configuration
T9 1.5-V On-board USB Blaster II configuration
T10 1.5-V On-board USB Blaster II configuration
R9 1.5-V On-board USB Blaster II configuration
T8 1.5-V On-board USB Blaster II configuration
R16 1.5-V On-board USB Blaster II configuration
T13 1.5-V On-board USB Blaster II configuration
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
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Configuration, Status, and Setup Elements
Table 2–4. MAX V CPLD System Controller Device Pin-Out (Part 5 of 5)
Schematic Signal Name
USB_CFG14
USB_CLK
MAX V CPLD
Pin Number
T15 1.5-V On-board USB Blaster II configuration
H5 2.5-V On-board USB Blaster II clock
I/O
Standard
Configuration, Status, and Setup Elements
This section describes the board's configuration, status, and setup elements.
Configuration
This section describes the FPGA, flash memory, and MAX V CPLD System Controller
device programming methods that the Stratix V Advanced Systems development
board supports.
The Stratix V Advanced Systems development board supports three configuration
methods:
■ On-Board USB-Blaster II is the default method for configuring the FPGA using the
Quartus II Programmer in JTAG mode with the supplied mini-USB cable.
■ Parallel flash memory download for configuring the FPGAs using stored images
from the flash memory via FPP at either board power-up or by pressing the
program configuration push button (S2).
Description
■ Serial flash memory download for configuring either FPGA at board power-up via
active serial (x4 AS).
■ External USB-Blaster for configuring the FPGA using an external USB-Blaster.
FPGA Programming over On-Board USB-Blaster II
The on-board USB-Blaster II is implemented using a mini-USB type-B connector (J6), a
USB 2.0 PHY device, and an Altera MAX II CPLD EPM570F100 (U77). This allows for
FPGA configuration using a USB cable that connects directly between the USB port on
the board and a USB port on a PC running the Quartus II software. The on-board
USB-Blaster II masters the JTAG chain.
f For more information about the on-board USB-Blaster II, refer to the on-board
USB-Blaster II page of the Altera Wiki website.
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Reference Manual
Chapter 2: Board Components 2–13
Configuration, Status, and Setup Elements
MAX II CPLD EPM570F100
The MAX II CPLD is dedicated to the on-board USB-Blaster II function. The CPLD
connects to the USB 2.0 PHY device on one side and drives the JTAG signals out the
other side through the general purpose I/O (GPIO) pins.
Tab le 2– 5 lists the I/O signals present on the MAX II CPLD EPM570F100.
Table 2–5. MAX II CPLD On-Board USB-Blaster II I/O Signals
Schematic Signal Name Type Description
SC_RX
SC_TX
JTAG_RX
JTAG_TX
C_JTAG_TCK
C_JTAG_TMS
C_JTAG_TDI
C_JTAG_TDO
USB_CFG(14:0)
USB_CLK
USB_OEn
USB_RESETn
USB_DATA(7:0)
USB_RDn
USB_WRn
USB_EMPTY
USB_FULL
USB_ADDR(1:0)
USB_SCL
USB_SDA
FACTORY_REQUEST
FACTORY_STATUS
M570_CLOCK
1.5-V CMOS output USB system console receive LED
1.5-V CMOS output USB system console transmit LED
1.5-V CMOS output USB-Blaster II JTAG receive LED
1.5-V CMOS output USB-Blaster II JTAG transmit LED
2.5-V CMOS output GPIO for on-board JTAG chain clock
2.5-V CMOS output GPIO for on-board JTAG chain mode
2.5-V CMOS output GPIO for on-board JTAG chain data in
2.5-V CMOS input GPIO for on-board JTAG chain data out
1.5-V CMOS input/output
Configuration data between the MAX V System
Controller and the on-board USB-Blaster II.
2.5-V CMOS input USB System Console clock
1.5-V CMOS input USB System Console FPGA output enable
1.5-V CMOS input USB System Console reset
1.5-V CMOS inout (8 bits) USB System Console FIFO data bus
1.5-V CMOS input USB System Console read from FIFO
1.5-V CMOS input USB System Console write to FIFO
1.5-V CMOS output USB System Console FIFO empty
1.5-V CMOS output USB System Console FIFO full
1.5-V CMOS input/output USB System Console address bus
1.5-V CMOS input/output USB System Console configuration clock
1.5-V CMOS input/output USB System Console configuration data
1.5-V CMOS input Send FACTORY command
1.5-V CMOS output FACTORY command status
1.5-V CMOS input 25-MHz input clock for FACTORY command
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
2–14 Chapter 2: Board Components
GPIO
Cypress
On-Board
USB-Blaster II
Analog
Switch
5M2210
System
Controller
FMC
HSMC
GPIO
GPIO
GPIO
JTAG Master
GPIO
DISABLE
JTAG Slave
JTAG Slave
Installed
HSMC
Card
Installed
FMC
Card
Flash
Memory
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
JTAG Slave
JTAG Slave
5SGXA7
FPGA1
5SGXA7
FPGA2
Analog
Switch
ENABLE
ENABLE
ALWAYS
ENABLED
(in chain)
ALWAYS
ENABLED
(in chain)
DIP Switch
DIP Switch
10-pin
JTAG Header
TCK
TMS
TDI
TDO
JTAG Slave
TCK
TMS
TDO
TDI
2.5 V
2.5 V
Configuration, Status, and Setup Elements
JTAG Chain
The on-board USB-Blaster II is automatically disabled when you connect an external
USB-Blaster to the JTAG chain or when you enable JTAG from the PCI Express edge
connector. Figure 2–3 illustrates the JTAG chain.
Figure 2–3. JTAG Chain
Each jumper shown in Figure 2–3 is located in the JTAG DIP switch (SW7) on the back
of the board. Both the Stratix V FPGAs and the MAX VSystem Controller are always
in the JTAG chain. To connect the HSMC or FMC interface in the chain, their
corresponding switch must be in the OFF position.
Stratix V Advanced Systems Development Board January 2014 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–15
Configuration, Status, and Setup Elements
1 By default, the on-board USB-Blaster II clocks
TCK
at 24 MHz. For the on-board
USB-Blaster II to function correctly, you must set the Quartus II clock constraint on the
altera_reserved_tck
input signal to 24 MHz.
System Console USB Interface
The System Console USB interface is a fast parallel interface available on FPGA1.
Together with the soft logic supplied by Altera, this interface provides a System
Console master for debug access.
The System Console controls the debug master via signals shown in Tab le 2 –6 to give
fast access to an Avalon
®
Memory-Mapped (Avalon-MM) master bus that the Qsys
system integration tool generates.
f For more information about the System Console, refer to the Analyzing and Debugging
Designs with the System Console chapter in volume 3 of the Quartus II Handbook.
Tab le 2 –6 lists the System Console USB interface pin connections relative to the FPGA.
Table 2–6. System Console USB Interface Pin Connections
Stratix V GX FPGA1 (U29) Pin Number Schematic Signal Name Direction Note
BC8
BD34
BA15, AJ13, AR16, AH13, BD14, AF17,
BC14, AP13
AW33
AU35
AJ29
AT33
AV34
AF13, BD10
BD35
BA31
usb_clk
usb_resetn
usb_data[7:0]
usb_full
usb_empty
usb_wrn
usb_rdn
usb_oen
usb_addr[1:0]
usb_scl
usb_sda
input 48 MHz
input —
bidirectional BA15 (MSB), AP13 (LSB)
output —
output —
input —
input —
input —
bidirectional Reserved
bidirectional —
bidirectional —
CFI Flash Programming
Flash programming is possible using the pre-built PFL design included in the
development kit to write configuration data to the CFI flash. The development board
implements the Altera PFL megafunction for flash programming. The PFL
megafunction is a block of logic that is programmed into an Altera programmable
logic device, in this case, the MAX V CPLD. The PFL functions as a utility for writing
to a compatible flash device.
This pre-built design contains the PFL megafunction that allows you to write either
page 0, page 1, or other areas of flash over the on-board USB-Blaster II interface using
the Quartus II software.
1 Use this method to restore the development board to its factory default settings.
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
2–16 Chapter 2: Board Components
Configuration, Status, and Setup Elements
FPGA Programming from CFI Flash Memory
On either board power-up or by pressing the program load push button (S2), the
MAX V CPLD System Controller’s parallel flash loader configures the FPGA from the
flash memory. The system controller uses the Altera Parallel Flash Loader (PFL)
megafunction which reads 16-bit data from the flash memory and converts it to fast
passive parallel (FPP) format. This 16-bit data is then written to the FPGA’s dedicated
configuration pins during configuration.
After a board power-up or reset event, the MAX V CPLD (U73) automatically
configures the FPGAs in FPP mode with the pre-installed factory .pof file. There are
three pages reserved for the FPGA configuration data—factory FPGA1 (page 0),
factory FPGA2 (page 1), and user design FPGA1 (page 2).
1 You must set the FPGA1_MSEL[4:0] or FPGA2_MSEL[4:0] DIP switch to FPP x8 mode
to configure FPGA1 or FPGA2 via FPP.
f For more information about the FPP configuration mode, refer to the Configuration,
Design Security, and Remote System Upgrades in Stratix V Devices chapter in the Stratix V
Handbook.
Three green configuration status LEDs,
PGM_LED[2:0]
(D1, D2, D3) indicates the status
of the FPP configuration. Ta bl e 2– 7 lists the configuration status LEDs settings.
Table 2–7. Configuration LED settings
LED
PGM_LED0 PGM_LED1 PGM_LED2
v — — Factory FPGA1
— v —Factory FPGA2
——v User design FPGA1
Note to Tab le 2–7 :
(1) A checkmark (v) indicates that the LED is ON (logic 0) while a dash (—) indicates that the LED is OFF (logic 1).
(1)
Design
Stratix V Advanced Systems Development Board January 2014 Altera Corporation
Reference Manual
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