Stratix V Advanced Systems Development Kit User Guide
Stratix V Advanced Systems Development Kit
User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
UG-01132-1.0
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February 2013 Altera Corporation Stratix V Advanced Systems Development Kit
User Guide
Contents
Chapter 1. About This Kit
Kit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Quartus II Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
The Kit Installer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Chapter 2. Getting Started
Before You Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Inspect the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Chapter 3. Software Installation
Installing the Quartus II Subscription Edition Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Licensing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Installing the Stratix V Advanced Systems Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Installing the USB-Blaster II Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Chapter 4. Development Board Setup
Setting Up the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Factory Default Switch and Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Chapter 5. Board Test System
Preparing the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Running the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Using the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
The Configure Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
The System Info Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
Board Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
The GPIO FPGA1 Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
User DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
Push Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
The GPIO FPGA2 Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
User DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
Push Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
The FMC/C2C Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
PMA Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
The HSMC Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
February 2013 Altera Corporation Stratix V Advanced Systems Development Kit
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iv Contents
Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
PMA Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
The Power Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14
Temperature Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15
Power Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15
Power Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15
Graph Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15
The Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16
Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16
Set New Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17
Configuring the FPGA Using the Quartus II Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17
Appendix A. Programming the Flash Memory Device
CFI Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
Converting .sof Files to a .pof . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
Programming Altera CPLDs and Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
Restoring the MAX V CPLD to the Factory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Stratix V Advanced Systems Development Kit February 2013 Altera Corporation
User Guide
Kit Features
f For a complete list of this kit’s contents and capabilities, refer to the
Hardware
1. About This Kit
The Altera® Stratix®V Advanced Systems Development Kit is a complete design
environment that includes both the hardware and software you need to develop
Stratix V GX FPGA designs.
This section briefly describes the development kit contents.
Stratix V Advanced Systems Development Kit.
The Stratix V Advanced Systems Development Kit includes the following hardware:
■ Stratix V GX advanced systems board—A development platform that allows you
to develop and prototype hardware designs running on the Stratix V GX FPGA.
f For detailed information about the board components and interfaces, refer
to the Stratix VAdvanced Systems Development Board Reference Manual.
■ HSMC loopback board—A daughtercard that allows for loopback testing all
signals on the HSMC interface using the Board Test System.
■ Power supply and cables—The kit includes the following items:
■ Power supply and AC adapters for North America/Japan, Europe, and the
United Kingdom
■ Standard USB A to mini-USB cable
Software
The software for this kit, described in the following sections, is available on the Altera
website for immediate downloading. You can also request to have Altera mail the
software to you on DVDs.
Quartus II Software
Your kit includes a license for the Development Kit Edition (DKE) of the Quartus II
software (Windows platform only). For one year, this license entitles you to most of
the features of the Subscription Edition (excluding the IP Base Suite).
1 After the year, your DKE license will no longer be valid and you will not be permitted
to use this version of the Quartus II software. To continue using the Quartus II
software, you should download the free Quartus II Web edition or purchase a
subscription to Quartus II software. For more information, refer to the Design
Software page of the Altera website.
February 2013 Altera Corporation Stratix V Advanced Systems Development Kit
User Guide
1–2 Chapter 1: About This Kit
Kit Features
The Quartus II Development Kit Edition (DKE) software includes the following items:
■ Quartus II Software—The Quartus II software, including the Qsys system
integration tool, provides a comprehensive environment for network on a chip
(NoC) design. The Quartus II software integrates into nearly any design
environment and provides interfaces to industry-standard EDA tools.
■ MegaCore
®
IP Library—A library that contains Altera IP MegaCore functions. You
can evaluate MegaCore functions by using the OpenCore Plus feature to do the
following:
■ Simulate behavior of a MegaCore function within your system.
■ Verify functionality of your design, and quickly and easily evaluate its size and
speed.
■ Generate time-limited device programming files for designs that include
MegaCore functions.
■ Program a device and verify your design in hardware.
1 The OpenCore Plus hardware evaluation feature is an evaluation tool for
prototyping only. You must purchase a license to use a MegaCore function
in production.
f For more information about OpenCore Plus, refer to AN 320: OpenCore Plus
Evaluation of Megafunctions.
■ Nios
®
II Embedded Design Suite (EDS)—A full-featured set of tools that allows
you to develop embedded software for the Nios II processor, which you can
include in your Altera FPGA designs.
The Kit Installer
The license-free Stratix V Advanced Systems Development Kit installer includes all
the documentation and design examples for the kit.
For information on installing the Development Kit Installer, refer to “Software
Installation” on page 3–1.
Stratix V Advanced Systems Development Kit February 2013 Altera Corporation
User Guide
The remaining chapters in this user guide lead you through the following
Stratix V GX advanced systems board setup steps:
■ Inspecting the contents of the kit
■ Installing the design and kit software
■ Setting up, powering up, and verifying correct operation of the advanced systems
■ Configuring the Stratix V GX FPGA
■ Running the Board Test System designs
f For complete information about the advanced systems board, refer to the
Stratix VAdvanced Systems Development Board Reference Manual.
Before You Begin
2. Getting Started
board
Inspect the Board
f For information about measuring board and FPGA temperature in real time, refer to
f For information about power consumption and thermal modeling, refer to AN 358:
References
Before using the kit or installing the software, check the kit contents and inspect the
board to verify that you received all of the items listed in “Kit Features” on page 1–1.
If any of the items are missing, contact Altera before you proceed.
To inspect the board, perform the following steps:
1. Place the board on an anti-static surface and inspect it to ensure that it has not been
damaged during shipment.
c Without proper anti-static handling, you can damage the board.
2. Verify that all components are on the board and appear intact.
“The Power Monitor” on page 5–13.
Thermal Management for FPGAs.
Use the following links to check the Altera website for other related information:
■ For the latest board design files and reference designs, refer to the
Stratix V Advanced Systems Development Kit page.
■ For additional daughter cards available for purchase, refer to the Development
Board Daughtercards page.
February 2013 Altera Corporation Stratix V Advanced Systems Development Kit
User Guide
2–2 Chapter 2: Getting Started
■ For the Stratix V GX device documentation, refer to the Literature: Stratix V
References
Devices page.
■ To purchase devices from the eStore, refer to the Devices page.
■ For Stratix V GX OrCAD symbols, refer to the Capture CIS Symbols page.
■ For Nios II 32-bit embedded processor solutions, refer to the Embedded
Processing page.
Stratix V Advanced Systems Development Kit February 2013 Altera Corporation
User Guide
3. Software Installation
This chapter explains how to install the following software:
■ Quartus II Subscription Edition Software
■ Stratix V Advanced Systems Development Kit
■ USB-Blaster™ II driver
Installing the Quartus II Subscription Edition Software
Included in the Quartus II Subscription Edition Software are the Quartus II software
(including Qsys), the Nios II EDS, and the MegaCore IP Library. To install the Altera
development tools, perform the following steps:
1. Download the Quartus II Subscription Edition Software from the Quartus II
Subscription Edition Software page of the Altera website. Alternatively, you can
request a DVD from the Altera IP and Software DVD Request Form page of the
Altera website.
2. Follow the on-screen instructions to complete the installation process. Choose an
installation directory that is relative to the Quartus II software installation
directory.
f If you have difficulty installing the Quartus II software, refer to the Altera Software
Installation and Licensing Manual.
Licensing Considerations
Purchasing this kit entitles you to a one-year license for the Development Kit Edition
(DKE) of the Quartus II software.
1 After the year, your DKE license will no longer be valid and you will not be permitted
to use this version of the Quartus II software. To continue using the Quartus II
software, you should download the free Quartus II Web edition or purchase a
subscription to Quartus II software.
Before using the Quartus II software, you must activate your license, identify specific
users and computers, and obtain and install a license file.
If you already have a licensed version of the subscription edition, you can use that
license file with this kit. If not, you need to obtain and install a license file. To begin,
go to the Self Service Licensing Center page of the Altera website, log into or create
your myAltera account, and take the following actions:
1. On the Activate Products page, enter the serial number provided with your
development kit in the License Activation Code box.
1 Your serial number is printed on the development kit box below the bottom
bar code. The number is consists of alphanumeric characters, such as
5SGXASxxxxxxxx, and does not contain hyphens.
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3–2 Chapter 3: Software Installation
Installing the Stratix V Advanced Systems Development Kit
2. Consult the Activate Products table, to determine how to proceed.
a. If the administrator listed for your product is someone other than you, skip the
remaining steps and contact your administrator to become a licensed user.
b. If the administrator listed for your product is you, proceed to step 3.
c. If the administrator listed for your product is Stocking, activate the product,
making you the administrator, and proceed to step 3.
3. Use the Create New License page to license your product for a specific user (you)
on specific computers. The Manage Computers and Manage Users pages allow
you to add users and computers not already present in the licensing system.
1 To license the Quartus II software, you need your computer’s network
interface card (NIC) ID, a number that uniquely identifies your computer.
On the computer you use to run the Quartus II software, type
/all
at a command prompt to determine the NIC ID. Your NIC ID is the
ipconfig
12-digit hexadecimal number on the Physical Address line.
4. When licensing is complete, Altera emails a license.dat file to you. Store the file on
your computer and use the License Setup page of the Options dialog box in the
Quartus_II software to enable the software.
f For complete licensing details, refer to the Altera Software Installation and Licensing
Manual.
Installing the Stratix V Advanced Systems Development Kit
To install the Stratix V Advanced Systems Development Kit, perform the following
steps:
1. Download the Stratix V Advanced Systems Development Kit installer from the
Stratix V Advanced Systems Development Kit page of the Altera website.
Alternatively, you can request a development kit DVD from the Altera Kit
Installations DVD Request Form page of the Altera website.
2. Run the Stratix V Advanced Systems Development Kit installer.
3. Follow the on-screen instructions to complete the installation process. Be sure that
the installation directory you choose is in the same relative location to the
Quartus II software installation.
Stratix V Advanced Systems Development Kit February 2013 Altera Corporation
User Guide
Chapter 3: Software Installation 3–3
<install dir>
documents
board_design_files
The default Windows installation directory is C:\altera\
<version>
\.
examples
factory_recovery
demos
kits
stratixVGX_5sgxea7nf45_as
Installing the USB-Blaster II Driver
The installation program creates the Stratix V Advanced Systems Development Kit
directory structure shown in Figure 3–1.
Figure 3–1. Stratix V Advanced Systems Development Kit Installed Directory Structure
Note to Figure 3–1:
(1) Early-release versions might have slightly different directory names.
Tab le 3– 1 lists the file directory names and a description of their contents.
Table 3–1. Installed Directory Contents
Directory Name Description of Contents
board_design_files
Contains schematic, layout, assembly, and bill of material board design files. Use these files as a
starting point for a new prototype board design.
demos Contains demonstration applications when available.
documents Contains the kit documentation.
examples Contains the sample design files for the Stratix V Advanced Systems Development Kit.
factory_recovery
Contains the original data programmed onto the board before shipment. Use this data to restore
the board with its original factory contents.
(1)
Installing the USB-Blaster II Driver
The Stratix V GX advanced systems board includes integrated On-Board USB-Blaster
II circuitry for FPGA programming. However, for the host computer and board to
communicate, you must install the USB-Blaster II driver on the host computer.
f Installation instructions for the USB-Blaster II driver for your operating system are
available on the Altera website. On the Altera Programming Cable Driver Information
February 2013 Altera Corporation Stratix V Advanced Systems Development Kit
page of the Altera website, locate the table entry for your configuration and click the
link to access the instructions.
User Guide
3–4 Chapter 3: Software Installation
Installing the USB-Blaster II Driver
Stratix V Advanced Systems Development Kit February 2013 Altera Corporation
User Guide
The instructions in this chapter explain how to set up the Stratix V GX advanced
systems board.
Setting Up the Board
To prepare and apply power to the board, perform the following steps:
1. The Stratix V GX advanced systems board ships with its board switches
preconfigured to support the design examples in the kit. If you suspect your board
might not be currently configured with the default settings, follow the instructions
in “Factory Default Switch and Jumper Settings” on page 4–2 to return the board
to its factory settings before proceeding.
2. The advanced systems board ships with design examples stored in the flash
memory device. Verify the DIP switch SW4.6 is set to the on (0) position to load the
design stored in the factory portion of flash memory. Figure 4–2 shows the DIP
switch location on the back of the board.
4. Development Board Setup
3. Verify that the HSMC card is installed on connector J1 of the board.
4. Ensure that the power switch SW2 is in the off position.
5. Connect the Power Adpater +15 V, 8.00 A to the DC Power Jack (J7) on the
advanced systems board and plug the cord into a power outlet.
c Use only the supplied power supply. Power regulation circuitry on the
board can be damaged by power supplies with greater voltage.
1 For designs requiring more than 120 W, a PCIe 2x4 ATX connector (J10)
providing an additional 12 V and 12.5 A is also available. This is the
standard PCIe 2x4 connector in a chassis or available with an ATX power
supply.
1 Alternatively, the board can be powered by the PCIe host adapter or the
laptop power adapter. If you want to power the board by the PCIe host
system, plug the FPGA development card into a standard PCIe connector.
6. Set the POWER switch (SW2) to the on position. When power is supplied to the
board, the blue LED (D27) illuminates indicating that the board has power.
The MAX V device on the board contains (among other things) a parallel flash loader
(PFL) megafunction. When the board powers up, the PFL reads a design from flash
memory and configures the FPGA. DIP switch SW4.6 controls whether the FPP is
active and loads the designs from flash into the Stratix V devices. When the switch is
in the on (0) position, the PFL loads the design from flash memory. For FPP to
function properly, the MSEL pins for both FPGAs must be set for FPP x8 on MSEL DIP
switches SW5 and SW6.
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4–2 Chapter 4: Development Board Setup
Factory Default Switch and Jumper Settings
1 The kit includes a MAX V design which contains the MAX V PFL megafunction. The
design resides in the <install dir>\kits\stratixVGX_5sgxea7nf45_as\examples\max5
directory.
When configuration is complete, the Config Done LED (D13) illuminates, signaling
that the Stratix V GX devices configured successfully.
f For more information about the PFL megafunction, refer to AN 386: Parallel Flash
Loader Megafunction User Guide.
Factory Default Switch and Jumper Settings
This section shows the factory switch and jumper settings for the Stratix V GX
advanced systems board.
Figure 4–1 shows the switch locations and the default position of each switch and
jumper on the top side of the board.
Figure 4–1. Default Settings on the Board Top (Detail)
1
SW1
0
7
6543210
ON
J2
FAN1
VCCIO_FMC
1.8 V
1.5 V
1.2 V
J3
7
6543210
1
SW3
ON
0
Default:
no jumper installed
for 2.5 V
FAN2
J12
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Chapter 4: Development Board Setup 4–3
SW6
FPGA2
MSEL
1 2 3 4
1
0
SW5
FPGA1
MSEL
1 2 3 4
1
SW8
1 2 3 4
X1 X4 X8 X16
SW7
1 2 3 4
0
0
1
0
1
SW4
1 2 3 4 5 6
FPGA1_FPP
FPGA2_FPP
EXTRA0
EXTRA1
CLK_EN
CLK_SEL
HSMC JTAG
FMC
Factory Default Switch and Jumper Settings
Figure 4–2 shows the switch locations and the default position of each switch on the
bottom side of the board.
Figure 4–2. Default Settings on the Board Bottom (Detail)
To restore the switches to their factory default settings, perform the following steps:
1. Set DIP switch (SW4) to match Ta bl e 4 –1 and Figure 4–2 on page 4–3.
Table 4–1. SW4 DIP Switch Settings
Switch Board Label Function
Default
Position
Switch 1 has the following options:
■ When on (0), FPP x8 is enabled to configure
FPGA1 from flash location 0 and FPGA2 from flash
1 FPGA1_FPP
location 1. FPGA1 MSEL (SW5) pins and FPGA2
On
MSEL (SW6) pins must be set correctly.
■ When off (1), no design is configured to FPGA1 or
FPGA2 using FPP x8.
2 FPGA2_FPP — On
3EXTRA0 — Off
4EXTRA1 — Off
Switch 5 has the following options:
5 CLK_EN
6 CLK_SEL
■ When on (0), the on-board oscillator is disabled.
■ When off (1), the on-board oscillator is enabled.
Switch 6 has the following options:
■ When on (0), the SMA input clock is selected.
■ When off (1), the programmable oscillator clock is
selected.
February 2013 Altera Corporation Stratix V Advanced Systems Development Kit
Off
On
User Guide
4–4 Chapter 4: Development Board Setup
Factory Default Switch and Jumper Settings
2. Set DIP switch (SW5) to match Ta bl e 4 –2 and Figure 4–2 on page 4–3.
Table 4–2. SW5 FPGA1 MSEL DIP Switch Settings
Switch Board Label Function
(1) (2) (3)
Default
Position
1 FPGA1 MSEL0 FPGA1 MSEL bit 0 configuration setting On (0)
2 FPGA1 MSEL1 FPGA1 MSEL bit 1 configuration setting On (0)
3 FPGA1 MSEL2 FPGA1 MSEL bit 2 configuration setting Off (1)
4— — —
Notes to Table 4–2:
(1) FPGA1 MSEL[4:3]=10 is hard wired on the board.
(2) FPGA1 MSEL[4:0] to valid configuration schemes as listed in the Stratix V Device Handbook.
(3) By default, FPGA1 MSEL is set for FPP x8.
3. Set DIP switch (SW6) to match Ta bl e 4 –3 and Figure 4–2 on page 4–3.
Table 4–3. SW6 FPGA2 MSEL DIP Switch Settings
Switch Board Label Function
(1) (2) (3)
Default
Position
1 FPGA2 MSEL0 FPGA2 MSEL bit 0 configuration setting On (0)
2 FPGA2 MSEL1 FPGA2 MSEL bit 1 configuration setting On (0)
3 FPGA2 MSEL2 FPGA2 MSEL bit 2 configuration setting Off (1)
4— — —
Notes to Table 4–3:
(1) FPGA2 MSEL[4:3]=10 is hard wired on the board.
(2) FPGA2 MSEL[4:0] to valid configuration schemes as listed in the Stratix V Device Handbook.
(3) By default, FPGA2 MSEL is set for FPP x8.
4. Set DIP switch (SW7) to match Ta bl e 4 –4 and Figure 4–2 on page 4–3.
Table 4–4. SW7 JTAG DIP Switch Settings
Switch Board Label Function
(1)
Default
Position
Switch 1 has the following options:
■ When on (1), removes the HSMC from the JTAG
1HSMC
chain.
■ When off (0), includes the HSMC in the JTAG
On (1)
chain.
Switch 1 has the following options:
2FMC
■ When on (1), removes the FMC from the JTAG
chain.
■ When off (0), includes the FMC in the JTAG chain.
On (1)
3— — —
4— — —
Note to Tab le 4–4:
(1) If you plug in an external USB-Blaster cable to the JTAG header (J11), the On Board USB-Blaster II is disabled. The
JTAG chain is normally mastered by the On-board USB-Blaster II.
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Chapter 4: Development Board Setup 4–5
Factory Default Switch and Jumper Settings
f For details on the JTAG chain, refer to the Stratix VAdvanced Systems Development
Board Reference Manual.
5. Set DIP switch (SW8) to match Ta bl e 4 –5 and Figure 4–2 on page 4–3.
Table 4–5. SW8 PCIe DIP Switch Settings
Switch Board Label Function
Default
Position
Switch 1 has the following options:
1X1
■ When on, x1 presence detect is available.
■ When off, x1 presence detect is unavailable.
Off
Switch 2 has the following options:
2X4
■ When on, x4 presence detect is available.
■ When off, x4 presence detect is unavailable.
Off
Switch 3 has the following options:
3X8
■ When on, x8 presence detect is available.
■ When off, x8 presence detect is unavailable.
Off
Switch 4 has the following options:
4X16
■ When on, x16 presence detect is available.
■ When off, x16 presence detect is unavailable.
Off
6. Set jumper blocks (J2, J3, and J12) to match Tab le 4 –6 and Figure 4–1 on page 4–2.
Table 4–6. Jumper Settings
Board Reference Description Shunt Position
J2 Fan 1 — 5 V and GND power Fan 1 power connected
J3 VCCIO_FMC 1.8 V Pins 1-2
J3 VCCIO_FMC 1.5 V Pins 3-4
J3 VCCIO_FMC 1.2 V Pins 5-6
J3 VCCIO_FMC 2.5 V Not installed (Default)
J12 Fan 2 — 5 V and GND power Fan 2 power connected
f For more information about the FPGA board settings, refer to the Stratix VAdvanced
Systems Development Board Reference Manual.
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Factory Default Switch and Jumper Settings
Stratix V Advanced Systems Development Kit February 2013 Altera Corporation
User Guide
The Stratix V Advanced Systems Development Kit includes an application called the
Board Test System (BTS) with related design examples. The BTS provides an
easy-to-use interface to alter functional settings and observe the results.
You can use the BTS to test board components, modify functional parameters, observe
performance, and measure power usage. While using the BTS, you reconfigure the
FPGA several times with test designs specific to the functionality you are testing. The
BTS is also useful as a reference for designing systems.
To install the BTS, follow the steps in “Installing the Stratix V Advanced Systems
Development Kit” on page 3–2.
The Board Test System communicates over the JTAG bus to a test design running in
the Stratix V GX device. Figure 5–1 shows the initial GUI for a board that is in the
factory configuration.
Figure 5–1. Board Test System Graphical User Interface
5. Board Test System
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5–2 Chapter 5: Board Test System
Several designs are provided to test the major board features. Each design provides
data for one or more tabs in the application. The Configure menu identifies the
appropriate design to download to the FPGA for each tab.
After successful FPGA configuration, the appropriate tab appears and allows you to
exercise the related board features. Highlights appear in the board picture around the
corresponding components.
The Power Monitor button starts the Power Monitor application that measures and
reports current power and temperature information for the board. Because the
application communicates over the JTAG bus to the MAX V device, you can measure
the power of any design in the FPGA, including your own designs.
Preparing the Board
1 The Board Test System and Power Monitor share the JTAG bus with other
applications like the Nios II debugger and the SignalTap
Analyzer. Because the Quartus II programmer uses most of the bandwidth of the
JTAG bus, other applications using the JTAG bus might time out. Be sure to close the
other applications before attempting to reconfigure the FPGA using the Quartus II
Programmer.
Preparing the Board
With the power to the board off, follow these steps:
1. Connect the mini-USB cable to the board.
2. Ensure that the board DIP switches are set to default positions as shown in the
“Factory Default Switch and Jumper Settings” section starting on page 4–2.
f For more information about the board’s DIP switch and jumper settings,
1 FPP x8 mode must be enabled for the BTS functionality to work.
3. Turn on the power to the board. By default, the board loads FPGA1 with the
design stored in the factory hardware 0 portion of flash memory and FPGA2 with
the factory hardware 1 portion of flash memory. If your board is still in the factory
configuration, the design loads the FPGA1 GPIO tests.
®
II Embedded Logic
refer to the Stratix VAdvanced Systems Development Board Reference Manual.
c To ensure operating stability, keep the USB cable connected and the board
powered on when running the demonstration application. The application
cannot run correctly unless the USB cable is attached and the board is on.
Running the Board Test System
To run the application, navigate to the <install
dir>\kits\stratixVGX_5sgxea7nf45_as\examples\board_test_system directory and
run the BoardTestSystem.exe application.
1 On Windows, click Start > All Programs > Altera > Stratix V Advanced Systems
Development Kit <version> > Board Test System to run the application.
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Chapter 5: Board Test System 5–3
Using the Board Test System
A GUI appears, displaying the application tab that corresponds to the design running
in the FPGA. The Stratix V GX advanced systems board’s flash memory ships
preconfigured with the design that corresponds to the GPIO and Flash tabs.
1 If you power up your board with the DIP switch SW4.6 in a position other than the on
(factory default) position, or if you load your own design into the FPGA with the
Quartus II Programmer, you receive a message prompting you to configure your
board with a valid Board Test System design. Refer to “The Configure Menu” for
information about configuring your board.
Using the Board Test System
This section describes each control in the Board Test System application.
The Configure Menu
Use the Configure menu (Figure 5–2) to select the design you want to use. Each design
example tests different functionality that corresponds to one or more application tabs.
Figure 5–2. The Configure Menu
To configure the FPGA with a test system design, perform the following steps:
1. Make sure there are no conflicts between the Quartus II software version and the
Board Test System GUI version. For example, BTS version 12.1.xx requires Quartus
II software version 12.1.
2. On the Configure menu, click the configure command that corresponds to the
functionality you wish to test.
3. When configuration finishes, close the Quartus II Programmer if open. The design
begins running in the FPGA. The corresponding GUI application tabs that
interface with the design are now enabled.
1 If the Board Test System is open while you configure FPGAs with the
Quartus II Programmer, to use the BTS again, you may need to restart it.
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5–4 Chapter 5: Board Test System
Using the Board Test System
The System Info Tab
The System Info tab shows information about the board’s current configuration.
Figure 5–1 on page 5–1 shows the System Info tab. The tab displays the contents of
the MAX V registers, the JTAG chain, the flash memory map, and other details stored
on the board.
The following sections describe the controls on the System Info tab.
Board Information
The Board information control displays static information about your board.
■ Board Name—Indicates the official name of the board.
■ Board P/N—Indicates the part number of the board.
■ Serial number—Indicates the serial number of the board.
■ Factory test version—Indicates the version of the Board Test System currently
running on the board.
JTAG Chain
The JTAG chain control shows all the devices currently in the JTAG chain. The
Stratix V GX devices are always the first devices in the chain, and the MAX V is
always the last device in the chain. The JTAG chain is normally mastered by the
On-board USB-Blaster II.
1 If you plug in an external USB-Blaster cable to the JTAG header (J11), the On-Board
USB-Blaster II is disabled.
1 DIP switch SW7 selects which interfaces are in the chain. Set SW7 switch positions in
the off position to include the interface in the JTAG chain. Refer to Table 4–4 on
page 4–4 for detailed settings.
f For details on the JTAG chain, refer to the Stratix VAdvanced Systems Development
Board Reference Manual. For USB-Blaster II configuration details, refer to the On-Board
USB-Blaster II page.
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Chapter 5: Board Test System 5–5
Using the Board Test System
The GPIO FPGA1 Tab
The GPIO FPGA1 tab allows you to interact with all the general purpose user I/O
components on your board associated with FPGA1 (U29). You can read DIP switch
settings, turn LEDs on or off, and detect push button presses. This test erases FPGA2.
Figure 5–3 shows the GPIO FPGA1 tab.
Figure 5–3. The GPIO FPGA1 Tab
The following sections describe the controls on the GPIO FPGA1 tab.
User DIP Switches
The read-only User DIP switch control displays the current positions of the switches
in the user DIP switch bank (SW1). Change the switches on the board to see the
graphical display change accordingly.
User LEDs
The User LEDs control displays the current state of the user LEDs. To toggle the board
LEDs, click the 0 to 7 buttons to toggle red or green LEDs, the All button, and the
graphical representation of the LEDs.
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Using the Board Test System
Push Button Switches
The read-only Push button switches control displays the current state of the board
user push buttons. Press a push button on the board to see the graphical display
change accordingly.
The GPIO FPGA2 Tab
The GPIO FPGA2 tab allows you to interact with all the general purpose user I/O
components on your board associated with FPGA2 (U35). You can read DIP switch
settings, turn LEDs on or off, and detect push button presses. This test erases FPGA1.
Figure 5–4 shows the GPIO FPGA2 tab.
Figure 5–4. The GPIO FPGA2 Tab
The following sections describe the controls on the GPIO FPGA2 tab.
User DIP Switches
The read-only User DIP switch control displays the current positions of the switches
in the user DIP switch bank (SW3). Change the switches on the board to see the
graphical display change accordingly.
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Using the Board Test System
User LEDs
The User LEDs control displays the current state of the user LEDs. To toggle the board
LEDs, click the 0 to 7 buttons to toggle red or green LEDs, the All button, and the
graphical representation of the LEDs.
Push Button Switches
The read-only Push button switches (S8-S10) control displays the current state of the
board user push buttons. Press a push button on the board to see the graphical display
change accordingly.
The FMC/C2C Tab
The FMC/C2C tab allows you to perform loopback tests on the FMC XCVR and FMC
parallel ports, Chip-to-Chip (C2C) XCVR, C2C LVDS, and C2C single-ended
loopback. FPGA 1 is configured with a design for FMC testing and C2C testing.
FPGA2 is configured with a design for C2C testing.
1 Altera recommends loading the C2C loopback design without Nios configured to
FPGA2. Configuring the FPGAs through the BTS GUI handles this by default.
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Using the Board Test System
Figure 5–5 shows the FMC/C2C tab.
Figure 5–5. The FMC/C2C Tab
1 For factory testing, you must have an FMC loopback card installed on the FMC
connector (J8) for this test to work correctly. Altera recommends the Acquitek FMC
Loopback Test Mezzanine (part number AF101). Otherwise, set the PMA setting tab to
test internal loopback mode (serial loopback = 1).
The following sections describe the controls on the FMC/C2C tab.
Status
The Status control displays the following status information during the loopback test:
■ PLL lock—Shows the PLL locked or unlocked state.
■ Channel lock—Shows the channel locked or unlocked state. When locked, all
lanes are word aligned and channel bonded.
■ Pattern sync—Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
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Using the Board Test System
Port
The Port control allows you to specify which interface to test. The following port tests
are available:
■ FMC XCVR x10 (10.3125 Gpbs+)
■ FMC CMOS x34 (25 MHz)
■ Chip to Chip XCVR x8 (12.5 Gbps)
■ Chip to Chip LVDS x1 (1.375 Gbps)
■ Chip to Chip CMOS x6 (25 MHz)
PMA Setting
The PMA Setting button allows you to make changes to the PMA parameters that
affect the active transceiver interface. The following settings are available for analysis:
■ Serial Loopback—Routes signals between the receiver to the transmitter. Enter the
following values to enable the serial loopbacks:
0
= high speed serial transceiver signals to loopback on the board
1
= serial loopback
2
= reverse serial loopback pre-CDR
4
= reverse serial loopback post-CDR
■ VOD—Specifies the voltage output differential of the transmitter buffer.
■ Pre-emphasis tap
■ Pre—Specifies the amount of pre-emphasis on the pre-tap of the transmitter
buffer.
■ First post—Specifies the amount of pre-emphasis on the first post tap of the
transmitter buffer.
■ Second post—Specifies the amount of pre-emphasis on the second post tap of
the transmitter buffer.
■ Equalizer—Specifies the setting for the receiver equalizer.
■ DC gain—Specifies the DC portion of the receiver equalizer.
Data Type
The Data type control specifies the type of data contained in the transactions. The
following data types are available for analysis:
■ PRBS7—Selects pseudo-random 7-bit sequences.
■ PRBS15—Selects pseudo-random 15-bit sequences.
■ PRBS23—Selects pseudo-random 23-bit sequences.
■ PRBS31—Selects pseudo-random 31-bit sequences.
■ HF1—highest frequency divide-by-2 data pattern "10101010"
■ HF2—next highest frequency divide-by-6 data pattern "111000111000"
■ HF3—second lowest frequency divide-by-22 data pattern
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■ LF —lowest frequency divide by 33 data pattern
Using the Board Test System
1 Settings HF1, HF2, HF3, LF are for transmit observation only and are not
used in the receiver data detection circuitry.
Error Control
This control displays data errors detected during analysis and allows you to insert
errors:
■ Detected errors—Displays the number of data errors detected in the hardware.
■ Inserted errors—Displays the number of errors inserted into the transmit data
stream.
■ Insert Error—Inserts a one-word error into the transmit data stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
■ Clear—Resets the Detected errors and Inserted errors counters to zeros.
Start
The Start control initiates transaction performance analysis.
1 Always click Clear before Start.
Stop
The Stop control terminates transaction performance analysis.
Loopback
These controls display current transaction performance analysis information collected
since you last clicked Start:
■ TX and RX performance bars—Show the percentage of maximum theoretical data
rate that the requested transactions are able to achieve.
■ Tx (MBps) and Rx (MBps)—Show the number of bytes of data analyzed per
second.
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Using the Board Test System
The HSMC Tab
The HSMC tab allows you to perform loopback tests on HSMC ports. This test erases
FPGA1. Figure 5–6 shows the HSMC tab.
Figure 5–6. The HSMC Tab
1 You must have the loopback HSMC installed on the HSMC connector for this test to
work correctly. Otherwise, set the PMA setting tab to test internal loopback mode
(serial loopback = 1).
The following sections describe the controls on the HSMC tab.
Status
The Status control displays the following status information during the loopback test:
■ PLL lock—Shows the PLL locked or unlocked state.
■ Channel lock—Shows the channel locked or unlocked state. When locked, all
lanes are word aligned and channel bonded.
■ Pattern sync—Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
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Using the Board Test System
Port
The Port control allows you to specify which interface to test. The following port tests
are available:
■ XCVR x7 (11.3 Gbps)
■ LVDS x17 (1.375 Gbps)
■ CMOS x3 (25 MHz)
PMA Setting
The PMA Setting button allows you to make changes to the PMA parameters that
affect the active transceiver interface. The following settings are available for analysis:
■ Serial Loopback—Routes signals between the receiver to the transmitter. Enter the
following values to enable the serial loopbacks:
0
= high speed serial transceiver signals to loopback on the board
1
= serial loopback
2
= reverse serial loopback pre-CDR
4
= reverse serial loopback post-CDR
■ VOD—Specifies the voltage output differential of the transmitter buffer.
■ Pre-emphasis tap
■ Pre—Specifies the amount of pre-emphasis on the pre-tap of the transmitter
buffer.
■ First post—Specifies the amount of pre-emphasis on the first post tap of the
transmitter buffer.
■ Second post—Specifies the amount of pre-emphasis on the second post tap of
the transmitter buffer.
■ Equalizer—Specifies the setting for the receiver equalizer.
■ DC gain—Specifies the DC portion of the receiver equalizer.
Data Type
The Data type control specifies the type of data contained in the transactions. The
following data types are available for analysis:
■ PRBS7—Selects pseudo-random 7-bit sequences.
■ PRBS15—Selects pseudo-random 15-bit sequences.
■ PRBS23—Selects pseudo-random 23-bit sequences.
■ PRBS31—Selects pseudo-random 31-bit sequences.
■ HF1—highest frequency divide-by-2 data pattern "10101010"
■ HF2—next highest frequency divide-by-6 data pattern "111000111000"
■ HF3—second lowest frequency divide-by-22 data pattern
■ LF —lowest frequency divide by 33 data pattern
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The Power Monitor
1 Settings HF1, HF2, HF3, LF are for transmit observation only and are not
used in the receiver data detection circuitry.
Error Control
This control displays data errors detected during analysis and allows you to insert
errors:
■ Detected errors—Displays the number of data errors detected in the hardware.
■ Inserted errors—Displays the number of errors inserted into the transmit data
stream.
■ Insert Error—Inserts a one-word error into the transmit data stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
■ Clear—Resets the Detected errors and Inserted errors counters to zeros.
Start
The Start control initiates transaction performance analysis.
1 Always click Clear before Start.
Stop
The Stop control terminates transaction performance analysis.
Loopback
These controls display current transaction performance analysis information collected
since you last clicked Start:
■ TX and RX performance bars—Show the percentage of maximum theoretical data
rate that the requested transactions are able to achieve.
■ Tx (MBps) and Rx (MBps)—Show the number of bytes of data analyzed per
second.
The Power Monitor
The Power Monitor measures and reports current power and temperature
information for the board. To start the application, click Power Monitor in the Board
Test System application.
1 You can also run the Power Monitor as a stand-alone application. PowerMonitor.exe
resides in the
<install dir>\kits\stratixVGX_5sgxea7nf45_as\examples\board_test_system
directory. On Windows, click Start > All Programs > Altera > Stratix V Advanced
Systems Development Kit <version> > Power Monitor to start the application.
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The Power Monitor
The Power Monitor communicates with the MAX V device on the board through the
JTAG bus. A power monitor circuit attached to the MAX V device allows you to
measure the power that each Stratix V GX FPGA device is consuming. Figure 5–7
shows the Power Monitor.
Figure 5–7. The Power Monitor
The following sections describe the Power Monitor controls.
General Information
The General information controls display the following information about the
MAX V device:
■ MAX V version—Indicates the version of MAX V code currently running on the
board. The MAX V code resides in the <install
dir>\kits\stratixVGX_5sgxea7nf45_as\factory_recovery and <install
dir>\kits\stratixVGX_5sgxea7nf45_as\examples\max5 directories. Newer
revisions of this code might be available on the Stratix VAdvanced Systems
Development Kit page of the Altera website.
■ Power rail—Selects the power rail to measure. After setting the Power rail list to
the desired rail, click Reset to refresh the screen with new board readings.
1 All rails use a 0.003 ohm resistor, except S5_VCC that uses 0.001 ohms.
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Chapter 5: Board Test System 5–15
The Clock Control
f For detailed information on how power rails are shared between FPGA1
and FPGA2, see the power rail table or the power tree diagram available in
the Stratix VAdvanced Systems Development Board Reference Manual.
Temperature Information
The Temperature information controls display the following temperature readings
for the board and the FPGA on the board:
■ FPGA1—Indicates the temperature of the FPGA1 (U29) device.
■ Board—Indicates the overall board temperature.
■ FPGA2—Indicates the temperature of the FPGA2 (U35) device.
Power Information
The Power information control displays current, maximum, and minimum power
readings for the following units:
■ mAmp
Power Graph
The power graph displays the mA power consumption of your board over time. The
green line indicates the current value. The red line indicates the maximum value read
since the last reset. The yellow line indicates the minimum value read since the last
reset.
Graph Settings
The following Graph settings controls allow you to define the look and feel of the
power graph:
■ Scale select—Specifies the amount to scale the power graph. Select a smaller
number to zoom in to see finer detail. Select a larger number to zoom out to see the
entire range of recorded values.
■ Update speed—Specifies how often to refresh the graph.
Reset
This Reset control clears the graph, resets the minimum and maximum values, and
restarts the Power Monitor.
The Clock Control
The Clock Control application sets the five Si5338 programmable oscillators. Each
Si5338 devices each have four independently programmable outputs. All four outputs
are programmable between 16 KHz and 350 MHz. All four outputs can support the
higher frequencies, but they cannot be programmed for multiple frequencies above
350 MHz. If you want multiple outputs above 350 MHz, all outputs above 350 MHz
must be the same frequency, and must be frequencies from 367 MHz to 473.33 MHz or
from 550 MHz to 710 MHz.
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5–16 Chapter 5: Board Test System
The Clock Control
The Clock Control application runs as a stand-alone application. ClockControl.exe
resides in the
<install dir>\kits\stratixVGX_5sgxea7nf45_as\examples\board_test_system
directory. On Windows, click Start > All Programs > Altera > Stratix V Advanced
Systems Development Kit <version> > Clock Control to start the application.
f For more information about the Si5338 oscillator and the Stratix V GX advanced
systems board’s clocking circuitry, default frequencies, and clock input pins, refer to
the Stratix VAdvanced Systems Development Board Reference Manual.
The Clock Control communicates with the MAX V device on the board through the
JTAG bus. The Si5338 (U53, U82, U91, U95, and U100) programmable oscillators are
connected to the MAX V device through a 2-wire serial bus. Clock frequencies will
return to the default values after power cycling the board. Figure 5–8 shows the Clock
Control.
Figure 5–8. The Clock Control
The following sections describe the Clock Control controls.
Read
The read control reads the current frequency setting for the oscillator associated with
the active tab.
Default
The Default control sets the frequency for the oscillator associated with the active tab
back to its default value. This can also be accomplished by power cycling the board.
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Chapter 5: Board Test System 5–17
Configuring the FPGA Using the Quartus II Programmer
Set New Frequency
The Set New Frequency control sets the programmable oscillator frequency for the
selected clock to the value in the Frequency (MHz) fields. Frequency changes might
take several milliseconds to take effect. You might see glitches on the clock during this
time. Altera recommends resetting the FPGA logic after changing frequencies.
Configuring the FPGA Using the Quartus II Programmer
You can use the Quartus II Programmer to configure the FPGA with a specific .sof.
Before configuring the FPGA, ensure that the Quartus II Programmer and the
USB-Blaster II driver are installed on the host computer, the mini-USB cable is
connected to the Stratix V GX advanced systems board, power to the board is on, and
no other applications that use the JTAG chain are running.
To configure the Stratix V GX FPGA, perform the following steps:
1. Start the Quartus II Programmer.
2. Click Auto Detect to display the devices in the JTAG chain.
3. Click Add File and select the path to the desired .sof.
4. Turn on the Program/Configure option for the added file.
5. Click Start to download the selected file to the FPGA. Configuration is complete
when the progress bar reaches 100%.
1 Using the Quartus II programmer to configure a device on the board causes other
JTAG-based applications such as the Board Test System, the Clock Control, and the
Power Monitor to lose their connection to the board. Restart those applications after
configuration is complete.
1 If the Quartus II programing window is already open, then you power cycle the
board, you may be required to click Hardware Setup in the Quartus II Programmer
window and reselect USB-Blaster II in order to properly detect the JTAG chain.
February 2013 Altera Corporation Stratix V Advanced Systems Development Kit
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5–18 Chapter 5: Board Test System
Configuring the FPGA Using the Quartus II Programmer
Stratix V Advanced Systems Development Kit February 2013 Altera Corporation
User Guide
As you develop your own project using the Altera tools, you can program the flash
memory device so that your own design loads from flash memory into the FPGA on
power up. This appendix describes the preprogrammed contents of the common flash
interface (CFI) flash memory device on the Stratix V GX advanced systems board and
how to reprogram the user portions of the flash memory device.
The Stratix V GX advanced systems board ships with the CFI flash device
preprogrammed with a default factory FPGA configuration for running the Board
Test System demonstration.
f For more information about Altera development tools, refer to the Design Software
page of the Altera website.
CFI Flash Memory Map
Tab le A –1 shows the default memory contents of the 1-Gb CFI flash devices. The flash
device has a 16-bit data bus connected to the Max V System Controller that is used to
configure FPGA1 or FPGA2 using FPP x8.
A. Programming the Flash Memory
Device
For the FPP to function correctly, the memory map PFL option bits should not be
altered.
Table A–1. Byte Address Flash Memory Map
Block Description Size (KB) Address Range
Unused 128 0x07FE.0000 - 0x07FF.FFFF
User software 24,320 0x0716.0000 - 0x07F7.FFFF
Factory software 8,192 0x0696.0000 - 0x0715.FFFF
zipfs (html, web content) 8,192 0x0616.0000 - 0x0695.FFFF
Unused 33,152 0x0410.0000 - 0x0615.FFFF
FPGA2 Hardware 33,152 0x020A.0000 - 0x040F.FFFF
FPGA1 Hardware 33,152 0x0002.0000 - 0x0209.FFFF
PFL option bits 32 0x0001.8000 - 0x0001.FFFF
Board information 32 0x0001.0000 - 0x0001.7FFF
Ethernet option bits 32 0x0000.8000 - 0x0000.FFFF
User design reset vector 32 0x0000.0000 - 0x0000.7FFF
c Altera recommends that you do not overwrite the factory hardware and factory
software images unless you are an expert with the Altera tools.
February 2013 Altera Corporation Stratix V Advanced Systems Development Kit
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A–2 Appendix A: Programming the Flash Memory Device
Converting .sof Files to a .pof
Converting .sof Files to a .pof
To generate a programming file with different compression features, you must
convert the .sof files to a .pof. To convert the .sof files to a .pof, follow these steps:
1. On the File menu of the Quartus II Programmer, click Convert Programming
Files.
f For more information, refer to the Quartus II Programmer chapter in
volume 3 of the Quartus II Handbook.
2. For Programming file type, specify Programmer Object File (.pof) and name of
the file.
3. For Configuration device, select CFI_1Gb.
4. For Mode, select Fast Passive Parallel x8.
5. To add the configuration data, under Input files to convert, select SOF Data.
6. Click Add File and browse to the .sof files you want to add.
If you want to store the data from other .sof files in a different page, click Add SOF
page. Add the .sof files to the new page. You can use Sof Data Page_0 to configure
FPGA1 and Sof Data Page_1 to configure FPGA2. From the factory, your board
will have contents written to flash memory in Page_0.
7. Select SOF Data and click Properties to set the page number and name. Under
Address mode for selected pages, select Block with the following address ranges:
■ For Page_0, the Start Address is 0x0020000. The End Address is 0x209FFFF.
■ For Page_1, the Start Address is 0x20A0000. The End Address is 0x40FFFFF.
Table A–1 on page A–1 shows the complete CFI flash memory mapping.
8. Click OK.
9. Click Options to specify the start address to store the option bits. The start address
for this kit is 0x018000. This start address must be identical to the address you
specify when creating the PFL megafunction. Ensure that the option bits sector
does not overlap with the configuration data pages and that the start address
resides on an 8-KB boundary.
10. Click Generate to create the .pof.
Once you have the necessary .pof files, you can use the MAX V based PFL to
reprogram the flash memory.
Programming Altera CPLDs and Flash Memory
Using the Quartus II Programmer, you can program Altera CPLDs and flash memory
device, allowing you to program, verify, erase, blank-check, or examine the
configuration data page, the user data page, and the option bits sector separately,
provided the CPLD contains the PFL megafunction.
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User Guide
Appendix A: Programming the Flash Memory Device A–3
Restoring the MAX V CPLD to the Factory Settings
The Quartus II programmer erases the flash memory device if you select the .pof of
the flash memory device before programming. To prevent the Quartus II Programmer
from erasing other sectors in the flash memory device, select only the pages, .hex data,
and option bits.
To program the CPLD and the flash memory devices separately, follow these steps:
1. Open the Quartus II Programmer window.
2. Click Auto Detect.
3. Highlight the row with the 5M2210 device, click Add File. The Add Programming
File Window dialog box appears.
4. Add the targeted <install
dir>\kits\stratixVGX_5sgxea7nf45_as\examples\memory\flash\pfl_m5.pof,
and click OK.
5. Check the boxes under the Program/Configure column of the .pof.
6. Click Start to program the CPLD.
7. After the programming progress bar reaches 100%, click Auto Detect. The
programmer window shows a CFI_1Gb flash in the chain.
Alternatively, you can add the flash memory device to the programmer manually.
Right-click the CPLD pfl_m5.pof and click Attach Flash Device. In the Attach
Flash Device dialog box, select the CFI_1Gb device.
8. Right-click the necessary flash memory device density and click Change File.
9. Select the .pof generated for the flash memory device. The .pof for the flash
memory device is attached to the .pof of the CPLD. The sv_as_dk_factory.pof is
the default file loaded to flash from the factory.
10. Check the boxes under the Program/Configure column for the added .pof and
click Start to program the flash memory devices.
Restoring the MAX V CPLD to the Factory Settings
This section describes how to restore the original factory contents to the MAX V
CPLD on the advanced systems board. Make sure you have the Nios II EDS installed,
and perform the following instructions:
1. Set the board switches to the factory default settings described in “Factory Default
Switch and Jumper Settings” on page 4–2.
2. Launch the Quartus II Programmer.
3. Click Auto Detect.
4. Click Add File and select <install
dir>\kits\stratixVGX_5sgxea7nf45_as\factory_recovery\max5.pof.
5. Turn on the Program/Configure option for the added file.
6. Click Start to download the selected configuration file to the MAX V CPLD.
Configuration is complete when the progress bar reaches 100%.
February 2013 Altera Corporation Stratix V Advanced Systems Development Kit
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A–4 Appendix A: Programming the Flash Memory Device
Restoring the MAX V CPLD to the Factory Settings
f To ensure that you have the most up-to-date factory restore files and information
about this product, refer to the Stratix VAdvanced Systems Development Kit page of
the Altera website.
Stratix V Advanced Systems Development Kit February 2013 Altera Corporation
User Guide
This chapter provides additional information about the document and Altera.
Document Revision History
The following table shows the revision history for this document.
Date Version Changes
February 2013 1.0 Initial release.
How to Contact Altera
To locate the most up-to-date information about Altera products, refer to the
following table.
Additional Information
Contact
Technical support Website www.altera.com/support
Technical training
Product literature Website www.altera.com/literature
Nontechnical support (general) Email nacomp@altera.com
Note to Table:
(1) You can also contact your local Altera sales office or sales representative.
(1)
(software licensing) Email authorization@altera.com
Contact Method Address
Website www.altera.com/training
Email custrain@altera.com
Typographic Conventions
The following table shows the typographic conventions this document uses.
Visual Cue Meaning
Bold Type with Initial Capital
Letters
bold type
Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.
italic type
Initial Capital Letters
Indicate command names, dialog box titles, dialog box options, and other GUI
labels. For example, Save As dialog box. For GUI elements, capitalization matches
the GUI.
Indicates directory names, project names, disk drive names, file names, file name
extensions, software utility names, and GUI labels. For example, \qdesigns
directory, D: drive, and chiptrip.gdf file.
Indicates variables. For example, n + 1.
Variable names are enclosed in angle brackets (< >). For example, <file name> and
<project name>.pof file.
Indicate keyboard keys and menu names. For example, the Delete key and the
Options menu.
February 2013 Altera Corporation Stratix V Advanced Systems Development Kit
User Guide
Info–2 Additional Information
Typographic Conventions
Visual Cue Meaning
“Subheading Title”
Quotation marks indicate references to sections in a document and titles of
Quartus II Help topics. For example, “Typographic Conventions.”
Indicates signal, port, register, bit, block, and primitive names. For example,
tdi
, and
input
. The suffix n denotes an active-low signal. For example,
resetn
data1
.
,
Indicates command line commands and anything that must be typed exactly as it
Courier type
appears. For example,
c:\qdesigns\tutorial\chiptrip.gdf
.
Also indicates sections of an actual file, such as a Report File, references to parts of
files (for example, the AHDL keyword
TRI
example,
).
SUBDESIGN
), and logic function names (for
r An angled arrow instructs you to press the Enter key.
1., 2., 3., and
a., b., c., and so on
■ ■ ■ Bullets indicate a list of items when the sequence of the items is not important.
Numbered steps indicate a list of items when the sequence of the items is important,
such as the steps listed in a procedure.
1 The hand points to information that requires special attention.
h The question mark directs you to a software help system with related information.
f The feet direct you to another document or website with related information.
m The multimedia icon directs you to a related multimedia presentation.
c
w
A caution calls attention to a condition or possible situation that can damage or
destroy the product or your work.
A warning calls attention to a condition or possible situation that can cause you
injury.
The envelope links to the Email Subscription Management Center page of the Altera
website, where you can sign up to receive update notifications for Altera documents.
The feedback icon allows you to submit feedback to Altera about the document.
Methods for collecting feedback vary as appropriate for each document.
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