Altera Stratix IV GX FPGA Development Board User Manual

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Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

Stratix IV GX FPGA Development Board, 530 Edition

Reference Manual

101 Innovation Drive San Jose, CA 95134

www.altera.com

MNL-01060-1.0

© 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 1. Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Chapter 2. Board Components

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Featured Device: Stratix IV GX Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Migration Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7

MAX II CPLD EPM2210 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7

Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12

FPGA Programming over Embedded USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12

FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Board Settings DIP switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

JTAG Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

PCI Express Control DIP switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

Reset Configuration Push-Button Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

Rotary Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

Stratix IV GX FPGA Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Stratix IV GX FPGA Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

User-Defined Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

User-Defined DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

General User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

HSMC User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29

LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29

Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31

10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

High-Speed Mezzanine Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

HDMI Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–43

SDI Video Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48

DDR3 Bottom Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48

DDR3 Top Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–52

QDRII+ Top Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–53

QDRII+ Top Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–56

SSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–58

Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–61

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

iv Contents

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–63

Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–64

Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–65

Temperature Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–66

Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–67

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

This document describes the hardware features of the Stratix® IV GX FPGA development board, including the detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board.

General Description

The Stratix IV GX FPGA Development Board, 530 Edition provides a hardware platform for developing and prototyping low-power, high-performance, and logicintensive designs. The board provides a wide range of peripherals and memory interfaces to facilitate the development of the Stratix IV GX FPGA designs.

Two High-Speed Mezzanine Card (HSMC) connectors are available to add additional functionality via a variety of HSMC cards available from both Altera and various partners.

1. Overview

f To see a list of the latest HSMC cards available or to download a copy of the HSMC

specification, refer to the Development Board Daughtercards page of the Altera website.

Design advancements and innovations, such as the 8.5 Gbps transceiver modules, the PCI Express hard IP implementation, and programmable power technology ensure that designs implemented in the Stratix IV GX FPGAs operate faster, with lower power than in previous FPGA families.

f For more information on the following topics, refer to the respective documents:

■ Stratix IV device family, refer to the Stratix IV Device Handbook.

■ PCI Express MegaCore function, refer to the PCI Express Compiler User Guide.

■ Altera Video and Image Processing Suite MegaCore functions, refer to the Vid eo

and Image Processing Suite User Guide.

■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.

Board Component Blocks

The board features the following major component blocks:

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

1–2 Chapter 1: Overview

Board Component Blocks

■ EP4SGX530KH40 FPGA in the 1517-pin FineLine BGA Package

■ 531,200 LEs

■ 212,480 adaptive logic modules (ALMs)

■ 27,376 Kbit on-die memory

■ 24 transceivers (8.5 Gbps)

■ 2 PCI Express hard IP blocks

■ 8 phase locked loops (PLLs)

■ 1,024 18x18 multipliers

■ 0.9-V core power

■ MAX

II CPLD EPM2210 System Controller in the 256-pin FineLine BGA Package

■ 1.8-V core power

■ FPGA Configuration Circuitry

■ MAX

II CPLD EPM2210 System Controller and Flash Fast Passive Parallel

(FPP) configuration

■ On-Board USB-Blaster

for use with the Quartus® II Programmer

■ On-Board Clocking Circuitry

■ 50-MHz/125-MHz/155.52-MHz/156.25-MHz fixed-frequency oscillators

■ 100-MHz oscillator, programmable to any frequency between 20–810 MHz

■ 148.5-MHz voltage-controlled crystal oscillator (VCXO)

■ SMA connectors for external clock input

■ SMA connector for clock output

■ Memory devices

■ 512-Mbyte DDR3 SDRAM with a 64-bit data bus (bottom port)

■ 128-Mbyte DDR3 SDRAM with a 16-bit data bus (top port)

■ Two 4-Mbyte QDRII+ SRAMs with 18-bit data buses

■ 2-Mbyte SSRAM with 36-bit data bus

■ 64-Mbyte synchronous flash

■ General User I/O

■ 16 user LEDs

■ Two-line character LCD display

■ One configuration done LED

■ One transmit/receive LED (TX/RX) per HSMC interface

■ Four PCI Express LEDs

■ Four Ethernet LEDs

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 1: Overview 1–3

Board Component Blocks

■ Push-Button Switches

■ One user reset (CPU Reset)

■ One configuration reset

■ Three general user push-button switches

■ DIP Switches

■ Eight user DIP switches

■ Eight MAX

II control DIP switches

■ Power

■ 16-V – 20-V DC input

■ PCI Express edge connector power

■ On-Board power measurement circuitry

■ Mechanical

■ PCI Express half-length full-height (6.6” x 4.376”)

■ PCI Express chassis or bench-top operation

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

1–4 Chapter 1: Overview

Development Board Block Diagram

Figure 1–1 shows the block diagram of the Stratix IV GX FPGA Development Board,

530 Edition.

Figure 1–1. Stratix IV GX FPGA Development Board, 530 Edition Block Diagram

USB

2.0

Embedded

Blaster

512 Mbytes

DDR3 BOT

REFCLK

SMA IN

TRIG

SMA OUT

GigE

PHY

HDMI

SDI

TX/TX

JTAG Chain

x64

x1 (LVPECL)

x24

XCVR x1

50 MHz, 100 MHz,

125 MHz, 148 MHz,

155 MHz, 156 MHz

Oscillators

Port A

x80

CLKIN x3

x80

XCVR x8

CLKOUT x3

EP4SGX530KH40

XCVR x8

x8 Edge

Port B

CLKIN x3

CLKOUT x3

x8 Config

CPLD

ADDR

XCVR x6

x32

x16

XCVR x1

x16

64 Mbytes

FLASH

128 Mbytes

DDR3 TOP

4 Mbytes

QDRII+ TOP 0

4 Mbytes

QDRII+ TOP 1

XCVR

SMA OUT

Buttons

Switches

LED

2 Mbytes

SSRAM

Handling the Board

When handling the board, it is important to observe the following static discharge precaution:

c Without proper anti-static handling, the board can be damaged. Therefore, use

anti-static handling precautions when touching the board.

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Introduction

1 A complete set of schematics, a physical layout database, and GERBER files for the

f For information about powering up the board and installing the demo software, refer

2. Board Components

This chapter introduces all the important components on the Stratix IV GX FPGA Development Board, 530 Edition. Figure 2–1 illustrates major component locations and Table 2–1 provides a brief description of all features of the board.

development board reside in the Stratix IV GX development kit documents directory.

to the Stratix IV GX FPGA Development Kit, 530 Edition User Guide.

This chapter consists of the following sections:

■ “Board Overview”

■ “Featured Device: Stratix IV GX Device” on page 2–5

■ “MAX II CPLD EPM2210 System Controller” on page 2–7

■ “Configuration, Status, and Setup Elements” on page 2–12

■ “Clock Circuitry” on page 2–21

■ “General User Input/Output” on page 2–26

■ “Components and Interfaces” on page 2–31

■ “Memory” on page 2–48

■ “Power Supply” on page 2–63

■ “Statement of China-RoHS Compliance” on page 2–67

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–2 Chapter 2: Board Components

Board Overview

This section provides an overview of the Stratix IV GX FPGA Development Board, 530 Edition, including an annotated board image and component descriptions. Figure 2–1 provides an overview of the development board features.

Figure 2–1. Overview of the Stratix IV GX FPGA Development Board, 530 Edition Features

User DIP Switch (SW3)

HSMC Port A (J1)

Reset Configuration

Push-Button

Switch (S1)

Configuration Done

DDR3 x64 Bottom Port

LED (D5)

(U5, U12, U18, U24)

SDI Video Port

(J3, J5)

Gigabit Ethernet Port

(J6)

USB Type-B

Connector (J7)

Stratix IV GX FPGA (U13)

CPU Reset Push-button Switch (S2)

EP4SGX530KH40C2N

Power Monitor Rotary Switch (SW2)

General User Push-button Switches (S3, S4, S5)

HSMC Port B (J2)

Power Switch (SW1)

DC Input Jack (J4)

QDRII+ x18/x18 Top Port 1 (U7)

DDR3 x16 Top Port (U14)

QDRII+ x18/x18 Top Port 0 (U22)

JTAG Connector (J8)

HDMI Video Port (J11)

Flash x16 Memory

(U32)

SSRAM x36 Memory (U30)

Transceiver TX SMA Connectors

Fan Power Header

PCI Express Edge Connector

(J17)

Character LCD (J16)

Max II CPLD EPM2210 System Controller (U31)

Clock Input SMA Connector (J14, J15)

Clock Output SMA Connector (J9)

Tab le 2– 1 describes the components and lists their corresponding board references.

Table 2–1. Stratix IV GX FPGA Development Board, 530 Edition Components (Part 1 of 3)

Board Reference Type Description

Featured Devices

U13 FPGA EP4SGX530KH40, 1517-pin BGA.

U31 CPLD EPM2210GF256, 256-pin BGA.

Configuration, Status, and Setup Elements

SW6 JTAG DIP switch Enables and disables devices in the JTAG chain.

II CPLD EPM2210 System Controller functions such

SW4 Board Settings DIP switch

Controls the Max as clock enable, power and temperature monitor, as well as voltage settings for transceivers and SMA clock input control.

J8 JTAG connector Disables embedded blaster (for use with external USB-Blasters).

SW5 PCI Express DIP switch

Controls the PCI Express lane width by connecting together on the PCI Express edge connector.

prsnt

pins

D5 Configuration done LED Illuminates when the FPGA is configured.

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–3

Board Overview

Table 2–1. Stratix IV GX FPGA Development Board, 530 Edition Components (Part 2 of 3)

Board Reference Type Description

D26 Load LED Illuminates during embedded USB-Blaster data transfers.

D27 Error LED Illuminates when the FPGA configuration from flash fails.

D24 Power LED Illuminates when 12-V power is present.

D32, D33, D34, D35

Ethernet LEDs Shows the connection speed as well as transmit or receive activity.

D3, D4 HSMC port A LEDs You can configure these LEDs to indicate transmit or receive activity.

D1 HSMC port A Present LED Illuminates when a daughtercard is plugged into the HSMC port A.

D14, D15 HSMC port B LEDs You can configure these LEDs to indicate transmit or receive activity.

D2 HSMC port B Present LED Illuminates when a daughtercard is plugged into the HSMC port B.

D30 SDI mute LED Illuminates when the SDI receiver is muted.

D25 PCI Express Gen 2 LED

D37, D38, D39 PCI Express Link LEDs

You can configure this LED to illuminate when PCI Express is in Gen 2 mode.

You can configure these LEDs to display the PCI Express link width (x1, x4, x8).

Clock Circuitry

X1 125 M oscillator

125.000-MHz crystal oscillator for Gigabit Ethernet, Serial RapidIO™ (SRIO), or PCI Express.

X2 156 M oscillator 156.250-MHz crystal oscillator for 10 Gigabit Ethernet or XAUI.

X3 148 M oscillator 148.500-MHz voltage controlled crystal oscillator for SDI Video.

100.000-MHz (programmable to any frequency between 20–810 MHz)

X6 100 M oscillator

crystal oscillator for PCI Express or general use such as memories. Multiplex with CLKIN_SMA_P based on CLK_SEL switch value.

X7 155 M oscillator 155.520-MHz crystal oscillator for SONET.

X8 50 M oscillator 50.000-MHz crystal oscillator for general purpose logic.

J15, J14 Clock input SMAs

Drives LVPECL-compatible clock inputs into the U50 clock multiplexer buffer.

J9 Clock output SMA Drives out 2.5-V CMOS clock outputs from the FPGA.

General User Input and Output

D 6 -D 1 3 D16-D23

User LEDs 16 user LEDs. Illuminates when driven low.

SW3 User DIP switch Octal user DIP switches. When the switch is ON, a logic 0 is selected.

S2 CPU reset push-button switch

S3, S4, S5

Reset configuration push-button switch

General user push-button switches

Press to reconfigure the FPGA from the flash memory.

Press to reset the Max II CPLD EPM2210 System Controller and FPGA logic.

Three user push-button switches. Driven low when pressed.

Selects the power rail being measured. It also selects the FPGA image

SW2 Power monitor rotary switch

to load on power-up; 0 selects factory image and 1 selects user-defined image.

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–4 Chapter 2: Board Components

Board Overview

Table 2–1. Stratix IV GX FPGA Development Board, 530 Edition Components (Part 3 of 3)

Board Reference Type Description

Memory Devices

U5, U12, U18, U24

DDR3 x64 bottom port A single 64-bit 512 Mbyte memory port.

U14 DDR3 x16 top port Independent 16-bit 128 Mbyte memory port.

U22 QDRII+ x18/x18 top port 0 18-bit read and 18-bit write 4 Mbyte SRAM port.

U7 QDRII+ x18/x18 top port 1 Second 18-bit read and 18-bit write 4 Mbyte SRAM port.

U30 SSRAM x36 memory

U32 Flash x16 memory

Standard synchronous RAM which makes a 36-bit 2 Mbyte SRAM port.

Synchronous burst mode flash device which provides a 16-bit 64 Mbyte non-volatile memory port.

Communication Ports

J17 PCI Express edge connector

J1 HSMC port A

J2 HSMC port B

J7 USB Type-B connector

Made of gold-plated edge fingers for up to ×8 signaling in either Gen1 or Gen2 mode.

Provides eight transceiver channels and 84 CMOS or 17 LVDS channels per the HSMC specification.

Provides six transceiver channels and 84 CMOS or 17 LVDS channels per the HSMC specification.

Embedded USB-Blaster JTAG for programming the FPGA via a type-B USB cable.

RJ-45 connector which provides a 10/100/1000 Ethernet connection

J6 Gigabit Ethernet port

via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed Ethernet MegaCore function in SGMII mode.

Video and Display Ports

J11 HDMI video port

19-pin HDMI connector which provides a HDMI video output of up to 1080i through an AD9889B PHY.

Two 75-Ω system management bus (SMB) connectors which provide a

J3, J5 SDI video port

full-duplex SDI interface through a LMH0302 driver and LMH0344 cable equalizer.

J16 Character LCD

Connector which interfaces to the provided 16 character × 2 line LCD module along with standoffs S1 and S2.

Power Supply

J17 PCI Express edge connector

Interfaces to a PCI Express root port such as an appropriate PC motherboard.

J4 DC input jack Accepts a 14-V – 20-V DC power supply.

SW1 Power switch

Switch to power on or off the board when power is supplied from the DC input jack.

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–5

Featured Device: Stratix IV GX Device

The Stratix IV GX FPGA Development Board, 530 Edition features the Stratix IV GX EP4SGX530KH40 device (U13) in a 1517-pin FineLine BGA package.

f For more information about the Stratix IV device family, refer to the Stratix IV Device

Handbook.

Tab le 2– 2 describes the features of the Stratix IV GX EP4SGX530KH40 device.

Table 2–2. Stratix IV GX Device EP4SGX530KH40 Features

ALMs

212,480 531,200 1,280 64 10,624 27,376 1,024 8 24, 12

Equivalent

LEs

M9K RAM

Blocks

M144K Blocks

MLAB

Blocks

Tot al

RAM

Kbits

18-bit × 18-bit

Multipliers

PLLs

Transceivers

(8.5 Gbps,

3.2 Gbps)

Tab le 2– 3 lists the Stratix IV GX component reference and manufacturing

information.

Table 2–3. Stratix IV GX Device Component Reference and Manufacturing Information

Board Reference Description Manufacturer

U13

FPGA, Stratix IV GX F1517,

531K LEs, leadfree

Corporation EP4SGX530KH40C2N www.altera.com

Altera

Manufacturing

Part Number

Package

Type

1517-pin

FineLine BGA

Manufacturer

Website

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–6 Chapter 2: Board Components

Bank 8A 40

Bank 8B 24

Bank 8C 32

Bank 7C 32

Bank 6A 48

Bank 6C

EP4SGX230 EP4SGX290 EP4SGX360 EP4SGX530

Bank Name

Number of I/Os

Bank 5C 40

Bank 5A

Bank 1A

Bank 1C

Bank 2C

Bank 2A 48

Bank 7B 24

Bank 7A 40

Bank Name

Number of I/Os

Bank 3A40

Bank 3B24

Bank 3C32

Bank 4C32

Bank 4B24

Bank 4A40

Bank

GXBL2

Bank

GXBL1

Bank

GXBL0

Bank

GXBR2

Bank

GXBR1

Bank

GXBR0

*Number of Transceiver

Channel

Featured Device: Stratix IV GX Device

I/O Resources

Figure 2–2 shows the bank organization and I/O count for the EP4SGX230 device in

the 1517-pin FineLine BGA package.

Figure 2–2. EP4SGX530KH40 Device I/O Bank Diagram

Tab le 2– 4 lists the Stratix IV GX device pin count and usage by function on the

development board.

Table 2–4. Stratix IV GX Device Pin Count and Usage (Part 1 of 2)

Function I/O Standard I/O Count Special Pins

DDR3 ×16 Top Port 1.5-V SSTL 49 2 Diff ×8 DQS

DDR3 ×64 Bottom Port 1.5-V SSTL 117 8 Diff ×8 DQS

QDRII+ Top Port 0 1.5-V HSTL 66 1 Diff ×18 DQS

QDRII+ Top Port 1 1.5-V HSTL 66 1 Diff ×18 DQS

Flash, SRAM, MAX FSM Bus 2.5-V CMOS 78 —

PCI Express ×8 2.5-V CMOS + XCVR 38 1 REFCLK, 8 XCVR

HSMC Port A 2.5-V CMOS + LVDS + XCVR 116 8 XCVR, 17 LVDS, 5 Clock Inputs

HSMC Port B 2.5-V CMOS + LVDS + XCVR 116 6 XCVR, 17 LVDS, 5 Clock Inputs

Gigabit Ethernet 2.5-V CMOS + LVDS 8 1 LVDS

HDMI Video 2.5-V CMOS 39 —

SDI Video XCVR 7 1 XCVR

Buttons 2.5-V CMOS 4 1 DEV_CLRn

Switches 2.5-V CMOS 8 —

LCD 2.5-V CMOS 11 —

LEDs 2.5-V CMOS 24 —

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–7

MAX II CPLD EPM2210 System Controller

Table 2–4. Stratix IV GX Device Pin Count and Usage (Part 2 of 2)

Function I/O Standard I/O Count Special Pins

Clocks or Oscillators 2.5-V CMOS + LVDS 11 4 REFCLK

Power or Temperature Sense 2.5-V CMOS10 10 1 tempdiode_p, 1 tempdiode_n

Device I/O Total:

768

Migration Support

Although the target FPGA for this development board is the EP4SGX530KH40 device, the board supports migration to the smallest Stratix IV GX device available in the F1517 package, the EP4SGX230KF40.

Tab le 2– 5 describes the features of the Stratix IV GX EP4SGX230KF40 device.

Table 2–5. Stratix IV GX Device EP4SGX230KF40 Features

M9K

RAM

Blocks

M144K

Blocks

MLAB

Blocks

ALMs

Equivalent

LEs

91,200 228,000 1,235 22 4,560 17,133 1,288 8 24, 12

The specific I/O resources available in the Stratix IV GX EP4SGX230KF40 device are the same for the Stratix IV GX EP4SGX530KH40 device.

f For information about the Stratix IV GX EP4SGX230KF40 device development board,

refer to the Stratix IV GX FPGA Development Board, Reference Manual.

Total RAM

Kbits

18-bit × 18-bit

Multipliers

PLLs

Transceivers

(8.5 Gbps,

3.2 Gbps)

Package

Type

1517-pin

Fineline BGA

MAX II CPLD EPM2210 System Controller

The board utilizes the EPM2210 System Controller, an Altera MAX II CPLD, for the following purposes:

■ FPGA configuration from flash memory

■ Power consumption monitoring

■ Temp er a ture m on it or in g

■ Fan control

■ Virtual JTAG interface for PC-based power and temperature GUI

■ Control registers for clocks

■ Control registers for Remote System Update

■ Control registers for SDI, SRAM, and fan speed.

■ Register with CPLD design revision and board information (read-only)

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–8 Chapter 2: Board Components

MAX1619

Controller

Information

EMB

Blaster

MAX II Device

Si570

Controller

SLD-HUB

PFL

FSM BUS

Power

Measure

Results

Virtual-JTAG

Temperature

Measure

Results

FPGA

LTC2418

Controller

FLASH

Decoder

Encoder

GPIO

JTAG Control

SRAM

Control

Fast Configuration

Downloader

Si570

Programmable

Oscillator

MAX II CPLD EPM2210 System Controller

Figure 2–3 illustrates the MAX II CPLD EPM2210 System Controller's functionality

and external circuit connections as a block diagram.

Figure 2–3. MAX II CPLD EPM2210 System Controller Block Diagram

Tab le 2– 6 lists the I/O signals present on the MAX

Controller. The signal names and functions are relative to the MAX

II CPLD EPM2210 System

II device (U30).

Table 2–6. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 1 of 4)

Schematic Signal

Name

FSM_A25

FSM_A24

FSM_A23

FSM_A22

FSM_A21

FSM_A20

FSM_A19

FSM_A18

FSM_A17

FSM_A16

FSM_A15

FSM_A14

FSM_A13

FSM_A12

FSM_A11

I/O Standard

2.5-V D5 AP30 FSM bus address

2.5-V B1 AN30 FSM bus address

2.5-V D4 AL31 FSM bus address

2.5-V B9 AK31 FSM bus address

2.5-V D9 AR32 FSM bus address

2.5-V A10 AP32 FSM bus address

2.5-V C9 AH29 FSM bus address

2.5-V B10 AG29 FSM bus address

2.5-V A11 AR35 FSM bus address

2.5-V E10 AP35 FSM bus address

2.5-V B11 AL32 FSM bus address

2.5-V D10 AK32 FSM bus address

2.5-V A12 AU33 FSM bus address

2.5-V C10 AT33 FSM bus address

2.5-V B12 AH30 FSM bus address

EPM2210

Pin Number

EP4SGX230

Pin Number

Description

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–9

MAX II CPLD EPM2210 System Controller

Table 2–6. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 2 of 4)

Schematic Signal

Name

FSM_A10

FSM_A9

FSM_A8

FSM_A7

FSM_A6

FSM_A5

FSM_A4

FSM_A3

FSM_A2

FSM_A1

FSM_A0

FSM_D31

FSM_D30

FSM_D29

FSM_D28

FSM_D27

FSM_D26

FSM_D25

FSM_D24

FSM_D23

FSM_D22

FSM_D21

FSM_D20

FSM_D19

FSM_D18

FSM_D17

FSM_D16

FSM_D15

FSM_D14

FSM_D13

FSM_D12

FSM_D11

FSM_D10

FSM_D9

FSM_D8

FSM_D7

FSM_D6

FSM_D5

FSM_D4

I/O Standard

EPM2210

Pin Number

EP4SGX230

Pin Number

2.5-V E11 AJ31 FSM bus address

2.5-V A13 AR34 FSM bus address

2.5-V D11 AT34 FSM bus address

2.5-V B13 AE27 FSM bus address

2.5-V C11 AD27 FSM bus address

2.5-V B14 AP34 FSM bus address

2.5-V D12 AN33 FSM bus address

2.5-V A15 AD26 FSM bus address

2.5-V C12 AC26 FSM bus address

2.5-V B16 AP33 FSM bus address

2.5-V C13 AN32 FSM bus address

2.5-V T13 T28 FSM bus data

2.5-V N11 R28 FSM bus data

2.5-V R12 F32 FSM bus data

2.5-V M11 E32 FSM bus data

2.5-V T12 L31 FSM bus data

2.5-V P10 K31 FSM bus data

2.5-V R11 F31 FSM bus data

2.5-V N10 E31 FSM bus data

2.5-V T11 N29 FSM bus data

2.5-V M10 M29 FSM bus data

2.5-V T10 H31 FSM bus data

2.5-V P9 G31 FSM bus data

2.5-V R9 N30 FSM bus data

2.5-V T9 M30 FSM bus data

2.5-V T8 D33 FSM bus data

2.5-V N9 C33 FSM bus data

2.5-V C7 N31 FSM bus data

2.5-V B5 M31 FSM bus data

2.5-V D7 C32 FSM bus data

2.5-V A5 B32 FSM bus data

2.5-V E7 J32 FSM bus data

2.5-V B6 H32 FSM bus data

2.5-V A6 D35 FSM bus data

2.5-V C8 C35 FSM bus data

2.5-V B7 N28 FSM bus data

2.5-V D8 M28 FSM bus data

2.5-V A7 D31 FSM bus data

2.5-V E8 C31 FSM bus data

Description

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–10 Chapter 2: Board Components

MAX II CPLD EPM2210 System Controller

Table 2–6. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 3 of 4)

Schematic Signal

Name

FSM_D3

FSM_D2

FSM_D1

FSM_D0

MAX2_CLK

MAX2_WEn

MAX2_CSn

MAX2_OEn

MAX2_BEn3

MAX2_BEn2

MAX2_BEn1

MAX2_BEn0

FLASH_CLK

FLASH_WEn

FLASH_CEn

FLASH_OEn

FLASH_RDYBSYn

FLASH_RESETn

FLASH_ADVn

FPGA_CONFIG_D7

FPGA_CONFIG_D6

FPGA_CONFIG_D5

FPGA_CONFIG_D4

FPGA_CONFIG_D3

FPGA_CONFIG_D2

FPGA_CONFIG_D1

FPGA_CONFIG_D0

FPGA_DCLK

FPGA_nSTATUS

FPGA_nCONFIG

FPGA_CONF_DONE

SENSE_SCK

SENSE_SDI

SENSE_SDO

SENSE_CS0n

SENSE_CS1n

SENSE_ADN_F0

SENSE_SMB_CLK

SENSE_SMB_DATA

I/O Standard

EPM2210

Pin Number

EP4SGX230

Pin Number

Description

2.5-V B8 K30 FSM bus data

2.5-V A8 J30 FSM bus data

2.5-V A9 D34 FSM bus data

2.5-V E9 C34 FSM bus data

2.5-V E1 K32 FSM bus MAX2 clock

2.5-V F4 T27 FSM bus MAX2 write enable

2.5-V E2 E34 FSM bus MAX2 chip select

2.5-V F3 J33 FSM bus MAX2 output enable

2.5-V F1 R27 FSM bus MAX2 byte enable 3

2.5-V F6 P29 FSM bus MAX2 byte enable 2

2.5-V F2 F34 FSM bus MAX2 byte enable 1

2.5-V F5 H34 FSM bus MAX2 byte enable 0

2.5-V C6 AF26 FSM bus flash clock

2.5-V A4 AT31 FSM bus flash write enable

2.5-V E6 AU31 FSM bus flash chip enable

2.5-V B4 AG27 FSM bus flash output enable

2.5-V D6 AT32 FSM bus flash ready

2.5-V C4 AL30 FSM bus flash reset

2.5-V B3 AN31 FSM bus flash address valid

2.5-V D1 R34 FPGA configuration data

2.5-V E5 R35 FPGA configuration data

2.5-V D2 W26 FPGA configuration data

2.5-V E4 V27 FPGA configuration data

2.5-V C3 P34 FPGA configuration data

2.5-V E3 N35 FPGA configuration data

2.5-V C2 W29 FPGA configuration data

2.5-V D3 W30 FPGA configuration data

2.5-V H4 AR11 FPGA configuration clock

2.5-V H3 AW35 FPGA configuration ready

2.5-V T2 AW36 FPGA configuration active

2.5-V J1 AV35 FPGA configuration done

2.5-V L5 AE28 Power monitor SPI clock

2.5-V M3 J35 Power monitor SPI data in

2.5-V L4 V28 Power monitor SPI data out

2.5-V N1 AB31 Power monitor 0 chip select

2.5-V L3 H35 Power monitor 1 chip select

2.5-V N2 G35 Power monitor frequency

2.5-V R1 W34 Temperature monitor SMB clock

2.5-V R4 AH32 Temperature monitor SMB data

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–11

MAX II CPLD EPM2210 System Controller

Table 2–6. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 4 of 4)

Schematic Signal

Name

OVERTEMPn

ALERTn

PHASE_0

PHASE_90

PHASE_135

PHASE_270

MAX_ERROR

MAX_LOAD

MAX_CONF_DONEn

USB_LED

HSMA_PRSNTn

HSMB_PRSNTn

MAX_DIP

USB_DISABLEn

LCD_PWRMON

FAN_FORCE_ON

CLK_SEL

CLK_ENABLE

PGM3

PGM2

PGM1

PGM0

RESET_CONFIGn

CPU_RESETn

SRAM_MODE

SRAM_ZZ

CLK50_EN

CLK100_EN

CLK100_SDA

CLK100_SCL

CLK125_EN

CLK148_EN

CLK155_EN

CLK156_EN

CLKIN_50

CLK_CONFIG

I/O Standard

EPM2210

Pin Number

EP4SGX230

Pin Number

Description

2.5-V P5 — Temperature monitor over-temperature indicator

2.5-V M2 — Temperature monitor alert

2.5-V T6 — Power clock 0 degrees

2.5-V R7 — Power clock 90 degrees

2.5-V P8 — Power clock 135 degrees

2.5-V T7 — Power clock 270 degrees

2.5-V G3 — FPGA configuration error LED

2.5-V G2 — FPGA configuration active LED

2.5-V E15 — FPGA configuration done LED

2.5-V F12 — Embedded USB-Blaster active

2.5-V J16 — HSMC port A present

2.5-V J13 — HSMC port B present

2.5-V F15 — DIP-reserved

2.5-V G14 — DIP-embedded USB-Blaster disable

2.5-V R5 — DIP-MAX2 LCD drive enable

2.5-V P7 — DIP-force fan on switch

2.5-V T5 — DIP-clock select SMA or oscillator

2.5-V N7 — DIP-clock oscillator enable

2.5-V J3 — Rotary switch input

2.5-V K1 — Rotary switch input

2.5-V J4 — Rotary switch input

2.5-V J2 — Rotary switch input

2.5-V K2 — Force FPGA configuration push-button switch

2.5-V M9 V34 Reset push-button switch

2.5-V P4 — SRAM mode

2.5-V L14 — SRAM sleep mode

2.5-V G12 — 50 MHz oscillator enable

2.5-V G16 — 100 MHz oscillator enable

2.5-V A2 — 100 MHz programming data

2.5-V C15 — 100 MHz programming clock

2.5-V H16 — 125 MHz oscillator enable

2.5-V H13 — 148 MHz oscillator enable

2.5-V H15 — 155 MHz oscillator enable

2.5-V H14 — 156 MHz oscillator enable

2.5-V J5 AC34 50 MHz clock input

2.5-V J12 — 125 MHz configuration clock

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–12 Chapter 2: Board Components

Configuration, Status, and Setup Elements

Tab le 2 –7 lists the MAX II CPLD EPM2210 System Controller component reference

and manufacturing information.

Table 2–7. MAX II CPLD EPM2210 System Controller Component Reference and Manufacturing Information

Board Reference Description Manufacturer

U30

IC - MAX II CPLD EPM2210 256FBGA -3 LF 1.8V VCCINT

Altera

Corporation EPM2210GF256C3N www.altera.com

Configuration, Status, and Setup Elements

This section describes the board's configuration, status, and setup elements.

Configuration

This section describes the FPGA, flash memory, and MAX II CPLD EPM2210 System Controller device programming methods supported by the Stratix IV GX FPGA Development Board, 530 Edition. The Stratix IV GX FPGA Development Board, 530 Edition supports three configuration methods:

■ Embedded USB-Blaster is the default method for configuring the FPGA at any

time using the Quartus II Programmer in JTAG mode with the supplied USB cable.

■ Flash memory download is used for configuring the FPGA using stored images

from the flash memory on either power-up or pressing the reset configuration push-button switch (S1).

■ External USB-Blaster for configuring the FPGA using the external USB-Blaster.

Manufacturing

Part Number

Manufacturer

Website

FPGA Programming over Embedded USB-Blaster

The USB-Blaster is implemented using a type-B USB connector (J7), a FTDI USB 2.0 PHY device (U39), and an Altera MAX II CPLD (U30). This allows the configuration of the FPGA using a USB cable directly connected between the USB port on the board (J7) and a USB port of a PC running the Quartus II software. The JTAG chain is normally mastered by the embedded USB-Blaster found in the MAX EPM2210 System Controller.

II CPLD

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–13

Embedded

Blaster

GPIO

TCK

4SGX230

FPGA

Analog Switch

EPM2210

System

Controller

HSMC Port A

HSMC Port B

GPIO

TMS

GPIO

TDO

GPIO

TDI

JTAG Master

GPIO

DISABLE

JTAG Master/Slave

Installed

HSMC

Card

Installed

HSMC

Card

TCK

TMS

TDI

TDO

TCK

TMS

TDI

TDO

TCK

TMS

TDI

TDO

TCK

TMS

TDI

TDO

JTAG Slave

Analog Switch

EPM2210_JTAG_EN

HSMA_JTAG_EN

HSMB_JTAG_EN

ALWAYS

ENABLED

(in chain)

SW6.1

SW6.2

SW6.3

SW4.2

10-pin

JTAG Header

Flash

Memory

(on install)

PCI Express

Edge

Connector

JTAG Master/Slave

PCI Express

Motherboard

TCK

TMS

TDI

TDO

Analog Switch

PCIE_JTAG_EN

SW6.4

Embedded

Blaster

Connection

USB PHY

Configuration, Status, and Setup Elements

The embedded USB-Blaster is automatically disabled when an external USB-Blaster is connected to the JTAG chain. Figure 2–4 illustrates the JTAG chain.

Figure 2–4. JTAG Chain

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–14 Chapter 2: Board Components

Configuration, Status, and Setup Elements

Each jumper shown in Figure 2–4 is located in the JTAG DIP switch (SW6) on the back of the board. To connect a device or interface in the chain, their corresponding switch must be in the down position. Push all the switches in the up position to only have the FPGA in the chain.

The MAX

II CPLD EPM2210 System Controller must be in the chain to use some of the GUI interfaces. For this setting, push the left-most switch in the down position and all other switches in the up position.

Flash Programming

Flash programming is possible through a variety of methods using the Stratix IV GX device.

The default method is to use the factory design called the Board Update Portal. This design is an embedded webserver, which serves the Board Update Portal web page. The web page allows you to select new FPGA designs including hardware, software, or both in an industry-standard S-Record File (.flash) and write the design to the user hardware page (page 1) of the flash over the network.

The secondary method is to use the pre-built PFL design included in the development kit. The development board implements the Altera PFL megafunction for flash programming. The PFL megafunction is a block of logic that is programmed into an Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for writing to a compatible flash device. This pre-built design contains the PFL megafunction that allows you to write either page 0, page 1, or other areas of flash over the USB interface using the Quartus II software. This method is used to restore the development board to its factory default settings.

Other methods to program the flash can be used as well, including the Nios

processor.

f For more information on the Nios II processor, refer to the Nios II Processor page of

the Altera website.

FPGA Programming from Flash Memory

On either power-up or by pressing the reset configuration push-button switch (S1), the MAX the FPGA from the flash memory. The PFL megafunction reads 16-bit data from the flash memory and converts it to fast passive parallel (FPP) format. This 8-bit data is then written to the FPGA’s dedicated configuration pins during configuration.

Figure 2–5 shows the PFL configuration.

II CPLD EPM2210 System Controller’s parallel flash loader (PFL) configures

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–15

MAX II CPLD

EPM2210 System Controller

FPGA_DATA [7:0]

FPGA_DCLK

FLASH_A [25:1]

FLASH_D [15:0]

DATA [7:0]

DCLK

INIT_DONE

nSTATUS

nCONFIG

CONF_DONE

MSEL0

MSEL1

MSEL2

MSEL3

2.5 V

10 kΩ

nCE

CFI Flash

CONF_DONE LED

10 kΩ

FLASH_CEn

FLASH_OEn

FLASH_WEn

FLASH_A [25:1]

FLASH_D [15:0]

FLASH_CEn FLASH_OEn

FLASH_WEn

FLASH_RSTn

FLASH_ADVn

MSEL [3:0]

FPGA_nCONFIG

FPGA_CONF_DONE

FSM Bus Interface

FLASH_RYBSYn

Rotary Switch

PGM [2:0]

FPGA_nSTATUS

USB_DISABLEn

2.5 V

10 kΩ

125 MHz

2.5 V

FLASH_ADVn

RESET_CONFIGn

CONF_DONE_LED

2.5 V

10 kΩ

FLASH_CLK

FLASH_RSTn

50 MHz

CONFIG_CLK

External JTAG Detect

Configuration, Status, and Setup Elements

Figure 2–5. PFL Configuration

Tab le 2 –8 shows the flash memory map storage.

Table 2–8. Flash Memory Map (Part 1 of 2)

Unused 128 0x03FE0000 – 0x03FFFFFF

User Software 11,797 0x034A0000 – 0x03FDFFFF

Name Size (Kbyte) Address

User Hardware 21,627 0x02000000 – 0x0349FFFF

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

zipfs—HTML, Web Content 5,898 0x01A60000 – 0x01FFFFFF

Factory Software 5,898 0x014C0000 – 0x01A5FFFF

Factory Hardware 21,627 0x00020000 – 0x014BFFFF

PFL Option Bits 32 0x00018000 – 0x0001FFFF

2–16 Chapter 2: Board Components

Table 2–8. Flash Memory Map (Part 2 of 2)

Name Size (Kbyte) Address

Board Information 32 0x00010000 – 0x00017FFF

Ethernet Option Bits 32 0x00008000 – 0x0000FFFF

User Design Reset Vector 32 0x00000000 – 0x00007FFF

Configuration, Status, and Setup Elements

There are two pages reserved for the FPGA configuration data. The factory hardware page is considered page 0 and is loaded if the rotary switch is in position 0 and when either power is cycled or the reset configuration push-button switch (S1) is pressed. The user hardware page is considered page 1 and is loaded if the rotary switch is in position 1 and when either power is cycled or the reset configuration push-button switch (S1) is pressed.

FPGA Programming over External USB-Blaster

The JTAG programming header provides another method for configuring the FPGA (U13) using an external USB-Blaster device with the Quartus II Programmer running on a PC. The external USB-Blaster is connected to the board through the JTAG connector (J8). The JTAG DIP switch (SW6) allows the MAX II CPLD device to be removed from the JTAG chain so that the FPGA is the only device on the JTAG chain.

f For more information on the following topics, refer to the respective documents:

■ Board Update Portal, refer to the Stratix IV GX FPGA Development Kit, 530 Edition

User Guide.

■ PFL design, refer to the Stratix IV GX FPGA Development Kit, 530 Edition User

Guide.

■ PFL megafunction, refer to AN 386: Using the Parallel Flash Loader with the Quartus

II Software.

Status Elements

The development board includes status LEDs. This section describes the status elements.

Tab le 2 –9 lists the LED board references, names, and functional descriptions.

Table 2–9. Board-Specific LEDs (Part 1 of 2)

Board Reference LED Name Description

D24 POWER Blue LED. Illuminates when 3.3-V power is active.

D5 CONF DONE

D26 Loading

Green LED. Illuminates when the FPGA is successfully configured. Driven by the MAX II CPLD EPM2210 System Controller.

Green LED. Illuminates when the MAX II CPLD EPM2210 System Controller is actively configuring the FPGA. Driven by the MAX II CPLD EPM2210 System Controller wire-OR'd with the Embedded Blaster CPLD.

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–17

Configuration, Status, and Setup Elements

Table 2–9. Board-Specific LEDs (Part 2 of 2)

Board Reference LED Name Description

D27 Error

D35 ENET TX

D34 ENET RX

D33 100

D32 1000

HSMC Port A Present

HSMC Port B Present

Red LED. Illuminates when the MAX II CPLD EPM2210 System Controller fails to configure the FPGA. Driven by the MAX II CPLD EPM2210 System Controller.

Green LED. Blinks to indicate Ethernet PHY transmit activity. Driven by the Marvell 88E1111 PHY.

Green LED. Blinks to indicate Ethernet PHY receive activity. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet linked at 100 Mbps connection speed Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates to indicate Ethernet linked at 1000 Mbps connection speed. Driven by the Marvell 88E1111 PHY.

Green LED. Illuminates when the HSMC port A has a board or cable plugged-in such that pin 160 becomes grounded. Driven by the add-in card.

Green LED. Illuminates when the HSMC port B has a board or cable plugged-in such that pin 160 becomes grounded. Driven by the add-in card.

D30 MUTE Green LED. Illuminates when the SDI receiver carrier detect is active.

D40 FAN LED

Green LED. Illuminates when a heat sink or fan should be installed. Driven by the MAX1619 thermal sensor

OVERTEMPn

signal.

Tab le 2 –1 0 lists the board-specific LEDs component references and manufacturing

information.

Table 2–10. Board-Specific LEDs Component References and Manufacturing Information

Board Reference Description Manufacturer

Manufacturer

Part Number

Manufacturer

Website

D1, D2, D26 Green LEDs Lumex Inc. SML-LX1206GC-TR www.lumex.com

D27 Red LED Lumex Inc. SML-LX1206USBC-TR www.lumex.com

D24 Blue LED Lumex Inc. SML-LX1206USBC-TR www.lumex.com

Setup Elements

The development board includes several different kinds of setup elements. This section describes the following setup elements:

■ Board settings DIP switch

■ JTAG control DIP switch

■ PCI Express control DIP switch

■ Reset configuration push-button switch

■ Rotary switch

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–18 Chapter 2: Board Components

Configuration, Status, and Setup Elements

Board Settings DIP switch

The board settings DIP switch controls various features specific to the board and the MAX

II CPLD EPM2210 System Controller logic design. Table 2–11 shows the switch

controls and descriptions.

Table 2–11. Board Settings DIP Switch Controls

Switch Schematic Signal Name Description Default

MAX_DIP

USB_DISABLEn

LCD_PWRMON

FAN_FORCE_ON

CLK_SEL

CLK_ENABLE

S4VCCH_SEL

S4VCCA_SEL

Reserved OFF

ON : Embedded USB-Blaster disabled

OFF : Embedded USB-Blaster enabled

ON : LCD driven from the Max II EPM2210 System Controller (power monitor)

OFF : LCD driven from the FPGA (no power monitor)

ON : Fan forced ON at full-speed

OFF : Fan speed controlled by the MAX1619 device

ON : 100 MHz oscillator input select

OFF : SMA input select

ON : On-Board oscillator enabled

OFF : On-Board oscillator disabled

ON : 1.4 V (default)

OFF : Reserved

ON : 3.0 V (default)

OFF : 2.5 V

OFF

Tab le 2 –1 2 lists the board settings DIP switch component reference and

manufacturing information.

Table 2–12. Board Settings DIP Switch Component Reference and Manufacturing Information

Board Reference Description Manufacturer

SW4

Eight-Position slide DIP switch

C & K Components TDA08H0SB1 www.ck-components.com

Manufacturer

Part Number

Manufacturer Website

JTAG Control DIP Switch

The JTAG control DIP switch is provided to either remove or include devices in the active JTAG chain. However, the Stratix IV GX FPGA device is always in the JTAG chain. Table 2–13 shows the switch controls and its descriptions.

Table 2–13. JTAG Control DIP Switch Controls (Part 1 of 2)

Switch Schematic Signal Name Description Default

EPM2210_JTAG_EN

HSMA_JTAG_EN

ON : Bypass Max II CPLD EPM2210 System Controller

OFF : Max II CPLD EPM2210 System Controller in-chain

ON : Bypass HSMA

OFF : HSMA in-chain

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Chapter 2: Board Components 2–19

Configuration, Status, and Setup Elements

Table 2–13. JTAG Control DIP Switch Controls (Part 2 of 2)

Switch Schematic Signal Name Description Default

HSMB_JTAG_EN

PCIE_JTAG_EN

ON : Bypass HSMB

OFF : HSMB in-chain

ON : Bypass PCI Express

OFF : Reserved (disables JTAG chain, do not use)

Tab le 2 –1 4 lists the JTAG control DIP switch component references and

manufacturing information.

Table 2–14. JTAG Control DIP Switch Component Reference and Manufacturing Information

Board Reference

SW6

Device

Description

Four-Position slide DIP switch

Manufacturer

C & K Components TDA04H0SB1 www.ck-components.com

Manufacturer

Part Number

Manufacturer Website

PCI Express Control DIP switch

The PCI Express control DIP switch is provided to enable or disable the different configurations. Table 2–15 shows the switch controls and descriptions.

Table 2–15. PCI Express Control DIP Switch Controls

Switch Schematic Signal Name Description Default

PCIE_PRSNT2n_x1

PCIE_PRSNT2n_x4

PCIE_PRSNT2n_x8

MAX_EN

Tab le 2 –1 6 lists the PCI Express control DIP switch component reference and

manufacturing information.

ON : Enable x1 presence detect

OFF : Disable x1 presence detect

ON : Enable x4 presence detect

OFF : Disable x4 presence detect

ON : Enable x8 presence detect

OFF : Disable x8 presence detect

Reserved OFF

Table 2–16. PCI Express Control DIP Switch Component Reference and Manufacturing Information

Board Reference Description Manufacturer

SW5

Four-Position slide DIP switch

C & K Components TDA04H0SB1 www.ck-components.com

Manufacturer

Part Number

Manufacturer Website

Reset Configuration Push-Button Switch

The reset configuration push-button switch, CPLD EPM2210 System Controller. The push-button switch forces a reconfiguration of the FPGA from flash memory. The location in the flash memory is based on the input from the rotary switch position when the button is released. Valid locations include 0 and 1 for the two pages in flash reserved for FPGA designs.

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

RESET_CONFIGn

, is an input to the MAX II

2–20 Chapter 2: Board Components

Configuration, Status, and Setup Elements

Tab le 2 –1 7 lists the reset configuration push-button switch component reference and

manufacturing information.

Table 2–17. Reset Configuration Push-Button Component Reference and Manufacturing Information

Board Reference Description Manufacturer

Manufacturer

Part Number

Manufacturer

Website

S1 Push-Button switch Panasonic Corporation EVQPAC07K www.panasonic.com

Rotary Switch

The 16-position rotary switch (SW2) is wired to the MAX II CPLD EPM2210 System Controller. This rotary switch serves the following purposes:

■ At power up or when the reset configuration push-button switch (S1) is pressed,

this switch selects either the factory (page 0) or the user (page 1) design to load into the FPGA.

■ After power up, the rotary switch selects the power rail monitored from among a

total of 16 rails. The power information is displayed in the Power GUI on a host PC with a USB connection to the board.

■ User applications can obtain the switch value by reading the

FSM bus in the MAX

II CPLD EPM2210 System Controller.

Tab le 2 –1 8 lists the power rails that are measured based on the rotary switch position.

Table 2–18. Power Rail Measurements Based on the Rotary Switch Position (Part 1 of 2)

Switch Schematic Signal Name Voltage (V) Device Pin Description

S4VCCIO_B7B8

S4VCC

3.3 V

1.5

0.90

3.3 — All 3.3 V power to board (mA only)

VCCIO_B7 Bank 7 I/O power (QDR2TOP0+DDR)

VCCIO_B8 Bank 8 I/O power (QDR2TOP1+DDR)

VCC FPGA core and periphery power

VCCHIP PCI Express hard IP block

VCCPD I/O pre-drivers

S4VCCIO_INT

S4VCCH_GXB

S4VCCAUX

S4VCCPT

S4VCCD_PLL

S4VCCA_GXB

S4VCCIO_B5

S4VCCIO_B6

S4VCCIO_B1B2

S4VCCIO_B3A

2.5

VCCPGM Configuration I/O

VCC_CLKIN V

clock input pins

1.4 VCCH_GXB XCVR clock buffers

2.5

VCCAUX Programmable power tech auxiliary

VCCA_PLL PLL analog

1.5 VCCPT Programmable power tech

0.90 VCCD_PLL PLL digital

3.0 VCCA_GXB XCVR analog TX/RX driver (mA only)

2.5 VCCIO_B5 Bank 5 I/O power (HSMC port A)

2.5 VCCIO_B6 Bank 6 I/O power (HSMC port B)

2.5

VCCIO_B1 Bank 1 I/O power (FSM bus)

VCCIO_B2 Bank 2 I/O power (FSM bus)

1.8 VCCIO_B3A Bank 3A I/O power (HDMI)

rsr

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Chapter 2: Board Components 2–21

Clock Circuitry

Table 2–18. Power Rail Measurements Based on the Rotary Switch Position (Part 2 of 2)

Switch Schematic Signal Name Voltage (V) Device Pin Description

S4VCCIO_B3B4

S4VCC_GXB

12 V

1.5

1.1

12 — All 12 V power

VCCIO_B3 Bank 3 I/O power (DDR3BOT)

VCCIO_B4 Bank 4 I/O power (DDR3BOT)

VCCR XCVR analog receive

VCCT XCVR analog transmit

VCCL_GXB XCVR clock distribution

Tab le 2 –1 9 lists the rotary switch component reference and manufacturing

information.

Table 2–19. Rotary Switch Component Reference and Manufacturing Information

Board Reference Description Manufacturer

SW2

16-position rotary switch

Grayhill Corporation 94HCB16WT www.grayhill.com

Clock Circuitry

This section describes the board's clock inputs and outputs.

Manufacturer

Part Number

Manufacturer

Website

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–22 Chapter 2: Board Components

B1B2

B6B5

CLK2p

CLK3p

CLKIN_50

HSMA_CLK_IN0

2.5V, NO OCT

REFCLK INPUT

SMA SMA

LVPECL or

Single-Ended

2-to-4 buffer

100 M*

CLK_SEL

CLKINRT_100_P

CLKINLT_100_P

CLKINTOP_100_P

CLKINBOT_100_P

DIPSW

SW4-5

To REFCLK Clock Inputs

CLK1p

CLK0p

CLK9p

CLK8p

CLK10p

CLK11p

CLK7p

CLK6p

CLK4p

CLK5p

CLK13p

CLK12p

CLK14p

CLK15p

PLL

HSMA_CLK_IN_P2

LVDS, OCT 100 Ω

CLK_125_P

LVDS, Differential OCT

HSMB_CLK_IN0

2.5V, NO OCT

CLKINBOT_100_P

LVDS, Differential OCT

HSMA_CLK_IN_P1

LVDS, OCT 100 Ω

HSMB_CLK_IN_P1

LVDS, OCT 100 Ω

HSMB_CLK_IN_P2

LVDS, OCT 100 Ω

CLKINTOP_100_P

LVDS, Differential OCT

*The 100 MHz oscillator (X6) can be programmed to any frequency between 20 MHz and 810 MHz but powers up to 100 MHz using the clock control GUI installed with the kit CD.

Clock Circuitry

Stratix IV GX FPGA Clock Inputs

The development board has two types of clock inputs: global clock inputs and transceiver reference clock inputs. Figure 2–6 shows the Stratix IV GX FPGA Development Board, 530 Edition global clock inputs. The development board’s transceiver reference clock inputs are shown in Figure 2–7.

Figure 2–6. Stratix IV GX FPGA Development Board, 530 Edition Global Clock Inputs

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–23

B1B2

B6B5

QL0 QL1 QL2

REFCLK_L0p

REFCLK_L1p

PCIE_REFCLK_P

REFCLK_L2p

REFCLK_L3p

REFCLK_L4p

REFCLK_L5p

CLK_155_P

CLKINLT_100_P

LVDS, OCT 100 Ω

LVPECL, OCT 100 Ω

HCSL, NO OCT

CLK_125_P

CLKINRT_100_P

LVDS, OCT 100 Ω

CLK_156_P

LVDS, OCT 100 Ω

CLK_148_P

LVDS, OCT 100 Ω

QR0 QR1 QR2

REFCLK_R0p

REFCLK_R1p

REFCLK_R2p

REFCLK_R3p

REFCLK_R4p

REFCLK_R5p

PCIe Edge Connector

REFCLK INPUT

SMA SMA

LVPECL or

Single-Ended

2-to-4 buffer

100 M*

CLK_SEL

CLKINTOP_100_P

CLKINBOT_100_P

CLKINRT_100_P

CLKINLT_100_P

DIPSW

SW4-5

To GPLL Clock Inputs

Right Edge

REFCLK Inputs

Left Edge

REFCLK Inputs

*The 100 MHz oscillator (X6) can be programmed to any frequency between 20 MHz and 810 MHz but powers up to 100 MHz using the clock control GUI installed with the kit CD.

Clock Circuitry

Figure 2–7. Stratix IV GX FPGA Development Board, 530 Edition Transceiver Reference Clock Inputs

Tab le 2 –2 0 shows the external clock inputs for the Stratix IV GX FPGA Development

Board, 530 Edition.

Table 2–20. Stratix IV GX FPGA Development Board, 530 Edition Clock Inputs (Part 1 of 2)

Source Schematic Signal Name Pin I/O Standard Description

125 MHz oscillator which drives the transceiver

CLK_125_P0 J2 LVDS

CLK_125_P1 AF34 LVDS

X2 CLK_156_P AA2 LVDS

X3 CLK_148_P AL2 LVDS

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

reference clock input with 100 Ω on-chip termination (OCT).

125 MHz oscillator which drives the global clock input with parallel OCT.

156.25 MHz oscillator which drives the transceiver reference clock input with 100 Ω OCT.

148.5 MHz oscillator which drives the transceiver reference clock input with 100 Ω OCT.

2–24 Chapter 2: Board Components

Clock Circuitry

Table 2–20. Stratix IV GX FPGA Development Board, 530 Edition Clock Inputs (Part 2 of 2)

Source Schematic Signal Name Pin I/O Standard Description

155.52 MHz oscillator which drives the

X7 CLK_155_P J38 LVPECL

transceiver reference clock input with 100 Ω OCT.

SMA or X6

Samtec HSMC

PCI Express

Edge

CLKIN_50

CLKINTOP_100_P

CLKINTOP_100_N

CLKINBOT_100_P

CLKINBOT_100_N

CLKINRT_100_P

CLKINRT_100_N

CLKINLT_100_P

CLKINLT_100_N

HSMA_CLK_IN0

HSMA_CLK_IN_P1

HSMA_CLK_IN_N1

HSMA_CLK_IN_P2

HSMA_CLK_IN_N2

HSMB_CLK_IN0

HSMB_CLK_IN_P1

HSMB_CLK_IN_N1

HSMB_CLK_IN_P2

HSMB_CLK_IN_N2

PCIE_REFCLK_P

PCIE_REFCLK_N

AC34 2.5-V CMOS

A21

A20

LVDS

AV22

AW22

LVDS

G38

G39

LVDS

AB34 LVTTL

AC6

AC5

AF6

AE5

LVDS or LVTTL

AA35 LVTTL

AB6

AA5

AN38

AN39

LVDS or LVTTL

HCSL

50 MHz oscillator which drives the global clock input.

100 MHz programmable oscillator which drives the fan-out buffer U50 and LVDS input to the top edge PLL input.

100 MHz programmable oscillator which drives the fan-out buffer U50 and LVDS to the transceiver QR2 REFCLK input.

Single-ended input from the installed HSMC cable or board.

LVDS input from the installed HSMC cable or board. Can also support two LVTTL inputs.

Single-ended input from the installed HSMC cable or board.

LVDS input from the installed HSMC cable or board. Can also support two LVTTL inputs.

HCSL input from the PCI Express edge connector.

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Chapter 2: Board Components 2–25

B1B2

B6B5

SRAM_CLK

MAX2_CLK

2.5V, 50

OCT

2.5V, 50

OCT

SMA

PLL

HSMA_CLK_OUT_P2

LVDS, NO OCT

FLASH_CLK

2.5V, 50

OCT

CLKOUT_SMA

2.5V, 50

OCT

HDMI_CLK

1.8V, 50 Ω OCT

HSMA_CLK_OUT_P1

LVDS, NO OCT

HSMB_CLK_OUT_P1

LVDS, NO OCT

HSMB_CLK_OUT_P2

LVDS, NO OCT

DDR3BOT_CK_P

SSTL-15 Class I

DDR3BOT_CK_N

SSTL-15 Class I

DDR3TOP_CK_P

SSTL-15 Class I, 50 Ω OCT

DDR3TOP_CK_N

SSTL-15 Class I, 50 Ω OCT

QDR2_TOP0_K_P

1.5V HSTL Class I, 50 Ω OCT

QDR2_TOP0_K_N

1.5V HSTL Class I, 50 Ω OCT

QDR2_TOP1_K_P

1.5V HSTL Class I, 50 Ω OCT

QDR2_TOP1_K_N

1.5V HSTL Class I, 50 Ω OCT

Clock Circuitry

Stratix IV GX FPGA Clock Outputs

Figure 2–8 shows the Stratix IV GX FPGA Development Board, 530 Edition clock

outputs.

Figure 2–8. Stratix IV GX FPGA Development Board, 530 Edition Clock Outputs

Tab le 2 –2 1 shows the clock outputs for the Stratix IV GX FPGA Development Board,

530 Edition.

Table 2–21. Stratix IV GX FPGA Development Board, 530 Edition Clock Outputs (Part 1 of 2)

Connector Schematic Signal Name Pin I/O Standard Description

SMA

Samtec HSMC

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

CLKOUT_SMA

HSMA_CLK_OUT0

HSMA_CLK_OUT_P1

HSMA_CLK_OUT_N1

HSMA_CLK_OUT_P2

HSMA_CLK_OUT_N2

HSMB_CLK_OUT0

W33 2.5-V FPGA CMOS output or general purpose I/O (GPIO)

AM29 2.5-V FPGA CMOS output or GPIO

AL10

AM10

AF13

AG13

LVDS or 2.5-V LVDS output or two 2.5-V CMOS outputs.

AK29 2.5-V FPGA CMOS output or GPIO

2–26 Chapter 2: Board Components

Table 2–21. Stratix IV GX FPGA Development Board, 530 Edition Clock Outputs (Part 2 of 2)

Connector Schematic Signal Name Pin I/O Standard Description

Samtec HSMC

HSMB_CLK_OUT_P1

HSMB_CLK_OUT_N1

HSMB_CLK_OUT_P2

HSMB_CLK_OUT_N3

K10

J10

LVDS or 2.5-V LVDS output or two 2.5-V CMOS outputs.

LVDS or 2.5-V

LVDS output. Can also support two CMOS outputs.

General User Input/Output

Tab le 2 –2 2 lists the crystal oscillators component references and manufacturing

information.

Table 2–22. Crystal Oscillator Component References and Manufacturing Information

Board

Reference

X1 125 MHz LVDS Saw Oscillator Epson

X8 50 MHz Crystal Oscillator Epson

X9 125 MHz Crystal Oscillator ECS ECS-3525-1250-B www.ecsxtal.com

156.25 MHz LVDS Saw Oscillator

148.5 MHz Voltage Controlled LVDS Crystal Oscillator

100 MHz LVDS Programmable Crystal Oscillator

155.5 MHz LVPECL Saw Oscillator

Description Manufacturer

Epson

Connor-Winfield V902-148.5MHz www.conwin.com

Silicon Labs 570FAB000433DG www.silabs.com

Epson

Manufacturer

Part Number

EG-2121CA

125.0000M-LGPNL3

EG-2121CA

156.2500M-LHPNL3

EG-2121CA

155.5200M-PGPNL3

XG-1000CB

50.0000M-DCL3

Manufacturer Website

www.eea.epson.com

General User Input/Output

This section describes the user I/O interface to the FPGA, including the push-buttons, DIP switches, status LEDs, and character LCD.

User-Defined Push-Button Switches

The development board includes four user-defined push-button switches: three general switches and one CPU reset. For information on the system and safe reset push-button switches, refer to “Reset Configuration Push-Button Switch” on

page 2–19.

Board references S3, S4, and S5 are push-button switches that allow you to interact with the Stratix IV GX device. When the switch is pressed and held down, the device pin is set to logic 0; when the switch is released, the device pin is set to logic 1. There is no board-specific function for these general user push-button switches.

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Chapter 2: Board Components 2–27

General User Input/Output

Board reference S2 is the CPU reset push-button switch, to both the Stratix IV GX device and MAX

CPU_RESETn

the Stratix IV GX device. The

is intended to be the master reset signal for the FPGA design loaded into

CPU_RESETn

II CPLD EPM2210 System Controller. The

signal must be enabled within the Quartus II

software for this reset function to work. Otherwise, the

CPU_RESETn

I/O pin. When enabled in the Quartus II software, and then pulled high on the board, this switch resets every register within the FPGA.

Tab le 2 –2 3 lists the user-defined push-button switch schematic signal names and their

corresponding Stratix IV GX device pin numbers.

Table 2–23. User-Defined Push-Button Switch Schematic Signal Names and Functions

Board Reference Description

User-Defined push-button switch

Schematic Signal

Name

CPU_RESETn

USER_PB2

USER_PB1

USER_PB0

I/O Standard

2.5-V

Stratix IV GX Device

Tab le 2 –2 4 lists the user-defined push-button switch component reference and the

manufacturing information.

Table 2–24. User-Defined Push-Button Switch Component Reference and Manufacturing Information

, which is an input

acts as a regular

Pin Number

V34

M34

W32

AK35

Board Reference Description Manufacturer

S2 to S5 Push-Button switch Panasonic Corporation EVQPAC07K www.panasonic.com

Manufacturer

Part Number

Manufacturer

Website

User-Defined DIP Switches

Board reference S6 is an 8-pin DIP switch. The switches in S6 are user-defined, and are provided for additional FPGA input control. There is no board-specific function for these switches.

Tab le 2 –2 5 lists the user-defined DIP switch schematic signal names and their

corresponding Stratix IV GX pin numbers.

Table 2–25. User-Defined DIP Switch Schematic Signal Names and Functions

Board Reference Description

SW3.1

SW3.2

SW3.3

SW3.4

SW3.5

SW3.6

SW3.7

SW3.8

User-Defined DIP switch connected to FPGA device. When the switch is in the OPEN or OFF position, a logic 1 is selected. When the switch is in the CLOSED or ON position, a logic 0 is selected.

Schematic

Signal Name

USER_DIPSW0

USER_DIPSW1

USER_DIPSW2

USER_DIPSW3

USER_DIPSW4

USER_DIPSW5

USER_DIPSW6

USER_DIPSW7

I/O Standard

2.5-V

Stratix IV GX Device

Pin Number

AL35

AC35

J34

AN35

G33

K35

AG34

AG31

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2–28 Chapter 2: Board Components

General User Input/Output

Tab le 2 –2 6 lists the user-defined DIP switch component reference and the

manufacturing information.

Table 2–26. User-Defined DIP Switch Component Reference and Manufacturing Information

Board

Reference

SW3 Eight-Position DIP switch C & K Components TDA08H0SB1 www.ck-components.com

Description Manufacturer

Manufacturer

Part Number

Manufacturer Website

User-Defined LEDs

The development board includes general and HSMC user-defined LEDs. This section describes all user-defined LEDs. For information on board specific or status LEDs, refer to“Status Elements” on page 2–16.

General User-Defined LEDs

Board references D6 through D13 and D16 through D23 are 16 user LEDs which allow status and debugging signals to be driven to the LEDs from the designs loaded into the Stratix IV GX device. The LEDs illuminate when a logic 0 is driven, and turns off when a logic 1 is driven. There is no board-specific function for these LEDs.

Tab le 2 –2 7 lists the user-defined LED schematic signal names and their corresponding

Stratix IV GX pin numbers.

Table 2–27. User-Defined LED Schematic Signal Names and Functions

Board Reference Description

D23

D22

D21

D20

D19

D18

D17

D16

D13

D12

D11

D10

User-Defined LEDs. Driving a logic 0 on the I/O port turns the LED ON. Driving a logic 1 on the I/O port turns the LED OFF.

Schematic

Signal Name

USR_LED0

USR_LED1

USR_LED2

USR_LED3

USR_LED4

USR_LED5

USR_LED6

USR_LED7

USR_LED8

USR_LED9

USR_LED10

USR_LED11

USR_LED12

USR_LED13

USR_LED14

USR_LED15

I/O Standard

2.5-V

Stratix IV GX Device

Pin Number

F33

AK33

W28

L34

AM34

M32

L35

AM35

N34

W35

AE30

V30

AG30

AD29

U31

U35

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Chapter 2: Board Components 2–29

General User Input/Output

Tab le 2 –2 8 lists the user-defined LED component reference and the manufacturing

information.

Table 2–28. User-Defined LED Component Reference and Manufacturing Information

Board Reference Device Description Manufacturer

D6 to D13

D16 to D23

Green LEDs, 1206, SMT, Clear Lens, 2.1 V

Lumex Inc. SML-LX1206GC-TR www.lumex.com

HSMC User-Defined LEDs

The HSMC port A and B have two LEDs located nearby. There are no board-specific functions for the HSMC LEDs. However, the LEDs are labeled TX and RX, and are intended to display data flow to and from the connected HSMC cards. The LEDs are driven by the Stratix IV GX device.

Tab le 2 –2 9 lists the HSMC user-defined LED schematic signal names and their

corresponding Stratix IV GX pin numbers.

Table 2–29. HSMC User-Defined LED Schematic Signal Names and Functions

Board

Reference

D14

D15

Description

User-Defined LEDs. Labeled TX for HSMC Port A.

User-Defined LEDs. Labeled RX for HSMC Port A.

User-Defined LEDs. Labeled TX for HSMC Port B.

User-Defined LEDs. Labeled RX for HSMC Port B.

Schematic

Signal Name

HSMA_TX_LED

HSMA_RX_LED

HSMB_TX_LED

HSMB_RX_LED

Manufacturer

Part Number

I/O Standard

2.5-V

Manufacturer

Website

Stratix IV GX Device

Pin Number

AH33

AT10

Tab le 2 –3 0 lists the HSMC user-defined LED component reference and the

manufacturing information.

Table 2–30. HSMC User-Defined LED Component Reference and Manufacturing Information

Board Reference Description Manufacturer

D3 to D4

D14 to D15

Green LEDs, 1206, SMT, Clear Lens, 2.1 V

Lumex Inc. SML-LX1206GC-TR www.lumex.com

Manufacturer

Part Number

Manufacturer

Website

LCD

The development board contains a single 14-pin 0.1" pitch dual-row header that interfaces to a 16 character × 2 line Lumex LCD display. The LCD has a 14-pin receptacle that mounts directly to the board's 14-pin header, so it can be easily removed for access to components under the display. You can also use the header for debugging or other purposes.

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–30 Chapter 2: Board Components

General User Input/Output

Tab le 2 –3 1 summarizes the LCD pin assignments. The signal names and directions are

relative to the Stratix IV GX FPGA.

Table 2–31. LCD Pin Assignments, Schematic Signal Names, and Functions

Stratix IV GX

Board Reference Description Schematic Signal

Name

J16.7 LCD data bus

J16.8 LCD data bus

J16.9 LCD data bus

J16.10 LCD data bus

J16.11 LCD data bus

J16.12 LCD data bus

J16.13 LCD data bus

J16.14 LCD data bus

J16.4 LCD data or command select

J16.5 LCD write enable

J16.6 LCD chip select

LCD_DATA0

LCD_DATA1

LCD_DATA2

LCD_DATA3

LCD_DATA4

LCD_DATA5

LCD_DATA6

LCD_DATA7

LCD_D_Cn

LCD_Wen

LCD_CSn

I/O Standard

2.5-V

Device

Pin Number

AD31

AJ34

R31

L32

T30

AN34

T31

AD30

AB30

AL34

K34

Tab le 2 –3 2 shows the LCD pin definitions, and is an excerpt from the Lumex data

sheet.

f For more information such as timing, character maps, interface guidelines, and other

related documentation, visit www.lumex.com.

Table 2–32. LCD Pin Definitions and Functions

Number

Symbol

Level

—

—GND (0 V)

Power supply

Function

5 V

— For LCD drive

4RS H/L

H: Data input

L: Instruction input

5R/W H/L

H: Data read (module to MPU)

L: Data write (MPU to module)

6 E H, H to L Enable

7–14 DB0–DB7 H/L Data bus, software selectable 4-bit or 8-bit mode

1 The particular model used does not have a backlight and the LCD drive pin is not

connected.

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–31

Components and Interfaces

Tab le 2 –3 3 lists the LCD component references and the manufacturing information.

Table 2–33. LCD Component References and Manufacturing Information

Board

Reference

J16

2×7 pin, 100 mil, vertical header Samtec TSM-107-01-G-DV www.samtec.com

2×16 character display, 5×8 dot matrix

Description Manufacturer

Components and Interfaces

This section describes the development board's communication ports and interface cards relative to the Stratix IV GX device. The development board supports the following communication ports:

■ PCI Express

■ 10/100/1000 Ethernet

■ HSMC

PCI Express

The Stratix IV GX FPGA Development Board, 530 Edition is designed to fit entirely into a PC motherboard with a ×8 or ×16 PCI Express slot that can accommodate a full height short form factor add-in card. This interface uses the Stratix IV GX device's PCI Express hard IP block, saving logic resources for the user logic application.

Manufacturer

Part Number

Lumex Inc. LCM-S01602DSR/C www.lumex.com

Manufacturer

Website

f For more information on using the PCI Express hard IP block, refer to the PCI Express

Compiler User Guide.

The PCI Express interface supports auto-negotiating channel width from ×1 to ×4 to ×8 as well as the connection speed of Gen1 at 2.5 Gbps/lane to Gen2 at 5.0 Gbps/lane for a maximum of 40 Gbps full-duplex.

The power for the board can be sourced entirely from the PCI Express edge connector when installed into a PC motherboard. Although the board can also be powered by a laptop power supply for use on a lab bench, it is not recommended to power from both supplies at the same time. Ideal diode power sharing devices have been designed into this board to prevent damages or back-current from one supply to the other.

The

PCIE_REFCLK_P

signal is a 100-MHz differential input that is driven from the PC motherboard on this board through the edge connector. This signal is connected directly to a Stratix IV GX

REFCLK

input pin pair using DC coupling. This clock is terminated on the motherboard and therefore, no on-board termination is required. This clock can have spread-spectrum properties that change its period between

9.847 ps to 10.203 ps. The I/O standard is High-Speed Current Steering Logic (HCSL).

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–32 Chapter 2: Board Components

MAX

= 1.15 V

CROSS MAX

= 550 mV

CROSS MIN

= 250 mV

MIN

= –0.30 V

REFCLK –

REFCLK +

Components and Interfaces

Figure 2–9 shows the PCI Express reference clock levels.

Figure 2–9. PCI Express Reference Clock Levels

The JTAG and SMB are optional signals in the PCI Express specification. Both types of signals are wired to the Stratix IV GX device but are not required for normal operation. The PCI Express control DIP switch allows the presence detect grounding to be altered to enable a ×1, ×4, or ×8 width edge connector. The PCI Express control DIP switch does not support auto-negotiation. Table 2–34 summarizes the PCI Express pin assignments. The signal names and directions are relative to the Stratix IV GX FPGA.

Table 2–34. PCI Express Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)

Board Reference Description Schematic Signal

I/O Standard

Name

J17.A47 Add-in card transmit bus

J17.A48 Add-in card transmit bus

J17.A43 Add-in card transmit bus

J17.A44 Add-in card transmit bus

J17.A39 Add-in card transmit bus

J17.A40 Add-in card transmit bus

J17.A35 Add-in card transmit bus

J17.A36 Add-in card transmit bus

J17.A29 Add-in card transmit bus

J17.A30 Add-in card transmit bus

J17.A25 Add-in card transmit bus

J17.A26 Add-in card transmit bus

J17.A21 Add-in card transmit bus

J17.A22 Add-in card transmit bus

J17.A16 Add-in card transmit bus

J17.A17 Add-in card transmit bus

J17.B45 Add-in card receive bus

J17.B46 Add-in card receive bus

J17.B41 Add-in card receive bus

J17.B42 Add-in card receive bus

J17.B37 Add-in card receive bus

PCIE_TX_P7

PCIE_TX_N7

PCIE_TX_P6

PCIE_TX_N6

PCIE_TX_P5

PCIE_TX_N5

PCIE_TX_P4

PCIE_TX_N4

PCIE_TX_P3

PCIE_TX_N3

PCIE_TX_P2

PCIE_TX_N2

PCIE_TX_P1

PCIE_TX_N1

PCIE_TX_P0

PCIE_TX_N0

PCIE_RX_P7

PCIE_RX_N7

PCIE_RX_P6

PCIE_RX_N6

PCIE_RX_P5

1.4-V PCML

Stratix IV GX

Device

Pin Number

P36

P37

T36

T37

AB36

AB37

AD36

AD37

AF36

AF37

AH36

AH37

AP36

AP37

AT36

AT37

R38

R39

U38

U39

AC38

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–33

Components and Interfaces

Table 2–34. PCI Express Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)

Stratix IV GX

Board Reference Description Schematic Signal

Name

J17.B38 Add-in card receive bus

J17.B33 Add-in card receive bus

J17.B34 Add-in card receive bus

J17.B27 Add-in card receive bus

J17.B28 Add-in card receive bus

J17.B23 Add-in card receive bus

J17.B24 Add-in card receive bus

J17.B19 Add-in card receive bus

J17.B20 Add-in card receive bus

J17.B14 Add-in card receive bus

J17.B15 Add-in card receive bus

J17.A13 Motherboard reference clock

J17.A14 Motherboard reference clock

J17.A11 Reset

J17.B11 Wake signal

J17.B5 SMB clock

J17.B6 SMB data

PCIE_RX_N5

PCIE_RX_P4

PCIE_RX_N4

PCIE_RX_P3

PCIE_RX_N3

PCIE_RX_P2

PCIE_RX_N2

PCIE_RX_P1

PCIE_RX_N1

PCIE_RX_P0

PCIE_RX_N0

PCIE_REFCLK_P

PCIE_REFCLK_N

PCIE_PERSTn

PCIE_WAKEn

PCIE_SMBCLK

PCIE_SMBDAT

I/O Standard

1.4-V PCML

HCSL

LVTTL

Device

Pin Number

AC39

AE38

AE39

AG38

AG39

AJ38

AJ39

AR38

AR39

AU38

AU39

AN38

AN39

R32

P31

AE31

P32

10/100/1000 Ethernet

A Marvell 88E1111 PHY device is used for 10/100/1000 BASE-T Ethernet connection. The device is an auto-negotiating Ethernet PHY with an SGMII interface to the FPGA. The Stratix IV GX device can communicate with the LVDS interfaces at up to 1.6 Gbps, which is faster than 1.25 Gbps for SGMII. The MAC function must be provided in the FPGA for typical networking applications. The Marvell 88E1111 PHY uses 2.5-V and

1.1-V power rails and requires a 25-MHz reference clock driven from a dedicated oscillator. It interfaces to an RJ-45 with internal magnetics that can be used for driving copper lines with Ethernet traffic.

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–34 Chapter 2: Board Components

Components and Interfaces

Figure 2–10 shows the SGMII interface between the FPGA (MAC) and Marvell

88E1111 PHY.

Figure 2–10. SGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY

S_OUT ±

MAC

S_IN

SGMII Interface

88E1111

Device

Transformer

Tab le 2 –3 5 lists the Ethernet PHY interface pin assignments.

Table 2–35. Ethernet PHY Pin Assignments, Signal Names and Functions

Board Reference Description Schematic Signal

Name

U21.82 SGMII TX data

U21.81 SGMII TX data

U21.77 SGMII RX data

U21.75 SGMII RX data

U21.25 Management bus control

U21.24 Management bus data

U21.23 Management bus interrupt

U21.28 Device reset

ENET_TX_P

ENET_TX_N

ENET_RX_P

ENET_RX_N

ENET_MDC

ENET_MDIO

ENET_INTn

ENET_RESETn

RJ45

I/O Standard

LVDS

2.5-V

CAT 5 UTP:

- 10BASE-T

- 100BASE-TX

- 1000BASE-T

Stratix IV GX

Device

Pin Number

L29

K29

AC31

AC32

AH34

M33

R30

V31

Tab le 2 –3 6 lists the Ethernet PHY interface component reference and manufacturing

information.

Table 2–36. Ethernet PHY Component Reference and Manufacturing Information

Board Reference Description Manufacturer

U21 Ethernet PHY BASE-T device

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Marvel Semiconductor

Manufacturing

Part Number

88E1111-B2-CAAIC000 www.marvell.com

Manufacturer

Website

Chapter 2: Board Components 2–35

Components and Interfaces

High-Speed Mezzanine Cards

The development board contains two HSMC interfaces called port A and port B. These HSMC interfaces support both single-ended and differential signaling. The HSMC interface also allows JTAG, SMB, clock outputs and inputs, as well as power for compatible HSMC cards. The HSMC is an Altera-developed open specification, which allows you to expand the functionality of the development board through the addition of daughtercards.

f For more information about the HSMC specification such as signaling standards,

signal integrity, compatible connectors, cabling solutions, and mechanical information, refer to the High Speed Mezzanine Card (HSMC) Specification manual.

The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins, and 13 ground pins. The ground pins are located between the two rows of signal and power pins, acting both as a shield and a reference. The HSMC host connector is based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board connectors from Samtec. There are three banks in this connector. Bank 1 has every third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have all the pins populated as done in the QSH/QTH series.

Figure 2–11 shows the bank arrangement of signals with respect to the Samtec

connector's three banks.

Figure 2–11. HSMC Signal and Bank Diagram

Bank 3

Powe r

D(79.40)

-or-

LVDS

CLKIN2, CLKOUT2

Bank 2

Powe r

D(39:0)

-or-

D[3:0] + LVDS

CLKIN1, CLKOUT1

Bank 1 8 TX Channels CDR 8 RX Channels CDR

JTAG

SMB

CLKIN0, CLKOUT0

The HSMC interface has programmable bi-directional I/O pins that can be used as

2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as various differential I/O standards including, but not limited to, LVDS, mini-LVDS, and RSDS with up to 17 full-duplex channels.

1 As noted in the High Speed Mezzanine Card (HSMC) Specification manual, LVDS and

single-ended I/O standards are only guaranteed to function when mixed according to either the generic single-ended pin-out or generic differential pin-out.

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–36 Chapter 2: Board Components

Components and Interfaces

Tab le 2 –3 7 lists the HSMC port A interface pin assignments, signal names, and

functions.

Table 2–37. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board

Reference

Description

J1.1 Transceiver TX bit 7

J1.2 Transceiver RX bit 7

J1.3 Transceiver TX bit 7n

J1.4 Transceiver RX bit 7n

J1.5 Transceiver TX bit 6

J1.6 Transceiver RX bit 6

J1.7 Transceiver TX bit 6n

J1.8 Transceiver RX bit 6n

J1.9 Transceiver TX bit 5

J1.10 Transceiver RX bit 5

J1.11 Transceiver TX bit 5n

J1.12 Transceiver RX bit 5n

J1.13 Transceiver TX bit 4

J1.14 Transceiver RX bit 4

J1.15 Transceiver TX bit 4n

J1.16 Transceiver RX bit 4n

J1.17 Transceiver TX bit 3

J1.18 Transceiver RX bit 3

J1.19 Transceiver TX bit 3n

J1.20 Transceiver RX bit 3n

J1.21 Transceiver TX bit 2

J1.22 Transceiver RX bit 2

J1.23 Transceiver TX bit 2n

J1.24 Transceiver RX bit 2n

J1.25 Transceiver TX bit 1

J1.26 Transceiver RX bit 1

J1.27 Transceiver TX bit 1n

J1.28 Transceiver RX bit 1n

J1.29 Transceiver TX bit 0

J1.30 Transceiver RX bit 0

J1.31 Transceiver TX bit 0n

J1.32 Transceiver RX bit 0n

Schematic Signal

Name

HSMA_TX_P7

HSMA_RX_P7

HSMA_TX_N7

HSMA_RX_N7

HSMA_TX_P6

HSMA_RX_P6

HSMA_TX_N6

HSMA_RX_N6

HSMA_TX_P5

HSMA_RX_P5

HSMA_TX_N5

HSMA_RX_N5

HSMA_TX_P4

HSMA_RX_P4

HSMA_TX_N4

HSMA_RX_N4

HSMA_TX_P3

HSMA_RX_P3

HSMA_TX_N3

HSMA_RX_N3

HSMA_TX_P2

HSMA_RX_P2

HSMA_TX_N2

HSMA_RX_N2

HSMA_TX_P1

HSMA_RX_P1

HSMA_TX_N1

HSMA_RX_N1

HSMA_TX_P0

HSMA_RX_P0

HSMA_TX_N0

HSMA_RX_N0

I/O Standard

1.4-V PCML

Stratix IV GX

Device

Pin Number

AB4

AC2

AB3

AC1

AD4

AE2

AD3

AE1

AF4

AG2

AF3

AG1

AH4

AJ2

AH3

AJ1

AP4

AR2

AP3

AR1

AT4

AU2

AT3

AU1

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Chapter 2: Board Components 2–37

Components and Interfaces

Table 2–37. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board

Reference

Description

J1.33 Management serial data

J1.34 Management serial clock

J1.35 JTAG clock signal

J1.36 JTAG mode select signal

J1.37 JTAG data output

J1.38 JTAG data input

J1.39 Dedicated CMOS clock out

J1.40 Dedicated CMOS clock in

J1.41 Dedicated CMOS I/O bit 0

J1.42 Dedicated CMOS I/O bit 1

J1.43 Dedicated CMOS I/O bit 2

J1.44 Dedicated CMOS I/O bit 3

J1.47 LVDS TX bit 0 or CMOS bit 4

J1.48 LVDS RX bit 0 or CMOS bit 5

J1.49 LVDS TX bit 0n or CMOS bit 6

J1.50 LVDS RX bit 0n or CMOS bit 7

J1.53 LVDS TX bit 1 or CMOS bit 8

J1.54 LVDS RX bit 1 or CMOS bit 9

J1.55 LVDS TX bit 1n or CMOS bit 10

J1.56 LVDS RX bit 1n or CMOS bit 11

J1.59 LVDS TX bit 2 or CMOS bit 12

J1.60 LVDS RX bit 2 or CMOS bit 13

J1.61 LVDS TX bit 2n or CMOS bit 14

J1.62 LVDS RX bit 2n or CMOS bit 15

J1.65 LVDS TX bit 3 or CMOS bit 16

J1.66 LVDS RX bit 3 or CMOS bit 17

J1.67 LVDS TX bit 3n or CMOS bit 18

J1.68 LVDS RX bit 3n or CMOS bit 19

J1.71 LVDS TX bit 4 or CMOS bit 20

J1.72 LVDS RX bit 4 or CMOS bit 21

J1.73 LVDS TX bit 4n or CMOS bit 22

J1.74 LVDS RX bit 4n or CMOS bit 23

J1.77 LVDS TX bit 5 or CMOS bit 24

J1.78 LVDS RX bit 5 or CMOS bit 25

J1.79 LVDS TX bit 5n or CMOS bit 26

J1.80 LVDS RX bit 5n or CMOS bit 27

J1.83 LVDS TX bit 6 or CMOS bit 28

J1.84 LVDS RX bit 6 or CMOS bit 29

Schematic Signal

Name

HSMA_SDA

HSMA_SCL

FPGA_JTAG_TCK

FPGA_JTAG_TMS

HSMA_JTAG_TDO

HSMA_JTAG_TDI

HSMA_CLK_OUT0

HSMA_CLK_IN0

HSMA_D0

HSMA_D1

HSMA_D2

HSMA_D3

HSMA_TX_D_P0

HSMA_RX_D_P0

HSMA_TX_D_N0

HSMA_RX_D_N0

HSMA_TX_D_P1

HSMA_RX_D_P1

HSMA_TX_D_N1

HSMA_RX_D_N1

HSMA_TX_D_P2

HSMA_RX_D_P2

HSMA_TX_D_N2

HSMA_RX_D_N2

HSMA_TX_D_P3

HSMA_RX_D_P3

HSMA_TX_D_N3

HSMA_RX_D_N3

HSMA_TX_D_P4

HSMA_RX_D_P4

HSMA_TX_D_N4

HSMA_RX_D_N4

HSMA_TX_D_P5

HSMA_RX_D_P5

HSMA_TX_D_N5

HSMA_RX_D_N5

HSMA_TX_D_P6

HSMA_RX_D_P6

I/O Standard

2.5-V

LVDS or 2.5-V

Stratix IV GX

Device

Pin Number

AJ11

L11

—

AM29

AB34

AW10

AV10

AW7

AV7

AN9

AT9

AP9

AU9

AN7

AT8

AP7

AU8

AE13

AP8

AE12

AR8

AL8

AW6

AM8

AW5

AK9

AV5

AL9

AW4

AK8

AT7

AK7

AU7

AH10

AT6

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–38 Chapter 2: Board Components

Components and Interfaces

Table 2–37. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Board

Reference

Description

J1.85 LVDS TX bit 6n or CMOS bit 30

J1.86 LVDS RX bit 6n or CMOS bit 31

J1.89 LVDS TX bit 7 or CMOS bit 32

J1.90 LVDS RX bit 7 or CMOS bit 33

J1.91 LVDS TX bit 7n or CMOS bit 34

J1.92 LVDS RX bit 7n or CMOS bit 35

J1.95 LVDS or CMOS clock out 1 or CMOS bit 36

J1.96 LVDS or CMOS clock in 1 or CMOS bit 37

J1.97 LVDS or CMOS clock out 1 or CMOS bit 38

J1.98 LVDS or CMOS clock in 1 or CMOS bit 39

J1.101 LVDS TX bit 8 or CMOS bit 40

J1.102 LVDS RX bit 8 or CMOS bit 41

J1.103 LVDS TX bit 8n or CMOS bit 42

J1.104 LVDS RX bit 8n or CMOS bit 43

J1.107 LVDS TX bit 9 or CMOS bit 44

J1.108 LVDS RX bit 9 or CMOS bit 45

J1.109 LVDS TX bit 9n or CMOS bit 46

J1.110 LVDS RX bit 9n or CMOS bit 47

J1.113 LVDS TX bit 10 or CMOS bit 48

J1.114 LVDS RX bit 10 or CMOS bit 49

J1.115 LVDS TX bit 10n or CMOS bit 50

J1.116 LVDS RX bit 10n or CMOS bit 51

J1.119 LVDS TX bit 11 or CMOS bit 52

J1.120 LVDS RX bit 11 or CMOS bit 53

J1.121 LVDS TX bit 11n or CMOS bit 54

J1.122 LVDS RX bit 11n or CMOS bit 55

J1.125 LVDS TX bit 12 or CMOS bit 56

J1.126 LVDS RX bit 12 or CMOS bit 57

J1.127 LVDS TX bit 12n or CMOS bit 58

J1.128 LVDS RX bit 12n or CMOS bit 59

J1.131 LVDS TX bit 13 or CMOS bit 60

J1.132 LVDS RX bit 13 or CMOS bit 61

J1.133 LVDS TX bit 13n or CMOS bit 62

J1.134 LVDS RX bit 13n or CMOS bit 63

J1.137 LVDS TX bit 14 or CMOS bit 64

J1.138 LVDS RX bit 14 or CMOS bit 65

J1.139 LVDS TX bit 14n or CMOS bit 66

J1.140 LVDS RX bit 14n or CMOS bit 67

Schematic Signal

Name

HSMA_TX_D_N6

HSMA_RX_D_N6

HSMA_TX_D_P7

HSMA_RX_D_P7

HSMA_TX_D_N7

HSMA_RX_D_N7

HSMA_CLK_OUT_P1

HSMA_CLK_IN_P1

HSMA_CLK_OUT_N1

HSMA_CLK_IN_N1

HSMA_TX_D_P8

HSMA_RX_D_P8

HSMA_TX_D_N8

HSMA_RX_D_N8

HSMA_TX_D_P9

HSMA_RX_D_P9

HSMA_TX_D_N9

HSMA_RX_D_N9

HSMA_TX_D_P10

HSMA_RX_D_P10

HSMA_TX_D_N10

HSMA_RX_D_N10

HSMA_TX_D_P11

HSMA_RX_D_P11

HSMA_TX_D_N11

HSMA_RX_D_N11

HSMA_TX_D_P12

HSMA_RX_D_P12

HSMA_TX_D_N12

HSMA_RX_D_N12

HSMA_TX_D_P13

HSMA_RX_D_P13

HSMA_TX_D_N13

HSMA_RX_D_N13

HSMA_TX_D_P14

HSMA_RX_D_P14

HSMA_TX_D_N14

HSMA_RX_D_N14

I/O Standard

LVDS or 2.5-V

Stratix IV GX

Device

Pin Number

AJ10

AU6

AH9

AR5

AH8

AT5

AL10

AC6

AM10

AC5

AG8

AP6

AG7

AP5

AG10

AN6

AG9

AN5

AF11

AM6

AF10

AM5

AD10

AL6

AD9

AL5

AE11

AK6

AE10

AK5

AD13

AJ6

AD12

AJ5

AB13

AH6

AB12

AH5

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–39

Components and Interfaces

Table 2–37. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)

Board

Reference

Description

J1.143 LVDS TX bit 15 or CMOS bit 68

J1.144 LVDS RX bit 15 or CMOS bit 69

J1.145 LVDS TX bit 15n or CMOS bit 70

J1.146 LVDS RX bit 15n or CMOS bit 71

J1.149 LVDS TX bit 16 or CMOS bit 72

J1.150 LVDS RX bit 16 or CMOS bit 73

J1.151 LVDS TX bit 16n or CMOS bit 74

J1.152 LVDS RX bit 16n or CMOS bit 75

J1.155 LVDS or CMOS clock out 2 or CMOS bit 76

J1.156 LVDS or CMOS clock in 2 or CMOS bit 77

J1.157 LVDS or CMOS clock out 2 or CMOS bit 78

J1.158 LVDS or CMOS clock in 2 or CMOS bit 79

J1.160 HSMC Port A presence detect

User LED to show RX data activity on HSMC Port A

User LED to show TX data activity on HSMC Port A

Schematic Signal

Name

HSMA_TX_D_P15

HSMA_RX_D_P15

HSMA_TX_D_N15

HSMA_RX_D_N15

HSMA_TX_D_P16

HSMA_RX_D_P16

HSMA_TX_D_N16

HSMA_RX_D_N16

HSMA_CLK_OUT_P2

HSMA_CLK_IN_P2

HSMA_CLK_OUT_N2

HSMA_CLK_IN_N2

HSMA_PRSNTn

HSMA_RX_LED

HSMA_TX_LED

I/O Standard

LVDS or 2.5-V

2.5-V

Stratix IV GX

Device

Pin Number

AB11

AG6

AB10

AG5

AC11

AB9

AC10

AC8

AF13

AF6

AG13

AE5

AG12

Tab le 2 –3 8 lists the HSMC port B interface pin assignments, signal names, and

functions.

Table 2–38. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board

Reference

J2.1 Transceiver TX bit 7

J2.2 Transceiver RX bit 7

J2.3 Transceiver TX bit 7n

J2.4 Transceiver RX bit 7n

J2.5 Transceiver TX bit 6

J2.6 Transceiver RX bit 6

J2.7 Transceiver TX bit 6n

J2.8 Transceiver RX bit 6n

J2.9 Transceiver TX bit 5

J2.10 Transceiver RX bit 5

J2.11 Transceiver TX bit 5n

J2.12 Transceiver RX bit 5n

J2.13 Transceiver TX bit 4

J2.14 Transceiver RX bit 4

J2.15 Transceiver TX bit 4n

Description Schematic Signal

Name

HSMB_TX_P7

HSMB_RX_P7

HSMB_TX_N7

HSMB_RX_N7

HSMB_TX_P6

HSMB_RX_P6

HSMB_TX_N6

HSMB_RX_N6

HSMB_TX_P5

HSMB_RX_P5

HSMB_TX_N5

HSMB_RX_N5

HSMB_TX_P4

HSMB_RX_P4

HSMB_TX_N4

I/O Standard

1.4-V PCML

Stratix IV GX

Device

Pin Number

—

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–40 Chapter 2: Board Components

Components and Interfaces

Table 2–38. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board

Reference

Description Schematic Signal

J2.16 Transceiver RX bit 4n

J2.17 Transceiver TX bit 3

J2.18 Transceiver RX bit 3

J2.19 Transceiver TX bit 3n

J2.20 Transceiver RX bit 3n

J2.21 Transceiver TX bit 2

J2.22 Transceiver RX bit 2

J2.23 Transceiver TX bit 2n

J2.24 Transceiver RX bit 2n

J2.25 Transceiver TX bit 1

J2.26 Transceiver RX bit 1

J2.27 Transceiver TX bit 1n

J2.28 Transceiver RX bit 1n

J2.29 Transceiver TX bit 0

J2.30 Transceiver RX bit 0

J2.31 Transceiver TX bit 0n

J2.32 Transceiver RX bit 0n

J2.33 Management serial data

J2.34 Management serial clock

J2.35 JTAG clock signal

J2.36 JTAG mode select signal

J2.37 JTAG data output

J2.38 JTAG data input

J2.39 Dedicated CMOS clock out

J2.40 Dedicated CMOS clock in

J2.41 Dedicated CMOS I/O bit 0

J2.42 Dedicated CMOS I/O bit 1

J2.43 Dedicated CMOS I/O bit 2

J2.44 Dedicated CMOS I/O bit 3

J2.47 LVDS TX bit 0 or CMOS bit 4

J2.48 LVDS RX bit 0 or CMOS bit 5

J2.49 LVDS TX bit 0n or CMOS bit 6

J2.50 LVDS RX bit 0n or CMOS bit 7

J2.53 LVDS TX bit 1 or CMOS bit 8

J2.54 LVDS RX bit 1 or CMOS bit 9

J2.55 LVDS TX bit 1n or CMOS bit 10

J2.56 LVDS RX bit 1n or CMOS bit 11

J2.59 LVDS TX bit 2 or CMOS bit 12

Name

HSMB_RX_N4

HSMB_TX_P3

HSMB_RX_P3

HSMB_TX_N3

HSMB_RX_N3

HSMB_TX_P2

HSMB_RX_P2

HSMB_TX_N2

HSMB_RX_N2

HSMB_TX_P1

HSMB_RX_P1

HSMB_TX_N1

HSMB_RX_N1

HSMB_TX_P0

HSMB_RX_P0

HSMB_TX_N0

HSMB_RX_N0

HSMB_SDA

HSMB_SCL

FPGA_JTAG_TCK

FPGA_JTAG_TMS

HSMB_JTAG_TDO

HSMB_JTAG_TDI

HSMB_CLK_OUT0

HSMB_CLK_IN0

HSMB_D0

HSMB_D1

HSMB_D2

HSMB_D3

HSMB_TX_D_P0

HSMB_RX_D_P0

HSMB_TX_D_N0

HSMB_RX_D_N0

HSMB_TX_D_P1

HSMB_RX_D_P1

HSMB_TX_D_N1

HSMB_RX_D_N1

HSMB_TX_D_P2

I/O Standard

1.4-V PCML

2.5-V

LVDS or 2.5-V

Stratix IV GX

Device

Pin Number

B36

C38

B37

C39

D36

E38

D37

E39

K36

L38

K37

L39

M36

N38

M37

N39

AF29

AB27

—

AK29

AA35

AP10

AN10

AW8

AV8

W12

W11

V12

V11

V10

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–41

Components and Interfaces

Table 2–38. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Board

Reference

Description Schematic Signal

J2.60 LVDS RX bit 2 or CMOS bit 13

J2.61 LVDS TX bit 2n or CMOS bit 14

J2.62 LVDS RX bit 2n or CMOS bit 15

J2.65 LVDS TX bit 3 or CMOS bit 16

J2.66 LVDS RX bit 3 or CMOS bit 17

J2.67 LVDS TX bit 3n or CMOS bit 18

J2.68 LVDS RX bit 3n or CMOS bit 19

J2.71 LVDS TX bit 4 or CMOS bit 20

J2.72 LVDS RX bit 4 or CMOS bit 21

J2.73 LVDS TX bit 4n or CMOS bit 22

J2.74 LVDS RX bit 4n or CMOS bit 23

J2.77 LVDS TX bit 5 or CMOS bit 24

J2.78 LVDS RX bit 5 or CMOS bit 25

J2.79 LVDS TX bit 5n or CMOS bit 26

J2.80 LVDS RX bit 5n or CMOS bit 27

J2.83 LVDS TX bit 6 or CMOS bit 28

J2.84 LVDS RX bit 6 or CMOS bit 29

J2.85 LVDS TX bit 6n or CMOS bit 30

J2.86 LVDS RX bit 6n or CMOS bit 31

J2.89 LVDS TX bit 7 or CMOS bit 32

J2.90 LVDS RX bit 7 or CMOS bit 33

J2.91 LVDS TX bit 7n or CMOS bit 34

J2.92 LVDS RX bit 7n or CMOS bit 35

J2.95 LVDS or CMOS clock out 1 or CMOS bit 36

J2.96 LVDS or CMOS clock in 1 or CMOS bit 37

J2.97 LVDS or CMOS clock out 1 or CMOS bit 38

J2.98 LVDS or CMOS clock in 1 or CMOS bit 39

J2.101 LVDS TX bit 8 or CMOS bit 40

J2.102 LVDS RX bit 8 or CMOS bit 41

J2.103 LVDS TX bit 8n or CMOS bit 42

J2.104 LVDS RX bit 8n or CMOS bit 43

J2.107 LVDS TX bit 9 or CMOS bit 44

J2.108 LVDS RX bit 9 or CMOS bit 45

J2.109 LVDS TX bit 9n or CMOS bit 46

J2.110 LVDS RX bit 9n or CMOS bit 47

J2.113 LVDS TX bit 10 or CMOS bit 48

J2.114 LVDS RX bit 10 or CMOS bit 49

J2.115 LVDS TX bit 10n or CMOS bit 50

Name

HSMB_RX_D_P2

HSMB_TX_D_N2

HSMB_RX_D_N2

HSMB_TX_D_P3

HSMB_RX_D_P3

HSMB_TX_D_N3

HSMB_RX_D_N3

HSMB_TX_D_P4

HSMB_RX_D_P4

HSMB_TX_D_N4

HSMB_RX_D_N4

HSMB_TX_D_P5

HSMB_RX_D_P5

HSMB_TX_D_N5

HSMB_RX_D_N5

HSMB_TX_D_P6

HSMB_RX_D_P6

HSMB_TX_D_N6

HSMB_RX_D_N6

HSMB_TX_D_P7

HSMB_RX_D_P7

HSMB_TX_D_N7

HSMB_RX_D_N7

HSMB_CLK_OUT_P1

HSMB_CLK_IN_P1

HSMB_CLK_OUT_N1

HSMB_CLK_IN_N1

HSMB_TX_D_P8

HSMB_RX_D_P8

HSMB_TX_D_N8

HSMB_RX_D_N8

HSMB_TX_D_P9

HSMB_RX_D_P9

HSMB_TX_D_N9

HSMB_RX_D_N9

HSMB_TX_D_P10

HSMB_RX_D_P10

HSMB_TX_D_N10

I/O Standard

LVDS or 2.5-V

Stratix IV GX

Device

Pin Number

U10

T10

R10

N11

N10

AB6

AA5

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–42 Chapter 2: Board Components

Components and Interfaces

Table 2–38. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)

Board

Reference

Description Schematic Signal

J2.116 LVDS RX bit 10n or CMOS bit 51

J2.119 LVDS TX bit 11 or CMOS bit 52

J2.120 LVDS RX bit 11 or CMOS bit 53

J2.121 LVDS TX bit 11n or CMOS bit 54

J2.122 LVDS RX bit 11n or CMOS bit 55

J2.125 LVDS TX bit 12 or CMOS bit 56

J2.126 LVDS RX bit 12 or CMOS bit 57

J2.127 LVDS TX bit 12n or CMOS bit 58

J2.128 LVDS RX bit 12n or CMOS bit 59

J2.131 LVDS TX bit 13 or CMOS bit 60

J2.132 LVDS RX bit 13 or CMOS bit 61

J2.133 LVDS TX bit 13n or CMOS bit 62

J2.134 LVDS RX bit 13n or CMOS bit 63

J2.137 LVDS TX bit 14 or CMOS bit 64

J2.138 LVDS RX bit 14 or CMOS bit 65

J2.139 LVDS TX bit 14n or CMOS bit 66

J2.140 LVDS RX bit 14n or CMOS bit 67

J2.143 LVDS TX bit 15 or CMOS bit 68

J2.144 LVDS RX bit 15 or CMOS bit 69

J2.145 LVDS TX bit 15n or CMOS bit 70

J2.146 LVDS RX bit 15n or CMOS bit 71

J2.149 LVDS TX bit 16 or CMOS bit 72

J2.150 LVDS RX bit 16 or CMOS bit 73

J2.151 LVDS TX bit 16n or CMOS bit 74

J2.152 LVDS RX bit 16n or CMOS bit 75

J2.155 LVDS or CMOS clock out 2 or CMOS bit 76

J2.156 LVDS or CMOS clock in 2 or CMOS bit 77

J2.157 LVDS or CMOS clock out 2 or CMOS bit 78

J2.158 LVDS or CMOS clock in 2 or CMOS bit 79

J2.160 HSMC Port B presence detect

D15

D14

User LED to show RX data activity on HSMC Port B

User LED to show TX data activity on HSMC Port B

Name

HSMB_RX_D_N10

HSMB_TX_D_P11

HSMB_RX_D_P11

HSMB_TX_D_N11

HSMB_RX_D_N11

HSMB_TX_D_P12

HSMB_RX_D_P12

HSMB_TX_D_N12

HSMB_RX_D_N12

HSMB_TX_D_P13

HSMB_RX_D_P13

HSMB_TX_D_N13

HSMB_RX_D_N13

HSMB_TX_D_P14

HSMB_RX_D_P14

HSMB_TX_D_N14

HSMB_RX_D_N14

HSMB_TX_D_P15

HSMB_RX_D_P15

HSMB_TX_D_N15

HSMB_RX_D_N15

HSMB_TX_D_P16

HSMB_RX_D_P16

HSMB_TX_D_N16

HSMB_RX_D_N16

HSMB_CLK_OUT_P2

HSMB_CLK_IN_P2

HSMB_CLK_OUT_N2

HSMB_CLK_IN_N2

HSMB_PRSNTn

HSMB_RX_LED

HSMB_TX_LED

I/O Standard

LVDS or 2.5-V

2.5-V

Stratix IV GX

Device

Pin Number

M10

L10

R12

R11

T13

T12

R13

F10

P13

E10

K10

J10

AT10

AH33

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–43

Components and Interfaces

Tab le 2 –3 9 lists the HSMC connector component reference and manufacturing

information.

Table 2–39. HSMC Connector Component Reference and Manufacturing Information

Board Reference Description Manufacturer

J1 and J2

HSMC, custom version of QSH-DP family high-speed socket.

Samtec ASP-122953-01 www.samtec.com

HDMI Video Output

The Stratix IV GX FPGA Development Board, 530 Edition supports a single HDMI video output port based on the Analog Devices AD9889B HDMI transmitter device.

With the capability of up to 80 MHz operation, this device supports all video resolutions from 480i to 1080i and UXGA at 60 Hz. This device also features a programmable two-way color space converter which supports RGB, YCbCr, and DDR, as well as ITU656-based embedded syncs and an automatic input video format timing detection (CEA-861B) circuit.

On the digital audio aspect, this device supports standard S/PDIF for stereo LPCM or compressed audio of up to 192 kHz. This device also supports 8-channel, uncompressed, LPCM I2S audio of up to 192 kHz. No audio master clock is needed for supporting S/PDIF and I2S.

This device supports an on-chip microcontroller (MCU) with I HDCP operations and EDID reading operations although the board does not have an HDCP EEPROM installed by default. The on-chip MPU, accessible from the FPGA through the serial port, reports HDMI events through interrupts and registers.

Manufacturing

Part Number

Manufacturer

Website

2C®

master to perform

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–44 Chapter 2: Board Components

Components and Interfaces

Figure 2–12 shows a block diagram of the AD9889B HDMI transmitter device.

Figure 2–12. AD9889B HDMI Transmitter Device Block Diagram

CLK

VSYNC

HSYNC

D [23:0]

S/PDIF

MCLK

S [3:0]

LRCLK

SCLK

SCL

SDA

I2C Slave

Logic

Video Data

Capture

Audio

Data

Capture

MCL MDA

Color

Space

Conversion

4:2:2 to 4:4:4

Conversion

HDCP

Core

XOR Mask

INT

Interrupt Handler

HDCP-EDID

Microcontroller

C Master

HDMI

Core

AD9889B

HPD

DDCSDA

DDCSCL

Tx0– /Tx0+

Tx1– / Tx1+

Tx2– / Tx2+

TxC– / TxC+

Tab le 2 –4 0 summarizes the HDMI video output interface pin assignments, signal

names, and functions.

Table 2–40. HDMI Video Output Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)

Board Reference Description Schematic Signal

I/O Standard

Name

U25.B1 Video data bus

U25.A1 Video data bus

U25.B2 Video data bus

U25.A2 Video data bus

U25.B3 Video data bus

U25.A3 Video data bus

U25.B4 Video data bus

U25.A4 Video data bus

U25.B5 Video data bus

U25.A5 Video data bus

U25.B6 Video data bus

HDMI_D0

HDMI_D1

HDMI_D2

HDMI_D3

HDMI_D4

HDMI_D5

HDMI_D6

HDMI_D7

HDMI_D8

HDMI_D9

HDMI_D10

1.8-V

Stratix IV GX

Device

Pin Number

AW34

AL25

AK25

AP26

AH26

AM26

AK26

AN26

AP27

AN27

AV28

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–45

Components and Interfaces

Table 2–40. HDMI Video Output Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)

Stratix IV GX

Board Reference Description Schematic Signal

Name

U25.A6 Video data bus

U25.B7 Video data bus

U25.A7 Video data bus

U25.B8 Video data bus

U25.A8 Video data bus

U25.B9 Video data bus

U25.A9 Video data bus

U25.B10 Video data bus

U25.A10 Video data bus

U25.C9 Video data bus

U25.C10 Video data bus

U25.D9 Video data bus

U25.D10 Video data bus

U25.D1 Video data bus clock

U25.C2 Video data bus DE

U25.C1 Video data bus HSYNC

U25.D2 Video data bus VSYNC

U25.E2 Audio SPDIF data

U25.E1 Audio SPDIF clock

U25.F2 Audio I

U25.F1 Audio I

U25.G2 Audio I

U25.G1 Audio I

U25.H2 Audio I

S bus

S bus clock

U25.H1 Audio LR clock

U25.F9 Management bus clock

U25.F10 Management bus data

U25.H10 Management bus interrupt

HDMI_D11

HDMI_D12

HDMI_D13

HDMI_D14

HDMI_D15

HDMI_D16

HDMI_D17

HDMI_D18

HDMI_D19

HDMI_D20

HDMI_D21

HDMI_D22

HDMI_D23

HDMI_CLK

HDMI_DE

HDMI_HSYNC

HDMI_VSYNC

HDMI_SPDIF

HDMI_MCLK

HDMI_I2S0

HDMI_I2S1

HDMI_I2S2

HDMI_I2S3

HDMI_SCLK

HDMI_LRCLK

HDMI_SDA

HDMI_SCL

HDMI_INTn

I/O Standard

1.8-V

Device

Pin Number

AW29

AW27

AW28

AV29

AW30

AW31

AV31

AV32

AW32

AW33

AJ25

AL27

AJ26

AD25

AK27

AE24

AE25

AR28

AP28

AT29

AU29

AU28

AT28

AH24

AG24

AU27

AT27

AV23

Tab le 2 –4 1 lists the HDMI video output component reference and manufacturing

information.

Table 2–41. HDMI Video Output Connector Component Reference and Manufacturing Information

Board Reference Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

U25 HDMI transmitter Analog Devices AD9889BBBCZ-80 www.analog.com

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–46 Chapter 2: Board Components

Differential

Input

ENABLE

LMH0302

1.0 μF

5.6 nH

75 Ω

750 Ω

75 Ω 75 Ω

49.9 Ω

1.0 μF

0.1 μF

4.7 μF

5.6 nH

SD/HD

SDO

ENABLE

SDI

REF

Components and Interfaces

SDI Video Input/Output

The serial digital interface (SDI) video port consists of a LMH0302SQ cable driver and a LMH0344 receiver cable equalizer. The PHY devices from National Semiconductor interface to single-ended 75-Ω SMB connectors which extends out through the PCI Express bracket for easy use while installed in a host PC.

The LMH0302SQ driver supports operation at 270 Mbit standard definition (SD),

1.5 Gbit high definition (HD), and 3.0 Gbit dual-link HD modes. Control signals are allowed for SD and HD modes selections, as well as device enable. The device can be clocked by the 148.5 MHz voltage-controlled crystal oscillator (VCXO) and matched to incoming signals within 50 ppm using the UP and DN voltage control lines to the VCXO.

Tab le 2 –4 2 shows the supported output standards for the SD and HD input.

Table 2–42. Supported Output Standards for SD and HD Input

SD_HD Input Supported Output Standards Rise TIme

0 SMPTE 424M, SMPTE 292M Faster

1 SMPTE 259M Slower

Tab le 2 –4 3 summarizes the SDI video output interface pin assignments. The signal

names and directions are relative to the Stratix IV GX FPGA.

Table 2–43. SDI Video Output Interface Pin Assignments, Schematic Signal Names, and Functions

Board

Reference

Description

U4.1 SDI video output P

U4.2 SDI video output N

U4.6 Device enable

U4.10 High definition select

Schematic

Signal Name

SDI_TX_P

SDI_TX_N

SDI_TX_EN

SDI_TX_SD_HDn

I/O Standard

1.4-V PCML

2.5-V

Figure 2–13 shows the SDI cable driver.

Figure 2–13. SDI Cable Driver

Stratix IV GX Device

Pin Number

V29

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–47

BYPASS

MUTE

REF

1.0 μF

75 Ω

37.4 Ω

1.0 μF

SDI

SDO

MUTE

REF

BYPASS

AEC+

AEC–

75 Ω

MUTE

Coaxial Cable

LMH0344 3G SDI

Adaptive Cable

Equalizer

To FPGA

3.9 nH

Components and Interfaces

The LMH0344 cable equalizer supports operation at 270 Mbit SD, 1.5 Gbit HD, and

3.0 Gbit dual-link HD modes. Control signals are allowed for bypassing or disabling the device, as well as a carrier detect or auto-mute signal interface.

Tab le 2 –4 4 shows the cable equalizer lengths.

Table 2–44. SDI Cable Equalizer Lengths

Data Rate (Mbps) Cable Type Maximum Cable Length (m)

270

1485 140

Belden 1694A

400

2970 120

Tab le 2 –4 5 summarizes the SDI video input interface pin assignments. The signal

names and directions are relative to the Stratix IV GX FPGA.

Table 2–45. SDI Video Input Interface Pin Assignments, Schematic Signal Names, and Functions

Board

Reference

Description

U2.11 SDI video input P

U2.10 SDI video input N

U2.7 Bypass enable

U2.14 Device enable

Figure 2–14 shows the SDI cable equalizer.

Figure 2–14. SDI Cable Equalizer

Schematic

Signal Name

SDI_RX_P

SDI_RX_N

SDI_RX_BYPASS

SDI_RX_EN

I/O Standard

1.4-V PCML

2.5-V

MAX II CPLD EPM2210

System Controller

Pin Number

—L2

—L1

T4 —

Stratix IV GX Device

Pin Number

—

(Automatically driven

by carrier detect)

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–48 Chapter 2: Board Components

Memory

This section describes the board’s memory interface support, signal names, types, and connectivity relative to the Stratix IV GX device. The board has the following memory interfaces:

■ DDR3 Bottom Port

■ DDR3 Top Port

■ QDRII+ Top Port 0

■ QDRII+ Top Port 1

■ SSRAM

■ Flash

f For more information about the memory interfaces, refer to the External Memory

Interface Handbook.

DDR3 Bottom Port

The DDR3 bottom port consists of four DDR3 devices, providing a single 512-Mbyte interface with a 64-bit data bus. The board supports addressing for up to 4 times the memory if larger devices become available.

This memory interface is designed to run between 300 MHz, the minimum frequency for DDR3, and 533 MHz for a maximum theoretical bandwidth of over 68.2 Gbps. The internal bus in the FPGA is typically 2 or 4 times the width at full-rate or half-rate respectively. For example, a 533 MHz 64-bit interface will become a 267 MHz 256-bit bus.

Tab le 2 –4 6 lists the DDR3 DIMM pin assignments, signal names, and functions. The

signal names and types are relative to the Stratix IV device in terms of I/O setting and direction.

Table 2–46. DDR3 Bottom Port Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board Reference Description Schematic Signal

Name

U5, U12, U18, U24 pin T7 Address bus

U5, U12, U18, U24 pin T3 Address bus

U5, U12, U18, U24 pin N7 Address bus

U5, U12, U18, U24 pin R7 Address bus

U5, U12, U18, U24 pin L7 Address bus

U5, U12, U18, U24 pin R3 Address bus

U5, U12, U18, U24 pin T8 Address bus

U5, U12, U18, U24 pin R2 Address bus

U5, U12, U18, U24 pin R8 Address bus

U5, U12, U18, U24 pin P2 Address bus

U5, U12, U18, U24 pin P8 Address bus

U5, U12, U18, U24 pin N2 Address bus

DDR3BOT_A14

DDR3BOT_A13

DDR3BOT_A12

DDR3BOT_A11

DDR3BOT_A10

DDR3BOT_A9

DDR3BOT_A8

DDR3BOT_A7

DDR3BOT_A6

DDR3BOT_A5

DDR3BOT_A4

DDR3BOT_A3

I/O Standard

1.5-V SSTL Class I

Stratix IV GX

Device

Pin Number

AJ14

AN15

AE14

AJ13

AE16

AK14

AH13

AP15

AG14

AL15

AF16

AT14

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–49

Memory

Table 2–46. DDR3 Bottom Port Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Stratix IV GX

Board Reference Description Schematic Signal

Name

U5, U12, U18, U24 pin P3 Address bus

U5, U12, U18, U24 pin P7 Address bus

U5, U12, U18, U24 pin N3 Address bus

U5, U12, U18, U24 pin M3 Bank address bus

U5, U12, U18, U24 pin J3 Row address select

U5, U12, U18, U24 pin K3 Column address select

U5, U12, U18, U24 pin L2 Chip select

U5, U12, U18, U24 pin L3 Write enable

U5, U12, U18, U24 pin K1 Termination enable

U5, U12, U18, U24 pin K9 Clock enable

U5, U12, U18, U24 pin J7 Clock P

U5, U12, U18, U24 pin K7 Clock N

U5.E3 Data bus byte lane 0

U5.F7 Data bus byte lane 0

U5.F2 Data bus byte lane 0

U5.F8 Data bus byte lane 0

U5.H3 Data bus byte lane 0

U5.H8 Data bus byte lane 0

U5.G2 Data bus byte lane 0

U5.H7 Data bus byte lane 0

U5.E7 Write mask byte lane 0

U5.F3 Data strobe P byte lane 0

U5.G3 Data strobe N byte lane 0

U5.D7 Data bus byte lane 1

U5.C3 Data bus byte lane 1

U5.C8 Data bus byte lane 1

U5.C2 Data bus byte lane 1

U5.A7 Data bus byte lane 1

U5.A2 Data bus byte lane 1

U5.B8 Data bus byte lane 1

U5.A3 Data bus byte lane 1

U5.D3 Write mask byte lane 1

U5.C7 Data strobe P byte lane 1

U5.B7 Data strobe N byte lane 1

U12.E3 Data bus byte lane 2

U12.F7 Data bus byte lane 2

DDR3BOT_A2

DDR3BOT_A1

DDR3BOT_A0

DDR3BOT_BA2

DDR3BOT_BA1

DDR3BOT_BA0

DDR3BOT_RASn

DDR3BOT_CASn

DDR3BOT_CSn

DDR3BOT_WEn

DDR3BOT_ODT

DDR3BOT_CKE

DDR3BOT_CK_P

DDR3BOT_CK_N

DDR3BOT_DQ0

DDR3BOT_DQ1

DDR3BOT_DQ2

DDR3BOT_DQ3

DDR3BOT_DQ4

DDR3BOT_DQ5

DDR3BOT_DQ6

DDR3BOT_DQ7

DDR3BOT_DM0

DDR3BOT_DQS_P0

DDR3BOT_DQS_N0

DDR3BOT_DQ8

DDR3BOT_DQ9

DDR3BOT_DQ10

DDR3BOT_DQ11

DDR3BOT_DQ12

DDR3BOT_DQ13

DDR3BOT_DQ14

DDR3BOT_DQ15

DDR3BOT_DM1

DDR3BOT_DQS_P1

DDR3BOT_DQS_N1

DDR3BOT_DQ16

DDR3BOT_DQ17

I/O Standard

1.5-V SSTL Class I

Device

Pin Number

AH14

AG15

AK13

AE15

AD15

AF14

AW21

AV19

AN20

AW20

AU20

AW19

AE20

AF20

AM14

AM13

AN14

AL14

AR14

AN13

AP14

AP13

AL13

AR13

AT13

AT12

AW14

AU12

AV14

AW11

AU14

AV11

AW12

AU11

AV13

AW13

AT16

AW16

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–50 Chapter 2: Board Components

Memory

Table 2–46. DDR3 Bottom Port Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Stratix IV GX

Board Reference Description Schematic Signal

Name

U12.F2 Data bus byte lane 2

U12.F8 Data bus byte lane 2

U12.H3 Data bus byte lane 2

U12.H8 Data bus byte lane 2

U12.G2 Data bus byte lane 2

U12.H7 Data bus byte lane 2

U12.E7 Write mask byte lane 2

U12.F3 Data strobe P byte lane 2

U12.G3 Data strobe N byte lane 2

U12.D7 Data bus byte lane 3

U12.C3 Data bus byte lane 3

U12.C8 Data bus byte lane 3

U12.C2 Data bus byte lane 3

U12.A7 Data bus byte lane 3

U12.A2 Data bus byte lane 3

U12.B8 Data bus byte lane 3

U12.A3 Data bus byte lane 3

U12.D3 Write mask byte lane 3

U12.C7 Data strobe P byte lane 3

U12.B7 Data strobe N byte lane 3

U18.E3 Data bus byte lane 4

U18.F7 Data bus byte lane 4

U18.F2 Data bus byte lane 4

U18.F8 Data bus byte lane 4

U18.H3 Data bus byte lane 4

U18.H8 Data bus byte lane 4

U18.G2 Data bus byte lane 4

U18.H7 Data bus byte lane 4

U18.E7 Write mask byte lane 4

U18.F3 Data strobe P byte lane 4

U18.G3 Data strobe N byte lane 4

U18.D7 Data bus byte lane 5

U18.C3 Data bus byte lane 5

U18.C8 Data bus byte lane 5

U18.C2 Data bus byte lane 5

U18.A7 Data bus byte lane 5

U18.A2 Data bus byte lane 5

U18.B8 Data bus byte lane 5

DDR3BOT_DQ18

DDR3BOT_DQ19

DDR3BOT_DQ20

DDR3BOT_DQ21

DDR3BOT_DQ22

DDR3BOT_DQ23

DDR3BOT_DM2

DDR3BOT_DQS_P2

DDR3BOT_DQS_N2

DDR3BOT_DQ24

DDR3BOT_DQ25

DDR3BOT_DQ26

DDR3BOT_DQ27

DDR3BOT_DQ28

DDR3BOT_DQ29

DDR3BOT_DQ30

DDR3BOT_DQ31

DDR3BOT_DM3

DDR3BOT_DQS_P3

DDR3BOT_DQS_N3

DDR3BOT_DQ32

DDR3BOT_DQ33

DDR3BOT_DQ34

DDR3BOT_DQ35

DDR3BOT_DQ36

DDR3BOT_DQ37

DDR3BOT_DQ38

DDR3BOT_DQ39

DDR3BOT_DM4

DDR3BOT_DQS_P4

DDR3BOT_DQS_N4

DDR3BOT_DQ40

DDR3BOT_DQ41

DDR3BOT_DQ42

DDR3BOT_DQ43

DDR3BOT_DQ44

DDR3BOT_DQ45

DDR3BOT_DQ46

I/O Standard

1.5-V SSTL Class I

Device

Pin Number

AN16

AV16

AP17

AT15

AR17

AU15

AU16

AP16

AR16

AJ16

AM17

AH16

AL17

AG16

AH17

AG17

AK17

AF17

AK16

AL16

AU23

AN23

AT23

AM23

AP23

AL22

AR23

AN22

AM22

AT24

AU24

AR19

AP19

AP18

AN19

AT18

AU18

AW18

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–51

Memory

Table 2–46. DDR3 Bottom Port Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)

Stratix IV GX

Board Reference Description Schematic Signal

Name

U18.A3 Data bus byte lane 5

U18.D3 Write mask byte lane 5

U18.C7 Data strobe P byte lane 5

U18.B7 Data strobe N byte lane 5

U24.E3 Data bus byte lane 6

U24.F7 Data bus byte lane 6

U24.F2 Data bus byte lane 6

U24.F8 Data bus byte lane 6

U24.H3 Data bus byte lane 6

U24.H8 Data bus byte lane 6

U24.G2 Data bus byte lane 6

U24.H7 Data bus byte lane 6

U24.E7 Write mask byte lane 6

U24.F3 Data strobe P byte lane 6

U24.G3 Data strobe N byte lane 6

U24.D7 Data bus byte lane 7

U24.C3 Data bus byte lane 7

U24.C8 Data bus byte lane 7

U24.C2 Data bus byte lane 7

U24.A7 Data bus byte lane 7

U24.A2 Data bus byte lane 7

U24.B8 Data bus byte lane 7

U24.A3 Data bus byte lane 7

U24.D3 Write mask byte lane 7

U24.C7 Data strobe P byte lane 7

U24.B7 Data strobe N byte lane 7

DDR3BOT_DQ47

DDR3BOT_DM5

DDR3BOT_DQS_P5

DDR3BOT_DQS_N5

DDR3BOT_DQ48

DDR3BOT_DQ49

DDR3BOT_DQ50

DDR3BOT_DQ51

DDR3BOT_DQ52

DDR3BOT_DQ53

DDR3BOT_DQ54

DDR3BOT_DQ55

DDR3BOT_DM6

DDR3BOT_DQS_P6

DDR3BOT_DQS_N6

DDR3BOT_DQ56

DDR3BOT_DQ57

DDR3BOT_DQ58

DDR3BOT_DQ59

DDR3BOT_DQ60

DDR3BOT_DQ61

DDR3BOT_DQ62

DDR3BOT_DQ63

DDR3BOT_DM7

DDR3BOT_DQS_P7

DDR3BOT_DQS_N7

I/O Standard

1.5-V SSTL Class I

Device

Pin Number

AT17

AN18

AU17

AV17

AV26

AU25

AT25

AN25

AR25

AP24

AP25

AW26

AN24

AT26

AU26

AJ23

AK24

AF23

AH23

AG22

AJ22

AH22

AE22

AF22

AK23

AL23

Tab le 2 –4 7 lists the DDR3 component reference and manufacturing information.

Table 2–47. DDR3 Component Reference and Manufacturing Information

Board Reference Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

U5, U12, U18, U24 8 M × 16-bit × 8 banks, 667M, CL9 Micron MT41J64M16LA-15E www.micron.com

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–52 Chapter 2: Board Components

Memory

DDR3 Top Port

The DDR3 top port consists of a single DDR3 devices, providing 128 Mbyte with a 16-bit data bus. The board supports addressing for up to 4 times the memory if larger devices become available.

This memory interface is designed to run between 300 MHz, the minimum frequency for DDR3, and 533 MHz for a maximum theoretical bandwidth of over 68.2 Gbps. The internal bus in the FPGA is typically 2 or 4 times the width at full rate or half rate respectively. For example, a 533 MHz 64-bit interface will become a 267 MHz 256-bit bus.

Tab le 2 –4 8 lists the DDR3 top port pin assignments, signal names, and its functions.

The signal names and types are relative to the Stratix IV device in terms of I/O setting and direction.

Table 2–48. DDR3 Top Port Pin Assignments, Signal Names and Functions (Part 1 of 2)

Stratix IV GX

Board Reference Description Schematic Signal

Name

U14.T7 Address bus

U14.T3 Address bus

U14.N7 Address bus

U14.R7 Address bus

U14.L7 Address bus

U14.R3 Address bus

U14.T8 Address bus

U14.R2 Address bus

U14.R8 Address bus

U14.P2 Address bus

U14.P8 Address bus

U14.N2 Address bus

U14.P3 Address bus

U14.P7 Address bus

U14.N3 Address bus

U14.M3 Bank address bus

U14.N8 Bank address bus

U14.M2 Bank address bus

U14.J3 Row address select

U14.K3 Column address select

U14.L2 Chip select

U14.L3 Write enable

U14.K1 Termination enable

U14.K9 Clock enable

U14.J7 Clock P

U14.K7 Clock N

DDR3TOP_A14

DDR3TOP_A13

DDR3TOP_A12

DDR3TOP_A11

DDR3TOP_A10

DDR3TOP_A9

DDR3TOP_A8

DDR3TOP_A7

DDR3TOP_A6

DDR3TOP_A5

DDR3TOP_A4

DDR3TOP_A3

DDR3TOP_A2

DDR3TOP_A1

DDR3TOP_A0

DDR3TOP_BA2

DDR3TOP_BA1

DDR3TOP_BA0

DDR3TOP_RASn

DDR3TOP_CASn

DDR3TOP_CSn

DDR3TOP_WEn

DDR3TOP_ODT

DDR3TOP_CKE

DDR3TOP_CK_P

DDR3TOP_CK_N

I/O Standard

1.5-V SSTL Class I

Device

Pin Number

B20

M22

A23

A19

B23

M21

F21

M20

G21

P19

D21

R20

N19

C22

D19

A14

E23

B14

A24

B19

D15

C19

K15

A25

D24

C24

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–53

Memory

Table 2–48. DDR3 Top Port Pin Assignments, Signal Names and Functions (Part 2 of 2)

Stratix IV GX

Board Reference Description Schematic Signal

Name

U14.E3 Data bus byte lane 0

U14.F7 Data bus byte lane 0

U14.F2 Data bus byte lane 0

U14.F8 Data bus byte lane 0

U14.H3 Data bus byte lane 0

U14.H8 Data bus byte lane 0

U14.G2 Data bus byte lane 0

U14.H7 Data bus byte lane 0

U14.E7 Write mask byte lane 0

U14.F3 Data strobe P byte lane 0

U14.G3 Data strobe N byte lane 0

U14.D7 Data bus byte lane 1

U14.C3 Data bus byte lane 1

U14.C8 Data bus byte lane 1

U14.C2 Data bus byte lane 1

U14.A7 Data bus byte lane 1

U14.A2 Data bus byte lane 1

U14.B8 Data bus byte lane 1

U14.A3 Data bus byte lane 1

U14.D3 Write mask byte lane 1

U14.C7 Data strobe P byte lane 1

U14.B7 Data strobe N byte lane 1

DDR3TOP_DQ0

DDR3TOP_DQ1

DDR3TOP_DQ2

DDR3TOP_DQ3

DDR3TOP_DQ4

DDR3TOP_DQ5

DDR3TOP_DQ6

DDR3TOP_DQ7

DDR3TOP_DM0

DDR3TOP_DQS_P0

DDR3TOP_DQS_N0

DDR3TOP_DQ8

DDR3TOP_DQ9

DDR3TOP_DQ10

DDR3TOP_DQ11

DDR3TOP_DQ12

DDR3TOP_DQ13

DDR3TOP_DQ14

DDR3TOP_DQ15

DDR3TOP_DM1

DDR3TOP_DQS_P1

DDR3TOP_DQS_N1

I/O Standard

1.5-V SSTL Class I

Device

Pin Number

A10

D11

B10

C12

C11

C13

A11

B13

B11

D14

C14

K22

D22

J22

E22

G22

F23

H22

D23

G23

J23

H23

Tab le 2 –4 9 lists the DDR3 component reference and manufacturing information.

Table 2–49. DDR3 Component Reference and Manufacturing Information

Board Reference Description Manufacturer

U14 8 M × 16-bit × 8 banks, 667M, CL9 Micron MT41J64M16LA-15E www.micron.com

Manufacturing

Part Number

Manufacturer

Website

QDRII+ Top Port 0

The QDRII+ top port 0 consists of a single QDRII+ burst-of-4 SRAM, providing 4 Mbyte with an 18-bit read data bus and an 18-bit write data bus.

This memory interface is designed to run between 120 MHz, the minimum frequency for this device, and 400 MHz for a maximum theoretical bandwidth of over 14.4 Gbps for reading and 14.4 Gbps for writing. The internal bus in the FPGA is typically 2 or 4 times the width at full rate or half rate respectively. For example, a 400 MHz 18-bit interface becomes a 200 MHz 72 bit bus.

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–54 Chapter 2: Board Components

Memory

Tab le 2 –5 0 lists the QDRII+ top port 0 pin assignments, signal names, and functions.

The signal names and types are relative to the Stratix IV GX device in terms of I/O setting and direction.

Table 2–50. QDRII+ Top Port 0 Pin Assignments, Signal Names and Functions (Part 1 of 2)

Stratix IV GX

Board Reference Description

U22.A10 Address bus

U22.A3 Address bus

U22.A9 Address bus

U22.R7 Address bus

U22.R5 Address bus

U22.R4 Address bus

U22.R3 Address bus

U22.P8 Address bus

U22.P7 Address bus

U22.P5 Address bus

U22.P4 Address bus

U22.N7 Address bus

U22.N6 Address bus

U22.N5 Address bus

U22.C7 Address bus

U22.C5 Address bus

U22.B8 Address bus

U22.B4 Address bus

U22.R8 Address bus

U22.R9 Address bus

U22.N2 Write data bus

U22.M3 Write data bus

U22.L3 Write data bus

U22.J3 Write data bus

U22.G2 Write data bus

U22.F3 Write data bus

U22.D2 Write data bus

U22.C3 Write data bus

U22.B3 Write data bus

U22.C11 Write data bus

U22.D11 Write data bus

U22.E10 Write data bus

U22.G11 Write data bus

U22.J11 Write data bus

U22.K10 Write data bus

Schematic Signal Name

QDR2TOP0_A19

QDR2TOP0_A18

QDR2TOP0_A17

QDR2TOP0_A16

QDR2TOP0_A15

QDR2TOP0_A14

QDR2TOP0_A13

QDR2TOP0_A12

QDR2TOP0_A11

QDR2TOP0_A10

QDR2TOP0_A9

QDR2TOP0_A8

QDR2TOP0_A7

QDR2TOP0_A6

QDR2TOP0_A5

QDR2TOP0_A4

QDR2TOP0_A3

QDR2TOP0_A2

QDR2TOP0_A1

QDR2TOP0_A0

QDR2TOP0_D17

QDR2TOP0_D16

QDR2TOP0_D15

QDR2TOP0_D14

QDR2TOP0_D13

QDR2TOP0_D12

QDR2TOP0_D11

QDR2TOP0_D10

QDR2TOP0_D9

QDR2TOP0_D8

QDR2TOP0_D7

QDR2TOP0_D6

QDR2TOP0_D5

QDR2TOP0_D4

QDR2TOP0_D3

I/O Standard

1.5-V HSTL Class I

Device

Pin Number

A28

J24

C28

G28

C30

C29

B28

R24

N20

A31

A29

P20

B31

B29

D27

F26

A27

G26

P24

N21

B25

G24

F24

M24

K23

M23

R22

N22

P22

A26

B26

C25

C26

D25

D26

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–55

Memory

Table 2–50. QDRII+ Top Port 0 Pin Assignments, Signal Names and Functions (Part 2 of 2)

Stratix IV GX

Board Reference Description

U22.M11 Write data bus

U22.N11 Write data bus

U22.P10 Write data bus

U22.B6 Write clock P

U22.A6 Write clock N

U22.A4 Write port select

U22.B7 Write byte write select 0

U22.A5 Write byte write select 1

U22.R6 Termination enable

U22.P3 Read data bus

U22.N3 Read data bus

U22.L2 Read data bus

U22.K3 Read data bus

U22.G3 Read data bus

U22.F2 Read data bus

U22.E3 Read data bus

U22.D3 Read data bus

U22.B2 Read data bus

U22.B11 Read data bus

U22.C10 Read data bus

U22.E11 Read data bus

U22.F11 Read data bus

U22.J10 Read data bus

U22.K11 Read data bus

U22.L11 Read data bus

U22.M10 Read data bus

U22.P11 Read data bus

U22.A11 Read clock P

U22.A1 Read clock N

Schematic Signal Name

QDR2TOP0_D2

QDR2TOP0_D1

QDR2TOP0_D0

QDR2TOP0_K_P

QDR2TOP0_K_N

QDR2TOP0_WPSn

QDR2TOP0_BWSn0

QDR2TOP0_BWSn1

QDR2TOP0_ODT

QDR2TOP0_Q17

QDR2TOP0_Q16

QDR2TOP0_Q15

QDR2TOP0_Q14

QDR2TOP0_Q13

QDR2TOP0_Q12

QDR2TOP0_Q11

QDR2TOP0_Q10

QDR2TOP0_Q9

QDR2TOP0_Q8

QDR2TOP0_Q7

QDR2TOP0_Q6

QDR2TOP0_Q5

QDR2TOP0_Q4

QDR2TOP0_Q3

QDR2TOP0_Q2

QDR2TOP0_Q1

QDR2TOP0_Q0

QDR2TOP0_CQ_P

QDR2TOP0_CQ_N

I/O Standard

1.5-V HSTL Class I

Device

Pin Number

E25

G25

F25

P23

N23

K24

L23

J25

A22

M25

L25

N25

P25

G27

F27

D28

E28

D29

E29

F28

G29

J26

K26

J27

L26

K28

M27

H28

K27

U22.A8 Read port select QDR2TOP0_RPSn C27

U22.P6 Read data valid

U22.H1 DLL enable

QDR2TOP0_QVLD

QDR2TOP0_DOFFn

H26

B22

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–56 Chapter 2: Board Components

Memory

Tab le 2 –5 1 lists the QDRII+ top port 0 component reference and manufacturing

information.

Table 2–51. QDRII+ Top Port 0 Component Reference and Manufacturing Information

Board

Reference

U22 QDRII+, 4 M × 18, 400 MHZ

Description Manufacturer

Cypress CY7C2563KV18-400BZXC www.cypress.com

NEC uPD44647186AF5-E22-FQ1 www.nec.com

Manufacturing

Part Number

QDRII+ Top Port 1

The QDRII+ top port 1 consists of a single QDRII+ burst-of-4 SRAM, providing 4 Mbyte with an 18-bit read data bus and an 18-bit write data bus.

Tab le 2 –5 2 lists the QDRII+ top port 1 pin assignments, signal names, and functions.

The signal names and types are relative to the Stratix IV GX device in terms of I/O setting and direction.

Table 2–52. QDRII+ Top Port 1 Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)

Board Reference Description

U7.A10 Address bus

U7.A3 Address bus

U7.A9 Address bus

U7.R7 Address bus

U7.R5 Address bus

U7.R4 Address bus

U7.R3 Address bus

U7.P8 Address bus

U7.P7 Address bus

U7.P5 Address bus

U7.P4 Address bus

U7.N7 Address bus

U7.N6 Address bus

U7.N5 Address bus

U7.C7 Address bus

U7.C5 Address bus

U7.B8 Address bus

U7.B4 Address bus

Schematic Signal Name

QDR2TOP1_A19

QDR2TOP1_A18

QDR2TOP1_A17

QDR2TOP1_A16

QDR2TOP1_A15

QDR2TOP1_A14

QDR2TOP1_A13

QDR2TOP1_A12

QDR2TOP1_A11

QDR2TOP1_A10

QDR2TOP1_A9

QDR2TOP1_A8

QDR2TOP1_A7

QDR2TOP1_A6

QDR2TOP1_A5

QDR2TOP1_A4

QDR2TOP1_A3

QDR2TOP1_A2

I/O Standard

1.5-V HSTL Class I

Manufacturer

Website

Stratix IV GX

Device

Pin Number

F20

B17

G20

E17

J18

M19

R18

F18

F17

F16

P18

D17

G18

L19

G19

C18

A18

A17

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–57

Memory

Table 2–52. QDRII+ Top Port 1 Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)

Stratix IV GX

Board Reference Description

U7.R8 Address bus

U7.R9 Address bus

U7.N2 Write data bus

U7.M3 Write data bus

U7.L3 Write data bus

U7.J3 Write data bus

U7.G2 Write data bus

U7.F3 Write data bus

U7.D2 Write data bus

U7.C3 Write data bus

U7.B3 Write data bus

U7.C11 Write data bus

U7.D11 Write data bus

U7.E10 Write data bus

U7.G11 Write data bus

U7.J11 Write data bus

U7.K10 Write data bus

U7.M11 Write data bus

U7.N11 Write data bus

U7.P10 Write data bus

U7.B6 Write clock P

U7.A6 Write clock N

U7.A4 Write port select

U7.B7 Write byte write select 0

U7.A5 Write byte write select 1

U7.R6 Termination enable

U7.P3 Read data bus

U7.N3 Read data bus

U7.L2 Read data bus

U7.K3 Read data bus

U7.G3 Read data bus

U7.F2 Read data bus

U7.E3 Read data bus

U7.D3 Read data bus

U7.B2 Read data bus

U7.B11 Read data bus

U7.C10 Read data bus

U7.E11 Read data bus

Schematic Signal Name

QDR2TOP1_A1

QDR2TOP1_A0

QDR2TOP1_D17

QDR2TOP1_D16

QDR2TOP1_D15

QDR2TOP1_D14

QDR2TOP1_D13

QDR2TOP1_D12

QDR2TOP1_D11

QDR2TOP1_D10

QDR2TOP1_D9

QDR2TOP1_D8

QDR2TOP1_D7

QDR2TOP1_D6

QDR2TOP1_D5

QDR2TOP1_D4

QDR2TOP1_D3

QDR2TOP1_D2

QDR2TOP1_D1

QDR2TOP1_D0

QDR2TOP1_K_P

QDR2TOP1_K_N

QDR2TOP1_WPSn

QDR2TOP1_BWSn0

QDR2TOP1_BWSn1

QDR2TOP1_ODT

QDR2TOP1_Q17

QDR2TOP1_Q16

QDR2TOP1_Q15

QDR2TOP1_Q14

QDR2TOP1_Q13

QDR2TOP1_Q12

QDR2TOP1_Q11

QDR2TOP1_Q10

QDR2TOP1_Q9

QDR2TOP1_Q8

QDR2TOP1_Q7

QDR2TOP1_Q6

I/O Standard

1.5-V HSTL Class I

Device

Pin Number

H19

C17

G15

F15

E16

D16

C15

C16

B16

A16

G16

G17

J16

K16

L16

P17

K17

N17

M17

P16

N16

M16

D18

H17

J17

C20

N13

N15

R14

P14

M14

N14

M13

K14

L14

E14

F14

F12

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–58 Chapter 2: Board Components

Table 2–52. QDRII+ Top Port 1 Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)

Stratix IV GX

Board Reference Description

U7.F11 Read data bus

U7.J10 Read data bus

U7.K11 Read data bus

U7.L11 Read data bus

U7.M10 Read data bus

U7.P11 Read data bus

U7.A11 Read clock P

U7.A1 Read clock N

U7.A8 Read port select QDR2TOP1_RPSn F19

U7.P6 Read data valid

U7.H1 DLL enable

Schematic Signal Name

QDR2TOP1_Q5

QDR2TOP1_Q4

QDR2TOP1_Q3

QDR2TOP1_Q2

QDR2TOP1_Q1

QDR2TOP1_Q0

QDR2TOP1_CQ_P

QDR2TOP1_CQ_N

QDR2TOP1_QVLD

QDR2TOP1_DOFFn

I/O Standard

Pin Number

1.5-V HSTL Class I

Memory

Device

G14

H14

K12

J12

K13

J13

H13

L13

D13

D20

Tab le 2 –5 3 lists the QDRII+ top port 1 component reference and manufacturing

information.

Table 2–53. QDRII+ Top Port 1 Component Reference and Manufacturing Information

Board

Reference

U7 QDRII+, 4 M × 18, 400 MHZ

Description Manufacturer

Cypress CY7C2563KV18-400BZXC www.cypress.com

NEC uPD44647186AF5-E22-FQ1 www.nec.com

Manufacturing

Part Number

SSRAM

The Synchronous Static Random Access Memory (SSRAM) device consists of a single standard synchronous SRAM, providing 2 Mbyte with a 36-bit data bus. This device is part of the shared FSM Bus, which connects to the flash memory, SSRAM, and the MAX

II CPLD EPM2210 System Controller.

The device speed is 250 MHz single-data-rate. There is no minimum speed for this device. The theoretical bandwidth of this 32-bit memory interface is 8.0 Gbps for continuous bursts. The read latency for any address is two clocks, in which at 250 MHz, the latency is 10 ns and at 50 MHz, the latency is 40 ns. The write latency is one clock.

Manufacturer

Website

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–59

Memory

Tab le 2 –5 4 lists the SSRAM pin assignments, signal names, and functions. The signal

names and types are relative to the Stratix IV GX device in terms of I/O setting and direction.

Table 2–54. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)

Board Reference Description

U30.P2 Address bus (576 M expansion)

U30.C10 Address bus (288 M expansion)

U30.B11 Address bus (144 M expansion)

U30.A1 Address bus (72 M expansion)

U30.B1 Address bus (36 M expansion)

U30.R11 Address bus

U30.R10 Address bus

U30.R9 Address bus

U30.R8 Address bus

U30.R4 Address bus

U30.R3 Address bus

U30.P11 Address bus

U30.P10 Address bus

U30.P9 Address bus

U30.P8 Address bus

U30.P4 Address bus

U30.P3 Address bus

U30.N6 Address bus

U30.B10 Address bus

U30.B2 Address bus

U30.A10 Address bus

U30.A2 Address bus

U30.P6 Address bus

U30.R6 Address bus

U30.M2 Data bus

U30.M1 Data bus

U30.L2 Data bus

U30.L1 Data bus

U30.K2 Data bus

U30.K1 Data bus

U30.J2 Data bus

U30.J1 Data bus

U30.G2 Data bus

U30.G1 Data bus

U30.F2 Data bus

Schematic Signal Name

FSM_A25

FSM_A24

FSM_A23

FSM_A22

FSM_A21

FSM_A20

FSM_A19

FSM_A18

FSM_A17

FSM_A16

FSM_A15

FSM_A14

FSM_A13

FSM_A12

FSM_A11

FSM_A10

FSM_A9

FSM_A8

FSM_A7

FSM_A6

FSM_A5

FSM_A4

FSM_A3

FSM_A2

FSM_D31

FSM_D30

FSM_D29

FSM_D28

FSM_D27

FSM_D26

FSM_D25

FSM_D24

FSM_D23

FSM_D22

FSM_D21

I/O Standard

2.5-V

Stratix IV GX Device

Pin Number

AP30

AN30

AL31

AK31

AR32

AP32

AH29

AG29

AR35

AP35

AL32

AK32

AU33

AT33

AH30

AJ31

AR34

AT34

AE27

AD27

AP34

AN33

AD26

AC26

T28

R28

F32

E32

L31

K31

F31

E31

N29

M29

H31

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–60 Chapter 2: Board Components

Memory

Table 2–54. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)

Board Reference Description

U30.F1 Data bus

U30.E2 Data bus

U30.E1 Data bus

U30.D2 Data bus

U30.D1 Data bus

U30.G11 Data bus

U30.G10 Data bus

U30.F11 Data bus

U30.F10 Data bus

U30.E11 Data bus

U30.E10 Data bus

U30.D11 Data bus

U30.D10 Data bus

U30.M11 Data bus

U30.M10 Data bus

U30.L11 Data bus

U30.L10 Data bus

U30.K11 Data bus

U30.K10 Data bus

U30.J11 Data bus

U30.J10 Data bus

U30.N11 Data bus parity byte lane 0

U30.C11 Data bus parity byte lane 1

U30.C1 Data bus parity byte lane 2

U30.N1 Data bus parity byte lane 3

U30.B6 Clock

U30.B8 Output enable

U30.A3 Chip enable

U30.B5 Byte lane 0 write enable

U30.A5 Byte lane 1 write enable

U30.A4 Byte lane 2 write enable

U30.B4 Byte lane 3 write enable

U30.A7 Byte write enable

U30.B7 Global write enable

U30.A8 Address status controller

U30.B9 Address status processor

U30.A9 Address valid

Schematic Signal Name

FSM_D20

FSM_D19

FSM_D18

FSM_D17

FSM_D16

FSM_D15

FSM_D14

FSM_D13

FSM_D12

FSM_D11

FSM_D10

FSM_D9

FSM_D8

FSM_D7

FSM_D6

FSM_D5

FSM_D4

FSM_D3

FSM_D2

FSM_D1

FSM_D0

SRAM_DQP0

SRAM_DQP1

SRAM_DQP2

SRAM_DQP3

SRAM_CLK

SRAM_OEn

SRAM_CEn

SRAM_BWn0

SRAM_BWn1

SRAM_BWn2

SRAM_BWn3

SRAM_BWEn

SRAM_GWn

SRAM_ADSCn

SRAM_ADSPn

SRAM_ADVn

I/O Standard

2.5-V

Stratix IV GX Device

Pin Number

G31

N30

M30

D33

C33

N31

M31

C32

B32

J32

H32

D35

C35

N28

M28

D31

C31

K30

J30

D34

C34

F35

AJ32

N33

AJ35

AE26

AK34

AT30

AH27

AR31

AH28

AL29

AK30

AC29

AM31

AG28

AU32

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–61

Memory

Table 2–54. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)

Board Reference Description

U30.R1 Mode

U30.H11 Sleep

Schematic Signal Name

SRAM_MODE

SRAM_ZZ

Tab le 2 –5 5 lists the SSRAM component reference and manufacturing information.

Table 2–55. SSRAM Component Reference and Manufacturing Information

Board Reference Description Manufacturer

U30

Standard synchronous pipelined SCD, 512K × 36 bit, 250 MHz

ISSI Inc. IS61VPS51236A-250B3 www.issi.com

Flash

The flash interface consists of a single synchronous flash memory device, providing 64 Mbyte interface with a 16-bit data bus. This device is part of the shared FSM Bus, which connects to flash memory, SSRAM, and the Max II CPLD EPM2210 System Controller.

I/O Standard

2.5-V

Manufacturing

Part Number

Stratix IV GX Device

Pin Number

—

(Connects to the MAX II

CPLD EPM2210 System

Controller)

AJ29

Manufacturer

Website

The parameter blocks of this device are located at the bottom of the address space. The parameter blocks are 32 K and main blocks are 128 K.

This 16-bit data memory interface can sustain burst read operations at up to 52 MHz for a throughput of 832 Mbps. The write performance is 125 µs for a single word and 440 µs for a 32-word buffer. The erase time is 400 ms for a 32 K parameter block and 1200 ms for a 128 K main block.

Tab le 2 –5 6 lists the flash pin assignments, signal names, and functions. The signal

names and types are relative to the Stratix IV GX device in terms of I/O setting and direction.

Table 2–56. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)

Board Reference Description

U32.B6 Address bus (die select)

U32.H8 Address bus

U32.G1 Address bus

U32.A8 Address bus

U32.C8 Address bus

U32.C7 Address bus

U32.B7 Address bus

U32.A7 Address bus

U32.D8 Address bus

Schematic Signal Name

FSM_A25

FSM_A24

FSM_A23

FSM_A22

FSM_A21

FSM_A20

FSM_A19

FSM_A18

FSM_A17

I/O Standard

2.5-V

Stratix IV GX

Device

Pin Number

AP30

AN30

AL31

AK31

AR32

AP32

AH29

AG29

AR35

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–62 Chapter 2: Board Components

Memory

Table 2–56. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)

Stratix IV GX

Board Reference Description

U32.D7 Address bus

U32.C5 Address bus

U32.B5 Address bus

U32.A5 Address bus

U32.C4 Address bus

U32.D3 Address bus

U32.C3 Address bus

U32.B3 Address bus

U32.A3 Address bus

U32.C2 Address bus

U32.A2 Address bus

U32.D2 Address bus

U32.D1 Address bus

U32.C1 Address bus

U32.B1 Address bus

U32.A1 Address bus

U32.E7 Data bus

U32.G7 Data bus

U32.H5 Data bus

U32.F5 Data bus

U32.F4 Data bus

U32.F3 Data bus

U32.E3 Data bus

U32.E1 Data bus

U32.H7 Data bus

U32.G6 Data bus

U32.G5 Data bus

U32.E5 Data bus

U32.E4 Data bus

U32.G3 Data bus

U32.E2 Data bus

U32.F2 Data bus

U32.E6 Data bus

U32.D4 Clock

U32.B4 Reset

U32.F8 Chip enable

U32.G8 Output enable

Schematic Signal Name

FSM_A16

FSM_A15

FSM_A14

FSM_A13

FSM_A12

FSM_A11

FSM_A10

FSM_A9

FSM_A8

FSM_A7

FSM_A6

FSM_A5

FSM_A4

FSM_A3

FSM_A2

FSM_A1

FSM_D16

FSM_D15

FSM_D14

FSM_D13

FSM_D12

FSM_D11

FSM_D10

FSM_D9

FSM_D8

FSM_D7

FSM_D6

FSM_D5

FSM_D4

FSM_D3

FSM_D2

FSM_D1

FSM_D0

FLASH_CLK

FLASH_RESETn

FLASH_CEn

FLASH_OEn

I/O Standard

2.5-V

Device

Pin Number

AP35

AL32

AK32

AU33

AT33

AH30

AJ31

AR34

AT34

AE27

AD27

AP34

AN33

AD26

AC26

AP33

C33

N31

M31

C32

B32

J32

H32

D35

C35

N28

M28

D31

C31

K30

J30

D34

C34

AF26

AL30

AU31

AG27

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–63

Power Supply

Table 2–56. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)

Stratix IV GX

Board Reference Description

U32.F6 Address valid

U32.F7 Ready

Schematic Signal Name

FLASH_ADVn

FLASH_RDYBSYn

I/O Standard

2.5-V

Device

Pin Number

AN31

AT32

Tab le 2 –5 7 lists the flash memory component reference and manufacturing

information.

Table 2–57. Flash Memory Component Reference and Manufacturing Information

Board Reference Description Manufacturer

U32 512-Mbyte synchronous flash Numonyx PC28F512P30BF www.numonyx.com

Manufacturing

Part Number

Manufacturer

Website

Power Supply

The development board’s power is provided through a laptop style DC power input. The input voltage must be in the range of 14 V to 20 V. The DC voltage is then stepped down to the various power rails used by the components on the board and installed into the HSMC connectors.

An on-board multi-channel analog-to-digital converter (ADC) is used to measure both the voltage and current for several specific board rails. The power utilization is displayed in a GUI that graphs power consumption versus time.

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–64 Chapter 2: Board Components

Power Supply

Power Distribution System

Figure 2–15 shows the power distribution system on the development board.

Regulator inefficiencies and sharing are reflected in the currents shown, which are conservative absolute maximum levels.

Figure 2–15. Power Distribution System

5.0V_USB

USB PHY Analog,

AT93C46DN EEPROM

5V_USB

0.039 A

2.5V_USB

EPM240 Emb. Blaster,

USB PHY IO,

24M OSC,

AT93C46DN EEPROM

12V_PCIe

3.74 A

DC INPUT 14 V - 20 V

3.3V_PCIe

0.69 A

5.0 V

0.025 A

U38

LT3010

Linear

(5.75 A with full HSMCs)

U35

LTM3727

Switching Regulator

(4.77 A with full HSMCs)

Dual

LTM4601 Switching Regulator

U17

LTM4614

Dual-Switching

Regulator

Only need bottom device

for larger 4SGX530 FPGA

U51 (bottom-side)

Switching

2x LTM4601 Regulator

Switching Regulator

U26 (top-side)

12V_SENSE_N

5.75 A

3.3V_SENSE_N

4.77 A

10.13 A

3.417 A

3.871 A

12.803 A

U15

diode mux

ideal

U19

D44

diode mux

ideal

D45

2.5 V

1.8 V

1.5 V

0.9 V

12 V R64

3.3 V R70

U49

U46

U48

U41

U44

U45

U50

U52

U57

U11

U10

LT3025-1

Linear

LT3080

Linear

LT3025-1

Linear

LT3080-1

Linear

LT3080-1

Linear

LT3025-1

Linear

LT3025-1

Linear

TPS51100

Linear

LT3010

Linear

LTM8021

Switcher

LT3025-1

Linear

LT3025-1

Linear

BEAD

R223

R105

R104

R158

R69

R187

R200

R144

BEAD

R171

R174

R155

R220

R52

R53

BEAD

12 V

2.095 A

2.5 V

0.837 A

1.8 V

0.080 A

1.8 V

0.100 A

1.8 V

0.080 A

2.5 V

0.050 A

2.5 V

0.181 A

2.5 V

0.181 A

2.5 V

0.484 A

1.4 V

0.567 A

1.5 V

0.286 A

1.8 V

1.971 A

1.8 V

0.010 A

1.1 V

1.343 A

1.1 V

0.093 A

1.5 V

2.100 A

1.5 V

0.410 A

1.5 V

0.880 A

0.9 V

0.100 A

1.0 V

0.253 A

0.75 V

0.128 A

0.9 V

12.803 A

5.0 V

0.006 A

5.0 V

0.044 A

3.0 V

0.331 A

2.5 V

0.250 A

2.5 V

0.051 A

3.3 V

4.050 A

12V

HSMC Port A and B

FPGA Cooling Fan

2.5V

Sync SRAM, Flash VDDQ,

NB6L11S, Enet PHY AVDD,

EPM2210, 7 Oscillators

HDMI_PVDD

HDMI Analog

HDMI_DVDD

HDMI Digital

HDMI_AVDD

HDMI TMDS Driver

S4VCCIO_B1B2

S4 Banks 1 & 2 VCCIO

S4VCCIO_B5

S4 Bank 5 VCCIO

S4VCCIO_B6

S4 Bank 6 VCCIO

S4VCCIO_INT

S4 VCC_CLKIN, VCCPGM,

VCCPD

S4VCCH_GXB

S4 Transceiver VCCH_GXB

S4VCCPT

S4 VCCPT

1.8V

QDRII VDD, Flash VDD,

EPM2210 VCCINT

S4VCCIO_B3A

S4 Bank 3A VCCIO

S4VCC_GXB

S4 Transceiver

VCCR/VCCT

S4VCCL_GXB

S4 Transceiver VCCL

1.5V

DDR3 VDD/VDDQ,

QDRII VDDQ,

S4 VCCIO B3/B4/B7/B8

S4VCCIO_B3B4

S4 Bank 3 & 4 VCCIO

S4VCCIO_B7B8

S4 Bank 7 & 8 VCCIO

S4VCCD_PLL

S4 VCCD_PLL

ENET_DVDD

Enet PHY DVDD

0.75V_VTT

DDR3BOT ADDR/CMD Term

S4VCC

S4 Core VCC

S4 VCCHIP

5.0V_MONITOR

2x LT2418 A/D

Linear Reg Inputs

5.0V

Char LCD, HDMI Cable

Linear Reg Inputs

S4VCCA_GXB

S4 Transceiver VCCA

S4VCCAUX

S4 VCCAUX

S4VCCA_PLL

S4 VCCA_PLL

3.3V

HSMC Port A and B, SDI

ICS 8543 LVDS Clock Buffer

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–65

SCK

DSI

DSO

CSn

8 Ch.

To Plane 0x0

To Plane 0xE

Supply

0x0

Supply

0xE

SENSE

SCK

DSI

DSO

CSn

8 Ch.

EPM2210

EP4SGX530

LTC2418

EPM

240

USB

PHY

To User PC

Power GUI

JTAG Chain

SPI Bus

Embedded

USB-Blaster

To Plane 0xF

12 V

Supply

SENSE

SCL

SDA

1 Ch.

LTC4151

SM Bus

U36

Power Supply

Power Measurement

There are 16 power supply rails which have on-board voltage and current sense capabilities. These 8-channel differential 24-bit ADC devices and rails are split from the primary supply plane by a low-value sense resistor for the ADC to measure voltage and current. A serial peripheral interface (SPI) bus connects these ADC devices to the MAX II CPLD EPM2210 System Controller as well as the Stratix IV GX FPGA.

Figure 2–16 shows the block diagram for the power measurement circuitry.

Figure 2–16. Power Measurement Circuit

Tab le 2 –5 8 lists the targeted rails. The schematic signal name specifies the name of the

rail being measured and the device pin specifies the devices attached to the rail. If no subnet is named, the power is the total output power for that voltage.

Table 2–58. Power Rail Measurements Based on the Rotary Switch Position (Part 1 of 2)

Switch Schematic Signal Name Voltage (V) Device Pin Description

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

S4VCCIO_B7B8

S4VCC

3.3 V

S4VCCIO_INT

S4VCCH_GXB

S4VCCAUX

1.5

0.9

3.3 — All 3.3 V power to board (mA only)

2.5

1.4 VCCH_GXB XCVR clock buffers

2.5

VCCIO_B7 Bank 7 I/O power (QDR2TOP+DDR3TOP)

VCCIO_B8 Bank 8 I/O power (QDR2TOP+DDR3TOP)

VCC FPGA core and periphery power

VCCHIP PCI Express hard IP block

VCCPD I/O pre-drivers

VCCPGM Configuration I/O

VCC_CLKIN V

VCCAUX Programmable power tech auxiliary

clock input pins

VCCA_PLL PLL analog

2–66 Chapter 2: Board Components

Table 2–58. Power Rail Measurements Based on the Rotary Switch Position (Part 2 of 2)

Switch Schematic Signal Name Voltage (V) Device Pin Description

F——— —

S4VCCPT

S4VCCD_PLL

S4VCCA_GXB

S4VCCIO_B5

S4VCCIO_B6

S4VCCIO_B1B2

S4VCCIO_B3A

S4VCCIO_B3B4

S4VCC_GXB

1.5 VCCPT Programmable power tech

0.9 VCCD_PLL PLL digital

3.0 VCCA XCVR analog TX/RX driver (mA only)

2.5 VCCIO_B5 Bank 5 I/O power (HSMC port A)

2.5 VCCIO_B6 Bank 6 I/O power (HSMC port B)

2.5

1.8 VCCIO_B3A Bank 3A I/O power (HDMI)

1.5

1.1

VCCIO_B1 Bank 1 I/O power (FSM bus)

VCCIO_B2 Bank 2 I/O power (FSM bus)

VCCIO_B3 Bank 3 I/O power (DDR3BOT)

VCCIO_B4 Bank 4 I/O power (DDR3BOT)

VCCR XCVR analog receive

VCCT XCVR analog transmit

VCCL_GXB XCVR clock distribution

Power Supply

Tab le 2 –5 9 lists the power measurement ADC component references and

manufacturing information.

Table 2–59. Power Measurement ADC Component References and Manufacturing Information

Board Reference Description Manufacturer

U1, U36 8-channel differential 24-bit ADC Linear Technology LTC2418CGN#PBF www.linear.com

U9 1-channel differential 12-bit ADC Linear Technology LTC4151CDD#PBF www.linear.com

Manufacturing

Part Number

Manufacturer

Website

Temperature Sense

Temperature monitoring for the Stratix IV GX FPGA die is achieved with a MAX1619 temperature sense device. The MAX1619 device connects to the MAX II CPLD EPM2210 System Controller and the Stratix IV GX device by a 2-wire SMB interface. The MAX 1619 device is located at address 0x1. This bus is also routed to a single voltage and power monitor chip for the 12-V power rail at address 0x2.

The

OVERTEMPn

sense device based on a programmable threshold temperature. The is driven to the MAX II EPM2210 System Controller which controls MAX II EPM2210 System Controller can control fan speed based on a register setting and can also override the MAX1619 device with the the fan to be on constantly at full speed. For more information on this control, refer to the MAX II EPM2210 System Controller source code found in the development board installation directory <install dir>\stratixIVGX_4sgx530_fpga\examples\max2.

and

TSENSE_ALERTn

signals are driven by the MAX1619 temperature

OVERTEMPn OVERTEMPn

FAN_FORCE_ON DIP

switch to force

signal . The

f For more information on the development board installation directory, refer to the

Stratix IV GX FPGA Development Kit, 530 Edition User Guide.

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Chapter 2: Board Components 2–67

Statement of China-RoHS Compliance

The remote sense is routed to the FPGA's diode pins to measure the voltage drop. For very accurate temperature readings, the I/O adjacent to the FPGA diode sense pins must be halted.

Tab le 2 –6 0 lists the temperature sense interface pin assignments, signal names, and

functions.

Table 2–60. Temperature Sense Pin Assignments, Schematic Signal Names, and Functions

Board

Reference

Description Schematic Signal

U27.14 SMB clock

U27.12 SMB data

U27.9

Programmable over-temperature

U27.11 Programmable alert

Name

SENSE_SMB_CLK

SENSE_SMB_DATA

OVERTEMPn

TSENSE_ALERTn

I/O Standard

2.5-V

MAX II CPLD EPM2210

System Controller

Tab le 2 –6 1 lists the temperature sense component reference and manufacturing

information.

Table 2–61. Temperature Sense Component Reference and Manufacturing Information

Board Reference Description Manufacturer

U26

Temperature sense, remote and local, programmable alert.

Maxim MAX1619MEE+T www.maxim-ic.com

Manufacturing

Part Number

Statement of China-RoHS Compliance

Tab le 2 –6 2 lists hazardous substances included with the kit.

Pin Number

R1 W34

R4 AH32

P5 —

M2 —

Manufacturer

Website

Stratix IV GX

Device

Pin Number

Table 2–62. Table of Hazardous Substances’ Name and Concentration Notes (1), (2)

Part Name

Lead

(Pb)

Cadmium

(Cd)

Hexavalent

Chromium

(Cr6+)

Mercury

(Hg)

Polybrominated biphenyls (PBB)

Polybrominated diphenyl Ethers

(PBDE)

Stratix IV GX development board X* 0 0 0 0 0

12 V power supply 0 0 0 0 0 0

Type A-B USB cable 0 0 0 0 0 0

User guide 0 0 0 0 0 0

Notes to Table 2–62:

(1) 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the

SJ/T11363-2006 standard.

(2) X* indicates that the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant

threshold of the SJ/T11363-2006 standard, but it is exempted by EU RoHS.

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

2–68 Chapter 2: Board Components

Statement of China-RoHS Compliance

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

This chapter provides additional information about the document and Altera.

Document Revision History

The following table shows the revision history for this document.

Date Version Changes

November 2010 1.0 Initial release.

How to Contact Altera

To locate the most up-to-date information about Altera products, refer to the following table.

Additional Information

Contact (1) Contact Method Address

Technical support Website www.altera.com/support

Technical training

Product literature Website www.altera.com/literature

Non-technical support (General) Email nacomp@altera.com

(Software Licensing) Email authorization@altera.com

Note to Table:

(1) You can also contact your local Altera sales office or sales representative.

Website www.altera.com/training

Email custrain@altera.com

Typographic Conventions

The following table shows the typographic conventions this document uses.

Visual Cue Meaning

Bold Type with Initial Capital Letters

bold type

Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.

italic type

Initial Capital Letters

Indicate command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI.

Indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \qdesigns directory, D: drive, and chiptrip.gdf file.

Indicates variables. For example, n + 1.

Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file.

Indicate keyboard keys and menu names. For example, the Delete key and the Options menu.

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

Info–2 Additional InformationAdditional Information

Typographic Conventions

Visual Cue Meaning

“Subheading Title”

Quotation marks indicate references to sections within a document and titles of Quartus II Help topics. For example, “Typographic Conventions.”

Indicates signal, port, register, bit, block, and primitive names. For example,

tdi

, and

input

. The suffix n denotes an active-low signal. For example,

data1

resetn

Indicates command line commands and anything that must be typed exactly as it

Courier type

appears. For example,

c:\qdesigns\tutorial\chiptrip.gdf

Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword

TRI

example,

SUBDESIGN

), and logic function names (for

r An angled arrow instructs you to press the Enter key.

1., 2., 3., and a., b., c., and so on

■ ■ ■ Bullets indicate a list of items when the sequence of the items is not important.

Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure.

1 The hand points to information that requires special attention.

A question mark directs you to a software help system with related information.

f The feet direct you to another document or website with related information. c

A caution calls attention to a condition or possible situation that can damage or destroy the product or your work.

A warning calls attention to a condition or possible situation that can cause you injury.

The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents.

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

Altera Stratix IV GX FPGA Development Board User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

General Description

1. Overview

Board Component Blocks

Development Board Block Diagram

Handling the Board

Introduction

2. Board Components

Board Overview

Featured Device: Stratix IV GX Device

I/O Resources

MAX II CPLD EPM2210 System Controller

Migration Support

Configuration, Status, and Setup Elements

Configuration

FPGA Programming over Embedded USB-Blaster

FPGA Programming from Flash Memory

FPGA Programming over External USB-Blaster

Status Elements

Setup Elements

Board Settings DIP switch

JTAG Control DIP Switch

PCI Express Control DIP switch

Reset Configuration Push-Button Switch

Rotary Switch

Clock Circuitry

Stratix IV GX FPGA Clock Inputs

Stratix IV GX FPGA Clock Outputs

General User Input/Output

User-Defined Push-Button Switches

User-Defined DIP Switches

User-Defined LEDs

General User-Defined LEDs

HSMC User-Defined LEDs

Components and Interfaces

PCI Express

10/100/1000 Ethernet

High-Speed Mezzanine Cards

HDMI Video Output

SDI Video Input/Output

Memory

DDR3 Bottom Port

DDR3 Top Port

QDRII+ Top Port 0

QDRII+ Top Port 1

SSRAM

Flash

Power Supply

Power Distribution System

Power Measurement

Temperature Sense

Statement of China-RoHS Compliance

Document Revision History

How to Contact Altera

Additional Information

Typographic Conventions