Stratix IV GX FPGA Development Board, 530 Edition
Reference Manual
Stratix IV GX FPGA Development Board, 530 Edition
Reference Manual
101 Innovation Drive
San Jose, CA 95134
www.altera.com
MNL-01060-1.0
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customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or
services.
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation
Contents
Chapter 1. Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Chapter 2. Board Components
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Featured Device: Stratix IV GX Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Migration Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
MAX II CPLD EPM2210 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
FPGA Programming over Embedded USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
Board Settings DIP switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
JTAG Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
PCI Express Control DIP switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19
Reset Configuration Push-Button Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19
Rotary Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
Stratix IV GX FPGA Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
Stratix IV GX FPGA Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
User-Defined Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
User-Defined DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28
General User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28
HSMC User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29
LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29
Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33
High-Speed Mezzanine Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35
HDMI Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–43
SDI Video Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48
DDR3 Bottom Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48
DDR3 Top Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–52
QDRII+ Top Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–53
QDRII+ Top Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–56
SSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–58
Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–61
November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual
iv Contents
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–63
Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–64
Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–65
Temperature Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–66
Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–67
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation
This document describes the hardware features of the Stratix® IV GX FPGA
development board, including the detailed pin-out and component reference
information required to create custom FPGA designs that interface with all
components of the board.
General Description
The Stratix IV GX FPGA Development Board, 530 Edition provides a hardware
platform for developing and prototyping low-power, high-performance, and logicintensive designs. The board provides a wide range of peripherals and memory
interfaces to facilitate the development of the Stratix IV GX FPGA designs.
Two High-Speed Mezzanine Card (HSMC) connectors are available to add additional
functionality via a variety of HSMC cards available from both Altera and various
partners.
1. Overview
f To see a list of the latest HSMC cards available or to download a copy of the HSMC
specification, refer to the Development Board Daughtercards page of the Altera
website.
Design advancements and innovations, such as the 8.5 Gbps transceiver modules, the
PCI Express hard IP implementation, and programmable power technology ensure
that designs implemented in the Stratix IV GX FPGAs operate faster, with lower
power than in previous FPGA families.
f For more information on the following topics, refer to the respective documents:
■ Stratix IV device family, refer to the Stratix IV Device Handbook.
■ PCI Express MegaCore function, refer to the PCI Express Compiler User Guide.
■ Altera Video and Image Processing Suite MegaCore functions, refer to the Vid eo
and Image Processing Suite User Guide.
■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.
Board Component Blocks
The board features the following major component blocks:
November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual
1–2 Chapter 1: Overview
Board Component Blocks
■ EP4SGX530KH40 FPGA in the 1517-pin FineLine BGA Package
■ 531,200 LEs
■ 212,480 adaptive logic modules (ALMs)
■ 27,376 Kbit on-die memory
■ 24 transceivers (8.5 Gbps)
■ 2 PCI Express hard IP blocks
■ 8 phase locked loops (PLLs)
■ 1,024 18x18 multipliers
■ 0.9-V core power
■ MAX
®
II CPLD EPM2210 System Controller in the 256-pin FineLine BGA Package
■ 1.8-V core power
■ FPGA Configuration Circuitry
■ MAX
®
II CPLD EPM2210 System Controller and Flash Fast Passive Parallel
(FPP) configuration
■ On-Board USB-Blaster
TM
for use with the Quartus® II Programmer
■ On-Board Clocking Circuitry
■ 50-MHz/125-MHz/155.52-MHz/156.25-MHz fixed-frequency oscillators
■ 100-MHz oscillator, programmable to any frequency between 20–810 MHz
■ 148.5-MHz voltage-controlled crystal oscillator (VCXO)
■ SMA connectors for external clock input
■ SMA connector for clock output
■ Memory devices
■ 512-Mbyte DDR3 SDRAM with a 64-bit data bus (bottom port)
■ 128-Mbyte DDR3 SDRAM with a 16-bit data bus (top port)
■ Two 4-Mbyte QDRII+ SRAMs with 18-bit data buses
■ 2-Mbyte SSRAM with 36-bit data bus
■ 64-Mbyte synchronous flash
■ General User I/O
■ 16 user LEDs
■ Two-line character LCD display
■ One configuration done LED
■ One transmit/receive LED (TX/RX) per HSMC interface
■ Four PCI Express LEDs
■ Four Ethernet LEDs
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation
Chapter 1: Overview 1–3
Board Component Blocks
■ Push-Button Switches
■ One user reset (CPU Reset)
■ One configuration reset
■ Three general user push-button switches
■ DIP Switches
■ Eight user DIP switches
■ Eight MAX
II control DIP switches
■ Power
■ 16-V – 20-V DC input
■ PCI Express edge connector power
■ On-Board power measurement circuitry
■ Mechanical
■ PCI Express half-length full-height (6.6” x 4.376”)
■ PCI Express chassis or bench-top operation
November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual
1–4 Chapter 1: Overview
Development Board Block Diagram
Development Board Block Diagram
Figure 1–1 shows the block diagram of the Stratix IV GX FPGA Development Board,
530 Edition.
Figure 1–1. Stratix IV GX FPGA Development Board, 530 Edition Block Diagram
USB
2.0
Embedded
Blaster
512 Mbytes
DDR3 BOT
REFCLK
SMA IN
TRIG
SMA OUT
GigE
PHY
HDMI
TX
SDI
TX/TX
JTAG Chain
x64
x1 (LVPECL)
x1
x1
x24
XCVR x1
50 MHz, 100 MHz,
125 MHz, 148 MHz,
155 MHz, 156 MHz
Oscillators
Port A
x80
CLKIN x3
x4
x80
XCVR x8
CLKOUT x3
EP4SGX530KH40
XCVR x8
x8 Edge
Port B
CLKIN x3
CLKOUT x3
x8 Config
CPLD
ADDR
XCVR x6
x32
x16
x16
x16
XCVR x1
x5
x8
x16
64 Mbytes
FLASH
128 Mbytes
DDR3 TOP
4 Mbytes
QDRII+ TOP 0
4 Mbytes
QDRII+ TOP 1
XCVR
SMA OUT
Buttons
Switches
LED
2 Mbytes
SSRAM
Handling the Board
When handling the board, it is important to observe the following static discharge
precaution:
c Without proper anti-static handling, the board can be damaged. Therefore, use
anti-static handling precautions when touching the board.
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation
Introduction
1 A complete set of schematics, a physical layout database, and GERBER files for the
f For information about powering up the board and installing the demo software, refer
2. Board Components
This chapter introduces all the important components on the Stratix IV GX FPGA
Development Board, 530 Edition. Figure 2–1 illustrates major component locations
and Table 2–1 provides a brief description of all features of the board.
development board reside in the Stratix IV GX development kit documents directory.
to the Stratix IV GX FPGA Development Kit, 530 Edition User Guide.
This chapter consists of the following sections:
■ “Board Overview”
■ “Featured Device: Stratix IV GX Device” on page 2–5
■ “MAX II CPLD EPM2210 System Controller” on page 2–7
■ “Configuration, Status, and Setup Elements” on page 2–12
■ “Clock Circuitry” on page 2–21
■ “General User Input/Output” on page 2–26
■ “Components and Interfaces” on page 2–31
■ “Memory” on page 2–48
■ “Power Supply” on page 2–63
■ “Statement of China-RoHS Compliance” on page 2–67
November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual
2–2 Chapter 2: Board Components
Board Overview
Board Overview
This section provides an overview of the Stratix IV GX FPGA Development Board, 530
Edition, including an annotated board image and component descriptions. Figure 2–1
provides an overview of the development board features.
Figure 2–1. Overview of the Stratix IV GX FPGA Development Board, 530 Edition Features
User DIP Switch (SW3)
HSMC Port A (J1)
Reset Configuration
Push-Button
Switch (S1)
Configuration Done
DDR3 x64 Bottom Port
LED (D5)
(U5, U12, U18, U24)
SDI Video Port
(J3, J5)
Gigabit Ethernet Port
(J6)
USB Type-B
Connector (J7)
Stratix IV GX FPGA (U13)
CPU Reset Push-button Switch (S2)
EP4SGX530KH40C2N
Power Monitor Rotary Switch (SW2)
General User Push-button Switches (S3, S4, S5)
HSMC Port B
(J2)
Power Switch
(SW1)
DC Input Jack (J4)
QDRII+ x18/x18
Top Port 1 (U7)
DDR3 x16
Top Port (U14)
QDRII+ x18/x18
Top Port 0 (U22)
JTAG Connector
(J8)
HDMI Video Port (J11)
Flash x16 Memory
(U32)
SSRAM x36 Memory (U30)
Transceiver TX SMA Connectors
Fan Power Header
PCI Express Edge Connector
(J17)
Character LCD (J16)
Max II CPLD EPM2210 System Controller (U31)
Clock Input SMA Connector (J14, J15)
Clock Output SMA Connector (J9)
Tab le 2– 1 describes the components and lists their corresponding board references.
Table 2–1. Stratix IV GX FPGA Development Board, 530 Edition Components (Part 1 of 3)
Board Reference Type Description
Featured Devices
U13 FPGA EP4SGX530KH40, 1517-pin BGA.
U31 CPLD EPM2210GF256, 256-pin BGA.
Configuration, Status, and Setup Elements
SW6 JTAG DIP switch Enables and disables devices in the JTAG chain.
II CPLD EPM2210 System Controller functions such
SW4 Board Settings DIP switch
Controls the Max
as clock enable, power and temperature monitor, as well as voltage
settings for transceivers and SMA clock input control.
J8 JTAG connector Disables embedded blaster (for use with external USB-Blasters).
SW5 PCI Express DIP switch
Controls the PCI Express lane width by connecting
together on the PCI Express edge connector.
prsnt
pins
D5 Configuration done LED Illuminates when the FPGA is configured.
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation
Chapter 2: Board Components 2–3
Board Overview
Table 2–1. Stratix IV GX FPGA Development Board, 530 Edition Components (Part 2 of 3)
Board Reference Type Description
D26 Load LED Illuminates during embedded USB-Blaster data transfers.
D27 Error LED Illuminates when the FPGA configuration from flash fails.
D24 Power LED Illuminates when 12-V power is present.
D32, D33, D34,
D35
Ethernet LEDs Shows the connection speed as well as transmit or receive activity.
D3, D4 HSMC port A LEDs You can configure these LEDs to indicate transmit or receive activity.
D1 HSMC port A Present LED Illuminates when a daughtercard is plugged into the HSMC port A.
D14, D15 HSMC port B LEDs You can configure these LEDs to indicate transmit or receive activity.
D2 HSMC port B Present LED Illuminates when a daughtercard is plugged into the HSMC port B.
D30 SDI mute LED Illuminates when the SDI receiver is muted.
D25 PCI Express Gen 2 LED
D37, D38, D39 PCI Express Link LEDs
You can configure this LED to illuminate when PCI Express is in Gen 2
mode.
You can configure these LEDs to display the PCI Express link width
(x1, x4, x8).
Clock Circuitry
X1 125 M oscillator
125.000-MHz crystal oscillator for Gigabit Ethernet, Serial RapidIO™
(SRIO), or PCI Express.
X2 156 M oscillator 156.250-MHz crystal oscillator for 10 Gigabit Ethernet or XAUI.
X3 148 M oscillator 148.500-MHz voltage controlled crystal oscillator for SDI Video.
100.000-MHz (programmable to any frequency between 20–810 MHz)
X6 100 M oscillator
crystal oscillator for PCI Express or general use such as memories.
Multiplex with CLKIN_SMA_P based on CLK_SEL switch value.
X7 155 M oscillator 155.520-MHz crystal oscillator for SONET.
X8 50 M oscillator 50.000-MHz crystal oscillator for general purpose logic.
J15, J14 Clock input SMAs
Drives LVPECL-compatible clock inputs into the U50 clock multiplexer
buffer.
J9 Clock output SMA Drives out 2.5-V CMOS clock outputs from the FPGA.
General User Input and Output
D 6 -D 1 3
D16-D23
User LEDs 16 user LEDs. Illuminates when driven low.
SW3 User DIP switch Octal user DIP switches. When the switch is ON, a logic 0 is selected.
S1
S2 CPU reset push-button switch
S3, S4, S5
Reset configuration
push-button switch
General user push-button
switches
Press to reconfigure the FPGA from the flash memory.
Press to reset the Max II CPLD EPM2210 System Controller and FPGA
logic.
Three user push-button switches. Driven low when pressed.
Selects the power rail being measured. It also selects the FPGA image
SW2 Power monitor rotary switch
to load on power-up; 0 selects factory image and 1 selects
user-defined image.
November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual
2–4 Chapter 2: Board Components
Board Overview
Table 2–1. Stratix IV GX FPGA Development Board, 530 Edition Components (Part 3 of 3)
Board Reference Type Description
Memory Devices
U5, U12, U18,
U24
DDR3 x64 bottom port A single 64-bit 512 Mbyte memory port.
U14 DDR3 x16 top port Independent 16-bit 128 Mbyte memory port.
U22 QDRII+ x18/x18 top port 0 18-bit read and 18-bit write 4 Mbyte SRAM port.
U7 QDRII+ x18/x18 top port 1 Second 18-bit read and 18-bit write 4 Mbyte SRAM port.
U30 SSRAM x36 memory
U32 Flash x16 memory
Standard synchronous RAM which makes a 36-bit 2 Mbyte SRAM
port.
Synchronous burst mode flash device which provides a 16-bit
64 Mbyte non-volatile memory port.
Communication Ports
J17 PCI Express edge connector
J1 HSMC port A
J2 HSMC port B
J7 USB Type-B connector
Made of gold-plated edge fingers for up to ×8 signaling in either Gen1
or Gen2 mode.
Provides eight transceiver channels and 84 CMOS or 17 LVDS
channels per the HSMC specification.
Provides six transceiver channels and 84 CMOS or 17 LVDS channels
per the HSMC specification.
Embedded USB-Blaster JTAG for programming the FPGA via a type-B
USB cable.
RJ-45 connector which provides a 10/100/1000 Ethernet connection
J6 Gigabit Ethernet port
via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed
Ethernet MegaCore function in SGMII mode.
Video and Display Ports
J11 HDMI video port
19-pin HDMI connector which provides a HDMI video output of up to
1080i through an AD9889B PHY.
Two 75-Ω system management bus (SMB) connectors which provide a
J3, J5 SDI video port
full-duplex SDI interface through a LMH0302 driver and LMH0344
cable equalizer.
J16 Character LCD
Connector which interfaces to the provided 16 character × 2 line LCD
module along with standoffs S1 and S2.
Power Supply
J17 PCI Express edge connector
Interfaces to a PCI Express root port such as an appropriate PC
motherboard.
J4 DC input jack Accepts a 14-V – 20-V DC power supply.
SW1 Power switch
Switch to power on or off the board when power is supplied from the
DC input jack.
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation
Chapter 2: Board Components 2–5
Featured Device: Stratix IV GX Device
Featured Device: Stratix IV GX Device
The Stratix IV GX FPGA Development Board, 530 Edition features the Stratix IV GX
EP4SGX530KH40 device (U13) in a 1517-pin FineLine BGA package.
f For more information about the Stratix IV device family, refer to the Stratix IV Device
Handbook.
Tab le 2– 2 describes the features of the Stratix IV GX EP4SGX530KH40 device.
Table 2–2. Stratix IV GX Device EP4SGX530KH40 Features
ALMs
212,480 531,200 1,280 64 10,624 27,376 1,024 8 24, 12
Equivalent
LEs
M9K
RAM
Blocks
M144K
Blocks
MLAB
Blocks
Tot al
RAM
Kbits
18-bit × 18-bit
Multipliers
PLLs
Transceivers
(8.5 Gbps,
3.2 Gbps)
Tab le 2– 3 lists the Stratix IV GX component reference and manufacturing
information.
Table 2–3. Stratix IV GX Device Component Reference and Manufacturing Information
Board Reference Description Manufacturer
U13
FPGA, Stratix IV GX F1517,
531K LEs, leadfree
Corporation EP4SGX530KH40C2N www.altera.com
Altera
Manufacturing
Part Number
Package
Type
1517-pin
FineLine BGA
Manufacturer
Website
November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual
2–6 Chapter 2: Board Components
Bank 8A 40
Bank 8B 24
Bank 8C 32
Bank 7C 32
Bank 6A 48
Bank 6C
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
Bank
Name
Number
of I/Os
40
Bank 5C 40
Bank 5A
Bank 1A
Bank 1C
Bank 2C
Bank 2A 48
48
40
40
48
Bank 7B 24
Bank 7A 40
Bank
Name
Number
of I/Os
Bank 3A40
Bank 3B24
Bank 3C32
Bank 4C32
Bank 4B24
Bank 4A40
4*
4*
Bank
GXBL2
4*
Bank
GXBL1
Bank
GXBL0
4*
4*
4*
Bank
GXBR2
Bank
GXBR1
Bank
GXBR0
*Number of
Transceiver
Channel
Featured Device: Stratix IV GX Device
I/O Resources
Figure 2–2 shows the bank organization and I/O count for the EP4SGX230 device in
the 1517-pin FineLine BGA package.
Figure 2–2. EP4SGX530KH40 Device I/O Bank Diagram
Tab le 2– 4 lists the Stratix IV GX device pin count and usage by function on the
development board.
Table 2–4. Stratix IV GX Device Pin Count and Usage (Part 1 of 2)
Function I/O Standard I/O Count Special Pins
DDR3 ×16 Top Port 1.5-V SSTL 49 2 Diff ×8 DQS
DDR3 ×64 Bottom Port 1.5-V SSTL 117 8 Diff ×8 DQS
QDRII+ Top Port 0 1.5-V HSTL 66 1 Diff ×18 DQS
QDRII+ Top Port 1 1.5-V HSTL 66 1 Diff ×18 DQS
Flash, SRAM, MAX FSM Bus 2.5-V CMOS 78 —
PCI Express ×8 2.5-V CMOS + XCVR 38 1 REFCLK, 8 XCVR
HSMC Port A 2.5-V CMOS + LVDS + XCVR 116 8 XCVR, 17 LVDS, 5 Clock Inputs
HSMC Port B 2.5-V CMOS + LVDS + XCVR 116 6 XCVR, 17 LVDS, 5 Clock Inputs
Gigabit Ethernet 2.5-V CMOS + LVDS 8 1 LVDS
HDMI Video 2.5-V CMOS 39 —
SDI Video XCVR 7 1 XCVR
Buttons 2.5-V CMOS 4 1 DEV_CLRn
Switches 2.5-V CMOS 8 —
LCD 2.5-V CMOS 11 —
LEDs 2.5-V CMOS 24 —
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation
Chapter 2: Board Components 2–7
MAX II CPLD EPM2210 System Controller
Table 2–4. Stratix IV GX Device Pin Count and Usage (Part 2 of 2)
Function I/O Standard I/O Count Special Pins
Clocks or Oscillators 2.5-V CMOS + LVDS 11 4 REFCLK
Power or Temperature Sense 2.5-V CMOS10 10 1 tempdiode_p, 1 tempdiode_n
Device I/O Total:
768
Migration Support
Although the target FPGA for this development board is the EP4SGX530KH40 device,
the board supports migration to the smallest Stratix IV GX device available in the
F1517 package, the EP4SGX230KF40.
Tab le 2– 5 describes the features of the Stratix IV GX EP4SGX230KF40 device.
Table 2–5. Stratix IV GX Device EP4SGX230KF40 Features
M9K
RAM
Blocks
M144K
Blocks
MLAB
Blocks
ALMs
Equivalent
LEs
91,200 228,000 1,235 22 4,560 17,133 1,288 8 24, 12
The specific I/O resources available in the Stratix IV GX EP4SGX230KF40 device are
the same for the Stratix IV GX EP4SGX530KH40 device.
f For information about the Stratix IV GX EP4SGX230KF40 device development board,
refer to the Stratix IV GX FPGA Development Board, Reference Manual.
Total
RAM
Kbits
18-bit × 18-bit
Multipliers
PLLs
Transceivers
(8.5 Gbps,
3.2 Gbps)
Package
Type
1517-pin
Fineline BGA
MAX II CPLD EPM2210 System Controller
The board utilizes the EPM2210 System Controller, an Altera MAX II CPLD, for the
following purposes:
■ FPGA configuration from flash memory
■ Power consumption monitoring
■ Temp er a ture m on it or in g
■ Fan control
■ Virtual JTAG interface for PC-based power and temperature GUI
■ Control registers for clocks
■ Control registers for Remote System Update
■ Control registers for SDI, SRAM, and fan speed.
■ Register with CPLD design revision and board information (read-only)
November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual
2–8 Chapter 2: Board Components
MAX1619
Controller
Information
Register
EMB
Blaster
MAX II Device
Si570
Controller
SLD-HUB
PFL
FSM BUS
Power
Measure
Results
Virtual-JTAG
PC
Temperature
Measure
Results
FPGA
LTC2418
Controller
FLASH
Decoder
Encoder
GPIO
JTAG Control
SRAM
Control
Register
Fast Configuration
Downloader
Si570
Programmable
Oscillator
MAX II CPLD EPM2210 System Controller
Figure 2–3 illustrates the MAX II CPLD EPM2210 System Controller's functionality
and external circuit connections as a block diagram.
Figure 2–3. MAX II CPLD EPM2210 System Controller Block Diagram
Tab le 2– 6 lists the I/O signals present on the MAX
Controller. The signal names and functions are relative to the MAX
II CPLD EPM2210 System
II device (U30).
Table 2–6. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 1 of 4)
Schematic Signal
Name
FSM_A25
FSM_A24
FSM_A23
FSM_A22
FSM_A21
FSM_A20
FSM_A19
FSM_A18
FSM_A17
FSM_A16
FSM_A15
FSM_A14
FSM_A13
FSM_A12
FSM_A11
I/O Standard
2.5-V D5 AP30 FSM bus address
2.5-V B1 AN30 FSM bus address
2.5-V D4 AL31 FSM bus address
2.5-V B9 AK31 FSM bus address
2.5-V D9 AR32 FSM bus address
2.5-V A10 AP32 FSM bus address
2.5-V C9 AH29 FSM bus address
2.5-V B10 AG29 FSM bus address
2.5-V A11 AR35 FSM bus address
2.5-V E10 AP35 FSM bus address
2.5-V B11 AL32 FSM bus address
2.5-V D10 AK32 FSM bus address
2.5-V A12 AU33 FSM bus address
2.5-V C10 AT33 FSM bus address
2.5-V B12 AH30 FSM bus address
EPM2210
Pin Number
EP4SGX230
Pin Number
Description
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation
Chapter 2: Board Components 2–9
MAX II CPLD EPM2210 System Controller
Table 2–6. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 2 of 4)
Schematic Signal
Name
FSM_A10
FSM_A9
FSM_A8
FSM_A7
FSM_A6
FSM_A5
FSM_A4
FSM_A3
FSM_A2
FSM_A1
FSM_A0
FSM_D31
FSM_D30
FSM_D29
FSM_D28
FSM_D27
FSM_D26
FSM_D25
FSM_D24
FSM_D23
FSM_D22
FSM_D21
FSM_D20
FSM_D19
FSM_D18
FSM_D17
FSM_D16
FSM_D15
FSM_D14
FSM_D13
FSM_D12
FSM_D11
FSM_D10
FSM_D9
FSM_D8
FSM_D7
FSM_D6
FSM_D5
FSM_D4
I/O Standard
EPM2210
Pin Number
EP4SGX230
Pin Number
2.5-V E11 AJ31 FSM bus address
2.5-V A13 AR34 FSM bus address
2.5-V D11 AT34 FSM bus address
2.5-V B13 AE27 FSM bus address
2.5-V C11 AD27 FSM bus address
2.5-V B14 AP34 FSM bus address
2.5-V D12 AN33 FSM bus address
2.5-V A15 AD26 FSM bus address
2.5-V C12 AC26 FSM bus address
2.5-V B16 AP33 FSM bus address
2.5-V C13 AN32 FSM bus address
2.5-V T13 T28 FSM bus data
2.5-V N11 R28 FSM bus data
2.5-V R12 F32 FSM bus data
2.5-V M11 E32 FSM bus data
2.5-V T12 L31 FSM bus data
2.5-V P10 K31 FSM bus data
2.5-V R11 F31 FSM bus data
2.5-V N10 E31 FSM bus data
2.5-V T11 N29 FSM bus data
2.5-V M10 M29 FSM bus data
2.5-V T10 H31 FSM bus data
2.5-V P9 G31 FSM bus data
2.5-V R9 N30 FSM bus data
2.5-V T9 M30 FSM bus data
2.5-V T8 D33 FSM bus data
2.5-V N9 C33 FSM bus data
2.5-V C7 N31 FSM bus data
2.5-V B5 M31 FSM bus data
2.5-V D7 C32 FSM bus data
2.5-V A5 B32 FSM bus data
2.5-V E7 J32 FSM bus data
2.5-V B6 H32 FSM bus data
2.5-V A6 D35 FSM bus data
2.5-V C8 C35 FSM bus data
2.5-V B7 N28 FSM bus data
2.5-V D8 M28 FSM bus data
2.5-V A7 D31 FSM bus data
2.5-V E8 C31 FSM bus data
Description
November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual
2–10 Chapter 2: Board Components
MAX II CPLD EPM2210 System Controller
Table 2–6. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 3 of 4)
Schematic Signal
Name
FSM_D3
FSM_D2
FSM_D1
FSM_D0
MAX2_CLK
MAX2_WEn
MAX2_CSn
MAX2_OEn
MAX2_BEn3
MAX2_BEn2
MAX2_BEn1
MAX2_BEn0
FLASH_CLK
FLASH_WEn
FLASH_CEn
FLASH_OEn
FLASH_RDYBSYn
FLASH_RESETn
FLASH_ADVn
FPGA_CONFIG_D7
FPGA_CONFIG_D6
FPGA_CONFIG_D5
FPGA_CONFIG_D4
FPGA_CONFIG_D3
FPGA_CONFIG_D2
FPGA_CONFIG_D1
FPGA_CONFIG_D0
FPGA_DCLK
FPGA_nSTATUS
FPGA_nCONFIG
FPGA_CONF_DONE
SENSE_SCK
SENSE_SDI
SENSE_SDO
SENSE_CS0n
SENSE_CS1n
SENSE_ADN_F0
SENSE_SMB_CLK
SENSE_SMB_DATA
I/O Standard
EPM2210
Pin Number
EP4SGX230
Pin Number
Description
2.5-V B8 K30 FSM bus data
2.5-V A8 J30 FSM bus data
2.5-V A9 D34 FSM bus data
2.5-V E9 C34 FSM bus data
2.5-V E1 K32 FSM bus MAX2 clock
2.5-V F4 T27 FSM bus MAX2 write enable
2.5-V E2 E34 FSM bus MAX2 chip select
2.5-V F3 J33 FSM bus MAX2 output enable
2.5-V F1 R27 FSM bus MAX2 byte enable 3
2.5-V F6 P29 FSM bus MAX2 byte enable 2
2.5-V F2 F34 FSM bus MAX2 byte enable 1
2.5-V F5 H34 FSM bus MAX2 byte enable 0
2.5-V C6 AF26 FSM bus flash clock
2.5-V A4 AT31 FSM bus flash write enable
2.5-V E6 AU31 FSM bus flash chip enable
2.5-V B4 AG27 FSM bus flash output enable
2.5-V D6 AT32 FSM bus flash ready
2.5-V C4 AL30 FSM bus flash reset
2.5-V B3 AN31 FSM bus flash address valid
2.5-V D1 R34 FPGA configuration data
2.5-V E5 R35 FPGA configuration data
2.5-V D2 W26 FPGA configuration data
2.5-V E4 V27 FPGA configuration data
2.5-V C3 P34 FPGA configuration data
2.5-V E3 N35 FPGA configuration data
2.5-V C2 W29 FPGA configuration data
2.5-V D3 W30 FPGA configuration data
2.5-V H4 AR11 FPGA configuration clock
2.5-V H3 AW35 FPGA configuration ready
2.5-V T2 AW36 FPGA configuration active
2.5-V J1 AV35 FPGA configuration done
2.5-V L5 AE28 Power monitor SPI clock
2.5-V M3 J35 Power monitor SPI data in
2.5-V L4 V28 Power monitor SPI data out
2.5-V N1 AB31 Power monitor 0 chip select
2.5-V L3 H35 Power monitor 1 chip select
2.5-V N2 G35 Power monitor frequency
2.5-V R1 W34 Temperature monitor SMB clock
2.5-V R4 AH32 Temperature monitor SMB data
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation
Chapter 2: Board Components 2–11
MAX II CPLD EPM2210 System Controller
Table 2–6. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 4 of 4)
Schematic Signal
Name
OVERTEMPn
ALERTn
PHASE_0
PHASE_90
PHASE_135
PHASE_270
MAX_ERROR
MAX_LOAD
MAX_CONF_DONEn
USB_LED
HSMA_PRSNTn
HSMB_PRSNTn
MAX_DIP
USB_DISABLEn
LCD_PWRMON
FAN_FORCE_ON
CLK_SEL
CLK_ENABLE
PGM3
PGM2
PGM1
PGM0
RESET_CONFIGn
CPU_RESETn
SRAM_MODE
SRAM_ZZ
CLK50_EN
CLK100_EN
CLK100_SDA
CLK100_SCL
CLK125_EN
CLK148_EN
CLK155_EN
CLK156_EN
CLKIN_50
CLK_CONFIG
I/O Standard
EPM2210
Pin Number
EP4SGX230
Pin Number
Description
2.5-V P5 — Temperature monitor over-temperature indicator
2.5-V M2 — Temperature monitor alert
2.5-V T6 — Power clock 0 degrees
2.5-V R7 — Power clock 90 degrees
2.5-V P8 — Power clock 135 degrees
2.5-V T7 — Power clock 270 degrees
2.5-V G3 — FPGA configuration error LED
2.5-V G2 — FPGA configuration active LED
2.5-V E15 — FPGA configuration done LED
2.5-V F12 — Embedded USB-Blaster active
2.5-V J16 — HSMC port A present
2.5-V J13 — HSMC port B present
2.5-V F15 — DIP-reserved
2.5-V G14 — DIP-embedded USB-Blaster disable
2.5-V R5 — DIP-MAX2 LCD drive enable
2.5-V P7 — DIP-force fan on switch
2.5-V T5 — DIP-clock select SMA or oscillator
2.5-V N7 — DIP-clock oscillator enable
2.5-V J3 — Rotary switch input
2.5-V K1 — Rotary switch input
2.5-V J4 — Rotary switch input
2.5-V J2 — Rotary switch input
2.5-V K2 — Force FPGA configuration push-button switch
2.5-V M9 V34 Reset push-button switch
2.5-V P4 — SRAM mode
2.5-V L14 — SRAM sleep mode
2.5-V G12 — 50 MHz oscillator enable
2.5-V G16 — 100 MHz oscillator enable
2.5-V A2 — 100 MHz programming data
2.5-V C15 — 100 MHz programming clock
2.5-V H16 — 125 MHz oscillator enable
2.5-V H13 — 148 MHz oscillator enable
2.5-V H15 — 155 MHz oscillator enable
2.5-V H14 — 156 MHz oscillator enable
2.5-V J5 AC34 50 MHz clock input
2.5-V J12 — 125 MHz configuration clock
November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual
2–12 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Tab le 2 –7 lists the MAX II CPLD EPM2210 System Controller component reference
and manufacturing information.
Table 2–7. MAX II CPLD EPM2210 System Controller Component Reference and Manufacturing Information
Board Reference Description Manufacturer
U30
IC - MAX II CPLD EPM2210
256FBGA -3 LF 1.8V VCCINT
Altera
Corporation EPM2210GF256C3N www.altera.com
Configuration, Status, and Setup Elements
This section describes the board's configuration, status, and setup elements.
Configuration
This section describes the FPGA, flash memory, and MAX II CPLD EPM2210 System
Controller device programming methods supported by the Stratix IV GX FPGA
Development Board, 530 Edition. The Stratix IV GX FPGA Development Board, 530
Edition supports three configuration methods:
■ Embedded USB-Blaster is the default method for configuring the FPGA at any
time using the Quartus II Programmer in JTAG mode with the supplied USB cable.
■ Flash memory download is used for configuring the FPGA using stored images
from the flash memory on either power-up or pressing the reset configuration
push-button switch (S1).
■ External USB-Blaster for configuring the FPGA using the external USB-Blaster.
Manufacturing
Part Number
Manufacturer
Website
FPGA Programming over Embedded USB-Blaster
The USB-Blaster is implemented using a type-B USB connector (J7), a FTDI USB 2.0
PHY device (U39), and an Altera MAX II CPLD (U30). This allows the configuration
of the FPGA using a USB cable directly connected between the USB port on the board
(J7) and a USB port of a PC running the Quartus II software. The JTAG chain is
normally mastered by the embedded USB-Blaster found in the MAX
EPM2210 System Controller.
II CPLD
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation
Chapter 2: Board Components 2–13
Embedded
Blaster
GPIO
TCK
4SGX230
FPGA
Analog
Switch
EPM2210
System
Controller
HSMC
Port A
HSMC
Port B
GPIO
TMS
GPIO
TDO
GPIO
TDI
JTAG Master
GPIO
DISABLE
JTAG Master/Slave
JTAG Master/Slave
Installed
HSMC
Card
Installed
HSMC
Card
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
JTAG Slave
JTAG Slave
Analog
Switch
Analog
Switch
EPM2210_JTAG_EN
HSMA_JTAG_EN
HSMB_JTAG_EN
ALWAYS
ENABLED
(in chain)
SW6.1
SW6.2
SW6.3
SW4.2
10-pin
JTAG Header
Flash
Memory
(on install)
PCI Express
Edge
Connector
JTAG Master/Slave
PCI Express
Motherboard
TCK
TMS
TDI
TDO
Analog
Switch
PCIE_JTAG_EN
SW6.4
Embedded
Blaster
Connection
USB
PHY
J7
J8
Configuration, Status, and Setup Elements
The embedded USB-Blaster is automatically disabled when an external USB-Blaster is
connected to the JTAG chain. Figure 2–4 illustrates the JTAG chain.
Figure 2–4. JTAG Chain
November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual
2–14 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Each jumper shown in Figure 2–4 is located in the JTAG DIP switch (SW6) on the back
of the board. To connect a device or interface in the chain, their corresponding switch
must be in the down position. Push all the switches in the up position to only have the
FPGA in the chain.
The MAX
II CPLD EPM2210 System Controller must be in the chain to use some of the
GUI interfaces. For this setting, push the left-most switch in the down position and all
other switches in the up position.
Flash Programming
Flash programming is possible through a variety of methods using the Stratix IV GX
device.
The default method is to use the factory design called the Board Update Portal. This
design is an embedded webserver, which serves the Board Update Portal web page.
The web page allows you to select new FPGA designs including hardware, software,
or both in an industry-standard S-Record File (.flash) and write the design to the user
hardware page (page 1) of the flash over the network.
The secondary method is to use the pre-built PFL design included in the development
kit. The development board implements the Altera PFL megafunction for flash
programming. The PFL megafunction is a block of logic that is programmed into an
Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for
writing to a compatible flash device. This pre-built design contains the PFL
megafunction that allows you to write either page 0, page 1, or other areas of flash
over the USB interface using the Quartus II software. This method is used to restore
the development board to its factory default settings.
Other methods to program the flash can be used as well, including the Nios
®
II
processor.
f For more information on the Nios II processor, refer to the Nios II Processor page of
the Altera website.
FPGA Programming from Flash Memory
On either power-up or by pressing the reset configuration push-button switch (S1),
the MAX
the FPGA from the flash memory. The PFL megafunction reads 16-bit data from the
flash memory and converts it to fast passive parallel (FPP) format. This 8-bit data is
then written to the FPGA’s dedicated configuration pins during configuration.
Figure 2–5 shows the PFL configuration.
II CPLD EPM2210 System Controller’s parallel flash loader (PFL) configures
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation
Chapter 2: Board Components 2–15
MAX II CPLD
EPM2210 System Controller
FPGA_DATA [7:0]
FPGA_DCLK
FLASH_A [25:1]
FLASH_D [15:0]
DATA [7:0]
DCLK
INIT_DONE
nSTATUS
nCONFIG
CONF_DONE
MSEL0
MSEL1
MSEL2
MSEL3
2.5 V
10 kΩ
nCE
CFI Flash
CONF_DONE LED
10 kΩ
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_A [25:1]
FLASH_D [15:0]
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_RSTn
FLASH_ADVn
MSEL [3:0]
FPGA_nCONFIG
FPGA_CONF_DONE
FSM Bus Interface
FLASH_RYBSYn
Rotary Switch
PGM [2:0]
FPGA_nSTATUS
USB_DISABLEn
2.5 V
10 kΩ
125 MHz
2.5 V
FLASH_ADVn
RESET_CONFIGn
CONF_DONE_LED
2.5 V
10 kΩ
FLASH_CLK
FLASH_CLK
FLASH_RSTn
FLASH_RSTn
50 MHz
CONFIG_CLK
External JTAG Detect
Configuration, Status, and Setup Elements
Figure 2–5. PFL Configuration
Tab le 2 –8 shows the flash memory map storage.
Table 2–8. Flash Memory Map (Part 1 of 2)
Unused 128 0x03FE0000 – 0x03FFFFFF
User Software 11,797 0x034A0000 – 0x03FDFFFF
Name Size (Kbyte) Address
User Hardware 21,627 0x02000000 – 0x0349FFFF
November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual
zipfs—HTML, Web Content 5,898 0x01A60000 – 0x01FFFFFF
Factory Software 5,898 0x014C0000 – 0x01A5FFFF
Factory Hardware 21,627 0x00020000 – 0x014BFFFF
PFL Option Bits 32 0x00018000 – 0x0001FFFF
2–16 Chapter 2: Board Components
Table 2–8. Flash Memory Map (Part 2 of 2)
Name Size (Kbyte) Address
Board Information 32 0x00010000 – 0x00017FFF
Ethernet Option Bits 32 0x00008000 – 0x0000FFFF
User Design Reset Vector 32 0x00000000 – 0x00007FFF
Configuration, Status, and Setup Elements
There are two pages reserved for the FPGA configuration data. The factory hardware
page is considered page 0 and is loaded if the rotary switch is in position 0 and when
either power is cycled or the reset configuration push-button switch (S1) is pressed.
The user hardware page is considered page 1 and is loaded if the rotary switch is in
position 1 and when either power is cycled or the reset configuration push-button
switch (S1) is pressed.
FPGA Programming over External USB-Blaster
The JTAG programming header provides another method for configuring the FPGA
(U13) using an external USB-Blaster device with the Quartus II Programmer running
on a PC. The external USB-Blaster is connected to the board through the JTAG
connector (J8). The JTAG DIP switch (SW6) allows the MAX II CPLD device to be
removed from the JTAG chain so that the FPGA is the only device on the JTAG chain.
f For more information on the following topics, refer to the respective documents:
■ Board Update Portal, refer to the Stratix IV GX FPGA Development Kit, 530 Edition
User Guide.
■ PFL design, refer to the Stratix IV GX FPGA Development Kit, 530 Edition User
Guide.
■ PFL megafunction, refer to AN 386: Using the Parallel Flash Loader with the Quartus
II Software.
Status Elements
The development board includes status LEDs. This section describes the status
elements.
Tab le 2 –9 lists the LED board references, names, and functional descriptions.
Table 2–9. Board-Specific LEDs (Part 1 of 2)
Board Reference LED Name Description
D24 POWER Blue LED. Illuminates when 3.3-V power is active.
D5 CONF DONE
D26 Loading
Green LED. Illuminates when the FPGA is successfully configured. Driven by the
MAX II CPLD EPM2210 System Controller.
Green LED. Illuminates when the MAX II CPLD EPM2210 System Controller is
actively configuring the FPGA. Driven by the MAX II CPLD EPM2210 System
Controller wire-OR'd with the Embedded Blaster CPLD.
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation
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