Altera Stratix IV GX Edition User Manual
Transceiver Signal Integrity Development Kit, Stratix IV
GX Edition Reference Manual
Transceiver Signal Integrity Development Kit,
Stratix IV GX Edition Reference Manual
101 Innovation Drive
San Jose, CA 95134
www.altera.com
MNL-01042-2.1
Subscribe
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix IV GX Edition Reference Manual
Contents
Chapter 1. Overview
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Chapter 2. Board Components
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Featured Device: Stratix IV GX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
Embedded USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
Fast Passive Parallel Download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
JTAG Programming Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
Status and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
Board Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Flash Memory Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
Ethernet Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
Transceiver Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
Banana Jacks and Fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
Appendix A. Board Revision History
Single-Die Flash Version Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
Engineering Silicon Version Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
Banana Jacks and Fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2
November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix IV GX Edition Reference Manual
iv Contents
Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation
Stratix IV GX Edition Reference Manual
Introduction
The Transceiver Signal Integrity Development Kit, Stratix® IV GX Edition allows you
to evaluate the performance Stratix IV GX transceivers and the low power benefits of
the device. This document provides detailed pin-out and component reference
information required to create FPGA designs for implementation on the development
board.
f For information about setting up the Stratix IV GX transceiver signal integrity
development board, and using the included software, refer to the Transceiver Signal
Integrity Development Kit, Stratix IV GX Edition Getting Started User Guide.
General Description
The Stratix IV GX transceiver signal integrity development board provides a
hardware platform for evaluating the performance and signal integrity features of the
®
Altera
blocks:
1. Overview
Stratix IV GX devices. The board features the following major component
■ EP4SGX230KF40 FPGA
■ 0.9-V core
■ 1517-pin Fineline BGA (FBGA)
■ FPGA Configuration
■ MAX
■ Flash storage for two configuration images (factory and user)
■ On-Board USB-Blaster
■ JTAG header for external USB-Blaster with the Quartus II Programmer
®
II+Flash Fast Passive Parallel (FPP) configuration
TM
using the Quartus® II Programmer
November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix IV GX Edition Reference Manual
1–2 Chapter 1: Overview
General Description
■ Status and Setup Elements
■ System reset push button
■ CPU reset push button
■ Four-position spread spectrum clock selection DIP switch
■ Three configuration status LEDs (factory, user, error)
■ USB-Blaster activity LED
■ Ethernet link 10 LED
■ Ethernet link 100 LED
■ Ethernet link 1000 LED
■ Ethernet full duplex LED
■ Ethernet TX activity LED
■ Ethernet RX activity LED
■ Over-Temperature warning LED
■ Power LED
■ FPGA Clock Sources
■ FPGA Core Clock Sources
■ 25-MHz/100-MHz/125-MHz/200-MHz selectable spread spectrum clock
oscillator
■ 50-MHz clock oscillator
■ SMA connectors for external differential clock input
■ FPGA Transceiver Clock Sources
■ 100-MHz clock oscillator
■ Socketed clock oscillator
■ 156.25-MHz clock oscillator
■ SMA connectors for external differential clock input
■ Clock Outputs and Triggers
■ Two FPGA I/O clock outputs to SMA connectors
■ 100-MHz clock trigger output to SMA connector
■ Socketed clock trigger output to SMA connector
■ 156.25-MHz clock trigger output to SMA connector
Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation
Stratix IV GX Edition Reference Manual
Chapter 1: Overview 1–3
General Description
■ General User Input/Output
■ Eight-position user DIP switch
■ Six user push buttons
■ Four directional LCD menu push buttons
■ Hex rotary switch
■ Eight user LEDs
■ 16 character × 2 line LCD
■ Components and Interfaces
■ 10/100/1000 Ethernet PHY and RJ-45 Jack
■ Transceiver Channels
■ Six full-duplex transceiver channels from the same transceiver block
brought out to SMA connectors using stripline routing
■ One full-duplex transceiver channel brought out to SMA connectors using
microstrip routing
■ One channel brought out to SMAs with microstrip routing with 33 in. board
trace length on transmit and 7 in. board trace length on receive to simulate
the degradation associated with backplanes or long traces
■ Power
■ 14-V – 20-V DC input
■ 2.5-mm Barrel Jack for DC power input
■ On/Off slide power switch
■ On-Board power measurement circuitry
■ Heat Sink and Fan
■ 40-mm heat sink and 5-V DC fan combo
November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix IV GX Edition Reference Manual
1–4 Chapter 1: Overview
LCD
Power
Measure
24-bit
ADC
ADC
TEMP
Dual Temp
Sensor
Temp
Measure
TDIODES
5-V FAN
USB-Blaster
USB
Type-B
Conn.
FTDI
745BL
USB
PHY
MAX
7064A
CPLD
10/100/1000
Ethernet
RJ45+
Magnetics
Marvell
88E1111
Ethernet
PHY
Pwrgood
FPP
Configuration
Clock
Circuitry
512-Mb
Flash
Configuration
Status LEDs
MAX II
EPM1270
CPLD
PGMSEL
Jumper
2 Reset
Push Buttons
Push Buttons
Switches
Displays
4 Menu
Push Buttons
Rotary
Switch
16 Char × 2 Line LCD
8 User DIP
6 User
Push
Buttons
8 User
LEDs
Transceivers Connected
to SMA Connectors
Flash
FPP Config
2-wire Ch1
Power
Circuitry
2-wire Ch8
EP4SGX230KF40
Development Board Block Diagram
Development Board Block Diagram
Figure 1–1 shows the block diagram of the Stratix IV GX transceiver signal integrity
board.
Figure 1–1. Stratix IV GX Transceiver Signal Integrity Board Block Diagram
Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation
Stratix IV GX Edition Reference Manual
Chapter 1: Overview 1–5
Handling the Board
Handling the Board
When handling the board, it is important to observe the following static discharge
precaution:
c Without proper anti-static handling, the board can be damaged. Therefore, use anti-
static handling precautions when touching the board.
The Stratix IV GX transceiver signal integrity board must be stored between –40º C
and 100º C. The recommended operating temperature is between 0º C and 55º C.
November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix IV GX Edition Reference Manual
1–6 Chapter 1: Overview
Handling the Board
Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation
Stratix IV GX Edition Reference Manual
Introduction
1 A complete set of schematics, a physical layout database, and GERBER files for the
f For information about powering up the board and installing the development kit
2. Board Components
This chapter introduces all the important components on the Stratix IV GX transceiver
signal integrity development board. Figure 2–1 illustrates major component locations
and Table 2–1 lists a brief description of all features of the board.
development board reside in the Stratix IV GX transceiver signal integrity
development kit installation directory.
software, refer to the Transceiver Signal Integrity Development Kit, Stratix IV GX Edition
Getting Started User Guide.
This chapter consists of the following sections:
■ “Board Overview”
■ “Featured Device: Stratix IV GX” on page 2–6
■ “Configuration, Status, and Setup Elements” on page 2–9
■ “General User Input/Output” on page 2–15
■ “Flash Memory Device” on page 2–18
■ “Components and Interfaces” on page 2–20
■ “Power” on page 2–25
November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix IV GX Edition Reference Manual
2–2 Chapter 2: Board Components
Powe r
Switch
(SW1)
DC Power
Jack (J1)
Power LED (D3)
LCD Display (J24)
Power Circuit (U1-U12)
MAX II CPLD
(U32)
Flash Memory (U39)
Power Select
Switch (SW16)
LCD Directional
Buttons
(SW3-SW6)
Spread Spectrum
Clock (X2, U21)
IO CLK OUT
from FPGA to SMA (J16, J17)
Spread Spectrum
Clock Settings (SW2)
Config
Program
Selection
Jumper
(J62)
User DIP Switches
(SW7)
156.25 MHz Osc (Y5)
External Clock SMA to FPGA
(J14, J15)
100 MHz Osc (Y4)
Socketed
Osc (Y3)
CPU Reset (SW9)
Board Reset (SW8)
Config Status LEDs
(D16-D18)
Fan Connector (J12)
Fan Jumper (J64)
Fan LED (D6)
Embedded
USB-Blaster
Activity LED (D7)
GXB2
TX/RX
SMAs
(J31, J33,
J35, J37)
GXB1
RX SMAs
(J38, J40,
J42, J44,
J46, J48,
J50, J52,
J54, J56,
J58, J60)
GXB1
TX SMAs
(J39, J41,
J43, J45,
J47, J49,
J51, J53,
J55, J57,
J59, J61)
Ethernet
Status
LEDs
(D19-D24)
Embedded
USB-Blaster
(CN1)
Stratix IV GX
FPGA (U33)
10/100 /1000
Ethernet (J68)
User
Push-Buttons
(SW10-SW15)
GXB0
External
SMA
Refclk0
to FPGA
(J19, J20)
User
LEDs
(D8-D15)
External Power
Input Banana
Jacks (J2-J5, J7, J9-J10)
GXB0 TX/RX
SMAs
(J30, J32,
J34, J36)
Board Overview
Board Overview
This section provides an overview of the Stratix IV GX transceiver signal integrity
development board, including an annotated board image and component
descriptions. Figure 2–1 shows an overview of the board features.
Figure 2–1. Overview of the Stratix IV GX Transceiver Signal Integrity Board Features
(1)
Note to Figure 2–1:
(1) The Stratix IV GX Transceiver Signal Integrity board depicted here is the engineering silicon board. For the production silicon board, components
F4, F5, J8, R21, and R23 have been removed and F84 has been added.
Tab le 2– 1 describes the components and lists their corresponding board references.
Table 2–1. Stratix IV GX Transceiver Signal Integrity Development Board Components (Part 1 of 4)
(1)
Board Reference Type Description
Featured Devices
U33 EP4SGX230KF40 Stratix IV GX device in a 1517-pin FBGA package.
Configuration, Status, and Setup Elements
Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation
Stratix IV GX Edition Reference Manual
Chapter 2: Board Components 2–3
Board Overview
Table 2–1. Stratix IV GX Transceiver Signal Integrity Development Board Components (Part 2 of 4)
(1)
Board Reference Type Description
J28 JTAG programming header
J26
J63
MAX II JTAG configuration
jumper
JTAG for embedded
USB-Blaster MAX II CPLD
U32 MAX II CPLD
D6 Fan LED
JTAG programming header for connecting an Altera USB-Blaster
dongle to program the FPGA and MAX II CPLD devices.
Jumper to bypass the MAX II CPLD from the JTAG programming
chain.
JTAG for embedded USB-Blaster MAX II CPLD device programming.
Altera EPM1270256C3N, MAX II 256-pin CPLD for MAX II+Flash FPP
configuration.
Indicates an FPGA over-temperature condition exists and a fan should
be attached to the FPGA and running.
D16–D18 Configuration status LEDs LEDs to indicate the status of FPP configuration.
J62
J65
Configuration program select
jumper
Socketed Y3 OSC
enable/disable jumper
Jumper to select the flash configuration image to load upon power-on
or reset.
Jumper to enable or disable the Y3 OSC.
J66 Y4 OSC enable/disable jumper Jumper to enable or disable the Y4 OSC.
J67 Y5 OSC enable/disable jumper Jumper to enable or disable the Y5 OSC.
D3 Power LED Blue LED indicates board power status.
D7 USB-Blaster LED Green activity status LED for embedded USB-Blaster.
D19–D24
J6 VCCA voltage selection jumper This jumper selects the V
J11
SW16
SW2
Bank of Ethernet LINK and
Status LEDs
VCCH voltage selection
jumper
Power measurement rotary
switch
Spread spectrum
configuration DIP switch
Ethernet Link, Speed, Full Duplex, Transmit and Receive activity LEDs.
voltage to the FPGA.
CCA
This jumper selects the V
voltage to the FPGA.
CCH
This switch selects 1 of 6 measured FPGA power rails to display on the
LCD.
DIP switch to set the spread spectrum output clock frequency and
down-spread percentages.
J18 Spread spectrum clock trigger Spread spectrum clock source routed to SMA for triggering purposes.
J21 Y3 OSC clock trigger Y3 oscillator clock source routed to SMA for triggering purposes.
J22 Y4 OSC clock trigger Y4 oscillator clock source routed to SMA for triggering purposes.
J23 Y5 OSC clock trigger Y5 oscillator clock source routed to SMA for triggering purposes.
J14, J15
J19, J20
J16, J17
Differential SMA clock input to
FPGA core
Differential SMA clock input to
FPGA transceiver
Differential SMA clock output
from FPGA core
SMA for receiving a differential external clock input to the FPGA core.
SMA for receiving a differential external clock input to the FPGA
transceiver.
SMA for sending a differential clock output from the FPGA core.
Clock Circuitry
Y2, U20 50-MHz OSC and clock buffer 50-MHz clock to FPGA and MAX II CPLD.
Y3, U22
November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
Socketed OSC and clock
buffer
5×7-mm oscillator socket for installing alternate oscillator frequencies
to the FPGA transceivers.
Stratix IV GX Edition Reference Manual
2–4 Chapter 2: Board Components
Board Overview
Table 2–1. Stratix IV GX Transceiver Signal Integrity Development Board Components (Part 3 of 4)
(1)
Board Reference Type Description
Y4, U23
Y5, U24
100-MHz OSC and clock
buffer
156.25-MHz OSC and clock
buffer
100-MHz clock to FPGA transceivers.
156.25-MHz clock to FPGA transceivers.
X1 6-MHz XTAL XTAL for FTDI USB PHY Device.
Y1 24-MHz OSC 24-MHz oscillator for embedded USB-Blaster MAX II CPLD.
X3 25-MHz OSC 25-MHz oscillator for Marvell 88E1111 Ethernet PHY device.
X2, U21
25-MHz OSC and spread
spectrum clock buffer
25-MHz oscillator and spread spectrum clock buffer circuitry.
General User Input and Output
SW7 Bank of 8 user DIP switches User DIP switches.
SW10–SW15 Bank of 6 user push buttons User push buttons.
D8–D15 Bank of 8 user LEDs User LEDs.
SW3–SW6 LCD control push buttons
J25
General purpose user I/O
header field
Up, Down, Back, and Enter push buttons for implementing user LCD
menu/control.
Four user I/Os brought out to a 0.1 in. header field.
J24 LCD interface header Header for interfacing a 16 character × 2 line LCD.
Memory Devices
U39 Flash memory 512-Mb flash memory.
Components and Interfaces
CN1 USB Type-B connector USB interface for embedded USB-Blaster.
U17 MAX II CPLD
Altera EPM7064AETC44 MAX II CPLD device for embedded
USB-Blaster circuitry.
J68 Ethernet RJ45 jack Halo HFJ11-1G02E RJ45 Ethernet jack with integrated magnetic.
U40 10/100/1000 Ethernet PHY Marvell 88E1111 triple speed Ethernet PHY.
J34, J36 GXB0 transmit channel 0 Transceiver GXB0 transmit channel 0 connected to SMA.
J30, J32 GXB0 receive channel 0 Transceiver GXB0 receive channel 0 connected to SMA.
J39, J41 GXB1 transmit channel 1 Transceiver GXB1 transmit channel 1 connected to SMA.
J43, J45 GXB1 transmit channel 2 Transceiver GXB1 transmit channel 2 connected to SMA.
J55, J57 GXB1 transmit channel 3 Transceiver GXB1 transmit channel 3 connected to SMA.
J59, J61 GXB1 transmit channel 4 Transceiver GXB1 transmit channel 4 connected to SMA.
J47, J49 GXB1 transmit channel 5 Transceiver GXB1 transmit channel 5 connected to SMA.
J51, J53 GXB1 transmit channel 6 Transceiver GXB1 transmit channel 6 connected to SMA.
J38, J40 GXB1 receive channel 1 Transceiver GXB1 receive channel 1 connected to SMA.
J42, J44 GXB1 receive channel 2 Transceiver GXB1 receive channel 2 connected to SMA.
J54, J56 GXB1 receive channel 3 Transceiver GXB1 receive channel 3 connected to SMA.
J58, J60 GXB1 receive channel 4 Transceiver GXB1 receive channel 4 connected to SMA.
J46, J48 GXB1 receive channel 5 Transceiver GXB1 receive channel 5 connected to SMA.
J50, J52 GXB1 receive channel 6 Transceiver GXB1 receive channel 6 connected to SMA.
Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation
Stratix IV GX Edition Reference Manual
Loading...