Altera Stratix IV GT Edition User Manual
Transceiver Signal Integrity Development Kit, Stratix IV
GT Edition Reference Manual
Transceiver Signal Integrity Development Kit,
Stratix IV GT Edition Reference Manual
101 Innovation Drive
San Jose, CA 95134
www.altera.com
MNL-01052-1.1
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described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
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ISO
9001:2008
Registered
November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix IV GT Edition Reference Manual
Contents
Chapter 1. Overview
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Chapter 2. Board Components
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Featured Device: Stratix IV GT Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
Embedded USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
Fast Passive Parallel Download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
JTAG Programming Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
Status and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
Board Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Flash Memory Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
Ethernet Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
Transceiver Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
Banana Jacks and Fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
Appendix A. Board Revision History
Single-Die Flash Version Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix IV GT Edition Reference Manual
iv Contents
Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation
Stratix IV GT Edition Reference Manual
Introduction
The Transceiver Signal Integrity Development Kit, Stratix® IV GT Edition allows you
to evaluate the performance the Stratix IV GT transceivers and the low power benefits
of the device itself. This document provides the detailed pin-out and component
reference information required to create FPGA designs for implementation on the
development board.
f For information about setting up the Stratix IV GT transceiver signal integrity
development board, and using the included software, refer to the Transceiver Signal
Integrity Development Kit, Stratix IV GT Edition User Guide.
General Description
The Stratix IV GT transceiver signal integrity development board provides a
hardware platform for evaluating the performance and signal integrity features of the
®
Altera
blocks:
1. Overview
Stratix IV GT devices. The board features the following major component
■ EP4S100G2F40I1N FPGA
■ 0.95-V core
■ 1517-pin Fineline BGA (FBGA)
■ FPGA Configuration
■ MAX
■ Flash storage for two configuration images (factory and user)
■ On-Board USB-Blaster
■ JTAG header for external USB-Blaster with the Quartus II Programmer
■ On-Board Memory
■ 64-MB synchronous flash
®
II+Flash Fast Passive Parallel (FPP) configuration
TM
using the Quartus® II Programmer
November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix IV GT Edition Reference Manual
1–2 Chapter 1: Overview
General Description
■ Status and Setup Elements
■ System reset push button
■ CPU reset push button
■ 4-position spread spectrum clock selection DIP switch
■ Three configuration status LEDs (factory, user, configuration error)
■ USB-Blaster activity LED
■ Ethernet link 10 LED
■ Ethernet link 100 LED
■ Ethernet link 1000 LED
■ Ethernet full duplex LED
■ Ethernet TX activity LED
■ Ethernet RX activity LED
■ Over-Temperature warning LED
■ Power LED
■ FPGA Clock Sources
■ FPGA core clock sources
■ 25-MHz/100-MHz/125-MHz/200-MHz selectable spread spectrum clock
oscillator
■ 50-MHz clock oscillator
■ SMA connectors for external differential clock input
■ FPGA transceiver clock sources
■ 100-MHz clock oscillator
■ 644.53-MHz clock oscillator
■ 706.25-MHz clock oscillator
■ SMA connectors for external differential clock input
■ Clock Outputs and Triggers
■ Two FPGA I/O clock outputs to SMA connectors
■ 100-MHz clock trigger output to SMA connector
■ 644.53-MHz clock trigger output to SMA connector
■ 706.25-MHz clock trigger output to SMA connector
Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation
Stratix IV GT Edition Reference Manual
Chapter 1: Overview 1–3
General Description
■ General User Input/Output
■ 8-position user DIP switch
■ Six user push buttons
■ Hex rotary switch
■ Eight user LEDs
■ 16 character × 2 line LCD
■ Components and Interfaces
■ 10/100/1000 Ethernet PHY and RJ-45 jack
■ Transceiver channels
■ Six full-duplex transceiver channels from GXB0 transceiver block brought
out to the backplane connectors
■ Four full-duplex transceiver channels from GXB1 transceiver block brought
out to the SMA connectors
■ Two channels from GXB2 transceiver block brought out to the SMA
connectors. One channel is routed with 15 inches of board trace length on
transmit and 5 inches board trace length on receive to simulate the
degradation associated with long trace PCB routing
■ Power
■ 14-V – 20-V DC input
■ 2.5-mm Barrel Jack for DC power input
■ On/Off slide power switch
■ On-Board power measurement circuitry
■ Heat Sink and Fan
■ 40-mm heat sink and 5-V DC fan combo
November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix IV GT Edition Reference Manual
1–4 Chapter 1: Overview
GT
LCD
Power
Measure
24-bit
ADC
Dual Temp
Sensor
Temp
Measure
TDIODES
5-V FAN
USB-Blaster
USB
Type-B
Conn
USB
PHY
MAX
7064A
CPLD
10/100/1000
Ethernet
RJ45
Magnetics
SMSC
8700
Ethernet
PHY
FPP
Configuration
Clock
Circuitry
512-Mbit
Flash
Configuration
Status
LEDs
MAX
7256A
CPLD
PGMSEL
Jumper
2 Reset
Buttons
Buttons
Switches
Displays
Rotary
Switch
16 Char × 2 Line LCD
8 User DIP
6 User
Buttons
8 User
LEDs
Transceivers
Flash
FPP Config
2-wire Ch1
Power
Circuitry
2-wire Ch8
EP4S100G2F40I2N
Backplane
Connectors
ADC
Header
Pwrgood
TEMP
Development Board Block Diagram
Development Board Block Diagram
Figure 1–1 shows the block diagram of the Stratix IV GT transceiver signal integrity
board.
Figure 1–1. Stratix IV GT Transceiver Signal Integrity Board Block Diagram
Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation
Stratix IV GT Edition Reference Manual
Chapter 1: Overview 1–5
Handling the Board
Handling the Board
When handling the board, it is important to observe the following static discharge
precaution:
c Without proper anti-static handling, the board can be damaged. Therefore, use
anti-static handling precautions when touching the board.
The Stratix IV GT transceiver signal integrity board must be stored between –40º C
and 100º C. The recommended operating temperature is between 0º C and 55º C.
November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix IV GT Edition Reference Manual
1–6 Chapter 1: Overview
Handling the Board
Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation
Stratix IV GT Edition Reference Manual
Introduction
1 A complete set of schematics, a physical layout database, and GERBER files for the
f For information about powering up the board and installing the development kit
2. Board Components
This chapter introduces all the important components on the Stratix IV GT transceiver
signal integrity development board. Figure 2–1 illustrates major component locations
and Table 2–1 provides a brief description of all features of the board.
development board reside in the Stratix IV GT transceiver signal integrity
development kit installation directory.
software, refer to the Transceiver Signal Integrity Development Kit, Stratix IV GT Edition
User Guide.
This chapter consists of the following sections:
■ “Board Overview”
■ “Featured Device: Stratix IV GT Device” on page 2–5
■ “Configuration, Status, and Setup Elements” on page 2–9
■ “General User Input/Output” on page 2–16
■ “Flash Memory Device” on page 2–18
■ “Components and Interfaces” on page 2–20
■ “Power” on page 2–25
November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix IV GT Edition Reference Manual
2–2 Chapter 2: Board Components
Powe r
Switch
(SW1)
DC Power Jack (J1)
Power LED
(D3)
LCD Display (J24)
Powe r
Circuit
(U1-U13)
MAX II CPLD (U32)
Flash Memory (U39)
Power Select Switch (SW16)
Spread Spectrum
Clock (X2, U21)
IO CLK OUT from
FPGA to SMA (J16, J17)
Config
Program
Selection
Jumper
(J62)
User DIP Switches (SW7)
706.25 MHz Osc (Y5)
External Clock
SMA to FPGA
(J14, J15)
100 MHz Osc (Y4)
644.53 MHz Osc (Y3)
CPU Reset (SW9)
Board Reset (SW8)
Config Status LEDs
(D16-D18)
Fan Connector (J12)
Fan Jumper (J64)
Fan LED (D6)
Embedded USB-Blaster Activity LED (D7)
GXB2
TX/RX
SMAs
(J30-J37)
GXB1
TX/RX
SMAs
(J38-J45,
J54-J61)
Ethernet Status
LEDs (D19-D24)
Embedded USB-Blaster (CN1)
Stratix IV GT FPGA (U33)
10/100 /1000 Ethernet (J68)
User Push-Buttons
(SW10-SW15)
User LEDs (D8-D15)
External Power
Input Banana Jacks
(J2-J4, J7-J10)
GXB0 TX/RX
to Backplane
Connector
(J70-J71)
External
Refclk
SMAs
(J19, J20)
Board Overview
Board Overview
This section provides an overview of the Stratix IV GT transceiver signal integrity
development board, including an annotated board image and component
descriptions. Figure 2–1 provides an overview of the board features.
Figure 2–1. Overview of the Stratix IV GT Transceiver Signal Integrity Board Features
Tab le 2– 1 describes the components and lists their corresponding board references.
Table 2–1. Stratix IV GT Transceiver Signal Integrity Development Board Components (Part 1 of 4)
Board Reference Type Description
Featured Devices
U33 EP4S100G2F40I1N Stratix IV GT device in a 1517-pin FBGA package.
Configuration, Status, and Setup Elements
J28 JTAG programming header
J26
J63
Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation
Stratix IV GT Edition Reference Manual
MAX II JTAG configuration
jumper
JTAG for embedded
USB-Blaster MAX II CPLD
JTAG programming header for connecting an Altera USB-Blaster
dongle to program the FPGA and MAX II CPLD devices.
Jumper to bypass the MAX II CPLD from the JTAG programming
chain.
JTAG for embedded USB-Blaster MAX II CPLD device programming.
Chapter 2: Board Components 2–3
Board Overview
Table 2–1. Stratix IV GT Transceiver Signal Integrity Development Board Components (Part 2 of 4)
Board Reference Type Description
U32 MAX II CPLD
D6 Fan LED
Altera EPM1270256C3N, MAX II 256-pin CPLD for MAX II+FPP
configuration.
Indicates an FPGA over-temperature condition exists and a fan should
be attached to the FPGA and running.
D16–D18 Configuration status LEDs LEDs to indicate the status of FPP configuration.
J62
Configuration program select
jumper
Jumper to select the flash configuration image to load upon power-on
or reset.
J65 Y3 OSC enable/disable jumper Jumper to enable or disable the Y3 OSC.
J66 Y4 OSC enable/disable jumper Jumper to enable or disable the Y4 OSC.
J67 Y5 OSC enable/disable jumper Jumper to enable or disable the Y5 OSC.
D3 Power LED Blue LED to indicate board power status.
D7 USB-Blaster LED Green activity status LED for the embedded USB-Blaster.
D19–D24
SW16
SW2
Bank of Ethernet LINK and
Status LEDs
Power measurement rotary
switch
Spread spectrum
configuration DIP switch
Ethernet Link, Speed, Full Duplex, Transmit and Receive activity LEDs.
This switch selects 1 of 6 measured FPGA power rails to display on the
LCD.
DIP switch to set the spread spectrum output clock frequency and
down-spread percentages.
J18 Spread spectrum clock trigger Spread spectrum clock source routed to SMA for triggering purposes.
J21 Y3 OSC clock trigger Y3 oscillator clock source routed to SMA for triggering purposes.
J22 Y4 OSC clock trigger Y4 oscillator clock source routed to SMA for triggering purposes.
J23 Y5 OSC clock trigger Y5 oscillator clock source routed to SMA for triggering purposes.
J14, J15
J19, J20
J16, J17
Differential SMA clock input to
FPGA core
Differential SMA clock input to
FPGA transceiver
Differential SMA clock output
from FPGA core
SMA for receiving a differential external clock input to the FPGA core.
SMA for receiving a differential external clock input to the FPGA
transceiver.
SMA for sending a differential clock output from the FPGA core.
Clock Circuitry
Y2, U20 50-MHz OSC and clock buffer 50-MHz clock to the FPGA and MAX II CPLD.
Y3, U22
Y4, U23
Y5, U24
644.53-MHz OSC and clock
buffer
100-MHz OSC and clock
buffer
706.25-MHz OSC and clock
buffer
644.53-MHz clock to the FPGA transceivers.
100-MHz clock to the FPGA transceivers.
706.25-MHz clock to the FPGA transceivers.
X1 6-MHz XTAL XTAL for FTDI USB PHY device.
Y1 24-MHz OSC 24-MHz oscillator for embedded USB-Blaster MAX II CPLD.
X3 25-MHz OSC 25-MHz oscillator for Marvell 88E1111 Ethernet PHY device.
X2, U21
November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
25-MHz OSC and spread
spectrum clock buffer
25-MHz oscillator and spread spectrum clock buffer circuitry.
Stratix IV GT Edition Reference Manual
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