Altera Stratix IV E FPGA Development Board User Manual
Stratix IV E FPGA Development Board Reference Manual
Stratix IV E FPGA Development Board
Reference Manual
101 Innovation Drive
San Jose, CA 95134
www.altera.com
MNL-01048-1.2
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© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.
& Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective
holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance
with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
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customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or
services.
Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation
Contents
Chapter 1. Overview
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Chapter 2. Board Components
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Featured Device: Stratix IV E Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
MAX II CPLD EPM2210 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
FPGA Programming over Embedded USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
Flash Memory Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
MAX II DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
User DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19
Clock Enable DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19
JTAG Chain Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
On-Board Memory Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
Reset Configuration Push-button Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
Rotary Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
Stratix IV E FPGA Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
User-Defined Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
General User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
HSMC User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
Seven-Segment LED Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28
Graphics LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30
Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
Embedded USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33
High-Speed Mezzanine Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–42
DDR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–42
QDR II+ SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–47
RLDRAM II CIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–49
SSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–52
Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–55
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–57
May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual
iv Contents
Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–58
Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–59
Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–60
Appendix A. Board Revision History
Graphics LCD Version Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
Single-Die Flash Version Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2
Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation
Introduction
This document describes the hardware features of the Altera® Stratix® IV E FPGA
development board, including the detailed pin-out and component reference
information required to create custom FPGA designs that interface with all
components of the board.
General Description
The Stratix IV E FPGA development board provides a hardware platform for
developing and prototyping high-performance and logic-intensive designs based on
Altera Stratix IV E devices. The board provides a wide range of peripherals and
memory interfaces to facilitate the development of the Stratix IV E FPGA designs.
Two high-speed mezzanine card (HSMC) connectors are available to add additional
functionality via a variety of HSMCs available from Altera and various partners.
1. Overview
f To see a list of the latest HSMCs available or to download a copy of the HSMC
specification, refer to the Development Board Daughtercards page of the Altera
website.
Stratix IV E devices provide a solution for applications that do not require high-speed
CDR-based transceivers, but are logic, user I/O, or memory intensive.
f For more information on the following topics, refer to the respective documents:
■ Stratix IV device family, refer to the Stratix IV Device Handbook.
■ Stratix IV E FPGA Development Kit, refer to the Stratix IV E FPGA Development Kit
User Guide.
■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.
Board Component Blocks
The board features the following major component blocks:
■ Stratix IV E EP4SE530H35C2N FPGA in the 1152-pin hybrid FineLine BGA
(FBGA) package
■ 531,200 LEs
■ 212,480 adaptive logic modules (ALMs)
■ 8 phase locked loops (PLLs)
■ 1024 18-bit x 18-bit multipliers
■ 0.9-V core power
May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual
1–2 Chapter 1: Overview
Board Component Blocks
■ MAX
®
II EPM2210F256C3N CPLD in the 256-pin FBGA package
■ 2.5-V core power
■ FPGA configuration circuitry
■ MAX
II CPLD EPM2210 System Controller and Flash fast passive parallel (FPP)
configuration
■ On-board USB-Blaster
■ On-Board ports
■ USB 2.0 – FTDI 12-Mbps PHY
■ One Gigabit Ethernet port
■ Two HSMC expansion ports
■ On-Board memory
■ 2-gigabytes (GB) DDR3 SDRAM DIMM with a 72-bit data bus
■ 72-megabits (Mb) QDR II+ SRAM with a 18-bit data bus
■ 576-Mb RLDRAM II combined input/output (CIO) with a 36-bit data bus
■ 18-Mb Synchronous Static Random Access Memory (SSRAM) with a 36-bit
TM
for use with the Quartus® II Programmer
data bus
■ 512-Mb Flash with a 16-bit data bus
■ On-Board clocking circuitry
■ Five on-board oscillators
■ 50-MHz oscillator (one single-ended input to the FPGA and Max II CPLD)
■ 66-MHz oscillator (two differential inputs to the FPGA)
■ 100-MHz oscillator (one differential inputs to the FPGA)
■ 100-MHz oscillator (one single-ended input to the Max II CPLD)
■ 125-MHz oscillator (two differential inputs to the FPGA)
■ SMA connectors for external clock input
■ SMA connector for clock output
■ HSMC input and output ports
Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation
Chapter 1: Overview 1–3
Board Component Blocks
■ General user I/O
■ LEDs and displays
■ Eight user LEDs
■ One power on LED
■ One configuration done LED
■ Three HSMC LEDs per interface — one transmit (TX), one receive (RX) and
one presence detect (PSNTn)
■ Factory LEDs (LOAD, FACTORY, ERROR, USER_1, and USER_2)
■ Single quad seven-segment display
■ 128 x 64 graphics display
■ 16-character x 2-line LCD display
■ Push-Button switches
■ One CPU reset push-button switch
■ One system reset push-button switch
■ One user reset push-button switch
■ One factory configuration push-button switch
■ One reset configuration push-button switch
■ Four general user push-button switches
■ One 16-position rotary switch
■ DIP switches
■ One eight-position user DIP switch
■ One eight-position MAX
II CPLD EPM2210 System Controller specific DIP
switch
■ One four-position clock enable DIP switch
■ Power supply
■ 14-V – 20-V DC input
■ On-board power measurement circuitry
■ 20-W per HSMC interface
■ Mechanical
■ 8.25” x 7” board
■ Bench-top operation
May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual
1–4 Chapter 1: Overview
EP4SE530H35
10/100/1000
Ethernet
128 x 64
Graphic Display
RLDRAM II CIO
(x36)
Quad 7-Seg,
User LEDs Push-Button
Switches
14-pin LCD
Header
CPLD
(x32)
64 MB Flash
(x16)
4 MB SSRAM
(x32)
RJ45
Jack
Power
Measure
2.5 V
CMOS
2.5 V
CMOS
CMOS +
LVDS
2.5 V
CMOS
1.5 V/1.8 V
HSTL
2.5 V CMOS
1.5 V
SSTL
CMOS +
LVDS
100 MHz
XTAL
Port
USB
Blaster
66 MHz XTAL
4 MB QDR II+
(x18)
SMA Input
1.5 V/1.8 V
HSTL
125 MHz XTAL
SMA Output
2 GB DDR3 SDRAM DIMM (x72)
Development Board Block Diagram
Development Board Block Diagram
Figure 1–1 shows the block diagram of the Stratix IV E FPGA development board.
Figure 1–1. Stratix IV E FPGA Development Board Block Diagram
Handling the Board
c Without proper anti-static handling, the board can be damaged. Therefore, use
When handling the board, it is important to observe the following static discharge
precaution:
anti-static handling precautions when touching the board. The Stratix IV E FPGA
Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation
The recommended operating temperature is between 0° C and 55° C.
development board must be stored in a temperature of between –40° C and 100° C.
Introduction
1 A complete set of schematics, a physical layout database, and GERBER files for the
f For information about powering up the board and installing the demonstration
2. Board Components
This chapter introduces the major components on the Stratix IV E FPGA development
board. Figure 2–1 illustrates major component locations and Table 2–1 provides a brief
description of all component features of the board.
development board reside in the Stratix IV E FPGA development kit documents
directory.
software, refer to the Stratix IV E FPGA Development Kit User Guide.
This chapter consists of the following sections:
■ “Board Overview”
■ “Featured Device: Stratix IV E Device” on page 2–5
■ “MAX II CPLD EPM2210 System Controller” on page 2–7
■ “Configuration, Status, and Setup Elements” on page 2–12
■ “Clock Circuitry” on page 2–22
■ “General User Input/Output” on page 2–24
■ “Components and Interfaces” on page 2–31
■ “Memory” on page 2–42
■ “Power Supply” on page 2–57
■ “Statement of China-RoHS Compliance” on page 2–60
May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual
2–2 Chapter 2: Board Components
HSMC Port A JTAG
Header (J15)
Character
LCD
Header
(J23)
System
Reset
Push-Button
Switch (S5)
Max II CPLD EPM2210 System Controller (U10)
DDR3 SDRAM
DIMM x72
Memory (J20)
Stratix IV E FPGA (U19)
HSMC Port B (J9)
Clock Input SMA (J17)
Speaker Header (J1)
HSMC Port A (J19)
HSMC Port B JTAG
Header (J5)
Fan Header (J12)
100 MHz Oscillator (X2)
QDRII+ x18 Memory (U11)
DC Input Jack (J22)
Power Switch (SW3)
Embedded USB-Blaster
Circuitry (J6)
JTAG Connector
(J24)
CLKIN_P SMA (J13)
HSMC Port B
Status LEDs
(D3, D4, D5)
CLKIN_N SMA (J14)
Clock Output SMA (J16)
HSMC Port A
Status LEDs
(D13, D14, D16)
CPU Reset Push-Button
Switch (S4)
User LEDs (D23-D30)
Gigabit Ethernet
Port (J8)
Ethernet LEDs
(D7-D12)
Reset Configuration
Push-Button Switch (S1)
MAX II DIP Switch (SW2)
MAX II LEDs
(D15, D17-D20)
User 1/User 2
Push-Button Switch (S3)
Power LED (D21)
Rotary Switch
(SW5)
Quad 7-Segment
Display
(U29)
User DIP
Switch
(SW4)
RLDRAM II CIO x36 (U24)
MAX II JTAG Header
(J10)
Factory Configuration
Push-Button Switch (S2)
User
Push-Button
Switches
(S6-S9)
66 MHz Oscillator (X3)
SSRAM x36 Memory (U3)
Flash x16 Memory (U2)
100 MHz Oscillator for MAX II (Y2)
Clock Enable DIP
Switch (SW1)
Configuration
Done
LED
(D22)
Board Overview
Board Overview
This section provides an overview of the Stratix IV E FPGA development board,
including an annotated board image and component descriptions. Figure 2–1
provides an overview of the development board features.
Figure 2–1. Overview of the Stratix IV E FPGA Development Board Features
Tab le 2– 1 describes the components and lists their corresponding board references.
Table 2–1. Stratix IV E FPGA Development Board Components (Part 1 of 4)
Board Reference Type Description
Featured Devices
U19 FPGA EP4SE530H35, 1152-pin FBGA.
U10 CPLD EPM2210F256, 256-pin FBGA.
Configuration, Status, and Setup Elements
J6 USB type-B connector
J24 JTAG connector (bottom side) Disables embedded blaster (for use with external USB-Blasters).
USB interface for programming the FPGA through embedded
USB-Blaster JTAG via a type-B USB cable.
Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation
Chapter 2: Board Components 2–3
Board Overview
Table 2–1. Stratix IV E FPGA Development Board Components (Part 2 of 4)
Board Reference Type Description
J15 HSMC Port A JTAG header
J5 HSMC Port B JTAG header
J10 MAX II JTAG header
SW1 Clock enable DIP switch
Place a shunt on this header to include the HSMC port A in the JTAG
chain.
Place a shunt on this header to include the HSMC port B in the JTAG
chain.
Place a shunt on this header to include the MAX II CPLD EPM2210
System Controller in the JTAG chain.
Enables the oscillators when the switch is ON (positioned on the left
side of the switch).
MAX II DIP switch MAX II user DIP switches.
SW2
66 MHz oscillator select
Selects the on board oscillator when driven low and selects the
differential SMA inputs when driven high.
Selects factory or user FPGA image to load on power up. After power
SW5 Rotary switch
up, this switch selects the power rail monitored from among a total of
12 rails.
D7-D12 Ethernet LEDs
Illuminates to show the connection speed as well as transmit or
receive activity.
Illuminates when the MAX II CPLD EPM2210 System Controller is
D15, D17-D20 MAX II LEDs
actively configuring the FPGA. The LED types include
(labeled as
(labeled as
USER_1
on the board),
USER_2
on the board), and
MAX_LOAD, MAX_FACTORY, MAX_PB
MAX_ERROR
MAX_EMB
.
D21 Power LED Illuminates when power is present.
D22 Configuration done LED Illuminates when the FPGA is configured.
D13, D14 HSMC port A status LEDs You can configure these LEDs to indicate transmit or receive activity.
D16 HSMC port A present LED Illuminates when a daughtercard is plugged into the HSMC port A.
D3, D4 HSMC port B status LEDs You can configure these LEDs to indicate transmit or receive activity.
D5 HSMC port B present LED Illuminates when a daughtercard is plugged into the HSMC port B.
Clock Circuitry
X2 100 MHz oscillator 100.0 MHz crystal oscillator to the FPGA.
66.6 MHz crystal oscillator with a single-ended input to the LVDS clock
buffer (U22). This oscillator is also MUXed with the differential SMA
X3 66 MHz oscillator
clock inputs (J13 and J14) based on the
CLK66_SEL
signal needs to be set to '0' on SW2 to enable the
CLK66_SEL
input. The
oscillator clock source. Two LVDS clocks are output from the clock
buffer to the FPGA.
X4 125 MHz oscillator
X5 50 MHz oscillator
Y2
100 MHz oscillator
(for MAX II CPLD)
125.000 MHz crystal oscillator to the LVDS clock buffer. Two LVDS
clocks are output from the clock buffer to the FPGA.
50 MHz single-ended oscillator to the FPGA and MAX II CPLD
EPM2210 System Controller.
100 MHz single-ended dedicated clock oscillator to the MAX II CPLD
EPM2210 System Controller.
J17 Clock input SMAs Drives LVPECL-compatible clock inputs into the FPGA.
J16 Clock output SMA Drives out 2.5-V CMOS clock output from the FPGA.
May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual
2–4 Chapter 2: Board Components
Board Overview
Table 2–1. Stratix IV E FPGA Development Board Components (Part 3 of 4)
Board Reference Type Description
J13 CLKIN_P SMA (positive) Drives LVPECL-compatible differential clock inputs into the LVDS clock
J14 CLKIN_N SMA (negative)
buffer (U22).The
CLK66_SEL
enable the SMA clock source. Two LVDS clocks are output from the
signal needs to be set to '1' on SW2 to
clock buffer to the FPGA.
General User Input/Output
SW4 User DIP switch
S1
S2
S3
Reset configuration
push-button switch
Factory configuration
push-button switch
User 1 /User 2 push-button
switch
Connects directly to the FPGA. When the switch is ON, a logic 0 is
selected.
Press to reconfigure the FPGA from flash memory.
Press to reconfigure the FPGA to the factory default design.
User-defined push-button switch. Driven to the MAX II CPLD EPM2210
System Controller.
S4 CPU reset push-button switch Press to reset the FPGA logic.
S5
System reset push-button
switch
Press to reset the MAX II CPLD EPM2210 System Controller and FPGA
logic.
S6-S9 User push-button switches Four user push-button switches. Driven low when pressed.
D23-D30 User LEDs Illuminates when driven low.
Display Ports
J23 Character LCD header
Header which interfaces to the provided 16 character × 2 line LCD
module along with two standoffs.
Quad digit seven-segment LED display. The display is controlled by the
U29 Seven-segment LED
Stratix IV E FPGA device. Each segment of the display can be
illuminated by driving a logic 0 to the connected device's I/O pin.
Connector to plug in the flex cable from the 128 × 64 graphics display.
Lift the connector latch to plug in the flex cable, and then close the
latch.
J27
Graphics LCD connector
(bottom side)
Components and Interfaces
J19 HSMC port A Provides 17 LVDS channels per the HSMC specification.
J9 HSMC port B Provides 17 LVDS channels per the HSMC specification.
RJ-45 connector providing a 10/100/1000 Ethernet connection via a
J8 Gigabit Ethernet
Marvell 88E1111 PHY and interfaces to the FPGA-based Altera Triple
Speed Ethernet MegaCore function in SGMII mode.
J12 Fan header Header to plug in the fan.
J1 Speaker header Optional speaker header for user design.
Memory Devices
DDR3 SDRAM DIMM (256 M x 72) 240-pin connector, populated with
a dual rank 2-GB memory module, and interfaces with a 72-bit data
width on the Vertical I/O (VIO) banks.
J20
DDR3 SDRAM DIMM x72
memory
U24 RLDRAM II CIO x36 memory 533-MHz RLDRAM II CIO device in a 16 M x 36 configuration.
U11 QDR II+ x18 memory
QDR II+ SRAM device in a 4 M x 18 configuration for high-speed,
low-latency memory access.
Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation
Chapter 2: Board Components 2–5
Featured Device: Stratix IV E Device
Table 2–1. Stratix IV E FPGA Development Board Components (Part 4 of 4)
Board Reference Type Description
A single 250-MHz 18-Mb (2 M x 36) SSRAM device with a 165-BGA
U3 SSRAM x36 memory
U2 Flash x16 memory
Power Supply
J22 DC input jack Accepts a 14-V – 20-V DC power supply.
SW3 Power switch
package footprint. This footprint allows for both Flow-Through and
Pipelined devices (single or dual cycle deselect).
Embedded memory device which provides a 16-bit 64-MB non-volatile
memory port.
Switch to power on or off the board when power is supplied from the
DC input jack.
Featured Device: Stratix IV E Device
The Stratix IV E FPGA development board features the Stratix IV E EP4SE530H35
device (U19) in a 1152-pin FBGA package.
f For more information about the Stratix IV device family, refer to the Stratix IV Device
Handbook.
Tab le 2– 2 describes the features of the Stratix IV E EP4SE530H35 device.
Table 2–2. Stratix IV E EP4SE530H35 Device Features
ALMs
212,480 531,200 1,280 64 27,376 1,024 736 8 1152-pin FBGA
Equivalent
LEs
M9K RAM
Blocks
M144K RAM
Blocks
Total RAM
bits
18-bit × 18-bit
Multipliers
Maximum
User I/O Pins
PLLs Package Type
Tab le 2– 3 lists the Stratix IV E EP4SE530H35 component reference and manufacturing
information.
Table 2–3. Stratix IV E EP4SE530H35 Device Component Reference and Manufacturing Information
Board Reference Description Manufacturer
U19 FPGA, Stratix IV E F1152, leadfree Altera
Corporation EP4SE530H35C2N www.altera.com
Manufacturing
Part Number
Manufacturer
Website
May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual
2–6 Chapter 2: Board Components
EP4SE290
EP4SE360
EP4SE530
EP4SE680
Bank 8B 24
Bank 7A 40
Bank 7B 24
Bank 7C 32
40 Bank 1C
40 Bank 2C
24 Bank 3B
40 Bank 4A
24 Bank 4B
32 Bank 4C
Bank 6C 40
Bank 5C 40
48 Bank 2A
Bank 8C 32
Bank 8A 40
32 Bank 3C
40 Bank 3A
Bank 5A 48
Bank 6A 48
Bank
Name
Number
of I/Os
Bank
Name
Number
of I/Os
48 Bank 1A
Featured Device: Stratix IV E Device
I/O Resources
Figure 2–2 illustrates the bank organization and I/O count for the EP4SE530 device in
the 1152-pin FBGA package.
Figure 2–2. EP4SE530 Device I/O Bank Diagram
Tab le 2– 4 lists the Stratix IV E device pin count and usage by function on the
development board.
Table 2–4. Stratix IV E Device Pin Count and Usage
Function I/O Standard I/O Count Special Pins
OSC/SMAs 1.5-V/2.5-V CMOS 13 12 Clock Inputs, 1 Output
DDR3 DIMM 1.5-V SSTL 153 18 DQS pins
QDR II+ 1.5-V HSTL 69 2 CQ pins
RLDRAM II CIO 1.5-V HSTL 77 —
HSMC Port A 2.5-V CMOS + LVDS 86 3 Clock Inputs
HSMC Port B 2.5-V CMOS + LVDS 86 3 Clock Inputs
Flash, SSRAM, MAX 2.5-V CMOS 91 —
Gigabit Ethernet 2.5-V CMOS 36 —
User I/O (LEDs, DIP Switch, Push-Buttons) 1.5-V/2.5-V CMOS 21 —
14-pin LCD Header 2.5-V CMOS 11 —
Graphic Display 2.5-V CMOS 15 —
Seven-Segment Display 2.5-V CMOS 13 —
EEPROM 2.5-V CMOS 4 —
MAX II Control, Speaker 2.5-V CMOS 6 —
Device I/O Total:
681
Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation
Chapter 2: Board Components 2–7
MAX1619
Controller
Information
Register
EMB
Blaster
MAX II Device
SLD-HUB
PFL
FSM BUS
Power
Measure
Results
Virtual-JTAG
PC
Temperature
Measure
Results
FPGA
LTC2418
Controller
FLASH
Decoder
Encoder
GPIO
JTAG Control
SRAM
Control
Register
Fast Configuration
Downloader
MAX II CPLD EPM2210 System Controller
MAX II CPLD EPM2210 System Controller
The board utilizes the EPM2210 System Controller, an Altera MAX II CPLD, for the
following purposes:
■ FPGA configuration from flash memory
■ Power consumption monitoring
■ Temp er a ture m on it or in g
■ Fan control
■ Virtual JTAG interface for PC-based power and temperature GUI
■ Control registers for clocks
■ Control registers for remote system update
Figure 2–3 illustrates the MAX II CPLD EPM2210 System Controller's functionality
and external circuit connections as a block diagram.
Figure 2–3. MAX II CPLD EPM2210 System Controller Block Diagram
Table 2–5. MAX II CPLD EPM2210 System Controller Device (U10) Pin-Out (Part 1 of 5)
Schematic Signal Name
2.5V_FPGA_PG
2.5V_HSMC_PG
May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual
Tab le 2– 5 lists the I/O signals present on the MAX
Controller. The signal names and functions are relative to the MAX
I/O
Standard
EPM2210
Pin Number
Stratix IV E
Device
Pin Number
Other
Connections
2.5-V E9 — U41.7 FPGA 2.5-V power good monitor
2.5-V A7 — U26.7 HSMC 2.5-V power good monitor
II CPLD EPM2210 System
II device (U10).
Description
2–8 Chapter 2: Board Components
MAX II CPLD EPM2210 System Controller
Table 2–5. MAX II CPLD EPM2210 System Controller Device (U10) Pin-Out (Part 2 of 5)
Schematic Signal Name
3.3V_PG
CLK100_EN
CLK125_EN
CLK50_EN
CLK66_EN
CLK66_SEL
CLKIN_50
CLKIN_MAX_100
FACTORY_CONFIGn
FLASH_ADVn
FLASH_CEn
FLASH_CLK
FLASH_OEn
FLASH_RDYBSYn
FLASH_RESETn
FLASH_WEn
FPGA_CONF_DONE
FPGA_CONFIGn
FPGA_DATA0
FPGA_DATA1
FPGA_DATA2
FPGA_DATA3
FPGA_DATA4
FPGA_DATA5
FPGA_DATA6
FPGA_DATA7
FPGA_DCLK
FPGA_STATUSn
FSM_A0
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
I/O
Standard
EPM2210
Pin Number
Stratix IV E
Device
Pin Number
Other
Connections
Description
2.5-V E8 — U9.G12 3.3-V power good monitor
2.5-V J1 — SW1.3, X2.1 100 MHz oscillator enable
2.5-V J2 — SW1.4, X4.1 125 MHz oscillator enable
2.5-V H3 — SW1.1, X5.1 50 MHz oscillator enable
2.5-V H4 — SW1.2, X3.1 66 MHz oscillator enable
2.5-V L14 — SW2.8, U22.3 DIP-clock select SMA or oscillator
2.5-V J12 J12 X5.3 50 MHz clock input
2.5-V H12 — Y2.3
2.5-V A10 — S2.2
2.5-V L13 D20 U2.F6
100 MHz oscillator to the MAX II
CPLD EPM2210 System Controller
Load factory or user design at
power-up
FSM bus flash memory address
valid
2.5-V K14 K25 U2.B4 FSM bus flash memory chip enable
2.5-V L15 K24 U2.E6 FSM bus flash memory clock
2.5-V M16 K23 U2.F8
FSM bus flash memory output
enable
2.5-V L11 C20 U2.F7 FSM bus flash memory ready
2.5-V M15 G21 U2.D4 FSM bus flash memory reset
2.5-V L12 L22 U2.G8 FSM bus flash memory write enable
2.5-V E3 AH29 — FPGA configuration done
2.5-V E4 AE25 — FPGA configuration active
2.5-V D3 T28 — FPGA configuration data
2.5-V L1 T27 — FPGA configuration data
2.5-V K5 R34 — FPGA configuration data
2.5-V L2 R33 — FPGA configuration data
2.5-V K4 T25 — FPGA configuration data
2.5-V M1 T24 — FPGA configuration data
2.5-V K3 T32 — FPGA configuration data
2.5-V M2 R31 — FPGA configuration data
2.5-V C2 AL3 — FPGA configuration clock
2.5-V C3 AH28 — FPGA configuration ready
2.5-V N9 F22 — FSM bus address
2.5-V T8 H23 U2.A1 FSM bus address
2.5-V T9 G23 U3.R6, U2.B1 FSM bus address
2.5-V R9 F23 U3.P6, U2.C1 FSM bus address
2.5-V P9 D27 U3.A2, U2.D1 FSM bus address
2.5-V T10 D28 U3.A10, U2.D2 FSM bus address
2.5-V P13 F25 U3.B2, U2.A2 FSM bus address
Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation
Chapter 2: Board Components 2–9
MAX II CPLD EPM2210 System Controller
Table 2–5. MAX II CPLD EPM2210 System Controller Device (U10) Pin-Out (Part 3 of 5)
Schematic Signal Name
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_A23
FSM_A24
FSM_A25
FSM_A26
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
FSM_D7
FSM_D8
FSM_D9
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
FSM_D15
FSM_D16
FSM_D17
I/O
Standard
EPM2210
Pin Number
Stratix IV E
Device
Pin Number
Other
Connections
2.5-V R10 F26 U3.B10, U2.C2 FSM bus address
2.5-V M10 G24 U3.N6, U2.A3 FSM bus address
2.5-V T11 F24 U3.P3, U2.B3 FSM bus address
2.5-V N10 E26 U3.P4, U2.C3 FSM bus address
2.5-V R11 D26 U3.P8, U2.D3 FSM bus address
2.5-V P10 A30 U3.P9, U2.C4 FSM bus address
2.5-V T12 A33 U3.P10, U2.A5 FSM bus address
2.5-V M11 B31 U3.P11, U2.B5 FSM bus address
2.5-V R12 A31 U3.R3, U2.C5 FSM bus address
2.5-V N11 B32 U3.R4, U2.D7 FSM bus address
2.5-V T13 A32 U3.R8, U2.D8 FSM bus address
2.5-V P11 M23 U3.R9, U2.A7 FSM bus address
2.5-V R13 L23 U3.R10, U2.B7 FSM bus address
2.5-V M12 B29 U3.R11, U2.C7 FSM bus address
2.5-V R14 C29 U3.B1, U2.C8 FSM bus address
2.5-V N12 C31 U3.A1, U2.A8 FSM bus address
2.5-V T15 D31 U3.B11, U2.G1 FSM bus address
2.5-V P12 F27 U3.C10, U2.H8 FSM bus address
2.5-V E13 D18 U3.P2, U2.B6 FSM bus address
2.5-V J16 W10 U2.B8 FSM bus address
2.5-V P4 G27 U3.J10, U2.F2 FSM bus data
2.5-V R1 F28 U3.J11, U2.E2 FSM bus data
2.5-V P5 E28 U3.K10, U2.G3 FSM bus data
2.5-V T2 D30 U3.K11, U2.E4 FSM bus data
2.5-V N5 C30 U3.L10, U2.E5 FSM bus data
2.5-V R3 F29 U3.L11, U2.G5 FSM bus data
2.5-V P6 E29 U3.M10, U2.G6 FSM bus data
2.5-V R4 J24 U3.M11, U2.H7 FSM bus data
2.5-V N6 J25 U3.D10, U2.E1 FSM bus data
2.5-V T4 A24 U3.D11, U2.E3 FSM bus data
2.5-V M6 A26 U3.E10, U2.F3 FSM bus data
2.5-V R5 B25 U3.E11, U2.F4 FSM bus data
2.5-V P7 A25 U3.F10, U2.F5 FSM bus data
2.5-V T5 J20 U3.F11, U2.H5 FSM bus data
2.5-V N7 K20 U3.G10, U2.G7 FSM bus data
2.5-V R6 K21 U3.G11, U2.E7 FSM bus data
2.5-V M7 K22 U3.D1 FSM bus data
2.5-V T6 C26 U3.D2 FSM bus data
Description
May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual
2–10 Chapter 2: Board Components
MAX II CPLD EPM2210 System Controller
Table 2–5. MAX II CPLD EPM2210 System Controller Device (U10) Pin-Out (Part 4 of 5)
Stratix IV E
Device
Pin Number
Other
Connections
J24.1, U8.L9,
J9.35, J19.35
J24.5, U8.J11,
J9.36, J19.36
Description
JTAG clock signal
JTAG mode select signal
Schematic Signal Name
FSM_D18
FSM_D19
FSM_D20
FSM_D21
FSM_D22
FSM_D23
FSM_D24
FSM_D25
FSM_D26
FSM_D27
FSM_D28
FSM_D29
FSM_D30
FSM_D31
HSMA_PSNTn
HSMB_PSNTn
JTAG_EPM2210_TDO
JTAG_FPGA_TDO
JTAG_TCK
I/O
Standard
2.5-V P14 B26 U3.E1 FSM bus data
2.5-V R7 J22 U3.E2 FSM bus data
2.5-V P8 J21 U3.F1 FSM bus data
2.5-V T7 C24 U3.F2 FSM bus data
2.5-V N8 E25 U3.G1 FSM bus data
2.5-V R8 D25 U3.G2 FSM bus data
2.5-V F12 D24 U3.J1 FSM bus data
2.5-V D16 A27 U3.J2 FSM bus data
2.5-V F13 A29 U3.K1 FSM bus data
2.5-V D15 C27 U3.K2 FSM bus data
2.5-V F14 C28 U3.L1 FSM bus data
2.5-V D14 E23 U3.L2 FSM bus data
2.5-V E12 D23 U3.M1 FSM bus data
2.5-V C15 B28 U3.M2 FSM bus data
2.5-V F16 — J19.160, R189 HSMC port A present
2.5-V G13 — J9.160, R189 HSMC port B present
2.5-V M5 — U35.5 JTAG data output for MAX II
2.5-V L6 G29 U35.2 JTAG data output for FPGA
2.5-V P3 F30
EPM2210
Pin Number
JTAG_TMS 2.5-V N4 H28
MAX_CLK 2.5-V H5 N3 — FSM bus MAX II clock
MAX_CSn 2.5-V L16 N29 — FSM bus MAX II chip select
MAX_DIP0
MAX_DIP1
MAX_DIP2
MAX_DIP3
MAX_DIP4
MAX_DIP5
MAX_DIP6
MAX_EMB 2.5-V E15 — D15
MAX_ERROR
MAX_FACTORY
MAX_LOAD
2.5-V E14 — SW2.1 DIP - reserved
2.5-V D13 — SW2.2 DIP - reserved
2.5-V K16 — SW2.3 DIP - reserved
2.5-V N2 — SW2.4 DIP - reserved
2.5-V N14 — SW2.5 DIP - reserved
2.5-V M13 — SW2.6 DIP - reserved
2.5-V N15 — SW2.7 DIP - reserved
User-defined push-button switch
(labeled as
USER_1
on the board)
2.5-V H15 — D20 FPGA configuration error LED
2.5-V G16 — D18 FPGA factory configuration LED
2.5-V H14 — D17 FPGA configuration active LED
MAX_OEn 2.5-V K13 K27 — FSM bus MAX II output enable
MAX_PB 2.5-V D4 — S3
User-defined push-button switch
(labeled as
USER_2
on the board)
Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation
Chapter 2: Board Components 2–11
MAX II CPLD EPM2210 System Controller
Table 2–5. MAX II CPLD EPM2210 System Controller Device (U10) Pin-Out (Part 5 of 5)
Stratix IV E
Device
Pin Number
Other
Connections
Description
Power regulator 0 degrees phase
control
Power regulator 180 degrees phase
control
Schematic Signal Name
I/O
Standard
EPM2210
Pin Number
MAX_PHASE_CLK0 2.5-V J4 — U30.A8
MAX_PHASE_CLK180 2.5-V K1 — U33.B9
MAX_TO_STRATIX4 2.5-V H1 K1 — Optional pin for user function
MAX_USER
2.5-V G12 — D19
User-defined LED (labeled as
USER_1/USER_2
on the board)
MAX_WEn 2.5-V K15 K28 — FSM bus MAX II write enable
OVERTEMP 2.5-V M4 — Q1 Fan speed control
OVERTEMPn 2.5-V E7 — U18.9
Temperature monitor
over-temperature indicator
PGM0 2.5-V N13 — SW5.1 Rotary switch input
PGM1 2.5-V P15 — SW5.2 Rotary switch input
PGM2 2.5-V M14 — SW5.4 Rotary switch input
PGM3 2.5-V N16 — SW5.8 Rotary switch input
PHASE0 2.5-V C13 — U49.4 Power clock 0 degrees
PHASE90 2.5-V B16 — U49.5, U36.A8 Power clock 90 degrees
PHASE180 2.5-V C12 — U49.6, U29.A8 Power clock 180 degrees
PHASE270 2.5-V A15 — U49.7, U6.A8 Power clock 270 degrees
RESET_CONFIGn 2.5-V R16 — S1
Force FPGA configuration
push-button switch
SENSE_ADC_F0 2.5-V E2 — U44.2 Power monitor frequency
SENSE_CS0n 2.5-V F5 — U43.3 Power monitor 0 chip select
SENSE_CS1n 2.5-V F2 — U43.2 Power monitor 1 chip select
SENSE_SCK 2.5-V E1 — U44.5 Power monitor SPI clock
SENSE_SDI 2.5-V F4 — U44.4 Power monitor SPI data in
SENSE_SDO 2.5-V F3 — U44.3 Power monitor SPI data out
SSRAM_GWn 2.5-V E11 — U3.B7 FSM bus SSRAM global write enable
SSRAM_MODE 2.5-V D11 — U3.R1
FSM bus SSRAM burst sequence
selection
SSRAM_ZZ 2.5-V A13 — U3.H11 FSM bus SSRAM power sleep mode
SYS_RESETn 2.5-V M9 U31 S5 User-defined reset
TSENSE_ALERTN 2.5-V J5 — U18.11 Temperature monitor alert
TSENSE_SMB_CLK 2.5-V L3 — U18.14, U21.6 Temperature monitor SMB clock
TSENSE_SMB_DATA 2.5-V N1 — U18.12, U21.7 Temperature monitor SMB data
VDDQ_QDRII_PG 2.5-V A9 — U16.7 I/O supply
May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual
2–12 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Tab le 2– 6 lists the MAX II CPLD EPM2210 System Controller component reference
and manufacturing information.
Table 2–6. MAX II CPLD EPM2210 System Controller Component Reference and Manufacturing Information
Board Reference Description Manufacturer
U10
IC - MAX II CPLD EPM2210
256FBGA -3 LF 2.5V VCCINT
Altera
Corporation EPM2210F256C3N www.altera.com
Configuration, Status, and Setup Elements
This section describes the board's configuration, status, and setup elements.
Configuration
This section describes the FPGA, flash memory, and MAX II CPLD EPM2210 System
Controller device programming methods supported by the Stratix IV E FPGA
development board. The Stratix IV E FPGA development board supports the
following three configuration methods:
■ Embedded USB-Blaster is the default method for configuring the FPGA at any
time using the Quartus II Programmer in JTAG mode with the supplied USB cable.
■ Flash memory programming using the Board Update Portal factory design.
■ FPGA Programming from Flash memory for configuring the FPGA using stored
images from the flash memory on either power-up or pressing the reset
configuration push-button switch (S1).
Manufacturing
Part Number
Manufacturer
Website
FPGA Programming over Embedded USB-Blaster
The USB-Blaster is implemented using a USB Type-B connector (J6), a FTDI USB 2.0
PHY device (U7), and an Altera MAX II CPLD (U10). This allows the configuration of
the FPGA using a USB cable directly connected between the USB port on the board
(J6) and a USB port of a PC running the Quartus II software. The JTAG chain is
normally mastered by the embedded USB-Blaster found in the MAX
EPM2210 System Controller.
II CPLD
Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation
Chapter 2: Board Components 2–13
Embedded
Blaster
GPIO
TCK
EP4S530
FPGA
Analog
Switch
MAX II CPLD
EPM2210
System
Controller
HSMC
Port A
HSMC
Port B
GPIO
TMS
GPIO
TDO
GPIO
TDI
JTAG Master
GPIO
DISABLE
JTAG Master/Slave
JTAG Master/Slave
Installed
HSMC
Card
Installed
HSMC
Card
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
JTAG Slave
JTAG Slave
Analog
Switch
Analog
Switch
ENABLE
ALWAYS
ENABLED
(in chain)
Jumper
10-pin
JTAG Connector
Flash
Memory
(on install)
J10
Jumper
Jumper
Jumper
J15
J5
ENABLE
ENABLE
J4
Configuration, Status, and Setup Elements
The embedded USB-Blaster is automatically disabled when an external USB-Blaster is
connected to the JTAG chain. Figure 2–4 illustrates the JTAG chain.
Figure 2–4. JTAG Chain
Each jumper shown in Figure 2–4 is located near its corresponding interface. To
connect a device or interface in the chain, the corresponding shunt must be installed
1 A board must be plugged into the HSMC port in order for the chain to be contiguous.
May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual
to the jumper. The FPGA, by default, is always in the chain.
If there is a shunt on the jumper without a board plugged in to the corresponding
HSMC port, the chain is broken and configuration cannot be performed.
The MAX
II CPLD EPM2210 System Controller must be in the chain to use some of the
GUI interfaces. For this setting, place a jumper shunt on the MAX II JTAG header
(J10).
2–14 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Flash Memory Programming
Flash memory programming is possible through a variety of methods using the
Stratix IV E device.
The default method is to use the factory design called the Board Update Portal. This
design is an embedded webserver, which serves the Board Update Portal web page.
The web page allows you to select new FPGA designs including hardware, software,
or both in an industry-standard S-Record File (.flash) and write the design to the user
hardware page (page 1) of the flash memory over the network.
The secondary method is to use the pre-built parallel flash loader (PFL) design
included in the development kit. The development board implements the Altera PFL
megafunction for flash memory programming. The PFL megafunction is a block of
logic that is programmed into an Altera programmable logic device (FPGA or CPLD).
The PFL functions as a utility for writing to a compatible flash memory device. This
pre-built design contains the PFL megafunction that allows you to write either page 0,
page 1, or other areas of flash memory over the USB interface using the Quartus II
software. This method is used to restore the development board to its factory default
settings.
Other methods to program the flash memory can be used as well, including the
®
Nios
II processor.
f For more information on the Nios II processor, refer to the Nios II Processor page of
the Altera website.
FPGA Programming from Flash Memory
On either power-up or by pressing the reset configuration push-button switch (S1),
the MAX
flash memory. The PFL megafunction reads 16-bit data from the flash memory and
converts it to fast passive parallel (FPP) format. This 8-bit data is then written to the
FPGA's dedicated configuration pins during configuration. The bit stream loaded into
the FPGA is selected by the PGM rotary switch (SW5) connected to the MAX
EPM2210 System Controller.
Figure 2–5 illustrates the connection for FPGA programming from flash memory.
Figure 2–5. FPGA Programming from Flash Memory
Flash Memory
Rotary Switch
II CPLD EPM2210 System Controller's PFL configures the FPGA from the
Flash Data
PGM
EPM2210F256
CPLD
Fast Passive Parallel
(FPP)
EP4SE530H35
II CPLD
Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation
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