Altera Stratix IV E FPGA User Manual
Stratix IV E FPGA Development Kit User Guide
Stratix IV E FPGA Development Kit
User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
UG-01067-2.1
Subscribe
Copyright © 2011 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, and specific device designations
are trademarks and/or service marks of Altera Corporation in the U.S. and other countries. All other words and logos identified as trademarks and/or service marks
are the property of Altera Corporation or their respective owners. Altera products are protected under numerous U.S. and foreign patents and pending applications,
maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard
warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of
the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to
obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation
Contents
Chapter 1. About This Kit
Kit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Quartus II Subscription Edition Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Stratix IV E FPGA Development Kit Installer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Chapter 2. Getting Started
Before You Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Inspect the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Chapter 3. Software Installation
Installing the Quartus II Subscription Edition Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Licensing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Installing the Stratix IV E FPGA Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Installing the USB-Blaster Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Chapter 4. Development Board Setup
Setting Up the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Factory Default Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Chapter 5. Board Update Portal
Connecting to the Board Update Portal Web Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Using the Board Update Portal to Update User Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Chapter 6. Board Test System
Preparing the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Running the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Using the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
The Configure Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
The Config Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
Board Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MAX II Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
SOPC Builder Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
The GPIO Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
User DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
Push Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
7-Segment Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
Graphics LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
The Flash Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
Random Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
June 2011 Altera Corporation Stratix IV E FPGA Development Kit User Guide
iv Contents
Increment Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
CFI Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
The SSRAM Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
Random Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
Increment Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
The DDR3 Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
Performance Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
Number of Addresses to Write and Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
Read and Write Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
The QDRII+ Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15
Performance Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15
Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16
Number of Addresses to Write and Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16
Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16
The RLDRAMII Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17
Performance Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17
Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18
Number of Addresses to Write and Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18
Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18
Read and Write Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18
The HSMC Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
Performance Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
The Power Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21
General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22
Temperature Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
Power Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
12-V Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
Power Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
Graph Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
Calculating Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24
Configuring the FPGA Using the Quartus II Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
4
Appendix A. Programming the Flash Memory Device
CFI Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation
Contents v
Preparing Design Files for Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
Creating Flash Files Using the Nios II EDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
Programming Flash Memory Using the Board Update Portal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3
Programming Flash Memory Using the Nios II EDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3
Restoring the Flash Device to the Factory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4
Restoring the MAX II CPLD to the Factory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
June 2011 Altera Corporation Stratix IV E FPGA Development Kit User Guide
vi Contents
Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation
1. About This Kit
The Altera® Stratix®IV E FPGA Development Kit is a complete design environment
that includes both the hardware and software you need to develop Stratix IV E FPGA
designs. The board and the one-year license for the Quartus
everything you need to begin developing custom Stratix IV E FPGA designs. The
following list describes what you can accomplish with the kit:
■ Develop and test memory subsystems consisting of DDR3, RLDRAM II, and
QDR II+ memories.
■ Build designs capable of migrating to Altera’s low-cost HardCopy
■ Take advantage of the modular and scalable design by using the high-speed
mezzanine card (HSMC) connectors to interface to over 30 different HSMCs
provided by Altera partners, supporting protocols such as Serial RapidIO
10 Gigabit Ethernet, SONET, Common Public Radio Interface (CPRI), Open Base
Station Architecture Initiative (OBSAI) and others.
■ Develop FPGAs design for cost-sensitive applications.
®
II software provide
®
IV ASICs.
®
,
Kit Features
Hardware
■ Measure the FPGA's low power consumption.
This section briefly describes the Stratix IV E FPGA Development Kit contents.
The Stratix IV E FPGA Development Kit includes the following hardware:
■ Stratix IV E FPGA development board—A development platform that allows you
to develop and prototype hardware designs running on the Stratix IV E EP4SE530
FPGA.
f For detailed information about the board components and interfaces, refer
to the Stratix IV E FPGA Development Board Reference Manual.
■ HSMC loopback board—A daughtercard that allows for loopback testing all
signals on the HSMC interface using the Board Test System.
■ HSMC debug breakout board—A daughtercard that routes 40 CMOS signals to a
0.1" header and adds 20 LEDs to the remaining 40 CMOS signals.
■ Power supply and cables—The kit includes the following items:
■ Power supply and AC adapters for North America/Japan, Europe, and the
United Kingdom
■ USB cable
■ Ethernet cable
June 2011 Altera Corporation Stratix IV E FPGA Development Kit User Guide
1–2 Chapter 1: About This Kit
Kit Features
Software
The software for this kit, described in the following sections, is available on the Altera
website for immediate downloading. You can also request to have Altera mail the
software to you on DVDs.
Quartus II Subscription Edition Software
The Quartus II Subscription Edition Software is a licensed set of Altera tools with full
functionality. Your kit includes a one-year Development Kit license for the Quartus II
software (Windows platform only). This license entitles you to all the features of the
subscription edition for a period of one year.
1 After the year, your Development Kit license will no longer be valid and you will not
be permitted to use this version of the Quartus II software. To continue using the
Quartus II software, you should download the free Quartus II Web edition or
purchase a subscription to Quartus II software.
f Download the Quartus II Subscription Edition Software from the Quartus II
Subscription Edition Software page of the Altera website. Alternatively, you can
request a DVD from the Altera IP and Software DVD Request Form page of the Altera
website.
The Quartus II Subscription Edition Software includes the following items:
■ Quartus II Software—The Quartus II software, including the Qsys and SOPC
Builder system development tool, provides a comprehensive environment for
system-on-a-programmable-chip (SOPC) design. The Quartus II software
integrates into nearly any design environment and provides interfaces to
industry-standard EDA tools.
■ MegaCore
®
IP Library—A library that contains Altera IP MegaCore functions. You
can evaluate MegaCore functions by using the OpenCore Plus feature to do the
following:
■ Simulate behavior of a MegaCore function within your system.
■ Verify functionality of your design, and quickly and easily evaluate its size and
speed.
■ Generate time-limited device programming files for designs that include
MegaCore functions.
■ Program a device and verify your design in hardware.
1 The OpenCore Plus hardware evaluation feature is an evaluation tool for
prototyping only. You must purchase a license to use a MegaCore function
in production.
f For more information about OpenCore Plus, refer to AN 320: OpenCore Plus
Evaluation of Megafunctions.
■ Nios
®
II Embedded Design Suite (EDS)—A full-featured set of tools that allow you
to develop embedded software for the Nios II processor which you can include in
your Altera FPGA designs.
Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation
Chapter 1: About This Kit 1–3
Kit Features
Stratix IV E FPGA Development Kit Installer
The license-free Stratix IV E FPGA Development Kit installer includes all the
documentation and design examples for the kit.
Download the Stratix IV E FPGA Development Kit installer from the Stratix IV E
FPGA Development Kit page of the Altera website. Alternatively, you can request a
Development Kit DVD from the Altera Kit Installations DVD Request Form page of
the Altera website.
June 2011 Altera Corporation Stratix IV E FPGA Development Kit User Guide
1–4 Chapter 1: About This Kit
Kit Features
Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation
The remaining chapters in this user guide lead you through the following Stratix IV E
FPGA development board setup steps:
■ Inspecting the contents of the kit
■ Installing the design and kit software
■ Setting up, powering up, and verifying correct operation of the FPGA
■ Configuring the Stratix IV E FPGA
■ Running the Board Test System designs
f For complete information about the FPGA development board, refer to the
Stratix IV E FPGA Development Board Reference Manual.
Before You Begin
2. Getting Started
development board
Before using the kit or installing the software, check the kit contents and inspect the
board to verify that you received all of the items listed in “Kit Features” on page 1–1.
If any of the items are missing, contact Altera before you proceed.
Inspect the Board
To inspect the board, perform the following steps:
1. Place the board on an anti-static surface and inspect it to ensure that it has not been
damaged during shipment.
c Without proper anti-static handling, you can damage the board.
2. Verify that all components are on the board and appear intact.
1 In typical applications with the Stratix IV E FPGA development board, a heat sink is
not necessary. However, under extreme conditions or for engineering sample silicon
the board might require additional cooling to stay within operating temperature
guidelines. You can perform power consumption and thermal modeling to determine
whether your application requires additional cooling. For information about
measuring board and FPGA temperature in real time, refer to “The Power Monitor”
on page 6–21.
f For more information about power consumption and thermal modeling, refer to
AN 358: Thermal Management for FPGAs.
June 2011 Altera Corporation Stratix IV E FPGA Development Kit User Guide
2–2 Chapter 2: Getting Started
References
References
Use the following links to check the Altera website for other related information:
■ For the latest board design files and reference designs, refer to the Stratix IV E
FPGA Development Kit page.
■ For additional daughter cards available for purchase, refer to the Development
Board Daughtercards page.
■ For the Stratix IV E device documentation, refer to the Literature: Stratix IV
Devices page.
■ To purchase devices from the eStore, refer to the Devices page.
■ For Stratix IV E OrCAD symbols, refer to the Capture CIS Symbols page.
■ For Nios II 32-bit embedded processor solutions, refer to the Embedded
Processing page.
Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation
3. Software Installation
This chapter explains how to install the following software:
■ Quartus II Subscription Edition Software
■ Stratix IV E FPGA Development Kit
■ USB-Blaster™ driver
Installing the Quartus II Subscription Edition Software
The Quartus II Subscription Edition Software provides the necessary tools used for
developing hardware and software for Altera FPGAs. Included in the Quartus II
Subscription Edition Software are the Quartus II software, the Nios II EDS, and the
MegaCore IP Library. The Quartus II software (including Qsys and SOPC Builder)
and the Nios II EDS are the primary FPGA development tools used to create the
reference designs in this kit. To install the Altera development tools, perform the
following steps:
1. Run the Quartus II Subscription Edition Software installer you acquired in
“Software” on page 1–2.
2. Follow the on-screen instructions to complete the installation process.
f If you have difficulty installing the Quartus II software, refer to Altera Software
Installation and Licensing Manual.
Licensing Considerations
Purchasing this kit entitles you to a one-year Development Kit license for the
Quartus II Subscription Edition Software.
1 After the year, your Development Kit license will no longer be valid and you will not
be permitted to use this version of the Quartus II software. To continue using the
Quartus II software, you should download the free Quartus II Web edition or
purchase a subscription to Quartus II software.
Before using the Quartus II software, you must activate your license, identify specific
users and computers, and obtain and install a license file.
If you already have a licensed version of the Subscription Edition, you can use that
license file with this kit. If not, you need to obtain and install a license file. To begin,
go to the Self Service Licensing Center page of the Altera website, log into or create
your myAltera account, and take the following actions:
1. On the Activate Products page, enter the serial number provided with your
development kit in the License Activation Code box.
June 2011 Altera Corporation Stratix IV E FPGA Development Kit User Guide
3–2 Chapter 3: Software Installation
Installing the Stratix IV E FPGA Development Kit
1 Your serial number is printed on the development kit box below the bottom
bar code. The number is 10 or 11 alphanumeric characters and does not
contain hyphens. Figure 3–1 shows 3S150SPXXXX as an example serial
number.
Figure 3–1. Locating Your Serial Number
2. Consult the Activate Products table, to determine how to proceed.
a. If the administrator listed for your product is someone other than you, skip the
remaining steps and contact your administrator to become a licensed user.
b. If the administrator listed for your product is you, proceed to step 3.
c. If the administrator listed for your product is Stocking, activate the product,
making you the administrator, and proceed to step 3.
3. Use the Create New License page to license your product for a specific user (you)
on specific computers. The Manage Computers and Manage Users pages allow
you to add users and computers not already present in the licensing system.
1 To license the Quartus II software, you need your computer’s network
interface card (NIC) ID, a number that uniquely identifies your computer.
On the computer you use to run the Quartus II software, type
ipconfig /all
at a command prompt to determine the NIC ID. Your NIC ID
is the 12-digit hexadecimal number on the Physical Address line.
4. When licensing is complete, Altera emails a license.dat file to you. Store the file on
your computer and use the License Setup page of the Options dialog box in the
Quartus_II software to enable the software.
f For complete licensing details, refer to Altera Software Installation and Licensing Manual.
Installing the Stratix IV E FPGA Development Kit
To install the Stratix IV E FPGA Development Kit, perform the following steps:
1. Run the Stratix IV E FPGA Development Kit installer you acquired in “Software”
on page 1–2.
Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation
Chapter 3: Software Installation 3–3
<install dir>
documents
board_design_files
The default Windows installation directory is C:\altera\
<version>
\.
examples
factory_recovery
demos
kits
stratixIVE_4se530_fpga
Installing the USB-Blaster Driver
2. Follow the on-screen instructions to complete the installation process. Be sure that
the installation directory you choose is in the same relative location to your
Quartus II software as the default locations.
The installation program creates the Stratix IV E FPGA Development Kit directory
structure shown in Figure 3–2.
Figure 3–2. Stratix IV E FPGA Development Kit Installed Directory Structure (1)
Note to Figure 3–2:
(1) Early-release versions might have slightly different directory names.
Tab le 3– 1 lists the file directory names and a description of their contents.
Table 3–1. Installed Directory Contents
Directory Name Description of Contents
board_design_files
demos Contains demonstration applications, if present; not all kits include demos.
documents Contains the kit documentation.
examples Contains the sample design files for the Stratix IV E FPGA Development Kit.
factory_recovery
Contains schematic, layout, assembly, and bill of material board design files. Use these files as a
starting point for a new prototype board design.
Contains the original data programmed onto the board before shipment. Use this data to restore
the board with its original factory contents.
Installing the USB-Blaster Driver
The Stratix IV E FPGA development board includes integrated USB-Blaster circuitry
for FPGA programming. However, for the host computer and board to communicate,
you must install the USB-Blaster driver on the host computer.
f Installation instructions for the USB-Blaster driver for your operating system are
available on the Altera website. On the Altera Programming Cable Driver Information
page of the Altera website, locate the table entry for your configuration and click the
link to access the instructions.
June 2011 Altera Corporation Stratix IV E FPGA Development Kit User Guide
3–4 Chapter 3: Software Installation
Installing the USB-Blaster Driver
Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation
The instructions in this chapter explain how to set up the Stratix IV E FPGA
development board.
Setting Up the Board
To prepare and apply power to the board, perform the following steps:
1. The Stratix IV E FPGA development board ships with its board switches
preconfigured to support the design examples in the kit. If you suspect your board
might not be currently configured with the default settings, follow the instructions
in “Factory Default Switch Settings” on page 4–2 to return the board to its factory
settings before proceeding.
2. The FPGA development board ships with design examples stored in the flash
memory device. Verify the PGM CONFIG SELECT rotary switch (SW5) is set to the
0 position to load the design stored in the factory portion of flash memory.
Figure 4–1 shows the switch location on the Stratix IV E FPGA development
board.
4. Development Board Setup
3. Connect the DC adapter (+16 V, 3.75 A) to the DC power jack (J22) on the FPGA
board and plug the cord into a power outlet.
c Use only the supplied power supply. Power regulation circuitry on the
board can be damaged by power supplies with greater voltage.
4. Set the POWER switch (SW3) to the on position. When power is supplied to the
board, a blue LED (D21) illuminates indicating that the board has power.
The MAX II device on the board contains (among other things) a parallel flash loader
(PFL) megafunction. When the board powers up, the PFL reads a design from flash
memory and configures the FPGA. The PGM CONFIG SELECT rotary switch (SW5)
controls which design to load. When the switch is in the 0 position, the PFL loads the
design from the factory portion of flash memory. When the switch is in the 1 position,
the PFL loads the design from the user hardware portion of flash memory.
1 The kit includes a MAX II design which contains the MAX II PFL megafunction. The
design resides in the <install dir>\kits\stratixIVE_4se530_fpga\examples\max2
directory.
When configuration is complete, the CONF DONE LED (D22) illuminates, signaling
that the Stratix IV E device configured successfully.
f For more information about the PFL megafunction, refer to Parallel Flash Loader
Megafunction User Guide.
June 2011 Altera Corporation Stratix IV E FPGA Development Kit User Guide
4–2 Chapter 4: Development Board Setup
12345678
ON
4321
12345678
0
123
QDRII_DRIVE
60
50
MIN
J7
VCC_VCCL_SEL
J21
USB
J4
Clock
Enable
SW1
MSEL0
J2
MAXII_JTAG_EN
J10
SHUNT = 1.8V_QDR
J11
FAN
J12
HSMB JTAG EN
J5
HSMA_JTAG_EN
J15
SHUNT = 1.8V_RLD
J18
SW5
SW2
MAX II DIPSWITCH
Rotary
Switch
OPEN
OPEN
SW4
Board Settings
PGM CONFIG SELECT
Factory Default Switch Settings
Factory Default Switch Settings
This section shows the factory switch settings for the Stratix IV E FPGA development
board. Figure 4–1 shows the switch locations and the default position of each switch
on the top side of the board.
Figure 4–1. Switch Locations and Default Settings on the Board Top
Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation
Loading...