Altera Stratix IV E FPGA User Manual

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Stratix IV E FPGA Development Kit User Guide

Stratix IV E FPGA Development Kit

User Guide

101 Innovation Drive San Jose, CA 95134

www.altera.com

UG-01067-2.1

Copyright © 2011 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, and specific device designations are trademarks and/or service marks of Altera Corporation in the U.S. and other countries. All other words and logos identified as trademarks and/or service marks are the property of Altera Corporation or their respective owners. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation

Chapter 1. About This Kit

Kit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Quartus II Subscription Edition Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Stratix IV E FPGA Development Kit Installer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

Chapter 2. Getting Started

Before You Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Inspect the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Chapter 3. Software Installation

Installing the Quartus II Subscription Edition Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Licensing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Installing the Stratix IV E FPGA Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Installing the USB-Blaster Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Chapter 4. Development Board Setup

Setting Up the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Factory Default Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

Chapter 5. Board Update Portal

Connecting to the Board Update Portal Web Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Using the Board Update Portal to Update User Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2

Chapter 6. Board Test System

Preparing the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3

Running the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3

Using the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4

The Configure Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4

The Config Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

Board Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

MAX II Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

SOPC Builder Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

The GPIO Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

User DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8

User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8

Push Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8

7-Segment Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8

Graphics LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8

Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8

The Flash Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9

Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9

Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

Random Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

June 2011 Altera Corporation Stratix IV E FPGA Development Kit User Guide

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Increment Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

CFI Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

The SSRAM Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11

Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11

Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12

Random Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12

Increment Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12

The DDR3 Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13

Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13

Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13

Performance Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13

Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14

Number of Addresses to Write and Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14

Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14

Read and Write Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14

The QDRII+ Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15

Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15

Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15

Performance Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15

Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16

Number of Addresses to Write and Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16

Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16

The RLDRAMII Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17

Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17

Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17

Performance Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17

Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18

Number of Addresses to Write and Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18

Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18

Read and Write Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18

The HSMC Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19

Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19

Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20

Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20

Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20

Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20

Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20

Performance Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20

The Power Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21

General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22

Temperature Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23

Power Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23

12-V Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23

Power Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23

Graph Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23

Calculating Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24

Configuring the FPGA Using the Quartus II Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2

Appendix A. Programming the Flash Memory Device

CFI Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1

Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation

Contents v

Preparing Design Files for Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2

Creating Flash Files Using the Nios II EDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2

Programming Flash Memory Using the Board Update Portal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3

Programming Flash Memory Using the Nios II EDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3

Restoring the Flash Device to the Factory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4

Restoring the MAX II CPLD to the Factory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

June 2011 Altera Corporation Stratix IV E FPGA Development Kit User Guide

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Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation

1. About This Kit

The Altera® Stratix®IV E FPGA Development Kit is a complete design environment that includes both the hardware and software you need to develop Stratix IV E FPGA designs. The board and the one-year license for the Quartus everything you need to begin developing custom Stratix IV E FPGA designs. The following list describes what you can accomplish with the kit:

■ Develop and test memory subsystems consisting of DDR3, RLDRAM II, and

QDR II+ memories.

■ Build designs capable of migrating to Altera’s low-cost HardCopy

■ Take advantage of the modular and scalable design by using the high-speed

mezzanine card (HSMC) connectors to interface to over 30 different HSMCs provided by Altera partners, supporting protocols such as Serial RapidIO 10 Gigabit Ethernet, SONET, Common Public Radio Interface (CPRI), Open Base Station Architecture Initiative (OBSAI) and others.

■ Develop FPGAs design for cost-sensitive applications.

II software provide

IV ASICs.

Kit Features

Hardware

■ Measure the FPGA's low power consumption.

This section briefly describes the Stratix IV E FPGA Development Kit contents.

The Stratix IV E FPGA Development Kit includes the following hardware:

■ Stratix IV E FPGA development board—A development platform that allows you

to develop and prototype hardware designs running on the Stratix IV E EP4SE530 FPGA.

f For detailed information about the board components and interfaces, refer

to the Stratix IV E FPGA Development Board Reference Manual.

■ HSMC loopback board—A daughtercard that allows for loopback testing all

signals on the HSMC interface using the Board Test System.

■ HSMC debug breakout board—A daughtercard that routes 40 CMOS signals to a

0.1" header and adds 20 LEDs to the remaining 40 CMOS signals.

■ Power supply and cables—The kit includes the following items:

■ Power supply and AC adapters for North America/Japan, Europe, and the

United Kingdom

■ USB cable

■ Ethernet cable

June 2011 Altera Corporation Stratix IV E FPGA Development Kit User Guide

1–2 Chapter 1: About This Kit

Kit Features

Software

The software for this kit, described in the following sections, is available on the Altera website for immediate downloading. You can also request to have Altera mail the software to you on DVDs.

Quartus II Subscription Edition Software

The Quartus II Subscription Edition Software is a licensed set of Altera tools with full functionality. Your kit includes a one-year Development Kit license for the Quartus II software (Windows platform only). This license entitles you to all the features of the subscription edition for a period of one year.

1 After the year, your Development Kit license will no longer be valid and you will not

be permitted to use this version of the Quartus II software. To continue using the Quartus II software, you should download the free Quartus II Web edition or purchase a subscription to Quartus II software.

f Download the Quartus II Subscription Edition Software from the Quartus II

Subscription Edition Software page of the Altera website. Alternatively, you can

request a DVD from the Altera IP and Software DVD Request Form page of the Altera website.

The Quartus II Subscription Edition Software includes the following items:

■ Quartus II Software—The Quartus II software, including the Qsys and SOPC

Builder system development tool, provides a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software integrates into nearly any design environment and provides interfaces to industry-standard EDA tools.

■ MegaCore

IP Library—A library that contains Altera IP MegaCore functions. You can evaluate MegaCore functions by using the OpenCore Plus feature to do the following:

■ Simulate behavior of a MegaCore function within your system.

■ Verify functionality of your design, and quickly and easily evaluate its size and

speed.

■ Generate time-limited device programming files for designs that include

MegaCore functions.

■ Program a device and verify your design in hardware.

1 The OpenCore Plus hardware evaluation feature is an evaluation tool for

prototyping only. You must purchase a license to use a MegaCore function in production.

f For more information about OpenCore Plus, refer to AN 320: OpenCore Plus

Evaluation of Megafunctions.

■ Nios

II Embedded Design Suite (EDS)—A full-featured set of tools that allow you to develop embedded software for the Nios II processor which you can include in your Altera FPGA designs.

Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation

Chapter 1: About This Kit 1–3

Kit Features

Stratix IV E FPGA Development Kit Installer

The license-free Stratix IV E FPGA Development Kit installer includes all the documentation and design examples for the kit.

Download the Stratix IV E FPGA Development Kit installer from the Stratix IV E

FPGA Development Kit page of the Altera website. Alternatively, you can request a

Development Kit DVD from the Altera Kit Installations DVD Request Form page of the Altera website.

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1–4 Chapter 1: About This Kit

Kit Features

Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation

The remaining chapters in this user guide lead you through the following Stratix IV E FPGA development board setup steps:

■ Inspecting the contents of the kit

■ Installing the design and kit software

■ Setting up, powering up, and verifying correct operation of the FPGA

■ Configuring the Stratix IV E FPGA

■ Running the Board Test System designs

f For complete information about the FPGA development board, refer to the

Stratix IV E FPGA Development Board Reference Manual.

Before You Begin

2. Getting Started

development board

Before using the kit or installing the software, check the kit contents and inspect the board to verify that you received all of the items listed in “Kit Features” on page 1–1. If any of the items are missing, contact Altera before you proceed.

Inspect the Board

To inspect the board, perform the following steps:

1. Place the board on an anti-static surface and inspect it to ensure that it has not been damaged during shipment.

c Without proper anti-static handling, you can damage the board.

2. Verify that all components are on the board and appear intact.

1 In typical applications with the Stratix IV E FPGA development board, a heat sink is

not necessary. However, under extreme conditions or for engineering sample silicon the board might require additional cooling to stay within operating temperature guidelines. You can perform power consumption and thermal modeling to determine whether your application requires additional cooling. For information about measuring board and FPGA temperature in real time, refer to “The Power Monitor”

on page 6–21.

f For more information about power consumption and thermal modeling, refer to

AN 358: Thermal Management for FPGAs.

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2–2 Chapter 2: Getting Started

References

Use the following links to check the Altera website for other related information:

■ For the latest board design files and reference designs, refer to the Stratix IV E

FPGA Development Kit page.

■ For additional daughter cards available for purchase, refer to the Development

Board Daughtercards page.

■ For the Stratix IV E device documentation, refer to the Literature: Stratix IV

Devices page.

■ To purchase devices from the eStore, refer to the Devices page.

■ For Stratix IV E OrCAD symbols, refer to the Capture CIS Symbols page.

■ For Nios II 32-bit embedded processor solutions, refer to the Embedded

Processing page.

Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation

3. Software Installation

This chapter explains how to install the following software:

■ Quartus II Subscription Edition Software

■ Stratix IV E FPGA Development Kit

■ USB-Blaster™ driver

Installing the Quartus II Subscription Edition Software

The Quartus II Subscription Edition Software provides the necessary tools used for developing hardware and software for Altera FPGAs. Included in the Quartus II Subscription Edition Software are the Quartus II software, the Nios II EDS, and the MegaCore IP Library. The Quartus II software (including Qsys and SOPC Builder) and the Nios II EDS are the primary FPGA development tools used to create the reference designs in this kit. To install the Altera development tools, perform the following steps:

1. Run the Quartus II Subscription Edition Software installer you acquired in

“Software” on page 1–2.

2. Follow the on-screen instructions to complete the installation process.

f If you have difficulty installing the Quartus II software, refer to Altera Software

Installation and Licensing Manual.

Licensing Considerations

Purchasing this kit entitles you to a one-year Development Kit license for the Quartus II Subscription Edition Software.

1 After the year, your Development Kit license will no longer be valid and you will not

Before using the Quartus II software, you must activate your license, identify specific users and computers, and obtain and install a license file.

If you already have a licensed version of the Subscription Edition, you can use that license file with this kit. If not, you need to obtain and install a license file. To begin, go to the Self Service Licensing Center page of the Altera website, log into or create your myAltera account, and take the following actions:

1. On the Activate Products page, enter the serial number provided with your development kit in the License Activation Code box.

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3–2 Chapter 3: Software Installation

Installing the Stratix IV E FPGA Development Kit

1 Your serial number is printed on the development kit box below the bottom

bar code. The number is 10 or 11 alphanumeric characters and does not contain hyphens. Figure 3–1 shows 3S150SPXXXX as an example serial number.

Figure 3–1. Locating Your Serial Number

2. Consult the Activate Products table, to determine how to proceed.

a. If the administrator listed for your product is someone other than you, skip the

remaining steps and contact your administrator to become a licensed user.

b. If the administrator listed for your product is you, proceed to step 3.

c. If the administrator listed for your product is Stocking, activate the product,

making you the administrator, and proceed to step 3.

3. Use the Create New License page to license your product for a specific user (you) on specific computers. The Manage Computers and Manage Users pages allow you to add users and computers not already present in the licensing system.

1 To license the Quartus II software, you need your computer’s network

interface card (NIC) ID, a number that uniquely identifies your computer. On the computer you use to run the Quartus II software, type

ipconfig /all

at a command prompt to determine the NIC ID. Your NIC ID

is the 12-digit hexadecimal number on the Physical Address line.

4. When licensing is complete, Altera emails a license.dat file to you. Store the file on your computer and use the License Setup page of the Options dialog box in the Quartus_II software to enable the software.

f For complete licensing details, refer to Altera Software Installation and Licensing Manual.

Installing the Stratix IV E FPGA Development Kit

To install the Stratix IV E FPGA Development Kit, perform the following steps:

1. Run the Stratix IV E FPGA Development Kit installer you acquired in “Software”

on page 1–2.

Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation

Chapter 3: Software Installation 3–3

documents

board_design_files

The default Windows installation directory is C:\altera\

examples

factory_recovery

demos

kits

stratixIVE_4se530_fpga

Installing the USB-Blaster Driver

2. Follow the on-screen instructions to complete the installation process. Be sure that the installation directory you choose is in the same relative location to your Quartus II software as the default locations.

The installation program creates the Stratix IV E FPGA Development Kit directory structure shown in Figure 3–2.

Figure 3–2. Stratix IV E FPGA Development Kit Installed Directory Structure (1)

Note to Figure 3–2:

(1) Early-release versions might have slightly different directory names.

Tab le 3– 1 lists the file directory names and a description of their contents.

Table 3–1. Installed Directory Contents

Directory Name Description of Contents

board_design_files

demos Contains demonstration applications, if present; not all kits include demos.

documents Contains the kit documentation.

examples Contains the sample design files for the Stratix IV E FPGA Development Kit.

factory_recovery

Contains schematic, layout, assembly, and bill of material board design files. Use these files as a starting point for a new prototype board design.

Contains the original data programmed onto the board before shipment. Use this data to restore the board with its original factory contents.

Installing the USB-Blaster Driver

The Stratix IV E FPGA development board includes integrated USB-Blaster circuitry for FPGA programming. However, for the host computer and board to communicate, you must install the USB-Blaster driver on the host computer.

f Installation instructions for the USB-Blaster driver for your operating system are

available on the Altera website. On the Altera Programming Cable Driver Information page of the Altera website, locate the table entry for your configuration and click the link to access the instructions.

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Installing the USB-Blaster Driver

Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation

The instructions in this chapter explain how to set up the Stratix IV E FPGA development board.

Setting Up the Board

To prepare and apply power to the board, perform the following steps:

1. The Stratix IV E FPGA development board ships with its board switches preconfigured to support the design examples in the kit. If you suspect your board might not be currently configured with the default settings, follow the instructions in “Factory Default Switch Settings” on page 4–2 to return the board to its factory settings before proceeding.

2. The FPGA development board ships with design examples stored in the flash memory device. Verify the PGM CONFIG SELECT rotary switch (SW5) is set to the 0 position to load the design stored in the factory portion of flash memory.

Figure 4–1 shows the switch location on the Stratix IV E FPGA development

board.

4. Development Board Setup

3. Connect the DC adapter (+16 V, 3.75 A) to the DC power jack (J22) on the FPGA board and plug the cord into a power outlet.

c Use only the supplied power supply. Power regulation circuitry on the

board can be damaged by power supplies with greater voltage.

4. Set the POWER switch (SW3) to the on position. When power is supplied to the board, a blue LED (D21) illuminates indicating that the board has power.

The MAX II device on the board contains (among other things) a parallel flash loader (PFL) megafunction. When the board powers up, the PFL reads a design from flash memory and configures the FPGA. The PGM CONFIG SELECT rotary switch (SW5) controls which design to load. When the switch is in the 0 position, the PFL loads the design from the factory portion of flash memory. When the switch is in the 1 position, the PFL loads the design from the user hardware portion of flash memory.

1 The kit includes a MAX II design which contains the MAX II PFL megafunction. The

design resides in the <install dir>\kits\stratixIVE_4se530_fpga\examples\max2 directory.

When configuration is complete, the CONF DONE LED (D22) illuminates, signaling that the Stratix IV E device configured successfully.

f For more information about the PFL megafunction, refer to Parallel Flash Loader

Megafunction User Guide.

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4–2 Chapter 4: Development Board Setup

12345678

4321

12345678

123

QDRII_DRIVE

MIN

VCC_VCCL_SEL

J21

USB

Clock

Enable

SW1

MSEL0

MAXII_JTAG_EN

J10

SHUNT = 1.8V_QDR

J11

FAN

J12

HSMB JTAG EN

HSMA_JTAG_EN

J15

SHUNT = 1.8V_RLD

J18

SW5

SW2

MAX II DIPSWITCH

Rotary Switch

OPEN

SW4

Board Settings

PGM CONFIG SELECT

Factory Default Switch Settings

This section shows the factory switch settings for the Stratix IV E FPGA development board. Figure 4–1 shows the switch locations and the default position of each switch on the top side of the board.

Figure 4–1. Switch Locations and Default Settings on the Board Top

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Chapter 4: Development Board Setup 4–3

RLD_ZQ_IMPED

MAX

J28

DDR3_TEST_HDR

J29

Factory Default Switch Settings

Figure 4–2 shows the switch locations and the default position of each switch on the

bottom side of the board.

Figure 4–2. Switch Locations and Default Settings on the Board Bottom

To restore the switches to their factory default settings, perform the following steps:

1. Set the PGM CONFIG SELECT rotary switch (SW5) to the 0 position, as shown in

Figure 4–1.

2. Set DIP switch bank (SW1) to match Ta bl e 4– 1 and Figure 4–1.

Table 4–1. SW1 Dip Switch Settings (Part 1 of 2)

Switch

Board

Label

Switch 1 has the following options:

1 CLK50_EN

2 CLK66_EN

■ When on, the 50 MHz clock is disabled.

■ When off, the 50 MHz clock is enabled.

Switch 2 has the following options:

■ When on, the 66 MHz clock is disabled.

■ When off, the 66 MHz clock is enabled.

Function

Default

Position

Off

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4–4 Chapter 4: Development Board Setup

Factory Default Switch Settings

Table 4–1. SW1 Dip Switch Settings (Part 2 of 2)

Switch

Board

Label

Switch 3 has the following options:

3 CLK100_EN

■ When on, the 100 MHz clock is disabled.

■ When off, the 100 MHz clock is enabled.

Switch 4 has the following options:

4 CLK125_EN

■ When on, the 125 MHz clock is disabled.

■ When off, the 125 MHz clock is enabled.

3. Set DIP switch bank (SW2) to match Ta bl e 4– 2 and Figure 4–1.

Table 4–2. SW2 Dip Switch Settings

Switch

Board

Label

Switch 1 is a MAX II user-defined switch and has the following options:

1DIP0

■ When closed, a logic 0 is selected.

■ When open, a logic 1 is selected.

Switch 2 is a MAX II user-defined switch and has the following options:

2DIP1

■ When closed, a logic 0 is selected.

■ When open, a logic 1 is selected.

Switch 3 is a MAX II user-defined switch and has the following options:

3DIP2

■ When closed, a logic 0 is selected.

■ When open, a logic 1 is selected.

Switch 4 is a MAX II user-defined switch and has the following options:

4DIP3

■ When closed, a logic 0 is selected.

■ When open, a logic 1 is selected.

Switch 5 is a MAX II user-defined switch and has the following options:

5DIP4

■ When closed, a logic 0 is selected.

■ When open, a logic 1 is selected.

Switch 6 is a MAX II user-defined switch and has the following options:

6DIP5

■ When closed, a logic 0 is selected.

■ When open, a logic 1 is selected.

Switch 7 is a MAX II user-defined switch and has the following options:

7DIP6

■ When closed, a logic 0 is selected.

■ When open, a logic 1 is selected.

Switch 8 has the following options:

8 CLK66_SEL

■ When closed, the 66 MHz clock is selected.

■ When open, the SMA input clock is selected.

Function

Default

Position

Off

Default

Position

Closed

Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation

Chapter 4: Development Board Setup 4–5

Factory Default Switch Settings

4. Set DIP switch bank (SW4) to match Ta bl e 4– 3 and Figure 4–1.

Table 4–3. SW4 Dip Switch Settings

Switch

Board

Label

1 USER_DIPSW0

2 USER_DIPSW1

3 USER_DIPSW2

4 USER_DIPSW3

5 USER_DIPSW4

6 USER_DIPSW5

7 USER_DIPSW6

8 USER_DIPSW7

Function

Switch 1 is a user-defined switch and has the following options:

■ When closed, a logic 0 is selected.

■ When open, a logic 1 is selected.

Switch 2 is a user-defined switch and has the following options:

■ When closed, a logic 0 is selected.

■ When open, a logic 1 is selected.

Switch 3 is a user-defined switch and has the following options:

■ When closed, a logic 0 is selected.

■ When open, a logic 1 is selected.

Switch 4 is a user-defined switch and has the following options:

■ When closed, a logic 0 is selected.

■ When open, a logic 1 is selected.

Switch 5 is a user-defined switch and has the following options:

■ When closed, a logic 0 is selected.

■ When open, a logic 1 is selected.

Switch 6 is a user-defined switch and has the following options:

■ When closed, a logic 0 is selected.

■ When open, a logic 1 is selected.

Switch 7 is a user-defined switch and has the following options:

■ When closed, a logic 0 is selected.

■ When open, a logic 1 is selected.

Switch 8 is a user-defined switch and has the following options:

■ When closed, a logic 0 is selected.

■ When open, a logic 1 is selected.

Default

Position

Open

Closed

5. Set the board jumpers to match Ta bl e 4 –4 , Figure 4–1, and Figure 4–2.

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4–6 Chapter 4: Development Board Setup

Factory Default Switch Settings

c Installing shunts in certain configurations might cause damage to devices

on your board. Pay specific attention to the Function column details.

Table 4–4. Jumper Settings (Part 1 of 2)

Board

Reference

Board

Label

J2 MSEL0

J4 USB DISABLE

J5 HSMB_JTAG_EN

J7 QDRII DRIVE

J10 MAXII_JTAG_EN

J11 SHUNT=1.8V QDR

J15 HSMA_JTAG_EN

J18 SHUNT=1.8V RLD

Function

This jumper has the following options:

■ Installing the shunt sets MSEL0 to logic 0.

■ Removing the shunt sets MSEL0 to logic 1.

This jumper has the following options:

■ Installing the shunt disables the onboard USB-Blaster.

■ Removing the shunt enables the onboard USB-Blaster.

This jumper has the following options:

■ Installing the shunt includes HSMC port B in the JTAG chain.

■ Removing the shunt removes HSMC port B from the JTAG chain.

This jumper has the following options:

■ Installing the shunt on pins 1 and 2 sets the QDR II output

impedance to the minimum value possible.

■ Installing the shunt on pins 3 and 4 sets the QDR II output

impedance to 50 Ω.

■ Installing the shunt on pins 5 and 6 sets the QDR II output

impedance to 60 Ω.

Always keep one and only one shunt installed. Other configurations might cause damage to the device.

This jumper has the following options:

■ Installing the shunt includes the MAX II EMP2210 device in the

JTAG chain.

■ Removing the shunt removes the MAX II device from the JTAG

chain.

This jumper has the following options:

■ Installing the shunt sets QDR II VDDQ to 1.8 V.

■ Removing the shunt sets QDR II VDDQ to 1.5 V.

This jumper has the following options:

■ Installing the shunt includes HSMC port A in the JTAG chain.

■ Removing the shunt removes HSMC port A from the JTAG chain.

This jumper has the following options:

■ Installing the shunt sets RLDRAM II VDDQ to 1.8 V.

■ Removing the shunt sets RLDRAM II VDDQ to 1.5 V.

Default

Shunt Position

Installed

Not installed

Installed on

pins 3 and 4

Installed

Not installed

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Chapter 4: Development Board Setup 4–7

Factory Default Switch Settings

Table 4–4. Jumper Settings (Part 2 of 2)

Board

Reference

Board

Label

J21 VCC_VCCL_SEL

J28 RLD_ZQ_IMPED

f For more information about the FPGA board settings, refer to the Stratix IV E FPGA

Development Board Reference Manual.

Function

This jumper has the following options:

■ Installing the shunt on pins 1 and 2 sets VCC and VCCL to 0.9 V.

■ Installing the shunt on pins 2 and 3 sets VCC and VCCL to 1.1 V.

■ Removing the shunt sets VCC and VCCL to 0.6 V.

Always keep a shunt installed on pins 1 and 2 only. The current version of the Stratix IV E device requires 0.9 V.

To use the RLDRAM II impedance drive jumpers, set the mode register. When the mode register is not set, the RLDRAM II output impedance is 50 Ω. The RLDRAM II impedance drive jumpers have the following options:

■ Installing the shunt on pins 1 and 2 sets the RLDRAM II output

impedance to the maximum value possible.

■ Installing the shunt on pins 3 and 4 sets the RLDRAM II output

impedance to 50 Ω.

■ Installing the shunt on pins 5 and 6 sets the RLDRAM II output

impedance to 60 Ω.

Installing more than one shunt might cause damage to the device.

Default

Shunt Position

Installed on

pins 1 and 2

Not installed

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4–8 Chapter 4: Development Board Setup

Factory Default Switch Settings

Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation

5. Board Update Portal

The Stratix IV E FPGA Development Kit ships with the Board Update Portal design example stored in the factory portion of the flash memory on the board. The design consists of a Nios II embedded processor, an Ethernet MAC, and an HTML web server.

When you power up the board with the PGM CONFIG SELECT rotary switch (SW5) in the 0 position, the Stratix IV E FPGA configures with the Board Update Portal design example. The design can obtain an IP address from any DHCP server and serve a web page from the flash on your board to any host computer on the same network. The web page allows you to upload new FPGA designs to the user hardware portion of flash memory, and provides links to useful information on the Altera website, including kit-specific links and design resources.

1 After successfully updating the user hardware flash memory, you can load the user

design from flash memory into the FPGA. To do so, set the PGM CONFIG SELECT rotary switch (SW5) to the 1 position and power cycle the board.

The source code for the Board Update Portal design resides in the <install dir>\kits\stratixIVE_4se530_fpga\examples directory. If the Board Update Portal is corrupted or deleted from the flash memory, refer to “Restoring the Flash Device to

the Factory Settings” on page A–4 to restore the board with its original factory

contents.

Connecting to the Board Update Portal Web Page

This section provides instructions to connect to the Board Update Portal web page.

1 Before you proceed, ensure that you have the following:

■ A PC with a connection to a working Ethernet port on a DHCP enabled network.

■ A separate working Ethernet port connected to the same network for the board.

■ The Ethernet and power cables that are included in the kit.

To connect to the Board Update Portal web page, perform the following steps:

1. With the board powered down, set the PGM CONFIG SELECT rotary switch (SW5) to the 0 position.

2. Attach the Ethernet cable from the board to your LAN.

3. Power up the board. The board connects to the LAN’s gateway router, and obtains an IP address. The LCD on the board displays the IP address.

4. Launch a web browser on a PC that is connected to the same network, and enter the IP address from the LCD into the browser address bar. The Board Update Portal web page appears in the browser.

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5–2 Chapter 5: Board Update Portal

1 You can click Stratix IV E FPGA Development Kit on the Board Update

Portal web page to access the kit’s home page for documentation updates and additional new designs.

f You c an al so n avi g ate directly to the Stratix IV E FPGA Development Kit page of the

Altera website to determine if you have the latest kit software.

Using the Board Update Portal to Update User Designs

The Board Update Portal allows you to write new designs to the user hardware portion of flash memory. Designs must be in the Nios II Flash Programmer File (.flash) format.

1 Design files available from the Stratix IV E FPGA Development Kit page include

.flash files. You can also create .flash files from your own custom design. Refer to

“Preparing Design Files for Flash Programming” on page A–2 for information about

preparing your own design for upload.

To upload a design over the network into the user portion of flash memory on your board, perform the following steps:

1. Perform the steps in “Connecting to the Board Update Portal Web Page” to access the Board Update Portal web page.

2. In the Hardware File Name field specify the .flash file that you either downloaded from the Altera website or created on your own. If there is a software component to the design, specify it in the same manner using the Software File Name field, otherwise leave the Software File Name field blank.

3. Click Upload. The progress bar indicates the percent complete.

4. To configure the FPGA with the new design after the flash memory upload process is complete, set the PGM CONFIG SELECT rotary switch (SW5) to the 1 position and power cycle the board, or press the RESET CONFIGn button (S1).

1 As long as you don’t overwrite the factory image in the flash memory device, you can

continue to use the Board Update Portal to write new designs to the user hardware portion of flash memory. If you do overwrite the factory image, you can restore it by following the instructions in “Restoring the Flash Device to the Factory Settings” on

page A–4.

Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation

6. Board Test System

The kit includes a design example and application called the Board Test System to test the functionality of the Stratix IV E FPGA development board. The application provides an easy-to-use interface to alter functional settings and observe the results. You can use the application to test board components, modify functional parameters, observe performance, and measure power usage. The application is also useful as a reference for designing systems. To install the application, follow the steps in

“Installing the Stratix IV E FPGA Development Kit” on page 3–2.

The application provides access to the following Stratix IV E FPGA development board features:

■ General purpose I/O (GPIO)

■ SRAM

■ Flash memory

■ DDR3, RLDRAM II, and QDR II+ memories

■ HSMC connectors

■ Character LCD

■ Graphics LCD

■ Ethernet

The application allows you to exercise most of the board components. While using the application, you reconfigure the FPGA several times with test designs specific to the functionality you are testing.

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6–2 Chapter 6: Board Test System

The Board Test System GUI communicates over the JTAG bus to a test design running in the Stratix IV E device. Figure 6–1 shows the initial GUI for a board that is in the factory configuration.

Figure 6–1. Board Test System Graphical User Interface

Several designs are provided to test the major board features. Each design provides data for one or more tabs in the application. The Configure menu identifies the appropriate design to download to the FPGA for each tab.

After successful FPGA configuration, the appropriate tab appears and allows you to exercise the related board features. Highlights appear in the board picture around the corresponding components.

The Power Monitor button starts the Power Monitor application that measures and reports current power and temperature information for the board. Because the application communicates over the JTAG bus to the MAX II device, you can measure the power of any design in the FPGA, including your own designs.

Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation

Chapter 6: Board Test System 6–3

Preparing the Board

1 The Board Test System and Power Monitor share the JTAG bus with other

applications like the Nios II debugger and the SignalTap Analyzer. Because the Quartus II programmer uses most of the bandwidth of the JTAG bus, other applications using the JTAG bus might time out. Be sure to close the other applications before attempting to reconfigure the FPGA using the Quartus II Programmer.

Preparing the Board

With the power to the board off, following these steps:

1. Connect the USB cable to the board.

2. Verify the settings for the board settings DIP switch banks (SW1, SW2, and SW4) match Table 4–1 on page 4–3, Table 4–2 on page 4–4, and Table 4–3 on page 4–5.

3. Set the PGM CONFIG SELECT rotary switch (SW5) to the 1 position.

4. Verify the settings for the jumpers match Table 4–4 on page 4–6. These settings determine the devices to include in the JTAG chain, among other important default settings.

f For more information about the board’s DIP switch and jumper settings,

II Embedded Logic

refer to the Stratix IV E FPGA Development Board Reference Manual.

5. Turn the power to the board on. The board loads the design stored in the user hardware portion of flash memory into the FPGA. If your board is still in the factory configuration or if you have downloaded a newer version of the Board Test System to flash memory through the Board Update Portal, the design loads the GPIO, SRAM, and flash memory tests.

c To ensure operating stability, keep the USB cable connected and the board

powered on when running the demonstration application. The application cannot run correctly unless the USB cable is attached and the board is on.

Running the Board Test System

To run the application, navigate to the <install dir>\kits\stratixIVE_4se530_fpga\examples\board_test_system directory and run

the BoardTestSystem.exe application.

1 On Windows, click Start > All Programs > Altera > Stratix IV E FPGA Development

Kit <version> > Board Test System to run the application.

A GUI appears, displaying the application tab that corresponds to the design running in the FPGA. The Stratix IV E FPGA development board’s flash memory ships preconfigured with the design that corresponds to the Config, GPIO, and SSRAM and Flash tabs.

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Using the Board Test System

1 If you power up your board with the PGM CONFIG SELECT rotary switch (SW5) in a

position other than the 1 position, or if you load your own design into the FPGA with the Quartus II Programmer, you receive a message prompting you to configure your board with a valid Board Test System design. Refer to “The Configure Menu” for information about configuring your board.

Using the Board Test System

This section describes each control in the Board Test System application.

The Configure Menu

Use the Configure menu (Figure 6–2) to select the design you want to use. Each design example tests different functionality that corresponds to one or more application tabs.

Figure 6–2. The Configure Menu

To configure the FPGA with a test system design, perform the following steps:

1. On the Configure menu, click one of the following options to determine how to pass data through the JTAG chain:

■ Use Fast Configuration—Compresses the data for faster loading.

■ Use Quartus II Programmer—Uses the standard JTAG-based configuration

method.

2. On the Configure menu, click the configure command that corresponds to the functionality you wish to test.

3. In the dialog box that appears, click Configure or Download Start to download the corresponding design’s SRAM Object File (.sof) to the FPGA. The download process usually takes about a minute.

4. When configuration finishes, close the Quartus II Programmer, if using it. The design begins running in the FPGA. The corresponding GUI application tabs that interface with the design enable.

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Chapter 6: Board Test System 6–5

Using the Board Test System

The Config Tab

The Config tab shows information about the board’s current configuration.

Figure 6–1 on page 6–2 shows the Config tab. The tab displays the contents of the

MAX II registers, the JTAG chain, the board’s MAC address, the flash memory map, and other details stored on the board.

The following sections describe the controls on the Config tab.

Board Information

The Board information controls display static information about your board.

■ MAX II ver—Indicates the version of MAX II code currently running on the board.

The MAX II code resides in the <install dir>\kits\stratixIVE_4se530_fpga\examples directory. Newer revisions of this code might be available on the Stratix IV E FPGA Development Kit page of the Altera website.

■ MAC—Indicates the MAC address of the board.

MAX II Registers

The MAX II registers control allow you to view and change the current MAX II register values as described in Table 6–1. Changes to the register values with the GUI take effect immediately. For example, writing a 0 to SRST resets the board.

Table 6–1. MAX II Registers

System Reset (SRST)

Page Select Register (PSR)

Read/Write

Capability

Description

Write only Set to 0 to initiate an FPGA reconfiguration.

Determines which of the up to eight (0-7) pages of flash

Read / Write

memory to use for FPGA reconfiguration. The flash memory ships with pages 0 and 1 preconfigured.

When set to 0, the value in PSR determines the page of Page Select Override (PSO)

Read / Write

flash memory to use for FPGA reconfiguration. When set to

1, the value in PSS determines the page of flash memory to

use for FPGA reconfiguration.

Page Select Switch (PSS)

■ PSO—Sets the MAX II PSO register. The following options are available:

■ Use PSR—Allows the PSR to determine the page of flash memory to use for

Read only Holds the current value of the rotary switch (SW5).

FPGA reconfiguration.

■ Use PSS—Allows the PSS to determine the page of flash memory to use for

FPGA reconfiguration.

■ PSR—Sets the MAX II PSR register. The numerical values in the list corresponds to

the page of flash memory to load during FPGA reconfiguration. Refer to Tabl e 6– 1 for more information.

■ PSS—Displays the MAX II PSS register value. Refer to Tab le 6– 1 for the list of

available options.

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■ SRST—Resets the system and reloads the FPGA with a design from flash memory

Using the Board Test System

based on the other MAX II register values. Refer to Tab le 6– 1 for more information.

1 Because the Config tab requires that a specific design is running in the FPGA, writing

a 0 to SRST or changing the PSO value can cause the Board Test System to stop running.

JTAG Chain

The JTAG chain control shows all the devices currently in the JTAG chain. The Stratix IV E device is always the first device in the chain.

1 Installing the shunt jumper on jumper J10 includes the MAX II device in the JTAG

chain.

SOPC Builder Memory Map

The SOPC Builder memory map control shows the memory map of the FPGA design’s SOPC Builder system.

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Chapter 6: Board Test System 6–7

Using the Board Test System

The GPIO Tab

The GPIO tab allows you to interact with all the general purpose user I/O components on your board. You can write to the character LCD, read DIP switch settings, turn LEDs on or off, write to the 7-segment display, load images to the graphics LCD, run a server program on the Ethernet port, and detect push button presses. Figure 6–3 shows the GPIO tab.

Figure 6–3. The GPIO Tab

The following sections describe the controls on the GPIO tab.

Character LCD

The Character LCD controls allow you to display text strings on the character LCD on your board. Type text in the text boxes and then click Write.

1 If you exceed the 16 character display limit on either line, a warning message appears.

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Using the Board Test System

User DIP Switches

The read-only User DIP switch control displays the current positions of the switches in the user DIP switch bank (SW1). Change the switches on the board to see the graphical display change accordingly.

User LEDs

The User LEDs control displays the current state of the user LEDs. Click the LED buttons to turn the board LEDs on and off.

Push Button Switches

The read-only Push Button switches control displays the current state of the board user push buttons. Press a push button on the board to see the graphical display change accordingly.

7-Segment Display

The 7-segment display controls allow you to display hexadecimal numbers on the 7-segment display on your board. Type hexadecimal numbers in the text box and then click Write.

Graphics LCD

The Graphics LCD control allows you to display Bitmap Image Files (.bmp) on the graphics LCD on your board.

■ Select File—Allows you to browse your file system and select a .bmp image to

load.

■ Load—Downloads the selected file to the board.

Ethernet

Click Start Simple Socket Server to run the simple_socket_server.elf program that was downloaded into FPGA during configuration.

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Chapter 6: Board Test System 6–9

Using the Board Test System

The Flash Tab

The Flash tab allows you to read and write flash memory on your board. Figure 6–4 shows the Flash tab.

Figure 6–4. The Flash Tab

The following sections describe the controls on the Flash tab.

Read

The Read control reads the flash memory on your board. Type a starting address in the text box and click Read. Values starting at the specified address appear in the table. The base address of flash memory in this Nios II-based BTS design is 0x0800.0000. The valid address range within the 64-MB flash memory is 0x0000.0000 through 0x03FF.FFFF, as shown in the GUI.

1 If you enter an address outside of the flash memory address space, a warning

message identifies the valid flash memory address range.

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Using the Board Test System

Write

The Wri te control writes the flash memory on your board. To update the flash memory contents, change values in the table and click Wr ite. The application writes the new values to flash memory and then reads the values back to guarantee that the graphical display accurately reflects the memory contents.

1 To prevent overwriting the dedicated portions of flash memory, the application limits

the writable flash memory address range from 0x03FE.0000 to 0x03FF.FFFF (which corresponds to the unused flash memory address range shown in Table A–1 on

page A–1).

Random Test

Starts a random data pattern test to flash memory where the data pattern contents are read back and displayed. Errors are reported in the messages window. This test takes 10-15 seconds to run with an hour-glass displayed while the test is busy.

Increment Test

Starts an incrementing data pattern test to flash memory where the data pattern contents are read back and displayed. Errors are reported in the messages window. This test takes 10-15 seconds to run with an hour-glass displayed while the test is busy.

CFI Query

The CFI Query control updates the memory table, displaying the CFI ROM table contents from the flash device.

Reset

The Reset control executes the flash device’s reset command and updates the memory table displayed on the Flash tab.

Erase

Erases flash memory, which is limited to a scratch page in the upper 128K block.

Flash Memory Map

Displays the flash memory map for the Stratix IV E FPGA Development Kit.

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Chapter 6: Board Test System 6–11

Using the Board Test System

The SSRAM Tab

The SSRAM tab allows you to read and write SSRAM on your board. Figure 6–5 shows the SSRAM tab.

Figure 6–5. The SSRAM Tab

The following sections describe the controls on the SSRAM tab.

Read

Reads the SSRAM on your board. To see the SSRAM contents, type a starting address in the text box and click Read. Values starting at the specified address appear in the table. The base address of SRAM in this Nios II-based BTS design is 0x0D00.0000. The valid address range within the 2-MB SRAM is 0x0000.0000 through 0x001F.FFFF, as shown in the GUI.

1 If you enter an address outside of the 0x0000.0000 to 0x001F.FFFF SSRAM address

space, a warning message identifies the valid SSRAM address range.

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Using the Board Test System

Write

Writes the SSRAM on your board. To update the SSRAM contents, change values in the table and click Write. The application writes the new values to SSRAM and then reads the values back to guarantee that the graphical display accurately reflects the memory contents.

Random Test

Starts a random data pattern to SSRAM. After writing a block of SRAM with this data pattern, the contents are read back and displayed. Errors are reported in the messages window.

Increment Test

Starts an incrementing data pattern test to SSRAM. After writing a block of SRAM with this data pattern, the contents are read back and displayed. Errors are reported in the messages window.

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Chapter 6: Board Test System 6–13

Using the Board Test System

The DDR3 Tab

The DDR3 tab allows you to read and write the DDR3 memory on your board.

Figure 6–6 shows the DDR3 tab.

Figure 6–6. The DDR3 Tab

The following sections describe the controls on the DDR3 tab.

Start

The Start control initiates DDR3 memory transaction performance analysis.

Stop

The Stop control terminates transaction performance analysis.

Performance Indicators

These controls display current transaction performance analysis information collected since you last pressed Start:

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■ Write, Read, and To t al performance bars—Show the percentage of maximum

Using the Board Test System

theoretical data rate that the requested transactions are able to achieve.

■ Write (MBps), Read (MBps), and Total (MBps)—Show the number of bytes of

data analyzed per second. The data bus is 72 bits wide and the frequency is 533 MHz double data rate (1066 Mbps per pin), equating to a theoretical maximum bandwidth of 9594 MBps.

Error Control

The Error control controls display data errors detected during analysis and allow you to insert errors:

■ Detected errors—Displays the number of data errors detected in the hardware.

■ Inserted errors—Displays the number of errors inserted into the transaction

stream.

■ Insert Error—Inserts a one-word error into the transaction stream each time you

click the button. Insert Error is only enabled during transaction performance analysis.

■ Clear—Resets the Detected errors and Inserted errors counters to zeros.

Number of Addresses to Write and Read

The Number of addresses to write and read control determines the number of addresses to use in each iteration of reads and writes. Valid values range from 8 to 16,777,216.

Data Type

The Data type control specifies the type of data contained in the transactions. The following data types are available for analysis:

■ PRBS—Selects pseudo-random bit sequences.

■ Memory—Selects a generic data pattern stored in the on chip memory of the

Stratix IV E device.

■ Math—Selects data generated from a simple math function within the FPGA

fabric.

Read and Write Control

The Read and write control specifies the type of transactions to analyze. The following transaction types are available for analysis:

■ Write then read—Selects read and write transactions for analysis.

■ Read only—Selects read transactions for analysis.

■ Write only—Selects write transactions for analysis.

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Chapter 6: Board Test System 6–15

Using the Board Test System

The QDRII+ Tab

The QDRII+ tab allows you to read and write the QDR II+ memory on your board.

Figure 6–7 shows the QDRII+ tab.

Figure 6–7. The QDRII+ Tab

The following sections describe the controls on the QDRII+ tab.

Start

The Start control initiates QDR II+ memory transaction performance analysis.

Stop

The Stop control terminates transaction performance analysis.

Performance Indicators

These controls display current transaction performance analysis information collected since you last clicked Start:

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■ Write and Read performance bars—Show the percentage of maximum theoretical

Using the Board Test System

data rate that the requested transactions are able to achieve.

■ Write (MBp s ) and Read (MBps)—Show the number of bytes of data analyzed per

second. The QDR II+ bus is 18 bits wide for both read and write, and the frequency is 400 MHz double data rate (800 Mbps per pin), equating to a theoretical maximum bandwidth of 1800 MBps, and 3600 MBps for simultaneous read and write.

Error Control

The Error control controls display data errors detected during analysis and allow you to insert errors:

■ Detected errors—Displays the number of data errors detected in the hardware.

■ Inserted errors—Displays the number of errors inserted into the transaction

stream.

■ Insert Error—Inserts a one-word error into the transaction stream each time you

click the button. Insert Error is only enabled during transaction performance analysis.

■ Clear—Resets the Detected errors and Inserted errors counters to zeros.

Number of Addresses to Write and Read

The Number of addresses to write and read control determines the number of addresses to use in each iteration of reads and writes. Valid values range from 8 to 1,048,576.

Data Type

The Data type control specifies the type of data contained in the transactions. The following data types are available for analysis:

■ PRBS—Selects pseudo-random bit sequences.

■ Memory—Selects a generic data pattern stored in the on chip memory of the

Stratix IV E device.

■ Math—Selects data generated from a simple math function within the FPGA

fabric.

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Chapter 6: Board Test System 6–17

Using the Board Test System

The RLDRAMII Tab

The RLDRAMII tab allows you to read and write the RLDRAM II on your board.

Figure 6–8 shows the RLDRAMII tab.

Figure 6–8. The RLDRAMII Tab

The following sections describe the controls on the RLDRAMII tab.

Start

The Start control initiates RLDRAM II memory transaction performance analysis.

Stop

The Stop control terminates transaction performance analysis.

Performance Indicators

These controls display current transaction performance analysis information collected since you last clicked Start:

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■ Write, Read, and To t al performance bars—Show the percentage of maximum

Using the Board Test System

theoretical data rate that the requested transactions are able to achieve.

■ Write (MBps), Read (MBps), and Total (MBps)—Show the number of bytes of

data analyzed per second. The RLDRAMII bus is 36 bits wide and the frequency is 400 MHz double data rate (800 Mbps per pin), equating to a theoretical maximum bandwidth of 3600 MBps.

Error Control

The Error control controls display data errors detected during analysis and allow you to insert errors:

■ Detected errors—Displays the number of data errors detected in the hardware.

■ Inserted errors—Displays the number of errors inserted into the transaction

stream.

■ Insert Error—Inserts a one-word error into the transaction stream each time you

click the button. Insert Error is only enabled during transaction performance analysis.

■ Clear—Resets the Detected errors and Inserted errors counters to zeros.

Number of Addresses to Write and Read

The Number of addresses to write and read control determines the number of addresses to use in each iteration of reads and writes. Valid values range from 8 to 16,777,216.

Data Type

The Data type control specifies the type of data contained in the transactions. The following data types are available for analysis:

■ PRBS—Selects pseudo-random bit sequences.

■ Memory—Selects a generic data pattern stored in the on chip memory of the

Stratix IV E device.

■ Math—Selects data generated from a simple math function within the FPGA

fabric.

Read and Write Control

The Read and write control control specifies the type of transactions to analyze. The following transaction types are available for analysis:

■ Write then read—Selects read and write transactions for analysis.

■ Read only—Selects read transactions for analysis.

■ Write only—Selects write transactions for analysis.

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Chapter 6: Board Test System 6–19

Using the Board Test System

The HSMC Tab

The HSMC tab allows you to perform loopback tests on the HSMC A and HSMC B ports. Figure 6–9 shows the HSMC tab.

Figure 6–9. The HSMC Tab

1 You must have the loopback HSMC installed on the HSMC connector that you are

testing for this test to work correctly.

The following sections describe the controls on the HSMC tab.

Status

The Status control displays the following status information during the loopback test:

■ PLL lock—Shows the PLL locked or unlocked state.

■ Channel lock—Shows the channel locked or unlocked state. When locked, all

lanes are word aligned and channel bonded.

■ Pattern sync—Shows the pattern synced or not synced state. The pattern is

considered synced when the start of the data sequence is detected.

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Using the Board Test System

Port

The Port control allows you to specify the type of test to run on the HSMC ports. The following HSMC port tests are available:

■ HSMA x17 LVDS SERDES

■ HSMA x3 single-ended loopback

■ HSMB x17 LVDS SERDES

■ HSMB x3 single-ended loopback

Data Type

The Data type control specifies the type of data contained in the transactions. The following data types are available for analysis:

■ PRBS—Selects pseudo-random bit sequences.

■ Memory—Selects a generic data pattern stored in the on chip memory of the

Stratix IV E device.

■ Math—Selects data generated from a simple math function within the FPGA

fabric.

Error Control

The Error control controls display data errors detected during analysis and allow you to insert errors:

■ Detected errors—Displays the number of data errors detected in the hardware.

■ Inserted errors—Displays the number of errors inserted into the transmit data

stream.

■ Insert Error—Inserts a one-word error into the transmit data stream each time you

click the button. Insert Error is only enabled during transaction performance analysis.

■ Clear—Resets the Detected errors and Inserted errors counters to zeros.

Start

The Start control initiates HSMC transaction performance analysis.

Stop

The Stop control terminates transaction performance analysis.

Performance Indicators

These controls display current transaction performance analysis information collected since you last clicked Start:

■ TX and RX performance bars—Show the percentage of maximum theoretical data

rate that the requested transactions are able to achieve.

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Chapter 6: Board Test System 6–21

The Power Monitor

■ Tx (MBps) and Rx (MBps)—Show the number of bytes of data analyzed per

second. The HSMC x17 SERDES buses on both HSMC A and HSMC B are 17 bits wide and clocked using the 125 MHz oscillator with a PLL multiplier of 13, equating to a 1.625 Gbps per pin, or a 27.625 Gbps bandwidth for each x17 SERDES port. The x3 single-ended data bus is 3 bits wide and clocked using a 100 MHz clock single-data-rate for 100 Mbps per pin, or a 300 Mbps bandwidth for each x3 single-ended data port.

The Power Monitor

The Power Monitor measures and reports current power and temperature information for the board. To start the application, click Power Monitor in the Board Test System application.

1 You can also run the Power Monitor as a stand-alone application. PowerTool.exe

resides in the <install dir>\kits\stratixIVE_4se530_fpga\examples\board_test_system directory. On Windows, click Start > All Programs > Altera > Stratix IV E FPGA Development Kit <version> > Power Monitor to start the application.

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The Power Monitor

The Power Monitor communicates with the MAX II device on the board through the JTAG bus. A power monitor circuit attached to the MAX II device allows you to measure the power that the Stratix IV E FPGA device is consuming regardless of the design currently running. Figure 6–10 shows the Power Monitor.

Figure 6–10. The Power Monitor

The following sections describe the Power Monitor controls.

General Information

The General information controls display the following information about the MAX II device:

■ MAX II version—Indicates the version of MAX II code currently running on the

board. The MAX II code resides in the <install

dir>\kits\stratixIVE_4se530_fpga\factory_recovery and <install dir>\kits\stratixIVE_4se530_fpga\examples\max2 directories. Newer revisions

of this code might be available on the Stratix IV E FPGA Development Kit page of the Altera website.

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Chapter 6: Board Test System 6–23

The Power Monitor

■ Power rail—Indicates the currently-selected power rail. The rotary switch (SW5)

on your board controls which rail to measure. After setting the switch for the desired rail, click Reset to refresh the screen with new board readings.

f A table with the power rail information is available in the Stratix IV E FPGA

Development Board Reference Manual.

Temperature Information

The Temperature information controls display the following temperature readings for the board and the FPGA on the board:

■ FPGA—Indicates the temperature of the FPGA device.

■ Board—Indicates the overall board temperature.

Power Information

The Power information control displays current, maximum, and minimum power readings for the following units:

■ mVolt

■ mAmp

■ mWatt

12-V Power Consumption

The 12-V Power consumption control displays 12-V power consumption readings for the following units:

■ mA

■ mW

Power Graph

The power graph displays the mWatt power consumption of your board over time. The green line indicates the current value. The red line indicates the maximum value read since the last reset. The yellow line indicates the minimum value read since the last reset.

Graph Settings

The following Graph settings controls allow you to define the look and feel of the power graph:

■ Scale select—Specifies the amount to scale the power graph. Select a smaller

number to zoom in to see finer detail. Select a larger number to zoom out to see the entire range of recorded values.

■ Update speed—Specifies how often to refresh the graph.

Reset

This Reset control clears the graph, resets the minimum and maximum values, and restarts the Power Monitor.

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Configuring the FPGA Using the Quartus II Programmer

Calculating Power

The Power Monitor calculates power by measuring two different voltages with the LT2418 A/D and applying the equation P = V × I to determine the power consumption. The LT2418 measures the voltage after the appropriate sense resistor (Vsense) and the voltage drop across that sense resistor (Vdif). The current (I) is calculated by dividing the measured voltage drop across the resistor by the value of the sense resistor (I = Vdif/R). Through substitution, the equation for calculating power becomes P = V × I = Vsense × (Vdif/R) = (Vsense) × (Vdif) × (1/.003).

You can verify the power numbers shown in the Power Monitor with a digital multimeter that is capable of measuring microvolts to ensure you have enough significant digits for an accurate calculation. Measure the voltage on one side of the resistor (the side opposite the power source) and then measure the voltage on the other side. The first measurement is Vsense and the difference between the two measurements is Vdif. Plug the values into the equation to determine the power consumption.

Configuring the FPGA Using the Quartus II Programmer

You can use the Quartus II Programmer to configure the FPGA with a specific .sof. Before configuring the FPGA, ensure that the Quartus II Programmer and the USB-Blaster driver are installed on the host computer, the USB cable is connected to the FPGA development board, power to the board is on, and no other applications that use the JTAG chain are running.

To configure the Stratix IV E FPGA, perform the following steps:

1. Start the Quartus II Programmer.

2. Click Add File and select the path to the desired .sof.

3. Turn on the Program/Configure option for the added file.

4. Click Start to download the selected file to the FPGA. Configuration is complete when the progress bar reaches 100%.

1 Using the Quartus II programmer to configure a device on the board causes other

JTAG-based applications such as the Board Test System and the Power Monitor to loose their connection to the board. Restart those applications after configuration is complete.

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A. Programming the Flash Memory

Device

As you develop your own project using the Altera tools, you can program the flash memory device so that your own design loads from flash memory into the FPGA on power up. This appendix describes the preprogrammed contents of the common flash interface (CFI) flash memory device on the Stratix IV E FPGA development board and the Nios II EDS tools involved with reprogramming the user portions of the flash memory device.

The Stratix IV E FPGA development board ships with the CFI flash device preprogrammed with a default factory FPGA configuration for running the Board Update Portal design example and a default user configuration for running the Board Test System demonstration. There are several other factory software files written to the CFI flash device to support the Board Update Portal. These software files were created using the Nios II EDS, just as the hardware design was created using the Quartus II software.

f For more information about Altera development tools, refer to the Design Software

page of the Altera website.

CFI Flash Memory Map

Tab le A– 1 shows the default memory contents of the 512-Mb single-die CFI flash

device. For the Board Update Portal to run correctly and update designs in the user memory, this memory map must not be altered.

Table A–1. Byte Address Flash Memory Map

Block Description Size (KB) Address Range

Unused 128 0x03FE.0000 - 0x03FF.FFFF

User software 11,699 0x034C.0000 - 0x03FD.FFFF

User hardware 21,627 0x0202.0000 - 0x034B.FFFF

Reserved 128 0x0200.0000 - 0x0201.FFFF

zipfs (html, web content) 5,898 0x01A6.0000 - 0x01FF.FFFF

Factory software 5,898 0x014C.0000 - 0x01A5.FFFF

Factory hardware 21,627 0x0002.0000 - 0x014B.FFFF

PFL option bits 32 0x0001.8000 - 0x0001.FFFF

Board information 32 0x0001.0000 - 0x0001.7FFF

Ethernet option bits 32 0x0000.8000 - 0x0000.FFFF

User design reset vector 32 0x0000.0000 - 0x0000.7FFF

c Altera recommends that you do not overwrite the factory hardware and factory

software images unless you are an expert with the Altera tools. If you unintentionally overwrite the factory hardware or factory software image, refer to “Restoring the

Flash Device to the Factory Settings” on page A–4.

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Preparing Design Files for Flash Programming

You can obtain designs containing prepared .flash files from the Stratix IV E FPGA

Development Kit page of the Altera website or create .flash files from your own

custom design.

The Nios II EDS sof2flash command line utility converts your Quartus II-compiled

.sof into the .flash format necessary for the flash device. Similarly, the Nios II EDS elf2flash command line utility converts your compiled and linked Executable and Linking Format File (.elf) software design to .flash. After your design files are in the .flash format, use the Board Update Portal or the Nios II EDS nios2-flashprogrammer utility to write the .flash files to the user hardware and user software

locations of the flash memory.

f For more information about Nios II EDS software tools and practices, refer to the

Embedded Software Development page of the Altera website.

Creating Flash Files Using the Nios II EDS

If you have an FPGA design developed using the Quartus II software, and software developed using the Nios II EDS, follow these instructions:

1. On the Windows Start menu, click All Programs > Altera > Nios II EDS > Nios II Command Shell.

2. In the Nios II command shell, navigate to the directory where your design files reside and type the following Nios II EDS commands:

■ For Quartus II .sof files:

sof2flash --input=<yourfile>_hw.sof --output=<yourfile>_hw.flash --offset=0x02020000

--pfl --optionbit=0x00018000 --programmingmode=PS r

■ For Nios II .elf files:

elf2flash --base=0x08000000 --end=0x0BFFFFFF --reset=0x0B4C0000

--input=<yourfile>_sw.elf --output=<yourfile>_sw.flash

--boot=$SOPC_KIT_NIOS2/components/altera_nios2/

boot_loader_cfi.srec r

1 For boards with dual-die CFI flash devices, use

--offset=0x00020000

--base=0x0A000000

and

f For more information, refer to the Board Revision History appendix of the

Stratix IV E FPGA Development Board Reference Manual.

The resulting .flash files are ready for flash device programming. If your design uses additional files such as image data or files used by the runtime program, you must first convert the files to .flash format and concatenate them into one .flash file before using the Board Update Portal to upload them.

1 The Board Update Portal standard .flash format conventionally uses either

<filename>_hw.flash for hardware design files or <filename>_sw.flash for software design files.

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Chapter : A–3

Programming Flash Memory Using the Board Update Portal

Once you have the necessary .flash files, you can use the Board Update Portal to reprogram the flash memory. Refer to “Using the Board Update Portal to Update User

Designs” on page 5–2 for more information.

1 If you have generated a .sof that operates without a software design file, you can still

use the Board Update Portal to upload your design. In this case, leave the Software File Name field blank.

Programming Flash Memory Using the Nios II EDS

The Nios II EDS offers a nios2-flash-programmer utility to program the flash memory directly. To program the .flash files or any compatible S-Record File (.srec) to the board using nios2-flash-programmer, perform the following steps:

1. Set the PGM CONFIG SELECT rotary switch (SW5) to the 0 position to load the Board Update Portal design from flash memory on power up.

2. Attach the USB-Blaster cable and power up the board.

3. If the board has powered up and the LCD displays either "Connecting..." or a valid IP address (such as 152.198.231.75), proceed to step 8. If no output appears on the LCD or if the CONF DONE LED (D22) does not illuminate, continue to step 4 to load the FPGA with a flash-writing design.

4. Launch the Quartus II Programmer to configure the FPGA with a .sof capable of flash programming. Refer to “Configuring the FPGA Using the Quartus II

Programmer” on page 6–24 for more information.

5. Click Add File and select <install dir>\kits\stratixIVE_4se530_fpga\factory_recovery\s4e530_fpga_bup.sof.

6. Turn on the Program/Configure option for the added file.

7. Click Start to download the selected configuration file to the FPGA. Configuration is complete when the progress bar reaches 100%. The CONF DONE LED (D22) and the eight user LEDs (D23-D30) illuminate indicating that the flash device is ready for programming.

8. On the Windows Start menu, click All Programs > Altera > Nios II EDS > Nios II Command Shell.

9. In the Nios II command shell, navigate to the <install dir>\kits\stratixIVE_4se530_fpga\factory_recovery directory (or to the directory of the .flash files you created in “Creating Flash Files Using the Nios II EDS” on

page A–2) and type the following Nios II EDS command:

nios2-flash-programmer --base=0x08000000 <yourfile>_hw.flash r

10. After programming completes, if you have a software file to program, type the following Nios II EDS command:

nios2-flash-programmer --base=0x08000000 <yourfile>_sw.flash r

1 For boards with dual-die CFI flash devices, use

June 2011 Altera Corporation Stratix IV E FPGA Development Kit User Guide

--base=0x0A000000

A–4 Chapter :

Restoring the Flash Device to the Factory Settings

f For more information, refer to the Board Revision History appendix of the

Stratix IV E FPGA Development Board Reference Manual.

11. Set the PGM CONFIG SELECT rotary switch (SW5) to the 1 position and power cycle the board, or press the RESET CONFIGn button (S1) to load and run the user hardware design.

Programming the board is now complete.

f For more information about the nios2-flash-programmer utility, refer to the Nios II

Flash Programmer User Guide.

Restoring the Flash Device to the Factory Settings

This section describes how to restore the original factory contents to the flash memory device on the FPGA development board. Make sure you have the Nios II EDS installed, and perform the following instructions:

1 For boards with dual-die CFI flash devices, use <install

dir>\kits\stratixIVE_4se530_fpga\factory_recovery\dual_die_flash directory. For more information, refer to the Board Revision History appendix of the Stratix IV E

FPGA Development Board Reference Manual.

1. Set the board switches to the factory default settings described in “Factory Default

Switch Settings” on page 4–2.

2. Launch the Quartus II Programmer to configure the FPGA with a .sof capable of flash programming. Refer to “Configuring the FPGA Using the Quartus II

Programmer” on page 6–24 for more information.

3. Click Add File and select <install dir>\kits\stratixIVE_4se530_fpga\factory_recovery\s4e530_fpga_bup.sof.

4. Turn on the Program/Configure option for the added file.

5. Click Start to download the selected configuration file to the FPGA. Configuration is complete when the progress bar reaches 100%. The CONF DONE LED (D22) and the eight user LEDs (D23-D30) illuminate indicating that the flash device is ready for programming.

6. On the Windows Start menu, click All Programs > Altera > Nios II EDS > Nios II Command Shell.

7. In the Nios II command shell, navigate to the <install dir>\kits\stratixIVE_4se530_fpga\factory_recovery directory and type the following command to run the restore script:

./restore.sh r

Restoring the flash memory might take several minutes. Follow any instructions that appear in the Nios II command shell.

8. After all flash programming completes, cycle the POWER switch (SW3) off then on.

9. Using the Quartus II Programmer, click Add File and select <install dir>\kits\stratixIVE_4se530_fpga\factory_recovery\s4e530_fpga_bup.sof.

Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation

Chapter : A–5

Restoring the MAX II CPLD to the Factory Settings

10. Turn on the Program/Configure option for the added file.

11. Click Start to download the selected configuration file to the FPGA. Configuration is complete when the progress bar reaches 100%. The CONF DONE LED (D22) and the eight user LEDs (D23-D30) illuminate indicating the flash memory device is now restored with the factory contents.

12. Cycle the POWER switch (SW3) off then on to load and run the restored factory design.

13. The restore script cannot restore the board’s MAC address automatically. In the Nios II command shell, type the following Nios II EDS command:

nios2-terminal r

and follow the instructions in the terminal window to generate a unique MAC address.

f To ensure that you have the most up-to-date factory restore files and information

about this product, refer to the Stratix IV E FPGA Development Kit page of the Altera website.

Restoring the MAX II CPLD to the Factory Settings

This section describes how to restore the original factory contents to the MAX II CPLD on the FPGA development board. Make sure you have the Nios II EDS installed, and perform the following instructions:

1. Set the board switches to the factory default settings described in “Factory Default

Switch Settings” on page 4–2.

1 Installing the shunt jumper on jumper J10 includes the MAX II device in the

JTAG chain.

2. Launch the Quartus II Programmer.

3. Click Auto Detect.

4. Click Add File and select <install dir>\kits\stratixIVE_4se530_fpga\factory_recovery\max2.pof.

5. Turn on the Program/Configure option for the added file.

6. Click Start to download the selected configuration file to the MAX II CPLD. Configuration is complete when the progress bar reaches 100%.

f To ensure that you have the most up-to-date factory restore files and information

about this product, refer to the Stratix IV E FPGA Development Kit page of the Altera website.

June 2011 Altera Corporation Stratix IV E FPGA Development Kit User Guide

A–6 Chapter :

Restoring the MAX II CPLD to the Factory Settings

Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation

This chapter provides additional information about the document and Altera.

Document Revision History

The following table shows the revision history for this document.

Date Version Changes

■ Changed dual-die CFI flash memory device to single-die.

June 2011 1.2

Feb 2010 1.1 Adjusted flash memory map.

November 2009 1.0 Initial release.

■ Added alert to Appendix A showing new dual_die_flash directory.

■ Many small text and graphic improvements.

Additional Information

How to Contact Altera

To locate the most up-to-date information about Altera products, refer to the following table.

Contact (1) Contact Method Address

Technical support Website www.altera.com/support

Technical training

Product literature Website www.altera.com/literature

Non-technical support (General) Email nacomp@altera.com

(Software Licensing) Email authorization@altera.com

Note to Table:

(1) You can also contact your local Altera sales office or sales representative.

Website www.altera.com/training

Email custrain@altera.com

Typographic Conventions

The following table shows the typographic conventions this document uses.

Visual Cue Meaning

Bold Type with Initial Capital Letters

bold type

Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.

Indicates command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI.

Indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \qdesigns directory, D: drive, and chiptrip.gdf file.

June 2011 Altera Corporation Stratix IV E FPGA Development Kit User Guide

Info–2 Additional Information

Typographic Conventions

Visual Cue Meaning

Indicates variables. For example, n + 1.

italic type

Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file.

Initial Capital Letters

“Subheading Title”

Indicates keyboard keys and menu names. For example, the Delete key and the Options menu.

Quotation marks indicate references to sections within a document and titles of Quartus II Help topics. For example, “Typographic Conventions.”

Indicates signal, port, register, bit, block, and primitive names. For example,

tdi

, and

input

. The suffix n denotes an active-low signal. For example,

data1

resetn

Indicates command line commands and anything that must be typed exactly as it

Courier type

appears. For example,

c:\qdesigns\tutorial\chiptrip.gdf

Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword example,

TRI

SUBDESIGN

), and logic function names (for

r An angled arrow instructs you to press the Enter key.

1., 2., 3., and a., b., c., and so on

■ ■ ■ Bullets indicate a list of items when the sequence of the items is not important.

Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure.

1 The hand points to information that requires special attention. h A question mark directs you to a software help system with related information. f The feet direct you to another document or website with related information.

A caution calls attention to a condition or possible situation that can damage or destroy the product or your work.

A warning calls attention to a condition or possible situation that can cause you injury.

The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents.

Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation

Altera Stratix IV E FPGA User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

1. About This Kit

Kit Features

Hardware

Software

Before You Begin

2. Getting Started

Inspect the Board

References

3. Software Installation

Installing the Quartus II Subscription Edition Software

Licensing Considerations

Installing the Stratix IV E FPGA Development Kit

Installing the USB-Blaster Driver

Setting Up the Board

4. Development Board Setup

Factory Default Switch Settings

5. Board Update Portal

Connecting to the Board Update Portal Web Page

Using the Board Update Portal to Update User Designs

6. Board Test System

Preparing the Board

Running the Board Test System

Using the Board Test System

The Configure Menu

The Config Tab

The GPIO Tab

The Flash Tab

The SSRAM Tab

The DDR3 Tab

The QDRII+ Tab

The RLDRAMII Tab

The HSMC Tab

The Power Monitor

Configuring the FPGA Using the Quartus II Programmer

Calculating Power

CFI Flash Memory Map

Preparing Design Files for Flash Programming

Creating Flash Files Using the Nios II EDS

Programming Flash Memory Using the Board Update Portal

Programming Flash Memory Using the Nios II EDS

Restoring the Flash Device to the Factory Settings

Restoring the MAX II CPLD to the Factory Settings

Document Revision History

Additional Information

How to Contact Altera

Typographic Conventions