Altera Stratix III Development Board User Manual

Download

Stratix III 3SL150 Development Board Reference Manual

Stratix III 3SL150 Development Board

Reference Manual

101 Innovation Drive San Jose, CA 95134

www.altera.com

MNL-01030-1.5

Feedback Subscribe

© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

Chapter 1. Overview

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Chapter 2. Board Components

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Featured FPGA (U22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

MAX II CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

FPGA Programming Over USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

Flash Programming over USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

Board Specific LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

Power Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

JTAG Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

MAX II Device Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

System Reset and Configuration Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

Power Select Rotary Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

PGM Config Select Rotary Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

Clocking Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

Stratix III FPGA Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

Stratix III FPGA Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

General User Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

User-Defined Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

User-Defined DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29

User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

General User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

HSMC User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31

7-Segment Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31

User 7-Segment Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32

Power 7-Segment Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

LCD Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

Graphics LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

Speaker Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38

Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39

USB 2.0 MAC/PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39

10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39

High-Speed Mezzanine Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–41

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

iv Contents

On-Board Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48

DDR2 SDRAM DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–49

DDR2 SDRAM Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–53

QDRII+ SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–55

P-SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–58

Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–63

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–67

Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–67

Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–68

Security Key and Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–69

Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–70

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Introduction

This document describes the hardware features of the Stratix®III development board, including detailed pin-out information to enable you to create custom FPGA designs that interface with all components of the board.

f For information about setting the Stratix III development board and using the kit’s

demo software, refer to the Stratix III Development Kit User Guide.

General Description

The Stratix III development board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs. The board provides a wide range of peripherals and memory interfaces to facilitate the design and development of Stratix III FPGA designs. Additionally, two high-speed mezzanine card (HSMC) connectors are available to add additional functionality via a variety of HSMCs available from both Altera and various partners.

1. Overview

f To see a list of the latest available HSMC cards and to request a copy of the HSMC

specification, visit www.altera.com.

Design advancements and innovations, such as Programmable Power Technology and selectable core voltage, ensure that designs implemented in Stratix III FPGAs operate faster, but consume less power than previous generation Stratix devices.

f For more information about Stratix III device Programmable Power Technology, refer

to the following documents:

■ Stratix III Programmable Power White Paper

■ PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook

With up to 7,280 KByte of enhanced TriMatrix memory and 384 embedded 18 × 18 multipliers, the on-board Stratix III device supplies internal memory while also providing I/O support for a variety of SDRAM (DDR2 or DDR3) and SRAM (QDRII or RLDRAM II) interfaces. Both DDR2 and QDRII are available on the Stratix III development board providing a high bandwidth, high-speed and low-latency solution.

The Stratix III development board is especially suitable for high-performance, logic-rich applications that require stringent signal and power integrity solutions. For example, the wireless, broadcast, and military markets require advanced signal processing techniques and very low power consumption, while also demanding flexibility and adaptability in the field.

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

1–2 Chapter 1: Overview

General Description

f For more information about:

■ External memory interfaces in Stratix III devices, refer to the External Memory

Interfaces chapter in the Stratix III Device Handbook

■ The Altera DDR and DDR2 SDRAM Controller Compiler MegaCore

function,

refer to the DDR and DDR2 SDRAM Controller Compiler User Guide

■ Power optimization, refer to AN 437: Power Optimization Techniques in Stratix III

FPGAs

■ Altera Video and Image Processing Suite MegaCore functions, refer to the

Video and Image Processing Suite User Guide

Board Component Blocks

The board features the following major component blocks:

■ 1,152-pin Altera Stratix III EP3SL150F FPGA in a ball-grid array (BGA) package

■ 142,000 logic elements (LEs)

■ 5,499 Kbits of memory

■ 384 multiplier blocks

■ Eight phase locked loops (PLLs)

■ 16 global clock networks

■ 736 user I/Os

■ 1.1-V core power

■ 256-pin Altera EPM2210GF256 CPLD in a BGA package

■ 1.8-V core power

■ On-board memory

■ 1-GByte DDR2 SDRAM DIMM

■ 72-Mbit QDRII/+ SRAM

■ 16-MByte DDR2 SDRAM devices

■ Individually addressable

■ 4-MByte SSRAM

■ 64-MByte flash memory

■ FPGA configuration circuitry

■ MAX

II CPLD and flash passive serial configuration

■ On-board USB-Blaster™ circuitry using the Quartus II Programmer

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 1: Overview 1–3

General Description

■ On-board clocking circuitry

■ Two clock oscillators to support Stratix III device user logic

■ 125 MHz

■ 50 MHz

■ SMA connector for external clock input and output

■ General user and configuration interfaces

■ LEDs/displays:

■ Eight user LEDs

■ One configuration-done LED

■ One transmit/receive LED (TX/RX) per HSMC interface

■ One HSMC-present LED per HSMC interface

■ Six Ethernet LEDs

■ User Quad 7-segment display

■ Power consumption display

■ Push-buttons:

■ User reset push-button (CPU reset)

■ Four general user push-buttons

■ System reset push-button (user configuration)

■ One factory push-button switch (factory configuration)

■ DIP switches:

■ MAX II control DIP switch

■ Eight user DIP switches

■ Speaker header

■ Displays

■ 128 × 64 graphics LCD

■ 16 × 2 line character LCD

■ Power supply

■ 14-V – 20-V DC input

■ On-board power measurement circuitry

■ Up to 20 W per HSMC interface

■ Mechanical

■ 7 in. × 8.25 in. board

■ Bench-top design

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

1–4 Chapter 1: Overview

1.5-V HSTL

Statix III

EP3SL1501152

EP3SL340H1152

125-MHz

XTAL

MAX II

Device (x16)

2.5-V CMOS

1.8-V CMOS

Power

Measure/

Display

72-Mbit QDRII/+

18/18

CMOS + LVDS

4-MB SSRAM

(x32)

64-MB Flash

(x16)

1-GByte DDR2

(x72)

USB

2.0

1.8-V SSTL

50-MHz

XTAL

1.8-V CMOS

Quad 7-Seg/

User LEDs,

Buttons,

Switches

SMA Input

1.8-V SSTL

SMA Output

10/100/1000

Ethernet

CMOS + LVDS

2.5-V CMOS

RJ45

Jack

Graphics Display

Header

14-Pin LCD

Header

16-MB

DDR2

(x8)

16-MB

DDR2

(x8)

HSMC Port B

HSMC Port A

Handling the Board

Block Diagram

Figure 1–1 shows the functional block diagram of the Stratix III development board.

Figure 1–1. Stratix III Development Board Block Diagram

Handling the Board

When handling the board, it is important to observe the following precaution:

c Static Discharge Precaution: Without proper anti-static handling, the board can be

damaged. Therefore, use anti-static handling precautions when touching the board.

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Introduction

2. Board Components

This chapter introduces the important components on the Stratix III development board. Figure 2–1 illustrates component locations and Table 2–1 describes component features.

This chapter consists of the following sections:

■ “Featured FPGA (U22)” on page 2–4

■ “MAX II CPLD” on page 2–8

■ “Configuration, Status, and Setup Elements” on page 2–17

■ “Clocking Circuitry” on page 2–25

■ “General User Interfaces” on page 2–28

■ “Components and Interfaces” on page 2–39

■ “On-Board Memory” on page 2–48

■ “Power Supply” on page 2–67

■ “Statement of China-RoHS Compliance” on page 2–70

1 A complete set of board schematics, a physical layout database, and GERBER files for

the Stratix III development board reside in the Stratix III Development Kit documents directory.

f For information about powering up the development board and installing the demo

software, refer to the Stratix III Development Kit User Guide.

Board Overview

This section provides an overview of the Stratix III development board, including an annotated board image and component descriptions.

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–2 Chapter 2: Board Components

Stratix III

FPGA (U22)

MAX II

CPLD (U5)

Device Select (J2)

Jumper

24-MHz Crystal (Y2)

6-MHz Crystal (Y3)

125-MHz MAX II Clock (Y1)

Type B USB Connector (J5)

MAX II Control DIP Switch (SW2)

Ethernet PHY LEDs (D6, D7, D8) & Duplex LED (D9)

PGM Config Select Rotary Switch (SW3)

RJ-45 Ethernet Connector (J14)

Clock In/Out SMAs (J16, J17)

Ethernet PHY TX/RX Activity LEDs (D14, D15)

Factory Configuration Push Button (S1)

Power Switch (SW4)

DC Power Jack (J21)

User Push Buttons (S2 through S5)

Reset Configuration Push Button (S7)

Configuration

Done LED (D32)

Board-Specific

LEDs (D33-D36)

User LEDs (D20 through D27)

CPU Reset

Push Button (S6)

Flash Memory Device (U9)

24-MHz Crystal (Y4)

DDR2 SDRAM (U17, U20)

DDR2 SDRAM DIMM Connector (J19)

Power Select

Rotary Switch (SW6)

Power LED (D16)

HSMC Port A (J18)

HSMC Port B (J8)

HSMC Port A

Present LED (D17)

Power Display (U27)

User DIP Switch (SW5)

HSMC Port A

TX/RX Activity

LEDs (D11, D12)

HSMC Port B

Present LED (D10)

Speaker Header (J1)

HSMC Port B

TX/RX Activity LEDs

(D2, D3)

User Display (U28)

QDRII+ SRAM (U15)

(Behind the LCD Screen)

JTAG Control DIP Switch (SW1)

MSEL0 to GND Jumper (J13)

Board Overview

Figure 2–1 shows the top view of the Stratix III development board.

Figure 2–1. Top View of the Stratix III Development Board

Tab le 2– 1 describes the components and lists their corresponding board references.

Table 2–1. Stratix III Development Board (Part 1 of 3)

Board Reference Type Description

Featured Devices

U22 FPGA EP3SL150F1152, 1152-pin BGA package.

U5 CPLD EPM2210GF256, 256-pin device in a BGA package.

Configuration Status and Setup Elements

Device select ( jumper

J5 Input

D32 Configuration done LED Green LED that illuminates when the FPGA is successfully configured.

D11, D12 (Port A)

D2, D3 (Port B)

Channel activity LEDs

J1 Header Speaker header.

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

DEV_SEL

)

Sets target device for JTAG signals when using an external USB Blaster or equivalent.

Type B USB connector that allows for connecting a Type A-B USB cable between a PC and the board.

Green LEDs that indicate the RX and TX activity on the HSMC Ports A or B.

Chapter 2: Board Components 2–3

Board Overview

Table 2–1. Stratix III Development Board (Part 2 of 3)

Board Reference Type Description

D6, D7, D8 Ethernet PHY LEDs

D9 Duplex Ethernet PHY LED

Green Ethernet PHY LEDs. Illuminate when Ethernet PHY is using the 10/100/1000 Mbps (D6, D7, D8) connection speeds.

Green Ethernet PHY LED. Illuminates when Ethernet PHY is both sending and receiving data.

D16 Power LED Blue LED indicates when power is applied to the board.

D14, D15

Ethernet PHY transmit/receive activity LEDs

SW2 MAX II Control DIP switch

SW1 JTAG control DIP switch

Green LEDs. Illuminates when transmit/receive data is active from the Ethernet PHY.

Controls various features of the MAX II device specific to the Stratix III development board.

JTAG control DIP switch used to remove or include devices in the active JTAG chain.

U27 Power display Displays power measured by the MAX II CPLD.

D11, D12

D2, D3

HSMC Port A transmit/receive activity LEDs

HSMC Port B transmit/receive activity LEDs

Illuminates when transmit/receive data is active from the HSMC Port A.

Illuminates when transmit/receive data is active from the HSMC Port B.

Clock Circuitry

Y1 125 MHz MAX II 125-MHz device clock.

Y2 24-MHz crystal Cypress USB PHY.

Y3 6-MHz crystal USB PHY FTDI reference clock.

Y4 24 MHz MAX II 24-MHz device clock.

Y5 125 MHz 125-MHz clock oscillator used for the system clock.

Y6 50 MHz 50-MHz clock oscillator used for data processing.

J16 SMA clock input SMA connector that allows the provision of an external clock input.

J17 SMA clock output SMA connector that allows the provision of an external clock output.

General User Input and Output

S2 through S5 User push-buttons Four 2.5-V push-button switches for user-defined, logic inputs.

S6 CPU reset push-button One 2.5-V push-button switch for FPGA logic and CPU reset.

S1 and S7

Reset and factory configuration push-button

Two 2.5-V push-button switches that control FPGA configuration from flash memory.

D20 through D27 User LEDs Eight user-defined LEDs.

SW3

PGM Config Select rotary switch

Rotary switch to select which FPGA configuration file is loaded from the flash device into the FPGA.

SW6 Power Select rotary switch Power rail select for on-board power monitor.

U28 User display User-defined, green 7-segment display.

SW5 User DIP switch User-defined, eight position DIP switch.

Memory

U9 Flash 512 Mbits of flash memory.

U4, U10 P-SRAM

The P-SRAM devices connect to the MAX II device as well as the flash memory device.

U17, U20 DDR2 SDRAM Two 16M × 8, 1.8-V core devices in 60-pin FBGA packages.

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–4 Chapter 2: Board Components

Featured FPGA (U22)

Table 2–1. Stratix III Development Board (Part 3 of 3)

Board Reference Type Description

U15 QDRII

J19 DDR2 SDRAM DIMM Connector for 1 GByte × 72 DDR2 SDRAM DIMM.

Components and Interfaces

U11 USB device

J14 Ethernet cable jack

J8 and J18 HSMC Port A and Port B HSMC connectors to allow for expansion via the addition of HSMCs.

Power Supply

J21 DC power jack 14–20 V DC power source.

SW4 Input Switches the board’s power on and off.

Burst-of-four, 2M × 18, 400-MHz QDRII memory interface in an FBGA package.

USB device that provides JTAG programming of on-board devices, including the Stratix III device and flash memory device.

The RJ-45 jack is for Ethernet cable connection. The connector is fed by a 10/100/1000 base T PHY device with an RGMII interface to the Stratix III device.

Featured FPGA (U22)

The Stratix III Development Kit features the EP3SL150F1152C2 device (U22) in a 1152-pin BGA package.

f For more information about Stratix III devices, refer to the Stratix III Device Handbook.

Tab le 2– 2 lists the main Stratix III EP3SL150 device features.

Table 2–2. Stratix III EP3SL150 Device Features

ALMs LEs

57 142.5 355 16 2,850 5,499 1,781 7,280 384 8

M9K

Blocks

M144K Blocks

MLAB

Blocks

Total Embedded RAM Kbits

MLAB

Kbits

Tab le 2– 3 lists the Stratix III device component reference and manufacturing

information.

Table 2–3. Stratix III Device Component Reference and Manufacturing Information

Board Reference Description Manufacturer

U22 High-speed, low-power FPGA Altera

Corporation EP3SL150F1152 www.altera.com

Total

Memory

Kbits

Manufacturing

Part Number

18 × 18 Bit Multipliers

Manufacturer

Website

PLLs

Tab le 2– 4 lists the Stratix III device EP3SL150F1152 pin count.

Table 2–4. Stratix III Device Pin Count (Part 1 of 2)

Function I/O Type I/O Count Special Pins

Oscillators and SMAs 1.8-V CMOS 4 Three clock inputs, one output

DDR2 DIMM 1.8-V SSTL 136 18 data strobe signal (DQS) pins

DDR2 devices 1.8-V SSTL 74 Four DQS pins

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–5

Bank 7A 40

Bank 7B 24

Bank 7C 32

Bank 8C 32

Bank 1A 48

Bank 1C

EP3SL150

QDR II

USER PB

1.5 V (73 pins)

2.5 V

(74 pins)

User, FLASH,

SRAM

1.8 V (98 pins)

Bank 2C 40

Bank 2A

Bank 6A

Bank 6C

Bank 5C

Bank 5A 48

Bank 8B 24

Bank 8A 40

Bank 4A 40

Bank 4B 24

Bank 4C 32

Bank 3C 32

Bank 3B 24

Bank 3A 40

LCD,

USER 7-SEG

2.5 V (35 pins)

DDR2 x 72 DIMM

1.8 V (136 pins)

HSMC A

2.5 V

(74 pins)

DDR2 x8

Devices

A & B

1.8 V

(70 pins)

2.5 V

(65 pins)

Ethernet,

Graphics LCD,

USB, Misc

HSMC B

Featured FPGA (U22)

Table 2–4. Stratix III Device Pin Count (Part 2 of 2)

Function I/O Type I/O Count Special Pins

QDRII+ 1.5-V/1.8-V HSTL 66 Two CQ pins

Flash/P-SRAM/MAX 1.8-V CMOS 79 —

Ethernet

2.5-V CMOS

2.5-V LVDS

36 6, 2.5 V LVDS

User I/O (LEDs, etc) 1.8-V/2.5 V 30 —

14-pin LCD header 2.5-V CMOS 11 —

Graphics display 2.5-V CMOS 16 —

USB 2.5-V CMOS 0 —

HSMC Port A

HSMC Port B

2.5-V CMOS

2.5-V LVDS

2.5-V CMOS

2.5-V LVDS

88 3 clock inputs

Device I/O total: 628

Stratix III device I/O total: 736

Figure 2–2 shows the EP3SL150 I/O bank diagram from a system perspective.

Figure 2–2. System I/O Bank Diagram

f For additional information about Altera devices, go to

www.altera.com/products/devices.

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–6 Chapter 2: Board Components

Featured FPGA (U22)

Device Support

Although the target FPGA for the Stratix III development board is the EP3SL150 device, which is the first device in the 65 nm Stratix III FPGA device family, the board is also designed to migrate to the Stratix III EP3SL340H1152 device.

The following list shows the main power rails for the target device:

■ 0.9-V/1.1-V V

■ 1.1-V V

■ 2.5-V V

■ 1.8-V/2.5-V/3.0-V V

■ 2.5-V/3.0-V V

■ 2.5-V V

■ 1.2-V to 3.3-V V

CCL

CCPT

CCPGM

CCPD

CCA_PLL

CC_CLKIN

CCBAT

CCIO

The board’s target device, the EP3SL150F1152C2, comprises the following:

■ 57,000 adaptive logic modules (ALMs)

■ 142,000 LEs

■ 1,775 KBytes of RAM

■ 736 user I/O

■ 8 PLLs

■ 16 global clocks

■ 384 18 × 18 multipliers in finite impulse response (FIR) mode

The board is designed to migrate to the EP3SL340H1152C3 device, which provides the following features in the H1152 package:

■ 135,000 ALMs

■ 338,000 LEs

■ 4,225 KBytes of RAM

■ 736 user I/O

■ 8 PLLs

■ 16 global clocks

■ 576 18 × 18 multipliers in FIR mode

I/O Resources

This section lists specific I/O resources available with the EP3SL150F1152 device, which is from the L family of Stratix III devices.

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–7

Bank 7A 40

Bank 7B 24

Bank 7C 32

Bank 8C 32

Bank 1A 48

Bank 1C

EP3SL150

Bank Name

Number of I/Os

Bank Name

Number of I/Os

Bank 2C 40

Bank 2A

Bank 6A

Bank 6C

Bank 5C

Bank 5A 48

Bank 8B 24

Bank 8A 40

Bank 4A 40

Bank 4B 24

Bank 4C 32

Bank 3C 32

Bank 3B 24

Bank 3A 40

Featured FPGA (U22)

Tab le 2– 3 shows the configuration of the 20 user I/O banks and each bank’s I/O count

for the EP3SL150 device. Incidentally, within the same package, the EP3SL150 and the EP3SL340 devices have the same number of PLLs, user I/O banks, and user I/Os.

Figure 2–3. EP3SL150F1152 Device I/O Bank Resources

Figure 2–4 shows the configuration of the 24 possible user I/O banks and each bank’s

I/O count for the EP3SL340 device in its largest package. Banks 1B, 2B, 5B, and 6B are not available in the F1152 package.

Figure 2–4. EP3SL340F1517 Device I/O Bank Diagram

Number of I/Os

Bank Name

Bank 7A 48

Bank 7B 48

Bank 7C 48

Bank 8C 48

Bank 8B 48

Bank 8A 48

Bank 6A

Bank 6B

Bank 5C

Bank 5C 48

Bank 5B36

Bank 5A48

Bank 4A 48

EP3SL340

Bank 4B 48

Bank 4C 48

Bank 3C 48

Bank 3B 48

Bank 1A 48

Bank 1B

Bank 1C 48

Bank 2C

Bank 2B 36

Bank 2A 48

Bank

Bank 3A 48

Name

Number of I/Os

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–8 Chapter 2: Board Components

MAX II CPLD

The board utilizes an Altera MAX II CPLD (U5) for the following purposes:

■ Power-up configuration of the FPGA from flash memory

■ Embedded USB-Blaster core for USB-based configuration of the FPGA

■ Power consumption monitoring and display

Additionally, the MAX II device is also used to help dual-footprint the FTDI USB device and Cypress USB device. Each device has a shared path between the USB device and the MAX II CPLD. This path then drives to the FPGA separately.

Figure 2–5 illustrates the MAX II device’s functional block diagram.

Figure 2–5. MAX II Device’s Block Diagram

Power Display

JTAG

Header

To FPGA

64-MB

Flash (x16)

8-MB

SRAM (x32)

Stratix III

Device

125 MHz

1.8-V CMOS FSM Bus

24 MHz

PS Config

JTAG Config

USB Data Bus

PGM_CONFIG_SEL

PWR_SEL

Tab le 2– 5 lists the I/O signals present on the MAX II CPLD. The signal names and

functions are relative to the MAX II device (U5).

Table 2–5. MAX II Device Pin-out (Part 1 of 9)

Power

Measure

2.5-V CMOS

MAX II CPLD

CPU_RESET

2.5-V CMOS

RESET_CONFIG

2.5-V CMOS

1.8-V CMOS

FACTORY_CONFIG

Cypress 480 Mb/s

USB (x16)

FTDI

12 Mb/s USB (x8)

MAX II Device

Control DIP Switch

JTAG Control

DIP Switch

Config Status

LEDs

MAX II

Pin Number

Description Schematic Signal Name

Address bus shared with flash and P-SRAM bit 0

Address bus shared with flash and P-SRAM bit 1

Address bus shared with flash and P-SRAM bit 2

FSM_A0

FSM_A1

FSM_A2

I/O

Standard

1.8 V F22 U9 pin A1

1.8 V H23

1.8 V G23

Stratix III

Number

Other Connections

U9 pin B1 and U4 pin A3 and U10 pin A3

U9 pin C1 and U4 pin A4 and U10 pin A4

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–9

MAX II CPLD

Table 2–5. MAX II Device Pin-out (Part 2 of 9)

MAX II

Pin Number

T10

P13

R10

M10

T11

N10

R11

P10

T12

M11

R12

N11

T13

P11

R13

M12

R14

N12

Description Schematic Signal Name

Address bus shared with flash and P-SRAM bit 3

Address bus shared with flash and P-SRAM bit 4

Address bus shared with flash and P-SRAM bit 5

Address bus shared with flash and P-SRAM bit 6

Address bus shared with flash and P-SRAM bit 7

Address bus shared with flash and P-SRAM bit 8

Address bus shared with flash and P-SRAM bit 9

Address bus shared with flash and P-SRAM bit 10

Address bus shared with flash and P-SRAM bit 11

Address bus shared with flash and P-SRAM bit 12

Address bus shared with flash and P-SRAM bit 13

Address bus shared with flash and P-SRAM bit 14

Address bus shared with flash and P-SRAM bit 15

Address bus shared with flash and P-SRAM bit 16

Address bus shared with flash and P-SRAM bit 17

Address bus shared with flash and P-SRAM bit 18

Address bus shared with flash and P-SRAM bit 19.

Address bus shared with flash and P-SRAM bit 20

Address bus shared with flash and P-SRAM bit 21

Address bus shared with flash and P-SRAM bit 22

FSM_A3

FSM_A4

FSM_A5

FSM_A6

FSM_A7

FSM_A8

FSM_A9

FSM_A10

FSM_A11

FSM_A12

FSM_A13

FSM_A14

FSM_A15

FSM_A16

FSM_A17

FSM_A18

FSM_A19

FSM_A20

FSM_A21

FSM_A22

I/O

Standard

Stratix III

Number

Other Connections

U9 pin D1 and U4

1.8 V F23

pin A5 and U10 pin A5

U9 pin D2 and U4

1.8 V D27

pin B3 and U10 pin B3

1.8 V D28

1.8 V F25

1.8 V F26

1.8 V G24

1.8 V F24

1.8 V E26

1.8 V D26

1.8 V A30

1.8 V A33

1.8 V B31

U9 pin A2 and U4 pin B4 and U10 pin B4

U9 pin C2 and U4 pin C3 and U10 pin C3

U9 pin A3 and U4 pin C4 and U10 pin C4

U9 pin B3 and U4 pin D4 and U10 pin D4

U9 pin C3 and U4 pin H2 and U10 pin H2

U9 pin C4 and U4 pin H3 and U10 pin H3

U9 pin C4 and U4 pin H4 and U10 pin H4

U9 pi A12 and U4 pin H5 and U10 pin H5

U9 pin B5 and U4 pin G3 and U10 pin G3

U9 pin C5 and U4 pin G4 and U10 pin G4

U9 pin D7 and U4

1.8 V A31

pin F3 and U10 pin F3

U9 pin D8 and U4

1.8 V B32

pin F4 and U10 pin F4

1.8 V A32

1.8 V M23

1.8 V L23

1.8 V B29

1.8 V C29

U9 pin A7 and U4 pin E4 and U10 pin E4

U9 pin B7 and U4 pin D3 and U10 pin D3

U9 pin C7 and U4 pin H1 and U10 pin H1

U9 pin C8 and U4 pin G2 and U10 pin G2

U9 pin A8 and U4 pin H6 and U10 pin H6

1.8 V C31 U9 pin G1

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–10 Chapter 2: Board Components

MAX II CPLD

Table 2–5. MAX II Device Pin-out (Part 3 of 9)

MAX II

Pin Number

T15

P12

P14

Description Schematic Signal Name

Address bus shared with flash and P-SRAM bit 23

Address bus shared with flash and P-SRAM bit 24

Data bus shared with flash and SRAM bit 0

Data bus shared with flash and SRAM bit 1

Data bus shared with flash and SRAM bit 2

Data bus shared with flash and SRAM bit 3

Data bus shared with flash and SRAM bit 4

Data bus shared with flash and SRAM bit 5

Data bus shared with flash and SRAM bit 6

Data bus shared with flash and SRAM bit 7

Data bus shared with flash and SRAM bit 8

Data bus shared with flash and SRAM bit 9

Data bus shared with flash and SRAM bit 10

Data bus shared with flash and SRAM bit 11

Data bus shared with flash and SRAM bit 12

Data bus shared with flash and SRAM bit 13

Data bus shared with flash and SRAM bit 14

Data bus shared with flash and SRAM bit 15

Data bus shared with flash and SRAM bit 16

Data bus shared with flash and SRAM bit 17

Data bus shared with flash and SRAM bit 18

Data bus shared with flash and SRAM bit 19

FSM_A23

FSM_A24

FSM_D0

FSM_D1

FSM_D2

FSM_D3

FSM_D4

FSM_D5

FSM_D6

FSM_D7

FSM_D8

FSM_D9

FSM_D10

FSM_D11

FSM_D12

FSM_D13

FSM_D14

FSM_D15

FSM_D16

FSM_D17

FSM_D18

FSM_D19

I/O

Standard

Stratix III

Number

Other Connections

1.8 V D31 U9 pin H8

1.8 V F27 U9 pin B6

1.8 V G27

1.8 V F28

1.8 V E28

1.8 V D30

1.8 V C30

1.8 V F29

1.8 V E29

1.8 V J24

1.8 V J25

1.8 V A24

1.8 V A26

1.8 V B25

1.8 V A25

1.8 V J20

1.8 V K20

1.8 V K21

U9 pin F2 and U4 pin B6

U9 pin E2 and U4 pin C5

U9 pin G3 and U4 pin C6

U9 pin E4 and U4 pin D5

U9 pin E5 and U4 pin E5

U9 pin G5 and U4 pin F5

U9 pin G6 and U4 pin F6

U9 pin H7 and U4 pin G6

U9 pin E1 and U4 pin B1

U9 pin E3 and U4 pin C1

U9 pin F3 and U4 pin C2

U9 pin F4 and U4 pin D2

U9 pin F5 and U4 pin E2

U9 pin H5 and U4 pin F2

U9 pin G7 and U4 pin F1

U9 pin E7 and U4 pin G1

1.8 V K22 U10 pin B6

1.8 V C26 U10 pin C5

1.8 V B26 U10 pin C6

1.8 V J22 U10 pin D5

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–11

MAX II CPLD

Table 2–5. MAX II Device Pin-out (Part 4 of 9)

MAX II

Pin Number

F12

D16

F13

D15

F14

D14

E12

C15

Data bus shared with flash and SRAM bit 20

Data bus shared with flash and SRAM bit 21

Data bus shared with flash and SRAM bit 22

Data bus shared with flash and SRAM bit 23

Data bus shared with flash and SRAM bit 24

Data bus shared with flash and SRAM bit 25

Data bus shared with flash and SRAM bit 26

Data bus shared with flash and SRAM bit 27

Data bus shared with flash and SRAM bit 28

Data bus shared with flash and SRAM bit 29

Data bus shared with flash and SRAM bit 30

Data bus shared with flash and SRAM bit 31

Description Schematic Signal Name

L13 Flash address valid

K14 Flash chip enable

L15 Flash clock

M16 Flash output enable

L11 Flash ready/busy

M15 Flash reset

L12 Flash write enable

N13 Flash page select

P15 Flash page select

M14 Flash page select

N16 Flash page select

D3 FPGA configuration complete

D3 FPP configuration data bus bit 0

K4 FPP configuration data bus bit 1

M2 FPP configuration data bus bit 2

K3 FPP configuration data bus bit 3

M2 FPP configuration data bus bit 4

FSM_D20

FSM_D21

FSM_D22

FSM_D23

FSM_D24

FSM_D25

FSM_D26

FSM_D27

FSM_D28

FSM_D29

FSM_D30

FSM_D31

FLASH_ADVn

FLASH_CEn

FLASH_CLK

FLASH_OEn

FLASH_RDYBSYn

FLASH_RESETn

FLASH_WEn

PGM0

PGM1

PGM2

PGM3

FPGA_CONF_DONE

FPGA_DATA0

FPGA_DATA1

FPGA_DATA2

FPGA_DATA3

FPGA_DATA4

I/O

Standard

Stratix III

Number

Other Connections

1.8 V J21 U10 pin E5

1.8 V C24 U10 pin F5

1.8 V E25 U10 pin F6

1.8 V D25 U10 pin G6

1.8 V D24 U10 pin B1

1.8 V A27 U10 pin C1

1.8 V A29 U10 pin C2

1.8 V C27 U10 pin D2

1.8 V C28 U10 pin E2

1.8 V E23 U10 pin F2

1.8 V D23 U10 pin F1

1.8 V B28 U10 pin G1

1.8 V C7 U9 pin F6

1.8 V K25 U9 pin B4

1.8 V K24 U9 pin E6

1.8 V K23 U9 pin F8

1.8 V L16 U9 pin F7

1.8 V E13 U9 pin D4

1.8 V L22 U9 pin G8

1.8 V — SW3 pin 1

1.8 V — SW3 pin 2

1.8 V — SW3 pin 4

1.8 V — SW3 pin 8

2.5 V AH29 —

2.5 V T28 —

2.5 V T27 —

2.5 V R34 —

2.5 V R33 —

2.5 V T25 —

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–12 Chapter 2: Board Components

MAX II CPLD

Table 2–5. MAX II Device Pin-out (Part 5 of 9)

MAX II

Pin Number

Description Schematic Signal Name

L5 FPP configuration data bus bit 5

M3 FPP configuration data bus bit 6

L4 FPP configuration data bus bit 7

C2 FPP configuration clock

E4 FPGA configuration start

C3 FPGA configuration status

E10 USB command/data select

B10

J14

A11

L16

USB empty from MAX II device to Stratix III device

USB data from MAX II to Stratix III bit 0

USB data from MAX II to Stratix III bit 1

USB data from MAX II to Stratix III bit 2

USB data from MAX II to Stratix III bit 3

USB data from MAX II to Stratix III bit 4

USB data from MAX II to Stratix III bit 5

USB data from MAX II to Stratix III bit 6

USB data from MAX II to Stratix III bit 7

USB full from MAX II to Stratix III device

USB clock from MAX II to Stratix III device

USB read enable from MAX II to Stratix III device

USB write enable from MAX II to Stratix III device

Cypress USB pin multiplexed for I/O or FIFO select

Cypress USB pin multiplexed for I/O or FIFO packet commit

Cypress USB pin multiplexed for I/O or gate for other FIFO slaves

C13 Cypress/FTDI USB data bus bit 0

B16 Cypress/FTDI USB data bus bit 1

FPGA_DATA5

FPGA_DATA6

FPGA_DATA7

FPGA_DCLK

FPGA_NCONFIG

FPGA_NSTATUS

USB_CMD_DATA

USB_EMPTY

USB_FD0

USB_FD1

USB_FD2

USB_FD3

USB_FD4

USB_FD5

USB_FD6

USB_FD7

USB_FULL

USB_IFCLK

USB_REN

USB_WEN

USB_PA5_IF0ADR1

USB_PA6_PKTEND

USB_PA7_SLCSn

USB_PHY_FD0

USB_PHY_FD1

I/O

Standard

Stratix III

Number

Other Connections

2.5 V T24 —

2.5 V T32 —

2.5 V R31 —

2.5 V AL3 —

2.5 V AE25 —

2.5 V AH28 —

2.5 V Y28 —

2.5 V AH12 —

2.5 V AE33 —

2.5 V AE31 —

2.5 V AC28 —

2.5 V AA24 —

2.5 V AF34 —

2.5 V AG33 —

2.5 V AA25 —

2.5 V AE32 —

2.5 V AE11 —

2.5 V U1 —

2.5 V N5 —

2.5 V W11 —

2.5 V — U12 pin 38

2.5 V — U12 pin 39

2.5 V — U12 pin 40

2.5 V —

U12 pin 18 and U11 pin 25

U12 pin 19 and U11 pin 24

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–13

MAX II CPLD

Table 2–5. MAX II Device Pin-out (Part 6 of 9)

MAX II

Pin Number

Description Schematic Signal Name

C12 Cypress/FTDI USB data bus bit 2

A15 Cypress/FTDI USB data bus bit 3

D12 Cypress/FTDI USB data bus bit 4

B14 Cypress/FTDI USB data bus bit 5

C11 Cypress/FTDI USB data bus bit 6

B13 Cypress/FTDI USB data bus bit 7

D11 Cypress USB data bus bit 8

A13 Cypress USB data bus bit 9

E11 Cypress USB data bus bit 10

B12 Cypress USB data bus bit 11

C10 Cypress USB data bus bit 12

A12 Cypress USB data bus bit 13

D10 Cypress USB data bus bit 14

B11 Cypress USB data bus bit 15

C7 Cypress USB clock

Cypress USB command/data select

E6 Cypress USB read enable

B4 Cypress USB write enable

D6 Cypress USB empty

C4 Cypress USB full

C6 Cypress USB reset

B3 Cypress USB clock out

C5 Cypress USB wake up

Cypress USB pin multiplexed for I/O or FIFO select

Cypress USB pin multiplexed for I/O or 8051 interrupt

Cypress USB pin multiplexed for

I/O or output enable for the slave FIFOs.

Cypress USB pin multiplexed for I/O or alternate wake up signal

USB_PHY_FD2

USB_PHY_FD3

USB_PHY_FD4

USB_PHY_FD5

USB_PHY_FD6

USB_PHY_FD7

USB_PHY_FD8

USB_PHY_FD9

USB_PHY_FD10

USB_PHY_FD11

USB_PHY_FD12

USB_PHY_FD13

USB_PHY_FD14

USB_PHY_FD15

USB_PHY_IFCLK

USB_PHY_CMD_DATA

USB_PHY_REN

USB_PHY_WEN

USB_PHY_EMPTY

USB_PHY_FULL

USB_RESETn

USB_CLKOUT

USB_WAKEUP

USB_PA4_IF0ADR0

USB_PA0_INT0n

USB_PA1_INT1n

USB_PA2_SLOE

USB_PA3_WU2

I/O

Standard

2.5 V —

Stratix III

Number

Other Connections

U12 pin 20 and U11 pin 23

U12 pin 21 and U11 pin 22

U12 pin 22 and U11 pin 21

U12 pin 23 and U11 pin 20

U12 pin 24 and U11 pin 19

U12 pin 25 and U11 pin 18

2.5 V — U12 pin 45

2.5 V — U12 pin 46

2.5 V — U12 pin 47

2.5 V — U12 pin 48

2.5 V — U12 pin 49

2.5 V — U12 pin 50

2.5 V — U12 pin 51

2.5 V — U12 pin 52

2.5 V — R89

2.5 V — U12 pin 29

2.5 V — U12 pin 30

2.5 V — U12 pin 31

2.5 V — U12 pin 1

2.5 V — U12 pin 29

2.5 V — U12 pin 41

2.5 V — U12 pin 54

2.5 V — U12 pin 44

2.5 V — U12 pin 37

2.5 V —

U12 pin 33 and U11 pin 14

U12 pin 34 and U11 pin 12

2.5 V — U12 pin 35

2.5 V —

U12 pin 36 and U11 pin 11

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–14 Chapter 2: Board Components

MAX II CPLD

Table 2–5. MAX II Device Pin-out (Part 7 of 9)

MAX II

Pin Number

Description Schematic Signal Name

C8 FTDI USB read enable

A6 FTDI USB write enable

A5 FTDI USB reset

D7 FTDI USB reset output

K12 FTDI USB power enable

E10

MAX II output to power seven segment display

MAX II output to power 7-segment display

Chip select to the power monitor A/D

Clock to/from the power monitor A/D

Data from the power monitor A/D

Data to the power monitor multiplexer

Frame synchronization signal to the power monitor multiplexer

J16 Power selection input

J13 Power selection input

USB_RDn

USB_WR

USB_RSTn

USB_RSTOUTn

USB_PWR_ENn

PWR_SEG_A

PWR_SEG_B

PWR_SEG_C

PWR_SEG_D

PWR_SEG_E

PWR_SEG_F

PWR_SEG_G

PWR_SEG_DP

PWR_SEG_MINUS

PWR_DIG_SEL1

PWR_DIG_SEL2

PWR_DIG_SEL3

PWR_DIG_SEL4

PMON_CSN

PMON_CLK

PMON_SDI

PMON_DATA

PMON_SYNC

PWR_SEL0

PWR_SEL1

I/O

Standard

Stratix III

Number

Other Connections

2.5 V — U11 pin 16

2.5 V — U11 pin 15

2.5 V — U11 pin 4

2.5 V — U11 pin 5

1.8 V — U11 pin 10

2.5 V — U27 pin 12

2.5 V — U27 pin 11

2.5 V — U27 pin 3

2.5 V — U27 pin 8

2.5 V — U27 pin 2

2.5 V — U27 pin 9

2.5 V — U27 pin 7

2.5 V — U27 pin 5

2.5 V — U27 pin 13

2.5 V — U27 pin 1

2.5 V — U27 pin 10

2.5 V — U27 pin 4

2.5 V — U27 pin 6

2.5 V — U18 pin 7

2.5 V —

U18 pin 9 and U19, pin 19

2.5 V — U18 pin 8

2.5 V — U19 pin 19

2.5 V — U19 pin 17

1.8 V — SW6 pin P1

1.8 V — SW6 pin P2

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–15

MAX II CPLD

Table 2–5. MAX II Device Pin-out (Part 8 of 9)

MAX II

Pin Number

Description Schematic Signal Name

H16 Power selection input

H13 Power selection input

M4 JTAG master data input signal

N2 JTAG master data output

L16 MAX II chip select

P3 JTAG clock

N4 JTAG mode select

K15 MAX II write enable

K13 MAX II output enable

H1 Connected to Stratix III device

G4 N/A

G1 N/A

G5 N/A

H2 N/A

Synchronous clock for switching regulators

N3 JTAG clock

P2 JTAG mode select

L6 JTAG data input

M5 JTAG data output

Push-button that re-loads the

A10

factory default image into the Stratix III device

B9 JTAG input to HSMC B

D9 JTAG input to HSMC A

C8 FTDI USB read enable

A6 FTDI USB write enable

A5 FTDI USB reset

D7 FTDI USB reset output

K12 FTDI USB power enable

J12 24 MHz clock input

H12 125 MHz clock input

PWR_SEL2

PWR_SEL3

FPGA_JTAG_TDI

FPGA_JTAG_TDO

MAX_CSn

MAX_JTAG_TCK

MAX_JTAG_TMS

MAX_WEn

MAX_OEn

MAX_TO_STRATIX3

MAXGP_JTAG_TCK

MAXGP_JTAG_TDI

MAXGP_JTAG_TDO

MAXGP_JTAG_TMS

LT4601_CLK0

LT4601_CLK90

LT4601_CLK180

FPGA_JTAG_TCK

FPGA_JTAG_TMS

MAX_JTAG_TDI

MAX_JTAG_TDO

FACTORY_CONFIGn

HSMB_JTAG_TDI

HSMA_JTAG_TDI

USB_RDn

USB_WR

USB_RSTn

USB_RSTOUTn

USB_PWR_ENn

CLKIN_24

CLKIN_MAX_125

I/O

Standard

Stratix III

Number

Other Connections

1.8 V — SW6 pin P4

1.8 V — SW6 pin P8

2.5 V G28 U2 pin 13

2.5 V G29 U2 pin 10

1.8 V C20 —

2.5 V F30

U3 pin 2 and U2 pin 2

2.5 V — U3 pin 5, U2 pin 5

1.8 V G21 —

1.8 V D20 —

2.5 V K1 —

2.5 V — U3 pin 3

2.5 V — U3 pin 13

2.5 V — U3 pin 10

2.5 V — U3 pin 6

2.5 V — U32 pin A8

2.5 V — U33 pin A8

2.5 V — U34 pin A8

2.5 V F30

2.5 V H28

2.5 V —

J18 pin 35 and J8 pin 35 and U2 pin 3

J18 pin 36 and J8 pin 36 and U2 pin 6

U3 pin 14 and U2 pin 14

U3 pin 11 and U2 pin 11

2.5 V — S1

2.5 V — J8 pin 38

2.5 V — J18 pin 38

2.5 V — U11 pin 16

2.5 V — U11 pin 15

2.5 V — U11 pin 4

2.5 V — U11 pin 5

1.8 V — U11 pin 10

1.8 V — Y4 pin 3

1.8 V — Y1 pin 4

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–16 Chapter 2: Board Components

MAX II CPLD

Table 2–5. MAX II Device Pin-out (Part 9 of 9)

MAX II

Pin Number

Description Schematic Signal Name

G15 JTAG output from HSMC A

F15 JTAG output from HSMC B

F16 HSMC A present

G13 HSMC B present

G14 JTAG control signal

E16 JTAG control signal

F11 JTAG control signal

C14 JTAG control signal

M9 MAX II reset

M8 MAX II enable

H15 MAX II status signal

H14 MAX II status signal

G16 MAX II status signal

G12 MAX II status signal

E15 MAX II status signal

E13 MAX II status signal

E14 Control signal

D13 Control signal

R16 Control signal

N14 PFL enable

M13 N/A

N15 N/A

L14 N/A

K16 N/A

J15 N/A

E7 N/A

N1 N/A

L3 N/A

HSMA_JTAG_TDO

HSMB_JTAG_TDO

HSMA_PSNTn

HSMB_PSNTn

FPGA_BYPASS

HSMA_BYPASS

HSMB_BYPASS

JTAG_SEL

CPU_RESETn

MAX_EN

MAX_ERROR

MAX_LOAD

MAX_FACTORY

MAX_USER

MAX_EMB

DEV_SEL

MWATTS_MAMPS

VOLTS_WATTS

RESET_CONFIGn

MAX_DIP0

MAX_DIP1

MAX_DIP2

MAX_DIP3

MAX_RESERVE0

MAX_RESERVE1

OVERTEMPn

TSENSE_SMB_DATA

TSENSE_SMB_CLK

I/O

Standard

Stratix III

Number

Other Connections

1.8 V — J18 pin 37

1.8 V — J8 pin 37

1.8 V — J18 pin 160

1.8 V — J8 pin 160

1.8 V — SW1 pin 8

1.8 V — SW1 pin 7

1.8 V — SW1 pin 6

1.8 V — U3 pin 1 and J3 pin 1

1.8 V AP5 S6

1.8 V — SW1 pin 5

1.8 V — D34

1.8 V — D33

1.8 V — D36

1.8 V — D35

1.8 V — D1

1.8 V — U2 pin 1 and J2 pin 1

1.8 V — SW2 pin 1

1.8 V — SW2 pin 2

1.8 V — S7

1.8 V — SW2 pin 5

1.8 V — SW2 pin 6

1.8 V — SW2 pin 7

1.8 V — SW2 pin 8

1.8 V — SW2 pin 3

1.8 V — SW2 pin 4

2.5 V — J7 pin 2

2.5 V — U16 pin 7

2.5 V — U16 pin 6

Table 2–6 lists the MAX II component reference and manufacturing information.

Table 2–6. MAX II Component Reference and Manufacturing Information

Board Reference Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

U5 256-pin device in a BGA package Altera Corporation EPM2210GF256C3N www.altera.com

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–17

Configuration, Status, and Setup Elements

This section describes the board’s configuration, status, and setup elements, and is divided into the following groups:

■ “Configuration” on page 2–17

■ FPGA programming over USB

■ FPGA programming from flash memory

■ Flash programming over USB

■ “Status Elements” on page 2–19

■ Board-specific LEDs

■ Power display

■ “Setup Elements” on page 2–21

■ JTAG control DIP switch

■ MAX II device control DIP switch

■ System reset and configuration push-button switches

■ Power Select rotary switch

■ PGM Config Select rotary switch

Configuration

This section discusses FPGA, flash memory, and MAX II device programming methods supported by the Stratix III development board.

FPGA Programming Over USB

You can configure the FPGA at any time the board is powered on using the USB 2.0 interface and the Quartus II Programmer in JTAG mode.

The JTAG chain is mastered by the embedded USB-Blaster function found in the MAX II device. Only a USB cable is needed to program the Stratix III FPGA. Any device can be bypassed by using the appropriate switch on the JTAG control DIP switch.

1 Board reference SW1 position 4 (SW1.4), labeled

for this feature to work properly.

For more information about:

■ Advanced JTAG settings, refer to Table 2–7.

MAX_ENABLE

must be in the 0 position

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–18 Chapter 2: Board Components

Configuration, Status, and Setup Elements

■ The JTAG control switch, refer to “JTAG Control DIP Switch” on page 2–21.

Figure 2–6. JTAG Chain with the MAX II Device and the Stratix III Device

(2.5V)

TCK TMS

USB 2.0

JTAG

Header

JTAG Control

DIP Switch

TCK TMS TDO TDI

Jumper

FPGA_Bypass HSMA_Bypass HSMA_Bypass MAX_EN

DEV_SEL

GPIO Pins

TCK TMS TDI TDO

GPIO Pins

MAX II

CPLD

GPIO Pins

TDI TDO

TCK TMS TDI TDO

PSNTn

TCK TMS TDI TDO

PSNTn

FPGA

(2.5V)

HSMC

HSMC Port A

Port A

(2.5V)

HSMC Port B

You can use the JTAG header can be used with an external USB-Blaster cable, or equivalent, to program either the MAX II CPLD or the Stratix III FPGA. Most users of the Stratix III development board do not use the JTAG header at all and instead use a USB cable along with the embedded USB-Blaster. Using an external USB-Blaster with the JTAG header requires disabling the embedded USB-Blaster function. See

Tab le 2– 7.

1 If complete repower is required, unplug and replug the USB cable into board

reference J5.

Table 2–7. JTAG Settings

Number Description

Notes to Table 2–7:

(1) The nomenclature SW1.1 indicates board reference SW1, position 1. (2) Requires USB cable plugged into board reference J5. (3) Board reference SW2.5 might need to be set to off (0) for the embedded USB-Blaster to program the Stratix III FPGA. (4) Requires external USB-Blaster or equivalent plugged into board reference J23 (PCB bottom). (5) “1” indicates the PFL is enabled and “0” indicates the PFL is disabled.

Embedded USB Blaster Stratix III target device only

Embedded USB Blaster Stratix III device + HSMC Port A

Embedded USB Blaster Stratix III device + HSMC Port B

External USB Blaster Stratix III target device only

External USB Blaster MAX II target device only

(1)

FPGA

Bypass

(SW1.1)

(2), (3)

HSMA

Bypass

(SW1.2)

HSMB

Bypass

(SW1.3)

MAX

Enable

(SW1.4)

10001 X

(2), (3)

11001 X

(2), (3)

10101 X

(4)

XXX11 Off

(4)

XXXXX On

PFL

Enable

(SW2.5)

(5)

Device

Select

(DEV_SEL)

Jumper, J2

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–19

Configuration, Status, and Setup Elements

FPGA Programming from Flash Memory

On power-up or after pressing the RESET_CONFIG or FACTORY_CONFIG push-button switch, the MAX II CPLD device’s parallel flash loader (PFL) megafunction configures the Stratix III FPGA from flash memory.

The PFL megafunction reads 16-bit data from the flash memory and converts it to passive serial format. The data is written to the Stratix III device’s dedicated

configuration pins at 12 MHz.

You can source the FPGA configuration from flash memory from one of eight images. The image is selected by the PGM Config Select rotary switch, board reference SW3. The rotary switch has 16 positions, but only the first eight are used. The positions correspond to an offset in flash memory where the PFL is directed to for FPGA configuration data.

DCLK

and

1 Board reference SW1 position 4 (SW1.4), labeled

(off) to enable the configuring from flash memory feature.

Flash Programming over USB Interface

You can program the flash memory at any time the board is powered up using the USB 2.0 interface and the Quartus II Programmer’s JTAG mode.

The development kit implements the Altera PFL megafunction for flash programming. The PFL is a block of logic that is programmed into an Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for writing to a compatible flash device. The development kit ships with a pre-built PFL design called stratixIII_3sl150_dev_pfl. The PFL design is programmed onto the FPGA whenever the flash is to be written using the Quartus II software.

f For more information about:

■ The PFL megafunction, refer to AN 386: Using the Parallel Flash Loader with the

Quartus II Software.

■ Basic flash programming instructions for the development board, refer to

Appendix A: Programming the Flash Device in the Stratix III Development Kit User

Guide.

Status Elements

MAX_ENABLE

, must be in the 0 position

The development board includes general user, board specific, and HSMC user-defined LEDs. This section discusses board-specific LEDs as well as the power display device. For information about general and HSMC user-defined LEDS, refer to

“User-Defined LEDs” on page 2–30.

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–20 Chapter 2: Board Components

Configuration, Status, and Setup Elements

Board Specific LEDs

There are 18 board-specific, factory-designated LEDs. Table 2–8 lists the LED board references, names, and descriptions.

Table 2–8. Board-Specific LEDs

Board

Reference

D16 Power

LED Name Description

Illuminates when board power switch SW4 is on.

(Requires 14 V to 20 V input to DC input jack J2)

D32 CONF DONE Illuminates when FPGA is successfully configured. Driven by Stratix III FPGA.

D33 Loading

D34 Error

D36 Factory

D35 User

D14 ENET TX

D15 ENET RX

D6 10 MBytes

D7 100 MBytes

D8 1000 MBytes

D9 Duplex

D17

D10

HSMC Port A

present

HSMC Port B

present

D2 HSMC Port B TX

Illuminates when MAX II CPLD is actively configuring the FPGA. Driven by the MAX II CPLD.

Illuminates when MAX II CPLD fails to successfully configure the FPGA. Driven by the MAX II CPLD.

Illuminates when FPGA is configured with the default factory FPGA design. Driven by the MAX II CPLD.

Illuminates when FPGA is configured with a design other than the default factory FPGA design. Driven by the MAX II CPLD.

Illuminates when transmit data is active from the Ethernet PHY. Driven by the Marvell 88E1111 PHY.

Illuminates when receive data is active from the Ethernet PHY. Driven by the Marvell 88E1111 PHY.

Illuminates when Ethernet PHY is using the 10-Mbps connection speed. Driven by the Marvell 88E1111 PHY.

Illuminates when Ethernet PHY is using the 100-Mbps connection speed. Driven by the Marvell 88E1111 PHY.

Illuminates when Ethernet PHY is using the 1000-Mbps connection speed. Driven by the Marvell 88E1111 PHY. Also connects to Stratix III FPGA.

Illuminates when Ethernet PHY is both sending and receiving data. Driven by the Marvell 88E1111 PHY.

Illuminates when HSMC Port A has a board or cable attached that grounds pin 160.

Illuminates when HSMC Port B has a board or cable attached that grounds pin 160.

Illuminates when transmit data is active from the HSMC. Driven by the Stratix III device.

D3 HSMC Port B RX Illuminates when receive data is active from the HSMC. Driven by the Stratix III device.

D11 HSMC Port A TX

Illuminates when transmit data is active from the HSMC. Driven by the Stratix III device.

D12 HSMC Port A RX Illuminates when receive data is active from the HSMC. Driven by the Stratix III device.

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–21

Configuration, Status, and Setup Elements

Tab le 2– 9 lists the board-specific LEDs component reference and manufacturing

information.

Table 2–9. Board-Specific LEDs Component Reference and Manufacturing Information

Board Reference Description Manufacturer

D2, D3, D6 – D12, D14, D15, D17, D32, D33, D35, D36

D16

D34

Green LED, 1206, SMT, clear lens,

2.1 V

Blue LED, 1206, SMT, clear lens,

3.5 V

Red LED, 1206, SMT, clear lens,

2.0 V

Lumex, Inc. SML-LX1206GC-TR www.lumex.com

Lumex, Inc. SML-LX1206USBC-TR www.lumex.com

Lumex, Inc. SML-LX1206IC-TR www.lumex.com

Power Display

The power being measured by the MAX II CPLD and associated A/D is displayed on a dedicated 7-segment display connected to the MAX II device called Power Display.

Setup Elements

The development board includes user, JTAG control, and board-specific DIP switches; system reset and configuration push-button switches; and rotary switches. This section discusses the following items:

■ JTAG control DIP switch

■ MAX II device control DIP switch

Manufacturing

Part Number

Manufacturer

Website

■ System reset and configuration push-buttons

■ Power Select rotary switch

■ PGM Config Select rotary switch

JTAG Control DIP Switch

Board reference SW1 is a four-position JTAG control DIP switch, provided to either remove or include devices in the active JTAG chain. Additionally, the JTAG control DIP switch is also used to disable the embedded USB-Blaster cable when using an external USB-Blaster cable. Tab le 2– 10 lists the switch position, name, and description.

Table 2–10. JTAG Control DIP Switch Signal Names and Descriptions (Part 1 of 2)

DIP Switch Signal Name Description

FPGA_BYPASS

HSMA_BYPASS

1 = FPGA in JTAG chain

0 = FPGA not in JTAG chain

1 = HSMC Port A in JTAG chain (only if installed)

0 = HSMC Port A not in JTAG chain

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–22 Chapter 2: Board Components

Configuration, Status, and Setup Elements

Table 2–10. JTAG Control DIP Switch Signal Names and Descriptions (Part 2 of 2)

DIP Switch Signal Name Description

3 HSMB_BYPASS

MAX_ENABLE

1 = HSMC Port B in JTAG chain (only if installed)

0 = HSMC Port B not in JTAG chain

1 = MAX II device disabled

0 = MAX II device enabled

Because the JTAG chain also contains the two HSMC interface connectors, the SW1 DIP switch allows data to bypass the HSMC interfaces as well as the MAX II CPLD. See “FPGA Programming Over USB” on page 2–17. For information about user-defined DIP switches, refer to “User-Defined DIP Switches” on page 2–29.

Tab le 2– 11 lists the JTAG control switch component reference and manufacturing

information.

Table 2–11. JTAG Control Switch Component Reference and Manufacturing Information

Board

Reference

SW1 Four-position slider DIP switch C&K Components ITT Industries TDA04H0SB1

Description Manufacturer

Manufacturing

Part Number

MAX II Device Control DIP Switch

Board reference SW2 is the MAX II device control DIP switch, which controls various features specific to the Stratix III development board. Table 2–12 lists the switch position, name, and description.

Table 2–12. MAX II Device Control DIP Switch Position, Name, and Description

Switch Name Description

MAX_DIP3

MAX_DIP2

MAX_DIP1

MAX_DIP0

RESERVE1

RESERVE0

VOLTS_WATTS

MWATTS_MAMPS

Reserved

1 = MAX II device PFL enabled, 0 = MAX II device PFL disabled

Reserved

1 = power display shows mW/mA, 0 = power display shows voltage

1 = power display shows mA, 0 = power display shows mW

Tab le 2– 13 lists the MAX II device control DIP switch component reference and

manufacturing information.

Table 2–13. MAX II Device Control DIP Switch Component Reference and Manufacturing Information

Board Reference Description Manufacturer

SW2 8-position rocker DIP switch Grayhill Corporation 76SB08ST www.grayhill.com

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Manufacturing

Part Number

Manufacturer

Website

Chapter 2: Board Components 2–23

Configuration, Status, and Setup Elements

System Reset and Configuration Switches

Board reference S7 is the system reset push-button switch, input to the MAX II device. This switch forces a reconfiguration of the FPGA from flash memory. The location in flash memory is based on the input from the PGM Config Select rotary switch position for the signals the

RESET_CONFIGn

pin as its reset along with the

PGM [2:0]

CPU_RESET

RESET_CONFIG

, which is an

. The MAX II device uses

pin push-button.

Board reference S6 is the CPU reset push-button switch, to both the Stratix III FPGA and the MAX II CPLD. The intended to be the master reset signal for the FPGA design loaded in the Stratix III device, and connects to a regular I/O pin on the FPGA. The MAX II device uses this push-button as its reset along with the

RESET_CONFIG

and

buttons.

Board reference S1 is the factory push-button, the MAX II device. The

FACTORY_CONFIG

pin forces a reconfiguration of the FPGA with the factory default FPGA design, which is located at the base of flash memory. See

Tab le 2– 14 .

Table 2–14. Push-Button Switch Signal Name and Function

Board Reference

Schematic

Signal Name

FACTORY_CONFIG

RESET_CONFIGn

CPU_RESET

Stratix III Device

Pin Number

—A10

—R16

T21 M9

Tab le 2– 15 lists the push-button switch component reference and manufacturing

information.

Table 2–15. Push-Button Switch Component Reference and Manufacturing Information

CPU_RESET

, which is an input

push-button is

FACTORY_CONFIG

, which is an input to

push-

MAX II Device

Pin Number

Board Reference Description Manufacturer

S1, S6, S7 Push-button switch Panasonic EVQAPAC07K www.panasonic.com

Manufacturing

Part Number

Manufacturer

Website

For information about user-defined push-buttons, refer to “User-Defined Push-Button

Switches” on page 2–28.

Power Select Rotary Switch

A 16-position rotary switch, board reference SW6, is used to select the current power rail whose power is being measured and displayed on the power display. The rotary switch is connected to the MAX II CPLD.

Upon first use, after configuring or powering up the board, make sure you initiate changes to the rotary switch (SW6) so that the measurement circuit can initiate a channel reading. Otherwise, the measurement might be reading a previous capture.

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–24 Chapter 2: Board Components

Configuration, Status, and Setup Elements

Tab le 2– 16 lists the Power Select rotary switch number, name, power pin, and

description.

Table 2–16. Power Select Rotary Switch Number, Name, Pin, and Description

Number

5— — —

10 — — —

11 — — —

12 — — —

13 — — —

14 — — —

15 — — —

Schematic

Signal Name

VCCL VCCL

1.1V_VCC VCC

2.5V_A VCCA, VCCPT

2.5V_VCCPD VCCPD

2.5V_VCCPGM VCCPGM

1.8 V_S3

2.5V_B2

2.5V_B4A_B5_B6

.5V_1.8V_B7

VCCIO

1A, 1C, 3A, 3B, 3C, 4B, 4C, 8A, 8B, 8C

VCCIO

2A, 2C

VCCIO

4A, 5A, 5C, 6A, 6C

VCCIO

7A, 7B, 7C

Power Pin Name Description

FPGA core voltage power

FPGA I/O registers power

FPGA analog power, programmable power technology

FPGA I/O pre-driver power

FPGA configuration pins power

FPGA I/O power banks 1A, 1C, 3A, 3B, 3C, 4B, 4C, 8A, 8B, 8C

FPGA I/O power banks 2A, 2C

FPGA I/O power banks 4A, 5A, 5C, 6A, 6C

FPGA I/O power banks 7A,7B,7C

Tab le 2– 17 lists Power Select rotary switch component reference and manufacturing

information.

Table 2–17. Power Select Rotary Switch Component Reference and Manufacturing Information

Board Reference Description Manufacturer

SW6 16-position rotary switch Grayhill Corporation 94HCB16WT www.grayhill.com

Manufacturing

Part Number

Manufacturer

Website

PGM Config Select Rotary Switch

A 16-position rotary switch, board reference SW3, is used to set the location in flash memory from which the Stratix III FPGA design is loaded. The rotary switch has 16 positions but only the first eight are used.

For information about the flash memory locations, refer to “Flash Memory” on

page 2–63.

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–25

Clocking Circuitry

Tab le 2– 18 lists PGM Config Select rotary switch component reference and

manufacturing information.

Table 2–18. PGM Config Select Rotary Switch Component Reference and Manufacturing Information

Board Reference Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

SW3 Rotary switch Grayhill Corporation 94HCB16WT www.grayhill.com

Clocking Circuitry

This section describes the Stratix III FPGA clocking inputs and outputs. The clocking block comprises the following items:

■ High-speed clock oscillators:

■ 50-MHz, FPGA PLL input

■ 125-MHz FPGA PLL input

■ 125-MHz MAX II CPLD input

■ 24-MHz MAX II CPLD input

■ Reference clocks:

■ 6-MHz USB PHY reference clock (FTDI device)

■ 24-MHz USB PHY reference clock (Cypress device)

■ 25-MHz Ethernet PHY reference clock

■ SMA connectors for clocking input and output signals

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–26 Chapter 2: Board Components

Bank 8C

1.8 V

CLK14N

CLKIN_125

CLK14P

CLK15N

CLK15P

CLK12N

CLK12P

CLK13N

CLK13P

CLK5N

CLK5P

CLK4N

CLK4P

CLK7N

CLK7P

CLK6N

CLK6P

CLK1N

CLK1P

USB_IFCLK

500 MHz

CLK0N

CLK0P

CLK3N

CLK3P

CLK2N

CLK2P

ENET_S_CLKP

ENET_S_CLKN

CLK11N

CLK11P

CLK10N

CLK10P

CLK8N

CLK8P

CLK9N

CLK9P

Bank 7C

1.5 V

Bank 3C

1.8 V

Bank 4C

1.8 V

Bank 6C

2.5 V

Bank 5C

2.5 V

Bank 1C

1.8 V

Bank 2C

2.5 V

HSMA_CLK_IN_P2

HSMA_CLK_IN_N2

HSMB_CLK_IN_P2

HSMB_CLK_IN_N2

CLKIN_SMA

500 MHz

ENET PHY

MAX II Device

HSMC Port A

HSMC Port B

SMA Input

Clocking Circuitry

Stratix III FPGA Clock Inputs

Figure 2–7 outlines the inputs from the Stratix III FPGA. All PLL inputs are located in

the C sub-bank of each device bank. The clocks are sourced by the on-board oscillators, SMA connectors, Ethernet, MAX II CPLD, and HSMC ports.

Figure 2–7. Stratix III FPGA Clock Inputs

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–27

Bank 8

1.8 V

Bank 7

1.5 V

Bank 3

1.8 V

Bank 4

1.8 V, 2.5 V

Bank 6

2.5 V

Bank 5

2.5 V

Bank 1

1.8 V

Bank 2

2.5 V

FLASH QDRII+

FLASH_CLK

QDRII_K_P

QDRII_K_N

SRAM

DDR2

SRAM_CLK

DDR2_DEVA_CK_P

DDR2_DEVA_CK_N

SMA

Output

DDR2_DEVB_CK_P

DDR2_DEVB_CK_N

ENET PHY

ENET_TX_CLK

ENET_GTX_CLK

DDR2_DEVB_CK_P

DDR2_DEVB_CK_N

DDR2 DIMM

DDR2_DIMM_CLK_N2

HSMB_CLK_OUT_N2

HSMB_CLK_OUT_P2

HSMB_CLK_OUT_N1

HSMB_CLK_OUT_P1

HSMC Port B

HSMA_CLK_OUT_N2

HSMA_CLK_OUT_P2

HSMA_CLK_OUT_N1

HSMA_CLK_OUT_P1

HSMC Port A

Clocking Circuitry

Stratix III FPGA Clock Outputs

Figure 2–8 outlines the outputs from the Stratix III FPGA. Most of the output clocks

originate from the regular I/O pins (non-PLL pins). These clocks drive each of the interfaces on the Stratix III development board.

Figure 2–8. Stratix III FPGA Clock Outputs

Tab le 2– 19 shows the clocking parts list.

Table 2–19. Stratix III Development Board Clocking Parts List

Board

Reference

Y6 50-MHz LVDS oscillator Pletronics SM5545TEX-50.00M www.pletronics.com

Y1,Y5 125-MHz LVDS oscillator Pletronics SM5545TEX-125.00M www.pletronics.com

J16, J17

Y2 24-MHz crystal Abracon Corporation ABL-24.000MHZ-12 www.abracon.com

Y3 6-MHz crystal Abracon Corporation ABL-6.000MHZ-B2 www.abracon.com

X1 25-MHz crystal oscillator ECS, Inc. ECS-3953C-250-B www.ecsxtal.com

Y4 24-MHz crystal oscillator Pletronics SM5545TEX-24.00M www.pletronics.com

Description Manufacturer

SMA for external clock input/output

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Manufacturer

Part Number

Manufacturer

Website

Lighthorse Technologies LTI-SASF546-P26-X1 www.rfconnector.com

Reference Manual

2–28 Chapter 2: Board Components

General User Interfaces

Tab le 2– 20 lists the board’s clock distribution system.

Table 2–20. Stratix III Development Board Clock Distribution

Source

125-MHz (Y5) oscillator

50-MHz (Y6) oscillator

User input (SMA clock input)

User output (SMA clock output)

clkin_125

clkin_50

clkin_sma

clkout_sma

25 MHz (reference clock)

This clock can change both speed and direction depending

enet_rx_clk

on the Ethernet link speed (10/100/1000)

24-MHz (Y4) oscillator

6-MHz crystal

24-MHz crystal

125-MHz (Y1) oscillator

clkin_24

XTIN/XTOUT

XTALIN/XTALOUT

clkin_max_125

f For more information about the board’s clocking scheme, refer to the Stratix III

development board schematics included with the Stratix III development board kit.

General User Interfaces

Schematic

Signal Name

Signal

I/O Standard

Originates

Signal Propagates To

From

Input Y5 Stratix III device pin B16

Input Y6 Stratix III device pin T33

Input J16 Stratix III device pin AP15

Output J17 From Stratix III device pin AE27

Input U25 Stratix III device pin AK28

Input Y4 MAX II device pin J12 (Bank 3)

Input Y3 FTDI USB PHY

Input Y2 Cypress USB PHY

Input Y1 MAX II device pin H12 (Bank 3)

To allow you to fully leverage the I/O capabilities of the Stratix III device for debugging, control, and monitoring purposes, the following general user interfaces are available on the board:

■ “User-Defined Push-Button Switches” on page 2–28

■ “User-Defined DIP Switches” on page 2–29

■ “User-Defined LEDs” on page 2–30

■ “7-Segment Displays” on page 2–31

■ “LCD Displays” on page 2–33

■ “Speaker Header” on page 2–38

User-Defined Push-Button Switches

The development board includes four general user and one user reset push-button. For information about the system and reset push-button switches, refer to “System

Reset and Configuration Switches” on page 2–23.

Board references S2 through S5 are push-button switches allowing user interactions with the Stratix III device. When the switch is pressed and held down, the device pin is set to a logic 0; when the switch is released, the device pin is set to a logic 1. There is no board-specific function for these four push-button switches.

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–29

General User Interfaces

Board reference S6 is the user reset push-button switch, to both the Stratix III device and MAX II CPLD. The

CPU_RESET

, which is an input

is intended to be the

master reset signal for the FPGA design loaded into the Stratix III device. Still, the

CPU_RESET

reset along with the

is also a regular I/O pin. The MAX II device uses the

RESET_CONFIG

push-button switch.

DEV_CLR

pin as its

Tab le 2– 21 lists the schematic signal names and corresponding Stratix III pin

numbers.

Table 2–21. User Push-Button Switch Signal Names and Functions

Board Reference Description

S2 User-defined push-button

S3 User-defined push-button

S4 User-defined push-button

S5 User-defined push-button

S6 User-defined push-button

Note to Table 2–21:

(1) The pull-up resistors for the push-buttons are connected to 2.5 V. The inputs pads on the FPGA can accept an input voltage up to the maximum

input voltage for the device. The logic threshold is determined by the VCCIO of the bank and the selected I/O configuration.

Schematic

Signal Name

USER_PB3

USER_PB2

USER_PB1

USER_PB0

CPU_RESET

Stratix III Device

Pin Number

K17 —

A16 —

A17 —

B17 —

AP5 U5 pin M9

Other

Connections

Tab le 2– 22 lists the push-button switch component reference and manufacturing

information.

Table 2–22. Push-Button Switch Component Reference and Manufacturing Information

Board Reference Description Manufacturer

S2 through S6 Push-button switch Panasonic EVQPAC07K www.panasonic.com

Manufacturing

Part Number

Manufacturer

Website

User-Defined DIP Switches

Board reference SW5 is an 8-pin DIP switch. The switches in SW5 are user-defined, and are provided for additional FPGA input control. Each pin can be set to a logic 1 by pushing it to the open position, and each pin can be set to a logic 0 by pushing it to the closed position. There is no board-specific function for these switches.

Tab le 2– 23 lists the user DIP switch settings, schematic signal name, and

corresponding Stratix III device’s pin number.

Table 2–23. User-Defined DIP Switch Pin-Out (SW5) (Part 1 of 2)

Stratix III

Device

Pin Number

Board Reference Description

SW5 pin1 User-defined DIP switch pin 1

SW5 pin 2 User-defined DIP switch pin 2

SW5 pin 3 User-defined DIP switch pin 3

SW5 pin 4 User-defined DIP switch pin 4

SW5 pin 5 User-defined DIP switch pin 5

SW5 pin 6 User-defined DIP switch pin 6

Schematic

Signal Name

USER_DIPSW0

USER_DIPSW1

USER_DIPSW2

USER_DIPSW3

USER_DIPSW4

USER_DIPSW5

I/O Standard

1.8 V B19

1.8 V A19

1.8 V C18

1.8 V A20

1.8 V K19

1.8 V J19

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–30 Chapter 2: Board Components

General User Interfaces

Table 2–23. User-Defined DIP Switch Pin-Out (SW5) (Part 2 of 2)

Stratix III

Device

Pin Number

Board Reference Description

SW5 pin 7 User-defined DIP switch pin 7

SW5 pin 8 User-defined DIP switch pin 8

Schematic

Signal Name

USER_DIPSW6

USER_DIPSW7

I/O Standard

1.8 V L19

1.8 V L20

Tab le 2– 24 lists the user-defined DIP switch component reference and manufacturing

information.

Table 2–24. User-Defined DIP Switch Component Reference and Manufacturing Information

Board Reference Description Manufacturer

SW5 8-position rocker DIP switch Grayhill Corporation 76SB08ST www.grayhill.com

Manufacturing

Part Number

Manufacturer

Website

User-Defined LEDs

The board includes general and HSMC user-defined LEDs. This section discusses all user-defined LEDs. For information about board specific or status LEDs, refer to

“Status Elements” on page 2–19.

General User-Defined LEDs

Board references D20 through D27 are eight user LEDs, which allow status and debugging signals to be driven to LEDs from the FPGA designs loaded into the Stratix III device. The LEDs illuminate when a logic 0 is driven, and do not illuminate when a logic 1 is driven. There is no board-specific function for these LEDs.

Tab le 2– 25 lists the general user LED reference number, schematic signal name, and

corresponding Stratix III device pin number.

Table 2–25. LED Reference Number, Schematic Signal Name, and Stratix III Device Pin Number

LED Board

Reference

D27 User-defined LED

D26 User-defined LED

D25 User-defined LED

D24 User-defined LED

D23 User-defined LED

D22 User-defined LED

D21 User-defined LED

D20 User-defined LED

Description

Schematic

Signal Name

USER_LED0

USER_LED1

USER_LED2

USER_LED3

USER_LED4

USER_LED5

USER_LED6

USER_LED7

I/O

Standard

1.8 V F21

1.8 V C23

1.8 V B23

1.8 V A23

1.8 V D19

1.8 V C19

1.8 V F19

1.8 V E19

Stratix III Device

Pin Number

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–31

General User Interfaces

Tab le 2– 26 lists the general user-defined LED component reference and

manufacturing information.

Table 2–26. General User-Defined LED Component Reference and Manufacturing Information

Board Reference Description Manufacturer

D20-D27

Green LEDs, 1206, SMT, clear lens,

2.1 V

Lumex, Inc. SML-LX1206GC-TR www.lumex.com

HSMC User-Defined LEDs

The HSMC cards Port A and Port B have two LEDs located nearby. There are no board-specific functions for the HSMC LEDs; however, the LEDs are labeled TX and RX, and are intended to display data flow to and from connected HSMC cards. The LEDs are driven by the Stratix III device.

Tab le 2– 27 lists the HSMC user-defined LED board reference number, schematic

signal name, and corresponding Stratix III device pin number.

Table 2–27. HSMC User-Defined LEDs

Board

Reference

D11

D12

Description

User-defined LED, but labeled TX in silk-screen for HSMC Port A.

User-defined LED, but labeled RX in silk-screen for HSMC Port A.

User-defined LED, but labeled TX in silk-screen for HSMC Port B.

User-defined LED, but labeled RX in silk-screen for HSMC Port B.

Schematic Signal

HSMA_TX_LED

HSMA_RX_LED

HSMA_TX_LED

HSMA_RX_LED

Name

Manufacturing

Part Number

I/O Standard

1.8 V AG29

1.8 V Y25

1.8 V AG34

1.8 V AJ12

Manufacturer

Website

Stratix III

Device

Pin Number

Tab le 2– 28 lists the HSMC user-defined LED component reference and manufacturing

information.

Table 2–28. HSMC User-Defined LED Component Reference and Manufacturing Information

Board Reference Description Manufacturer

D2, D3, D11, D12

Green LED, 1206, SMT, clear lens,

2.1 V

Lumex, Inc. SML-LX1206GC-TR www.lumex.com

Manufacturing

Part Number

Manufacturer

Website

7-Segment Displays

This section discusses the following two on-board displays:

■ User 7-segment display

■ Power 7-segment display

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–32 Chapter 2: Board Components

12 B 11

C 3 D 8 E 2 F 9 G 7 DP

4 8

DIGIT2

DIGIT1

U28

F B

E C

QUAD_7SEG_M2212R1

DIGIT3 DIGIT4

General User Interfaces

User 7-Segment Display

Board reference U28 is a four-digit, user-defined, 7-segment display that is labeled User Display. Each segment’s LED driver input signals are multiplexed to each of the four digits and a minus sign. Tab le 2 –2 9 lists the 7-segment display pin-out.

Table 2–29. User-Defined 7-Segment Display Pin-Out

Board Reference Description

U28 pin 12 User-defined display signal

U28 pin 11 User-defined display signal

U28 pin 3 User-defined display signal

U28 pin 8 User-defined display signal

U28 pin 9 User-defined display signal

U28 pin 7 User-defined display signal

U28 pin 5 User-defined display signal

U28 pin 2 User-defined display signal

U28 pin 13 User-defined display signal

U28 pin 1 User-defined display select signal

U28 pin 10 User-defined display select signal

U28 pin 4 User-defined display select signal

U28 pin 6 User-defined display select signal

1 The four-pin, 7-segment display uses fewer pins than 2-digit, 7-segment displays. See

Figure 2–9.

Schematic

Signal Name

SEVEN_SEG_A

SEVEN_SEG_B

SEVEN_SEG_C

SEVEN_SEG_D

SEVEN_SEG_E

SEVEN_SEG_F

SEVEN_SEG_G

SEVEN_SEG_DP

SEVEN_SEG_MINUS

SEVEN_SEG_SEL1

SEVEN_SEG_SEL2

SEVEN_SEG_SEL3

SEVEN_SEG_SEL4

I/O Standard

2.5 V AE10

2.5 V AL5

2.5 V AC12

2.5 V AM5

2.5 V AF11

2.5 V AM6

2.5 V AP3

2.5 V AK6

2.5 V AH11

2.5 V AM4

2.5 V AE12

2.5 V AL4

2.5 V AH8

Stratix III

Device

Pin Name

Figure 2–9. 7-Segment Display

Tab le 2– 30 lists the 7-segment display component reference and manufacturing

information.

Table 2–30. 7-Segment Display Component Reference and Manufacturing Information

Board Reference Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

U28 7-segment, green LED display Lumex, Inc. LDQ-M2212R1 www.lumex.com

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–33

General User Interfaces

Power 7-Segment Display

The power measured by the MAX II CPLD and associated A/D is displayed on board reference U27, which is a dedicated 7-segment display connected to the MAX II CPLD, labeled Power Display.

Tab le 2– 31 lists the power 7-segment display component reference and manufacturing

information.

Table 2–31. Power 7-Segment Display Component Reference and Manufacturing Information

Board

Reference

U27 7-segment, green LED display Lumex, Inc. LDQ-M2212R1 www.lumex.com

Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

LCD Displays

The development board accommodates two LCD displays:

■ Character LCD

■ Graphics LCD

The character display is a 16-character, by 2-line LCD display. The graphics is a 128 × 64 pixel transmissive graphics LCD. The two displays have separate buses. This section describes both displays.

Character LCD

The board contains a single 14-pin 0.1 in. pitch dual-row header, used to interface to a 16-character by 2-line LCD display, manufactured by Lumex (part number LCM-S01602DSR/C). The LCD has a 14-pin receptacle that mounts directly to the board’s 14-pin header, so it can be easily removed for access to components under the display—or to use the header for debugging or other purposes.

Tab le 2– 32 summarizes the character LCD interface pins. Signal name and direction

are relative to the Stratix III FPGA. For functional descriptions, see Table 2–33.

Table 2–32. Character LCD (J22) Header I/O

Board

Reference

J22 pin 7 LCD data bus bit 0

J22 pin 8 LCD data bus bit 1

J22 pin 9 LCD data bus bit 2

J22 pin 10 LCD data bus bit 3

J22 pin 11 LCD data bus bit 4

J22 pin 12 LCD data bus bit 5

J22 pin 13 LCD data bus bit 6

J22 pin 14 LCD data bus bit 7

J22 pin 4 LCD data/command select

J22 pin 5 LCD write enable

J22 pin 6 LCD chip select

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Description

Schematic

Signal Name

LCD_DATA0

LCD_DATA1

LCD_DATA2

LCD_DATA3

LCD_DATA4

LCD_DATA5

LCD_DATA6

LCD_DATA7

LCD_D_Cn

LCD_WEn

LCD_CSn

I/O

Standard

2.5 V AJ8

2.5 V AJ6

2.5 V AD13

2.5 V AJ7

2.5 V AF10

2.5 V AN6

2.5 V AN3

2.5 V AK7

2.5 V AP2

2.5 V AL8

2.5 V AD12

Stratix III

Pin Number

Reference Manual

2–34 Chapter 2: Board Components

General User Interfaces

Tab le 2– 33 shows pin definitions, and is an excerpt from the Lumex data sheet.

f For more information such as timing, character maps, interface guidelines, and

related documentation, visit www.lumex.com.

Table 2–33. Character LCD Display Pin Definitions

Pin Number Symbol Level Function

—

— GND (0V)

Power supply

— For LCD drive

4RS H/L

H: Data input

L: Instruction input

5R/W H/L

H: Data read (module to MPU)

L: Data write (MPU to module)

6 E H, H to L Enable

7~14 DB0~DB7 H/L Data bus, software selectable 4- or 8-bit mode

Figure 2–10 shows a functional block diagram of the Lumex LCD display device.

1 The particular model used does not have a backlight and the LCD drive pin is not

connected.

Figure 2–10. LCD Display Block Diagram

Block Diagram 16 X 2, 1/16 Duty, 1/5 Bias

DB[7:0]

R/W

SS DD

LCD

A K

Controller

LSI and

Driver

SEC 80

COM 16

LCD

Panel

LED Backlight

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–35

15.24 [0.600] (P2.54 x 7)

24.00 [0.945]

30.00 0.50

[1.18 0.020]

24.00 [0.945]

16.00 [0.630] V.A.

2.54 [0.100]

13 14

11.50 [0.453]

3.00 [0.118]

7.38 [0.291] REF.

1 2

2.00 [0.079]

85.00 0.50 [3.346 0.020]

71.20 [2.803]

81.00 [3.189]

66.00 [2.598] V.A.

56.21 [2.213]

4.325 [1.703]

14 - 1.00 [ 0.039]

(PAD 1.80 [ 0.071])

1.00 [ 0.039] (5 PLS.)

2.50 [ 0.098] (4 PLS.)

General User Interfaces

Figure 2–11 shows a mechanical diagram of the LCD display. The 14-pin receptacle

mounts underneath the display in the holes to the left.

Figure 2–11. LCD Display Dimensions

Table 2–34. Character LCD Display Component Reference and Manufacturing Information

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Board

Reference

J22

Tab le 2– 34 lists the character LCD display component reference and manufacturing

information.

Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

2 × 7 pin, 100 mil, vertical header Samtec TSM-107-01-G-DV www.samtec.com

2 × 16 character display, 5 × 8 dot matrix Lumex Inc. LCM-S01602DSR/C www.lumex.com

Graphics LCD

The board contains a 30-pin, fine-pitch connector to interface directly to a 128 × 64 dot matrix graphics LCD display via a flex-cable that is soldered to the display itself. The display is an Optrex, part number F-51852GNFQJ-LB-AIN (blue pixels) or F-51852GNFQJ-LB-CAN (green pixels). The pin-out of this interface connector is compatible with a variety of displays.

f For the graphics LCD data sheet and related documentation, visit www.optrex.com.

Tab le 2– 35 lists the graphics LCD pin name, description, and type. Signal name and

direction are relative to the Stratix III FPGA.

Table 2–35. Graphics LCD Header (J24) (Part 1 of 2)

Description

Schematic

Signal Name

OLED_DATA0

OLED_DATA1

OLED_DATA2

OLED_DATA3

I/O

Standard

2.5 V AB31

2.5 V AG32

2.5 V AB27

2.5 V AC32

Reference Manual

Board

Reference

J24 pin 6 LCD data bus bit 0

J24 pin 7 LCD data bus bit 1

J24 pin 8 LCD data bus bit 2

J24 pin 9 LCD data bus bit 3

Stratix III

Pin Number

2–36 Chapter 2: Board Components

General User Interfaces

Table 2–35. Graphics LCD Header (J24) (Part 2 of 2)

Board

Reference

Description

J24 pin 10 LCD data bus bit 4

J24 pin 11 LCD data bus bit 5

J24 pin 12

J24 pin 13

J24 pin 28

LCD data bus bit 6 (or

SCLK

)

LCD data bus bit 7

SDATA

(or

)

Parallel interface selection (high = 68 series, low = 80 series)

J24 pin 1 LCD chip select

J24 pin 3 LCD data/command select

J24 pin 5 LCD read enable

J24 pin 2 LCD reset

J24 pin 29 LCD parallel/serial data select

J24 pin 4 LCD write enable

Schematic

Signal Name

OLED_DATA4

OLED_DATA5

OLED_DATA6

OLED_DATA7

OLED_BS1

OLED_CSn

OLED_D_Cn

OLED_E_RDn

OLED_RSTn

OLED_SERn

OLED_WEn

I/O

Standard

Stratix III

Pin Number

2.5 V AL32

2.5 V AB30

2.5 V AC26

2.5 V AA30

2.5 V Y26

2.5 V AE30

2.5 V AD26

2.5 V AG31

2.5 V AP4

2.5 V AA27

2.5 V AA31

f For more information about the data sheet and related documentation, visit Lumex at

www.lumex.com.

1 Board defaults graphics LCD interface to 80 series CPU mode and parallel interface.

You can modify these defaults by writing to the appropriate register in the MAX II CPLD using the FSM bus.

Figure 2–12 is an excerpt from the Optrex data sheet showing the control chip in the

LCD module and illustrates the functional block diagram of the display driver. The control chip is from New Japan Radio Corporation, part number NJU6676.

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–37

Segment Drivers

Common

Drivers

Shift

Common

Drivers

Display Data RAM

65 X 132 = 8,580-bit

Display Data Latch

Low Address Deocder

Line Address Deocder

Column Address Decoder

Vss

VDD

Oscillator

Bus Holder Busy Flag

Instruction

Decoder

Status

Voltage

Followers

Voltage

Regulator

Voltage

Converter

Multiplexer

Line Counter

Initial Display Line

Common Direction Page Address Register

Column Address Counter

Column Address Register

MPU Interface

Reset

Common

Timing

Display Timing

C1+/C1C2+/C2-

C3-

Vss2

Vout

V1 to V6

Internal

Power

Circuits

C0 - - - C21 C63 - - - C32

S0 - - - S131

FR FRS CL CLS DOF

OSC1 OSC2

D5 to D0 P/S D6

(SCL)

(SI)

C86 A0 CS2 CS1 WR

Status

Internal Bus Line

RES

COMM

General User Interfaces

f For more information, contact Optrex America at www.optrex.com or New Japan

Radio at www.njr.co.jp.

Figure 2–12. Graphics LCD Functional Block Diagram of Display Driver

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–38 Chapter 2: Board Components

A0, CS1

D0~D7

(Write)

D0~D7 (Read)

WR, RD

CYC8

CCH(W/R)

CCL(W/R)

AW8

AH8

DS8

ACC8

OH8

DH8

General User Interfaces

Figure 2–13 is an excerpt from the Optrex data sheet and shows the module interface

signals for both read and write transactions.

Figure 2–13. Graphics LCD Timing Diagram

f For more information about timing parameters, visit www.optrex.com.

Tab le 2– 36 lists the graphics LCD display component reference and manufacturing

information.

Table 2–36. Graphics LCD Display Component Reference and Manufacturing Information

Board

Reference

J24

FPC/FFC 30-position flick lock connector, bottom contact

128 × 64 graphics module, blue LCD

(1)

128 × 64 graphics module, green LCD

(1)

Description Manufacturer

Hirose Electronics, Co. FH12S-30S-0.55H(55) www.hirose.com

Optrex America, Inc. F-51852GNFQJ-LB-AIN www.optrex.com

Optrex America, Inc. F-51852GNFQJ-LG-ACN www.optrex.com

Note to Table 2–36:

(1) The Stratix III development board is shipped with either a blue or green Optrex LCD display.

Manufacturing

Part Number

Speaker Header

A four-pin 0.1 in. pitch header, board reference J1, is used for a PC speaker connection. The FPGA drives an R/C filter from a 2.5-V CMOS I/O pin allowing tones to be generated by driving different frequencies to the pin. Stratix III device pin the input of the R/C filter (U1).

Tab le 2– 37 lists speaker header component reference and manufacturing information.

Manufacturer

Website

AJ11

drives

Manufacturing

Part Number

Manufacturer

Website

Table 2–37. Speaker Header Component Reference and Manufacturing Information

Board Reference Description Manufacturer

J1 Speaker header Samtec TSW-104-07-G-S www.samtec.com

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–39

Components and Interfaces

This section describes the board’s communication ports and interface cards relative to the Stratix III device. The board supports the following communication ports:

■ “USB 2.0 MAC/PHY” on page 2–39

■ “10/100/1000 Ethernet” on page 2–39

■ “High-Speed Mezzanine Cards” on page 2–41

USB 2.0 MAC/PHY

The board incorporates the FTDI USB 2.0 PHY chip. The device interfaces to J5, a Type B USB connector. The maximum speed of the interface is 12 Mbps. Typical application speeds are around 1.5 Mbps; however, actual system speed may vary.

The primary usage for the USB device is to provide JTAG programming of on-board devices such as the FPGA and flash memory. The interface is also the default connection between the FPGA and the host PC applications such as SignalTap DSP Builder, and the Nios

II JTAG universal asynchronous receiver/transmitter

(UART).

II,

f For more information about the data sheet and related documentation, contact FTDI

at www.ftdichip.com.

Tab le 2– 38 lists the FTDI USB interface component reference and manufacturing

information.

Table 2–38. FTDI Interface Component Reference and Manufacturing Information

Board Reference Description Manufacturer

U11 FTDI USB device FTDI Ltd. FT245BL www.ftdichip.com

Manufacturing

Part Number

Manufacturer

Website

10/100/1000 Ethernet

A Marvell 88E1111 device is used for 10/100/1000 base-T Ethernet connection. The device is an auto-negotiating Ethernet PHY with a GMII, RGMII, or SGMII interface to the FPGA. Stratix III devices can communicate with LVDS interfaces at up to

1.25 Gbps, which is well above the 1.0 Gbps SGMII requirement. The MAC function must be provided in the FPGA for typical networking applications. The Marvell PHY uses 2.5-V and 1.1-V power rails and requires a 25-MHz reference clock driven from a dedicated oscillator. It interfaces to a HALO HFJ11-1G02E model RJ-45 with internal magnetics that can be used for driving copper lines with Ethernet traffic.

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–40 Chapter 2: Board Components

GTX_CLK

TX_ER

TX_EN

TXD[7:0]

GTX_CLK

Stratix III Device

MAC Block

Marvell 88E1111 GMII PHY Layer

TX_ER

TX_EN

TXD[7:0]

RX_CLK

RX_ER

RX_DV

RX_CLK

RX_ER

RX_DV

RXD[7:0]

CRS

COL

RXD[7:0]

CRS

COL

GMII Interface

RXCLK

S_OUT+/-

S_CLK +/-

S_IN +/-

Stratix III

Device

MAC Block

Marvell 88E1111

SGMII Interface

PHY Layer

Components and Interfaces

Figure 2–14 and Figure 2–15 show the GMII and the SGMII interfaces between the

FPGA (MAC) and Marvell PHY 88E1111 device.

Figure 2–14. Marvell 88E1111 GMII Interface

Figure 2–15. Marvell 88E1111 SGMII Interface

Tab le 2– 39 lists the pins of the Gigabit Ethernet interface.

Table 2–39. Ethernet PHY (U25) Pin-Out (Part 1 of 2)

Board Reference Description Schematic Signal Name

U25 pin 8 RGMII interface transmit clock

U25 pin 23 Management bus interrupt

U25 pin 73 1000 MBytes link established

U25 pin 25 Management bus data clock

U25 pin 24 Management bus data

U25 pin 28 Reset

U25 pin 2 RGMII interface receive clock

U25 pin 83 GMII interface collision

U25 pin 84 GMII interface carrier sense

U25 pin 95 GMII/ RGMII interface receive data bus bit 0

U25 pin 92 GMII/ RGMII interface receive data bus bit 1

U25 pin 93 GMII/ RGMII interface receive data bus bit 2

U25 pin 91 GMII/ RGMII interface receive data bus bit 3

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

ENET_GTX_CLK

ENET_INTn

ENET_LED_LINK1000

ENET_MDC

ENET_MDIO

ENET_RESETN

ENET_RX_CLK

ENET_RX_COL

ENET_RX_CRS

ENET_RX_D0

ENET_RX_D1

ENET_RX_D2

ENET_RX_D3

I/O

Standard

2.5 V AB33

2.5 V AB32

2.5 V A28

2.5 V Y2

2.5 V AD30

2.5 V Y31

1.8 V AK28

2.5 V V33

2.5 V V3

2.5 V AE29

2.5 V AM34

2.5 V AL33

2.5 V AJ32

Stratix III

Number

Chapter 2: Board Components 2–41

Components and Interfaces

Table 2–39. Ethernet PHY (U25) Pin-Out (Part 2 of 2)

Board Reference Description Schematic Signal Name

U25 pin 90 GMII interface receive data bus bit 4

U25 pin 89 GMII interface receive data bus bit 5

U25 pin 87 GMII interface receive data bus bit 6

U25 pin 86 GMII interface receive data bus bit 7

U25 pin 94 RGMII interface receive control

U25 pin 3 GMII interface receive error

U25 pin 75 SGMII interface receive data

U25 pin 77 SGMII interface receive data

U25 pin 80 SGMII interface (625 MHz) clock

U25 pin 79 SGMII interface (625 MHz) clock

U25 pin 4 MII interface (25 MHz) clock

U25 pin 11 RGMII interface transmit data bus bit 0

U25 pin 12 RGMII interface transmit data bus bit 1

U25 pin 14 RGMII interface transmit data bus bit 2

U25 pin 16 RGMII interface transmit data bus bit 3

U25 pin 17 RGMII interface transmit data bus bit 4

U25 pin 18 RGMII interface transmit data bus bit 5

U25 pin 19 RGMII interface transmit data bus bit 6

U25 pin 20 RGMII interface transmit data bus bit 7

U25 pin 9 RGMII interface transmit control

U25 pin 7 RGMII interface transmit error

U25 pin 81 SGMII interface transmit data

U25 pin 82 SGMII interface transmit data

ENET_RX_D4

ENET_RX_D5

ENET_RX_D6

ENET_RX_D7

ENET_RX_DV

ENET_RX_ER

ENET_RX_N

ENET_RX_P

ENET_S_CLKN

ENET_S_CLKP

ENET_TX_CLK

ENET_TX_D[0]

ENET_TX_D[1]

ENET_TX_D[2]

ENET_TX_D[3]

ENET_TX_D[4]

ENET_TX_D[5]

ENET_TX_D[6]

ENET_TX_D[7]

ENET_TX_EN

ENET_TX_ER

ENET_TX_N

ENET_TX_P

I/O

Standard

2.5 V AH34

2.5 V AF29

2.5 V AH33

2.5 V V34

2.5 V W5

2.5 V AJ10

LVDS Y 34

LVDS AA33

LVDS W3 4

LVDS W3 3

2.5 V AB34

2.5 V AF28

2.5 V AD34

2.5 V AL34

2.5 V W30

2.5 V AD33

2.5 V AJ34

2.5 V AJ31

2.5 V AG30

2.5 V AA34

2.5 V AA29

LVDS V 29

LVDS W2 8

Stratix III

Number

Tab le 2– 40 lists the Ethernet PHY component reference and manufacturing

information.

Table 2–40. Ethernet PHY Component Reference and Manufacturing Information

Board

Reference

U25 Ethernet PHY base-T device Marvel Semiconductor 88E1111-B2-CAAIC000 www.marvell.com

Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

High-Speed Mezzanine Cards

The board contains two HSMC interfaces called Port A and Port B. These HSMC interfaces support both single-ended and differential signaling. The connector part number is Samtec ASP-122953-01. The HSMC interface also allows for JTAG, SMBus, clock outputs and inputs, as well as power for compatible HSMCs.

The HSMC is an Altera-developed specification, which allows users to expand the functionality of the development board through the addition of daughter cards (HSMCs).

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–42 Chapter 2: Board Components

Components and Interfaces

f For more information about the HSMC specification such as signaling standards,

signal integrity, compatible connectors, and mechanical information, visit

www.altera.com.

The HSMC connector has 172 total pins, including 120 signal pins, 39 power pins, and 13 ground pins. The ground pins are located between the two rows of signal and power pins, acting as both shield and reference. The HSMC host connector is based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board connectors from Samtec. There are three banks in this connector. Bank 1 has every third pin removed as it is done in the QSH-DP/QTH-DP series. Banks 2 and 3 have all of the pins populated as it is done in the QSH/QTH series.

The Stratix III development board does not use bank 1 transceiver signals intended for clock-data-recover (CDR) applications such as PCI Express and Rapid I/O

©.

These 32 pins are left floating. Banks 2 and 3 are fully supported and can be used in two different configurations, as shown in Figure 2–16.

Figure 2–16. HSMC Signal and Bank Diagram

Bank 3

Powe r

D(79.40)

-or-

LVDS

CLKIN2, CLKOUT2

Bank 2

Powe r

D(39:0)

-or-

D[3:0] + LVDS

CLKIN1, CLKOUT1

Bank 1

8 TX Channels CDR

8 RX Channels CDR

JTAG

SMBus

CLKIN0, CLKOUT0

The HSMC interface has programmable bi-directional I/O pins that can be used as

2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as various differential I/O standards including, but not limited to LVDS, mini-LVDS, and RSDS with up to 17-channels full-duplex.

1 As noted in the HSMC specification, LVDS and single-ended I/O standards are only

guaranteed to function when mixed according to either the generic single-ended pin-out or the generic differential pin-out.

For the Stratix III FPGA Development Kit, there is only one clock per HSMC interface that can drive a PLL. If you want to drive a PLL from the HSMC interface make sure you use either

HSMA_CLK_P2

for Port A or

HSMB_CLK_P2

for Port B.

Section 2.2.4 of the HSMC Specification recommends that a dedicated clock input be used for the single-ended clock (CMOS CLK) on pin 40 of the HSMC connector. The Stratix III board uses a regular input pin due to lack of input clock resources. This means that clocks driven from the HSMC cannot be routed to a PLL. This limitation is true for both HSMC Port A and HSMC Port B.

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–43

Components and Interfaces

Section 2.2.5 of the HSMC Specification recommends that dedicated clock inputs are used for the differential LVDS clocks (LVDS CLK/CMOS) on pin pairs (96, 98) and (156, 158) of the HSMC connector. The specification makes

CLKIN2p/n

the priority as such the Stratix III board has a standard LVDS input pair due to lack of input clock resources. This means that the clock driven into

CLKIN1p/n

from the HSMC cannot be

routed to a PLL. This limitation is true for both HSMC Port A and HSMC Port B.

If you must use another clock, you can drive the clock to the SMA output of the board, then attach a cable from the SMA output to the SMA input. In this case, assign the Stratix III pin that corresponds to the SMA input as your clock.

Tab le 2– 41 lists the HSMC Port A interface signal name, description, and signal type.

Table 2–41. HSMC Port A Interface Signal Name, Description, and Type (Part 1 of 3)

Board

Reference

J18 pin 33 Management serial data

J18 pin 34 Management serial clock

J18 pin 35 JTAG clock signal

J18 pin 36 JTAG mode select signal

J18 pin 37 JTAG data output

J18 pin 38 JTAG data input

J18 pin 39 Dedicated CMOS clock out

J18 pin 40 Dedicated CMOS clock in

J18 pin 41 Dedicated CMOS I/O bit 0

J18 pin 42 Dedicated CMOS I/O bit 1

J18 pin 43 Dedicated CMOS I/O bit 2

J18 pin 44 Dedicated CMOS I/O bit 3

J18 pin 47 LVDS TX or CMOS I/O bit 0

J18 pin 48 LVDS RX or CMOS I/O bit 0

J18 pin 49 LVDS TX or CMOS I/O bit 0

J18 pin 50 LVDS RX or CMOS I/O bit 0

J18 pin 53 LVDS TX or CMOS I/O bit 1

J18 pin 54 LVDS RX or CMOS I/O bit 1

J18 pin 55 LVDS TX or CMOS I/O bit 1

J18 pin 56 LVDS RX or CMOS I/O bit 1

J18 pin 59 LVDS TX or CMOS I/O bit 2

J18 pin 60 LVDS RX or CMOS I/O bit 2

J18 pin 61 LVDS TX or CMOS I/O bit 2

J18 pin 62 LVDS RX or CMOS I/O bit 2

J18 pin 65 LVDS TX or CMOS I/O bit 3

J18 pin 66 LVDS RX or CMOS I/O bit 3

J18 pin 67 LVDS TX or CMOS I/O bit 3

J18 pin 68 LVDS RX or CMOS I/O bit 3

J18 pin 71 LVDS TX or CMOS I/O bit 4

Description

Schematic

Signal Name

HSMA_SDA

HSMA_SCL

FPGA_JTAG_TCK

FPGA_JTAG_TMS

HSMA_JTAG_TDO

HSMA_JTAG_TDI

HSMA_CLK_OUT0

HSMA_CLK_IN0

HSMA_D0

HSMA_D1

HSMA_D2

HSMA_D3

HSMA_TX_P0

HSMA_RX_P0

HSMA_TX_N0

HSMA_RX_N0

HSMA_TX_P1

HSMA_RX_P1

HSMA_TX_N1

HSMA_RX_N1

HSMA_TX_P2

HSMA_RX_P2

HSMA_TX_N2

HSMA_RX_N2

HSMA_TX_P3

HSMA_RX_P3

HSMA_TX_N3

HSMA_RX_N3

HSMA_TX_P4

I/O

Standard

2.5 V P8

2.5 V AA32

2.5 V F30

2.5 V N/A

2.5 V AD28

2.5 V W10

2.5 V AK9

2.5 V AJ9

2.5 V AL7

2.5 V AL9

LVDS or 2.5 V AC11

LVDS or 2.5 V AJ4

LVDS or 2.5 V AB10

LVDS or 2.5 V AJ3

LVDS or 2.5 V AC9

LVDS or 2.5 V AG4

LVDS or 2.5 V AC8

LVDS or 2.5 V AG3

LVDS or 2.5 V AH5

LVDS or 2.5 V AM2

LVDS or 2.5 V AH4

LVDS or 2.5 V AM1

LVDS or 2.5 V AE8

LVDS or 2.5 V AL2

LVDS or 2.5 V AE7

LVDS or 2.5 V AL1

LVDS or 2.5 V AF6

Stratix III

Pin Number

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–44 Chapter 2: Board Components

Components and Interfaces

Table 2–41. HSMC Port A Interface Signal Name, Description, and Type (Part 2 of 3)

Board

Reference

Description

J18 pin 72 LVDS RX or CMOS I/O bit 4

J18 pin 73 LVDS TX or CMOS I/O bit 4

J18 pin 74 LVDS RX or CMOS I/O bit 4

J18 pin 77 LVDS TX or CMOS I/O bit 5

J18 pin 78 LVDS RX or CMOS I/O bit 5

J18 pin 79 LVDS TX or CMOS I/O bit 5

J18 pin 80 LVDS RX or CMOS I/O bit 5

J18 pin 83 LVDS TX or CMOS I/O bit 6

J18 pin 84 LVDS RX or CMOS I/O bit 6

J18 pin 85 LVDS TX or CMOS I/O bit 6

J18 pin 86 LVDS RX or CMOS I/O bit 6

J18 pin 89 LVDS TX or CMOS I/O bit 7

J18 pin 90 LVDS RX or CMOS I/O bit 7

J18 pin 91 LVDS TX or CMOS I/O bit 7

J18 pin 92 LVDS RX or CMOS I/O bit 7

J18 pin 95 LVDS or CMOS clock out

J18 pin 96 LVDS or CMOS clock in

J18 pin 97 LVDS or CMOS clock out

J18 pin 98 LVDS or CMOS clock in

J18 pin 101 LVDS TX or CMOS I/O bit 8

J18 pin 102 LVDS RX or CMOS I/O bit 8

J18 pin 103 LVDS TX or CMOS I/O bit 8

J18 pin 104 LVDS RX or CMOS I/O bit 8

J18 pin 107 LVDS TX or CMOS I/O bit 9

J18 pin 108 LVDS RX or CMOS I/O bit 9

J18 pin 109 LVDS TX or CMOS I/O bit 9

J18 pin 110 LVDS RX or CMOS I/O bit 9

J18 pin 113 LVDS TX or CMOS I/O bit 10

J18 pin 114 LVDS RX or CMOS I/O bit 10

J18 pin 115 LVDS TX or CMOS I/O bit 10

J18 pin 116 LVDS RX or CMOS I/O bit 10

J18 pin 119 LVDS TX or CMOS I/O bit 11

J18 pin 120 LVDS RX or CMOS I/O bit 11

J18 pin 121 LVDS TX or CMOS I/O bit 11

J18 pin 122 LVDS RX or CMOS I/O bit 11

J18 pin 125 LVDS TX or CMOS I/O bit 12

J18 pin 126 LVDS RX or CMOS I/O bit 12

J18 pin 127 LVDS TX or CMOS I/O bit 12

J18 pin 128 LVDS RX or CMOS I/O bit 12

Schematic

Signal Name

HSMA_RX_P4

HSMA_TX_N4

HSMA_RX_N4

HSMA_TX_P5

HSMA_RX_P5

HSMA_TX_N5

HSMA_RX_N5

HSMA_TX_P6

HSMA_RX_P6

HSMA_TX_N6

HSMA_RX_N6

HSMA_TX_P7

HSMA_RX_P7

HSMA_TX_N7

HSMA_RX_N7

HSMA_CLK_OUT_P1

HSMA_CLK_IN_P1

HSMA_CLK_OUT_N1

HSMA_CLK_IN_N1

HSMA_TX_P8

HSMA_RX_P8

HSMA_TX_N8

HSMA_RX_N8

HSMA_TX_P9

HSMA_RX_P9

HSMA_TX_N9

HSMA_RX_N9

HSMA_TX_P10

HSMA_RX_P10

HSMA_TX_N10

HSMA_RX_N10

HSMA_TX_P11

HSMA_RX_P11

HSMA_TX_N11

HSMA_RX_N11

HSMA_TX_P12

HSMA_RX_P12

HSMA_TX_N12

HSMA_RX_N12

I/O

Standard

Stratix III

Pin Number

LVDS or 2.V5 AJ2

LVDS or 2.5 V AF5

LVDS or 2.5 V AK1

LVDS or 2.5 V AD7

LVDS or 2.5 V AH2

LVDS or 2.5 V AD6

LVDS or 2.5 V AJ1

LVDS or 2.5 V AE6

LVDS or 2.5 V AF4

LVDS or 2.5 V AE5

LVDS or 2.5 V AF3

LVDS or 2.5 V AD4

LVDS or 2.5 V AG1

LVDS or 2.5 V AD3

LVDS or 2.5 V AH1

LVDS or 2.5 V V10

LVDS or 2.5 V Y4

LVDS or 2.5 V W9

LVDS or 2.5 V W3

LVDS or 2.5 V AC6

LVDS or 2.5 V AF2

LVDS or 2.5 V AC5

LVDS or 2.5 V AF1

LVDS or 2.5 V AB6

LVDS or 2.5 V AE2

LVDS or 2.5 V AB5

LVDS or 2.5 V AE1

LVDS or 2.5 V AB8

LVDS or 2.5 V AE4

LVDS or 2.5 V AC7

LVDS or 2.5 V AE3

LVDS or 2.5 V Y6

LVDS or 2.5 V AC2

LVDS or 2.5 V Y5

LVDS or 2.5 V AD1

LVDS or 2.5 V AA7

LVDS or 2.5 V AB2

LVDS or 2.5 V AA6

LVDS or 2.5 V AC1

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–45

Components and Interfaces

Table 2–41. HSMC Port A Interface Signal Name, Description, and Type (Part 3 of 3)

Board

Reference

Description

J18 pin 131 LVDS TX or CMOS I/O bit 13

J18 pin 132 LVDS RX or CMOS I/O bit 13

J18 pin 133 LVDS TX or CMOS I/O bit 13

J18 pin 134 LVDS RX or CMOS I/O bit 13

J18 pin 137 LVDS TX or CMOS I/O bit 14

J18 pin 138 LVDS RX or CMOS I/O bit 14

J18 pin 139 LVDS TX or CMOS I/O bit 14

J18 pin 140 LVDS RX or CMOS I/O bit 14

J18 pin 143 LVDS TX or CMOS I/O bit 15

J18 pin 144 LVDS RX or CMOS I/O bit 15

J18 pin 145 LVDS TX or CMOS I/O bit 15

J18 pin 146 LVDS RX or CMOS I/O bit 15

J18 pin 149 LVDS TX or CMOS I/O bit 16

J18 pin 150 LVDS RX or CMOS I/O bit 16

J18 pin 151 LVDS TX or CMOS I/O bit 16

J18 pin 152 LVDS RX or CMOS I/O bit 16

J18 pin 155 LVDS or CMOS clock out

J18 pin 156 LVDS or CMOS clock in

J18 pin 157 LVDS or CMOS clock out

J18 pin 158 LVDS or CMOS clock in

N/A

User LED intended to show RX data activity on the HSMC interface

User LED intended to show TX data activity on the HSMC interface

Schematic

Signal Name

HSMA_TX_P13

HSMA_RX_P13

HSMA_TX_N13

HSMA_RX_N13

HSMA_TX_P14

HSMA_RX_P14

HSMA_TX_N14

HSMA_RX_N14

HSMA_TX_P15

HSMA_RX_P15

HSMA_TX_N15

HSMA_RX_N15

HSMA_TX_P16

HSMA_RX_P16

HSMA_TX_N16

HSMA_RX_N16

HSMA_CLK_OUT_P2

HSMA_CLK_IN_P2

HSMA_CLK_OUT_N2

HSMA_CLK_IN_N2

HSMA_RX_LED

HSMA_TX_LED

I/O

Standard

Stratix III

Pin Number

LVDS or 2.5 V Y8

LVDS or 2.5 V AA1

LVDS or 2.5 V Y7

LVDS or 2.5 V AB1

LVDS or 2.5 V Y10

LVDS or 2.5 V AC4

LVDS or 2.5 V Y9

LVDS or 2.5 V AB3

LVDS or 2.5 V W12

LVDS or 2.5 V AB4

LVDS or 2.5 V Y11

LVDS or 2.5 V AA3

LVDS or 2.5 V AA12

LVDS or 2.5 V AA4

LVDS or 2.5 V AB11

LVDS or 2.5 V Y3

LVDS W 8

LVDS T2

2.5 V W7

2.5 V T1

2.5 V Y25

2.5 V AG29

Tab le 2– 42 lists the HSMC Port B interface signal name, description, and signal type.

Table 2–42. HSMC Port B Interface Signal Name, Description, and Type (Part 1 of 4)

Board

Reference

J8 pin 33 Serial data

J8 pin 34 Serial clock

J8 pin 35 JTAG clock signal

J8 pin 36 JTAG mode select signal

J8 pin 37 JTAG data output

J8 pin 38 JTAG data input

J8 pin 39 Dedicated CMOS clock out

J8 pin 40 Dedicated CMOS clock in

J8 pin 41 Dedicated CMOS I/O bit 0

J8 pin 42 Dedicated CMOS I/O bit 1

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Description

HSMB_SDA

HSMB_SCL

FPGA_JTAG_TCK

FPGA_JTAG_TMS

HSMB_JTAG_TDO

HSMB_JTAG_TDI

HSMB_CLK_OUT0

HSMB_CLK_IN0

HSMB_D0

HSMB_D1

Schematic

Signal Name

I/O Standard

Stratix III

Pin Number

2.5 V U11

2.5 V AD31

2.5 V F30

2.5 V N/A

2.5 V G28

2.5 V N/A

2.5 V AC34

2.5 V V4

2.5 V AB24

2.5 V AB25

Reference Manual

2–46 Chapter 2: Board Components

Components and Interfaces

Table 2–42. HSMC Port B Interface Signal Name, Description, and Type (Part 2 of 4)

Board

Reference

Description

J8 pin 43 Dedicated CMOS I/O bit 2

J8 pin 44 Dedicated CMOS I/O bit 3

J8 pin 47 LVDS TX or CMOS I/O bit 0

J8 pin 48 LVDS RX or CMOS I/O bit 0

J8 pin 49 LVDS TX or CMOS I/O bit 0

J8 pin 50 LVDS RX or CMOS I/O bit 0

J8 pin 53 LVDS TX or CMOS I/O bit 1

J8 pin 54 LVDS RX or CMOS I/O bit 1

J8 pin 55 LVDS TX or CMOS I/O bit 1

J8 pin 56 LVDS RX or CMOS I/O bit 1

J8 pin 59 LVDS TX or CMOS I/O bit 2

J8 pin 60 LVDS RX or CMOS I/O bit 2

J8 pin 61 LVDS TX or CMOS I/O bit 2

J8 pin 62 LVDS RX or CMOS I/O bit 2

J8 pin 65 LVDS TX or CMOS I/O bit 3

J8 pin 66 LVDS RX or CMOS I/O bit 3

J8 pin 67 LVDS TX or CMOS I/O bit 3

J8 pin 68 LVDS RX or CMOS I/O bit 3

J8 pin 71 LVDS TX or CMOS I/O bit 4

J8 pin 72 LVDS RX or CMOS I/O bit 4

J8 pin 73 LVDS TX or CMOS I/O bit 4

J8 pin 74 LVDS RX or CMOS I/O bit 4

J8 pin 77 LVDS TX or CMOS I/O bit 5

J8 pin 78 LVDS RX or CMOS I/O bit 5

J8 pin 79 LVDS TX or CMOS I/O bit 5

J8 pin 80 LVDS RX or CMOS I/O bit 5

J8 pin 83 LVDS TX or CMOS I/O bit 6

J8 pin 84 LVDS RX or CMOS I/O bit 6

J8 pin 85 LVDS TX or CMOS I/O bit 6

J8 pin 86 LVDS RX or CMOS I/O bit 6

J8 pin 89 LVDS TX or CMOS I/O bit 7

J8 pin 90 LVDS RX or CMOS I/O bit 7

J8 pin 91 LVDS TX or CMOS I/O bit 7

J8 pin 92 LVDS RX or CMOS I/O bit 7

J8 pin 95 LVDS or CMOS clock out

J8 pin 96 LVDS or CMOS clock in

J8 pin 97 LVDS or CMOS clock out

J8 pin 98 LVDS or CMOS clock in

J8 pin 101 LVDS TX or CMOS I/O bit 8

Schematic

Signal Name

HSMB_D2

HSMB_D3

HSMB_TX_P0

HSMB_RX_P0

HSMB_TX_N0

HSMB_RX_N0

HSMB_TX_P1

HSMB_RX_P1

HSMB_TX_N1

HSMB_RX_N1

HSMB_TX_P2

HSMB_RX_P2

HSMB_TX_N2

HSMB_RX_N2

HSMB_TX_P3

HSMB_RX_P3

HSMB_TX_N3

HSMB_RX_N3

HSMB_TX_P4

HSMB_RX_P4

HSMB_TX_N4

HSMB_RX_N4

HSMB_TX_P5

HSMB_RX_P5

HSMB_TX_N5

HSMB_RX_N5

HSMB_TX_P6

HSMB_RX_P6

HSMB_TX_N6

HSMB_RX_N6

HSMB_TX_P7

HSMB_RX_P7

HSMB_TX_N7

HSMB_RX_N7

HSMB_CLK_OUT_P1

HSMB_CLK_IN_P1

HSMB_CLK_OUT_N1

HSMB_CLK_IN_N1

HSMB_TX_P8

I/O Standard

Stratix III

Pin Number

2.5 V AF32

2.5 V AF31

LVDS or 2.5 V P11

LVDS or 2.5 V R4

LVDS or 2.5 V P10

LVDS or 2.5 V R3

LVDS or 2.5 V T9

LVDS or 2.5 V P4

LVDS or 2.5 V T8

LVDS or 2.5 V P3

LVDS or 2.5 V T7

LVDS or 2.5 V P2

LVDS or 2.5 V U6

LVDS or 2.5 V R1

LVDS or 2.5 V T5

LVDS or 2.5 V N2

LVDS or 2.5 V T4

LVDS or 2.5 V P1

LVDS or 2.5 V R10

LVDS or 2.5 V M1

LVDS or 2.5 V R9

LVDS or 2.5 V N1

LVDS or 2.5 V R7

LVDS or 2.5 V L2

LVDS or 2.5 V R6

LVDS or 2.5 V L1

LVDS or 2.5 V N9

LVDS or 2.5 V K4

LVDS or 2.5 V N8

LVDS or 2.5 V K3

LVDS or 2.5 V M7

LVDS or 2.5 V J4

LVDS or 2.5 V M6

LVDS or 2.5 V J3

LVDS or 2.5 V P6

LVDS or 2.5 V N4

LVDS or 2.5 V P5

LVDS or 2.5 V N3

LVDS or 2.5 V L7

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–47

Components and Interfaces

Table 2–42. HSMC Port B Interface Signal Name, Description, and Type (Part 3 of 4)

Board

Reference

Description

J8 pin 102 LVDS RX or CMOS I/O bit 8

J8 pin 103 LVDS TX or CMOS I/O bit 8

J8 pin 104 LVDS RX or CMOS I/O bit 8

J8 pin 107 LVDS TX or CMOS I/O bit 9

J8 pin 108 LVDS TX or CMOS I/O bit 9

J8 pin 109 LVDS RX or CMOS I/O bit 9

J8 pin 110 LVDS RX or CMOS I/O bit 9

J8 pin 113 LVDS TX or CMOS I/O bit 10

J8 pin 114 LVDS RX or CMOS I/O bit 10

J8 pin 115 LVDS TX or CMOS I/O bit 10

J8 pin 116 LVDS RX or CMOS I/O bit 10

J8 pin 119 LVDS TX or CMOS I/O bit 11

J8 pin 120 LVDS RX or CMOS I/O bit 11

J8 pin 121 LVDS TX or CMOS I/O bit 11

J8 pin 122 LVDS RX or CMOS I/O bit 11

J8 pin 125 LVDS TX or CMOS I/O bit 12

J8 pin 126 LVDS RX or CMOS I/O bit 12

J8 pin 127 LVDS TX or CMOS I/O bit 12

J8 pin 128 LVDS RX or CMOS I/O bit 12

J8 pin 131 LVDS TX or CMOS I/O bit 13

J8 pin 132 LVDS RX or CMOS I/O bit 13

J8 pin 133 LVDS TX or CMOS I/O bit 13

J8 pin 134 LVDS RX or CMOS I/O bit 13

J8 pin 137 LVDS TX or CMOS I/O bit 14

J8 pin 138 LVDS RX or CMOS I/O bit 14

J8 pin 139 LVDS TX or CMOS I/O bit 14

J8 pin 140 LVDS RX or CMOS I/O bit 14

J8 pin 143 LVDS TX or CMOS I/O bit 15

J8 pin 144 LVDS RX or CMOS I/O bit 15

J8 pin 145 LVDS TX or CMOS I/O bit 15

J8 pin 146 LVDS RX or CMOS I/O bit 15

J8 pin 149 LVDS TX or CMOS I/O bit 16

J8 pin 150 LVDS RX or CMOS I/O bit 16

J8 pin 151 LVDS TX or CMOS I/O bit 16

J8 pin 152 LVDS RX or CMOS I/O bit 16

J8 pin 155 LVDS or CMOS clock out

J8 pin 156 LVDS or CMOS clock in

J8 pin 157 LVDS or CMOS clock out

J8 pin 158 LVDS or CMOS clock in

Schematic

Signal Name

HSMB_RX_P8

HSMB_TX_N8

HSMB_RX_N8

HSMB_TX_P9

HSMB_RX_P9

HSMB_TX_N9

HSMB_RX_N9

HSMB_TX_P10

HSMB_RX_P10

HSMB_TX_N10

HSMB_RX_N10

HSMB_TX_P11

HSMB_RX_P11

HSMB_TX_N11

HSMB_RX_N11

HSMB_TX_P12

HSMB_RX_P12

HSMB_TX_N12

HSMB_RX_N12

HSMB_TX_P13

HSMB_RX_P13

HSMB_TX_N13

HSMB_RX_N13

HSMB_TX_P14

HSMB_RX_P14

HSMB_TX_N14

HSMB_RX_N14

HSMB_TX_P15

HSMB_RX_P15

HSMB_TX_N15

HSMB_RX_N15

HSMB_TX_P16

HSMB_RX_P16

HSMB_TX_N16

HSMB_RX_N16

HSMB_CLK_OUT_P2

HSMB_CLK_IN_P2

HSMB_CLK_OUT_N2

HSMB_CLK_IN_N2

I/O Standard

Stratix III

Pin Number

LVDS or 2.5 V H2

LVDS or 2.5 V L6

LVDS or 2.5 V J1

LVDS or 2.5 V L5

LVDS or 2.5 V G2

LVDS or 2.5 V L4

LVDS or 2.5 V H1

LVDS or 2.5 V K6

LVDS or 2.5 V F1

LVDS or 2.5 V K5

LVDS or 2.5 V G1

LVDS or 2.5 V J7

LVDS or 2.5 V H4

LVDS or 2.5 V J6

LVDS or 2.5 V H3

LVDS or 2.5 V H6

LVDS or 2.5 V E2

LVDS or 2.5 V H5

LVDS or 2.5 V E1

LVDS or 2.5 V K8

LVDS or 2.5 V C1

LVDS or 2.5 V K7

LVDS or 2.5 V D1

LVDS or 2.5 V L8

LVDS or 2.5 V D3

LVDS or 2.5 V L8

LVDS or 2.5 V D2

LVDS or 2.5 V M10

LVDS or 2.5 V G5

LVDS or 2.5 V M9

LVDS or 2.5 V G4

LVDS or 2.5 V N11

LVDS or 2.5 V F4

LVDS or 2.5 V N10

LVDS or 2.5 V F3

LVDS R 12

LVDS U4

2.5 V T11

2.5 V U3

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–48 Chapter 2: Board Components

On-Board Memory

Table 2–42. HSMC Port B Interface Signal Name, Description, and Type (Part 4 of 4)

Board

Reference

N/A

Description

User LED intended to show RX Data activity on the HSMC

User LED intended to show TX Data activity on the HSMC

HSMB_RX_LED

HSMB_TX_LED

Schematic

Signal Name

The board provides both 12-V and 3.3-V power supply to install daughter cards up to

18.6 W each. Table 2–43 shows the maximum current allowed per voltage.

Table 2–43. HSMC Power Supply

Voltage Minimum Current From Host Minimum Wattage

12 V 1.0 A 12.0 W

3.3 V 2.0 A 6.6 W

Tab le 2– 44 lists HSMC component reference and manufacturing information.

Table 2–44. HSMC Component Reference and Manufacturing Information

Board Reference Description Manufacturer

J8 and J18

High-speed mezzanine card (HSMC), custom version of QSH-DP family high-speed socket

Samtec ASP-122953-01 www.samtec.com

I/O Standard

2.5 V AJ12

2.5 V AG34

Manufacturing

Manufacturer

Part Number

Stratix III

Pin Number

Website

On-Board Memory

This section describes the on-board memory interface support, and provides signal name, type, and signal connectivity relative to the Stratix III device.

The board has the following on-board memory:

■ “DDR2 SDRAM DIMM” on page 2–49

■ “DDR2 SDRAM Devices” on page 2–53

■ “QDRII+ SRAM ” on page 2–55

■ “P-SRAM” on page 2–58

■ “Flash Memory” on page 2–63

f For more information, refer to:

■ AN 435: Using DDR and DDR2 SDRAM in Stratix III and Stratix IV Devices

■ AN 438: Constraining and Analyzing Timing for External Memory Interfaces in

Stratix III and Cyclone III Devices

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–49

On-Board Memory

DDR2 SDRAM DIMM

The board has 1 GByte DDR2 SDRAM DIMM memory interface with a 72-bit data width on the vertical I/O banks, which is typically used as a 64-bit interface with the additional 8 bits serving as error correction coding (ECC) bits for each of the 8-byte lanes. The target frequency is 400 MHz (800 Mbps) with potential operation of up to 533 MHz (1,066 Mbps). The theoretical bandwidth of the entire DDR2 interface is 6,388 Mbps plus ECC, or 7,187 Mbps raw throughput.

The data interface to the FPGA fabric runs at either one-half or one-quarter the physical layer data rate when using the Altera DDR2 MegaCore equates to a doubling or quadrupling of the physical data bus width (144 bits or 288 bits, respectively). For example, a 72-bit interface with a 400-MHz external clock speed can have a 400-MHz 144-bit internal bus or a 200-MHz 288-bit interface.

Tab le 2– 45 lists the DDR2 DIMM interface signals. Signal names and type are relative

to the Stratix III device regarding the I/O setting and direction. JEDEC bus widths are used.

Table 2–45. DDR2 DIMM Interface I/O Signals (Part 1 of 4)

Board Reference Description

J19 pin 188 Address bit 0

J19 pin 183 Address bit 1

J19 pin 63 Address bit 2

J19 pin 182 Address bit 3

J19 pin 61 Address bit 4

J19 pin 60 Address bit 5

J19 pin 180 Address bit 6

J19 pin 58 Address bit 7

J19 pin 179 Address bit 8

J19 pin 177 Address bit 9

J19 pin 70 Address bit 10

J19 pin 57 Address bit 11

J19 pin 176 Address bit 12

J19 pin 196 Address bit 13

J19 pin 174 Address bit 14

J19 pin 173 Address bit 15

J19 pin 71 Bank address bit 0

J19 pin 190 Bank address bit 1

J19 pin 54 Bank address bit 2

J19 pin 125 Data write mask (byte enables) bit 0

J19 pin 134 Data write mask (byte enables) bit 1

J19 pin 146 Data write mask (byte enables) bit 2

J19 pin 155 Data write mask (byte enables) bit 3

J19 pin 202 Data write mask (byte enables) bit 4

Schematic

Signal Name

DDR2_DIMM_A0

DDR2_DIMM_A1

DDR2_DIMM_A2

DDR2_DIMM_A3

DDR2_DIMM_A4

DDR2_DIMM_A5

DDR2_DIMM_A6

DDR2_DIMM_A7

DDR2_DIMM_A8

DDR2_DIMM_A9

DDR2_DIMM_A10

DDR2_DIMM_A11

DDR2_DIMM_A12

DDR2_DIMM_A13

DDR2_DIMM_A14

DDR2_DIMM_A15

DDR2_DIMM_BA0

DDR2_DIMM_BA1

DDR2_DIMM_BA2

DDR2_DIMM_DM0

DDR2_DIMM_DM1

DDR2_DIMM_DM2

DDR2_DIMM_DM3

DDR2_DIMM_DM4

function, which

I/O Standard

SSTL-18 class I AM19

SSTL-18 class I AM18

SSTL-18 class I AF16

SSTL-18 class I AN16

SSTL-18 class I AM17

SSTL-18 class I AL19

SSTL-18 class I AK18

SSTL-18 class I AD16

SSTL-18 class I AE16

SSTL-18 class I AM16

SSTL-18 class I AH19

SSTL-18 class I AL16

SSTL-18 class I AF20

SSTL-18 class I AE23

SSTL-18 class I AG19

SSTL-18 class I AP12

SSTL-18 class I AN18

SSTL-18 class I AL17

SSTL-18 class I AD15

SSTL-18 class I AL12

SSTL-18 class I AP10

SSTL-18 class I AJ15

SSTL-18 class I AL22

SSTL-18 class I AE22

Stratix III

Pin Number

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–50 Chapter 2: Board Components

On-Board Memory

Table 2–45. DDR2 DIMM Interface I/O Signals (Part 2 of 4)

Board Reference Description

J19 pin 211 Data write mask (byte enables) bit 5

J19 pin 223 Data write mask (byte enables) bit 6

J19 pin 232 Data write mask (byte enables) bit 7

J19 pin 164 Data write mask (byte enables) bit 8

J19 pin 3 Data bit 0

J19 pin 4 Data bit 1

J19 pin 9 Data bit 2

J19 pin 10 Data bit 3

J19 pin 122 Data bit 4

J19 pin 123 Data bit 5

J19 pin 128 Data bit 6

J19 pin 129 Data bit 7

J19 pin 12 Data bit 8

J19 pin 13 Data bit 9

J19 pin 21 Data bit 10

J19 pin 22 Data bit 11

J19 pin 131 Data bit 12

J19 pin 132 Data bit 13

J19 pin 140 Data bit 14

J19 pin 141 Data bit 15

J19 pin 24 Data bit 16

J19 pin 25 Data bit 17

J19 pin 30 Data bit 18

J19 pin 31 Data bit 19

J19 pin 143 Data bit 20

J19 pin 144 Data bit 21

J19 pin 149 Data bit 22

J19 pin 150 Data bit 23

J19 pin 33 Data bit 24

J19 pin 34 Data bit 25

J19 pin 39 Data bit 26

J19 pin 40 Data bit 27

J19 pin 152 Data bit 28

J19 pin 153 Data bit 29

J19 pin 158 Data bit 30

J19 pin 159 Data bit 31

J19 pin 80 Data bit 32

J19 pin 81 Data bit 33

J19 pin 86 Data bit 34

Schematic

Signal Name

DDR2_DIMM_DM5

DDR2_DIMM_DM6

DDR2_DIMM_DM7

DDR2_DIMM_DM8

DDR2_DIMM_DQ0

DDR2_DIMM_DQ1

DDR2_DIMM_DQ2

DDR2_DIMM_DQ3

DDR2_DIMM_DQ4

DDR2_DIMM_DQ5

DDR2_DIMM_DQ6

DDR2_DIMM_DQ7

DDR2_DIMM_DQ8

DDR2_DIMM_DQ9

DDR2_DIMM_DQ10

DDR2_DIMM_DQ11

DDR2_DIMM_DQ12

DDR2_DIMM_DQ13

DDR2_DIMM_DQ14

DDR2_DIMM_DQ15

DDR2_DIMM_DQ16

DDR2_DIMM_DQ17

DDR2_DIMM_DQ18

DDR2_DIMM_DQ19

DDR2_DIMM_DQ20

DDR2_DIMM_DQ21

DDR2_DIMM_DQ22

DDR2_DIMM_DQ23

DDR2_DIMM_DQ24

DDR2_DIMM_DQ25

DDR2_DIMM_DQ26

DDR2_DIMM_DQ27

DDR2_DIMM_DQ28

DDR2_DIMM_DQ29

DDR2_DIMM_DQ30

DDR2_DIMM_DQ31

DDR2_DIMM_DQ32

DDR2_DIMM_DQ33

DDR2_DIMM_DQ34

I/O Standard

Stratix III

Pin Number

SSTL-18 class I AK27

SSTL-18 class I AJ28

SSTL-18 class I AP32

SSTL-18 class I AH23

SSTL-18 class I AP6

SSTL-18 class I AN7

SSTL-18 class I AK10

SSTL-18 class I AK12

SSTL-18 class I AM7

SSTL-18 class I AM8

SSTL-18 class I AM11

SSTL-18 class I AP8

SSTL-18 class I AE13

SSTL-18 class I AF13

SSTL-18 class I AP11

SSTL-18 class I AF15

SSTL-18 class I AE14

SSTL-18 class I AE15

SSTL-18 class I AP9

SSTL-18 class I AN10

SSTL-18 class I AN12

SSTL-18 class I AM12

SSTL-18 class I AG15

SSTL-18 class I AH15

SSTL-18 class I AN13

SSTL-18 class I AP13

SSTL-18 class I AP14

SSTL-18 class I AK15

SSTL-18 class I AJ21

SSTL-18 class I AM22

SSTL-18 class I AN21

SSTL-18 class I AP21

SSTL-18 class I AJ20

SSTL-18 class I AK21

SSTL-18 class I AP20

SSTL-18 class I AM21

SSTL-18 class I AE20

SSTL-18 class I AF21

SSTL-18 class I AP24

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–51

On-Board Memory

Table 2–45. DDR2 DIMM Interface I/O Signals (Part 3 of 4)

Board Reference Description

J19 pin 87 Data bit 35

J19 pin 199 Data bit 36

J19 pin 200 Data bit 37

J19 pin 205 Data bit 38

J19 pin 206 Data bit 39

J19 pin 89 Data bit 40

J19 pin 90 Data bit 41

J19 pin 95 Data bit 42

J19 pin 96 Data bit 43

J19 pin 208 Data bit 44

J19 pin 209 Data bit 45

J19 pin 214 Data bit 46

J19 pin 215 Data bit 47

J19 pin 98 Data bit 48

J19 pin 99 Data bit 49

J19 pin 107 Data bit 50

J19 pin 108 Data bit 51

J19 pin 217 Data bit 52

J19 pin 218 Data bit 53

J19 pin 226 Data bit 54

J19 pin 227 Data bit 55

J19 pin 110 Data bit 56

J19 pin 111 Data bit 57

J19 pin 116 Data bit 58

J19 pin 117 Data bit 59

J19 pin 229 Data bit 60

J19 pin 230 Data bit 61

J19 pin 235 Data bit 62

J19 pin 236 Data bit 63

J19 pin 42 Data bit 64

J19 pin 43 Data bit 65

J19 pin 48 Data bit 66

J19 pin 49 Data bit 67

J19 pin 161 Data bit 68

J19 pin 162 Data bit 69

J19 pin 167 Data bit 70

J19 pin 168 Data bit 71

J19 pin 6 Data strobe bit 0

J19 pin 15 Data strobe bit 1

Schematic

Signal Name

DDR2_DIMM_DQ35

DDR2_DIMM_DQ36

DDR2_DIMM_DQ37

DDR2_DIMM_DQ38

DDR2_DIMM_DQ39

DDR2_DIMM_DQ40

DDR2_DIMM_DQ41

DDR2_DIMM_DQ42

DDR2_DIMM_DQ43

DDR2_DIMM_DQ44

DDR2_DIMM_DQ45

DDR2_DIMM_DQ46

DDR2_DIMM_DQ47

DDR2_DIMM_DQ48

DDR2_DIMM_DQ49

DDR2_DIMM_DQ50

DDR2_DIMM_DQ51

DDR2_DIMM_DQ52

DDR2_DIMM_DQ53

DDR2_DIMM_DQ54

DDR2_DIMM_DQ55

DDR2_DIMM_DQ56

DDR2_DIMM_DQ57

DDR2_DIMM_DQ58

DDR2_DIMM_DQ59

DDR2_DIMM_DQ60

DDR2_DIMM_DQ61

DDR2_DIMM_DQ62

DDR2_DIMM_DQ63

DDR2_DIMM_DQ64

DDR2_DIMM_DQ65

DDR2_DIMM_DQ66

DDR2_DIMM_DQ67

DDR2_DIMM_DQ68

DDR2_DIMM_DQ69

DDR2_DIMM_DQ70

DDR2_DIMM_DQ71

DDR2_DIMM_DQS_N0

DDR2_DIMM_DQS_N1

I/O Standard

Stratix III

Pin Number

SSTL-18 class I AP26

SSTL-18 class I AD21

SSTL-18 class I AE21

SSTL-18 class I AP23

SSTL-18 class I AN24

SSTL-18 class I AP27

SSTL-18 class I AN27

SSTL-18 class I AL28

SSTL-18 class I AK25

SSTL-18 class I AM26

SSTL-18 class I AL26

SSTL-18 class I AP29

SSTL-18 class I AM28

SSTL-18 class I AN30

SSTL-18 class I AM30

SSTL-18 class I AJ26

SSTL-18 class I AH27

SSTL-18 class I AM29

SSTL-18 class I AL29

SSTL-18 class I AJ29

SSTL-18 class I AJ27

SSTL-18 class I AF24

SSTL-18 class I AG24

SSTL-18 class I AF23

SSTL-18 class I AN31

SSTL-18 class I AH25

SSTL-18 class I AH26

SSTL-18 class I AP31

SSTL-18 class I AP30

SSTL-18 class I AH22

SSTL-18 class I AM23

SSTL-18 class I AJ23

SSTL-18 class I AJ24

SSTL-18 class I AK22

SSTL-18 class I AL23

SSTL-18 class I AL25

SSTL-18 class I AK24

SSTL-18 class I AL11

SSTL-18 class I AN9

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–52 Chapter 2: Board Components

On-Board Memory

Table 2–45. DDR2 DIMM Interface I/O Signals (Part 4 of 4)

Board Reference Description

J19 pin 27 Data strobe bit 2

J19 pin 36 Data strobe bit 3

J19 pin 83 Data strobe bit 4

J19 pin 92 Data strobe bit 5

J19 pin 104 Data strobe bit 6

J19 pin 113 Data strobe bit 7

J19 pin 45 Data strobe bit 8

J19 pin 7 Data strobe bit 0

J19 pin 16 Data strobe bit 1

J19 pin 28 Data strobe bit 2

J19 pin 37 Data strobe bit 3

J19 pin 84 Data strobe bit 4

J19 pin 93 Data strobe bit 5

J19 pin 105 Data strobe bit 6

J19 pin 114 Data strobe bit 7

J19 pin 46 Data strobe bit 8

J19 pin 195 On-die termination control bit 0

J19 pin 77 On-die termination control bit 1

J19 pin 52 Clock enable bit 0

J19 pin 171 Clock enable bit 1

J19 pin 186 Differential output clock 0

J19 pin 138 Differential output clock 1

J19 pin 221 Differential output clock 2

J19 pin 185 Differential output clock 0

J19 pin 137 Differential output clock 1

J19 pin 220 Differential output clock 2

J19 pin 193 Chip select

J19 pin 76 Chip select

J19 pin 74 Column address strobe

J19 pin 192 Row address strobe

J19 pin 18 Reset

J19 pin 120 Presence-detect clock

J19 pin 119 Presence-detect data

J19 pin 73 Write enable

Schematic

Signal Name

DDR2_DIMM_DQS_N2

DDR2_DIMM_DQS_N3

DDR2_DIMM_DQS_N4

DDR2_DIMM_DQS_N5

DDR2_DIMM_DQS_N6

DDR2_DIMM_DQS_N7

DDR2_DIMM_DQS_N8

DDR2_DIMM_DQS_P0

DDR2_DIMM_DQS_P1

DDR2_DIMM_DQS_P2

DDR2_DIMM_DQS_P3

DDR2_DIMM_DQS_P4

DDR2_DIMM_DQS_P5

DDR2_DIMM_DQS_P6

DDR2_DIMM_DQS_P7

DDR2_DIMM_DQS_P8

DDR2_DIMM_ODT0

DDR2_DIMM_ODT1

DDR2_DIMM_CKE0

DDR2_DIMM_CKE1

DDR2_DIMM_CLK_N0

DDR2_DIMM_CLK_N1

DDR2_DIMM_CLK_N2

DDR2_DIMM_CLK_P0

DDR2_DIMM_CLK_P1

DDR2_DIMM_CLK_P2

DDR2_DIMM_CSn0

DDR2_DIMM_CSn1

DDR2_DIMM_CASn

DDR2_DIMM_RASn

DDR2_DIMM_RESETn

DDR2_DIMM_SCL

DDR2_DIMM_SDA

DDR2_DIMM_WEn

I/O Standard

Stratix III

Pin Number

SSTL-18 class I AJ14

SSTL-18 class I AP22

SSTL-18 class I AP25

SSTL-18 class I AP28

SSTL-18 class I AM32

SSTL-18 class I AP33

SSTL-18 class I AM24

SSTL-18 class I AL10

SSTL-18 class I AM9

SSTL-18 class I AH14

SSTL-18 class I AN22

SSTL-18 class I AN25

SSTL-18 class I AN28

SSTL-18 class I AM31

SSTL-18 class I AN33

SSTL-18 class I AL24

SSTL-18 class I AE19

SSTL-18 class I AD19

SSTL-18 class I AJ16

SSTL-18 class I AP7

SSTL-18 class I AM14

SSTL-18 class I AL13

SSTL-18 class I AM15

SSTL-18 class I AL14

SSTL-18 class I AK13

SSTL-18 class I AL15

SSTL-18 class I AG21

SSTL-18 class I AC22

SSTL-18 class I AD18

SSTL-18 class I AN19

SSTL-18 class I AE18

SSTL-18 class I AN15

SSTL-18 class I AK19

SSTL-18 class I AJ19

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–53

On-Board Memory

Tab le 2– 46 lists the DDR2 SDRAM DIMM component reference and manufacturing

information.

Table 2–46. DDR2 SDRAM DIMM Component Reference and Manufacturing Information

Board Reference Description Manufacturer

J19

400 MHz DIMM for 128 M × 72 (1 GByte plus ECC)

Micron Technology, Inc.

DDR2 SDRAM Devices

The board supports two independent 8-bit DDR2 SDRAM interfaces on the horizontal I/O banks.

The target speed on the side bank is 300-MHz DDR.

Tab le 2– 47 lists the DDR2 device A interface signals. JEDEC bus widths are used. Tab le 2– 47 also shows a summary of the required number of pins to support the

largest possible DDR2 devices available in a ×8 data configuration.

Table 2–47. DDR2 Device A Interface I/O (Part 1 of 2)

Board Reference Description

U17 pin H8 Address bit 0

U17 pin H3 Address bit 1

U17 pin H7 Address bit 2

U17 pin J2 Address bit 3

U17 pin J8 Address bit 4

U17 pin J3 Address bit 5

U17 pin J7 Address bit 6

U17 pin K2 Address bit 7

U17 pin K8 Address bit 8

U17 pin K3 Address bit 9

U17 pin H2 Address bit 10

U17 pin K7 Address bit 11

U17 pin L2 Address bit 12

U17 pin L8 Address bit 13

U17 pin L3 Address bit 14

U17 pin G2 Bank address bit 0

U17 pin G3 Bank address bit 1

U17 pin G1 Bank address bit 2

U17 pin C8 Data bit 0

U17 pin C2 Data bit 1

U17 pin D7 Data bit 2

U17 pin D3 Data bit 3

U17 pin D1 Data bit 4

Schematic

Signal Name

DDR2_DEVA_A0

DDR2_DEVA_A1

DDR2_DEVA_A2

DDR2_DEVA_A3

DDR2_DEVA_A4

DDR2_DEVA_A5

DDR2_DEVA_A6

DDR2_DEVA_A7

DDR2_DEVA_A8

DDR2_DEVA_A9

DDR2_DEVA_A10

DDR2_DEVA_A11

DDR2_DEVA_A12

DDR2_DEVA_A13

DDR2_DEVA_A14

DDR2_DEVA_BA0

DDR2_DEVA_BA1

DDR2_DEVA_BA2

DDR2_DEVA_DQ0

DDR2_DEVA_DQ1

DDR2_DEVA_DQ2

DDR2_DEVA_DQ3

DDR2_DEVA_DQ4

Manufacturing

Part Number

MT9HTF12872AY-800 www.micron.com

I/O

Standard

SSTL-18 class I U22-F34

SSTL-18 class I U22-G34

SSTL-18 class I U22-G31

SSTL-18 class I U22-N24

SSTL-18 class I U22-L29

SSTL-18 class I U22-M30

SSTL-18 class I U22-L31

SSTL-18 class I U22-P25

SSTL-18 class I U22-K33

SSTL-18 class I U22-M29

SSTL-18 class I U22-J34

SSTL-18 class I U22-L32

SSTL-18 class I U22-P23

SSTL-18 class I U22-M26

SSTL-18 class I U22-N26

SSTL-18 class I U22-H34

SSTL-18 class I U22-K30

SSTL-18 class I U22-J33

SSTL-18 class I U22-K27

SSTL-18 class I U22-J30

SSTL-18 class I U22-K28

SSTL-18 class I U22-J29

SSTL-18 class I U22-H32

Manufacturer

Website

Stratix III

Pin Number

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–54 Chapter 2: Board Components

On-Board Memory

Table 2–47. DDR2 Device A Interface I/O (Part 2 of 2)

Board Reference Description

U17 pin D9 Data bit 5

U17 pin B1 Data bit 6

U17 pin B9 Data bit 7

U17 pin A8 Data strobe

U17 pin B7 Data strobe

U17 pin F8 Differential output clock

U17 pin E8 Differential output clock

U17 pin F2 Clock enable

U17 pin G8 Chip select

U17 pin F3 Write enable

U17 pin G7 Column address strobe

U17 pin F7 Row address strobe

U17 pin B3 Data write mask

U17 pin F9 On-die termination control pin

Schematic

Signal Name

DDR2_DEVA_DQ5

DDR2_DEVA_DQ6

DDR2_DEVA_DQ7

DDR2_DEVA_DQS_N

DDR2_DEVA_DQS_P

DDR2_DEVA_CK_N

DDR2_DEVA_CK_P

DDR2_DEVA_CKE

DDR2_DEVA_CSn

DDR2_DEVA_WEn

DDR2_DEVA_CASn

DDR2_DEVA_RASn

DDR2_DEVA_DM

DDR2_DEVA_ODT

SSTL-18 class I U22-M24

SSTL-18 class I U22-H31

SSTL-18 class I U22-N25

SSTL-18 class I U22-C34

SSTL-18 class I U22-C33

SSTL-18 class I U22-K32

SSTL-18 class I U22-K31

SSTL-18 class I U22-M27

SSTL-18 class I U22-E34

SSTL-18 class I U22-G33

SSTL-18 class I U22-G30

SSTL-18 class I U22-F32

SSTL-18 class I U22-F31

SSTL-18 class I U22-M28

I/O

Standard

Tab le 2– 48 lists the DDR2 SDRAM devices A and B component reference and

manufacturing information.

Table 2–48. DDR2 SDRAM Devices A and B Component Reference and Manufacturing Information

Stratix III

Pin Number

Board Reference Description Manufacturer

U17, U20

333 MHz devices for 32M ×8 (256 MBytes)

Micron Technology, Inc. MT47H32M8BP-3:B www.micron.com

Tab le 2– 49 lists the DDR2 device B interface signals. JEDEC bus widths are used.

Table 2–49. DDR2 Device B Interface I/O (Part 1 of 2)

Board Reference Description

U20 pin H8 Address bit 0

U20 pin H3 Address bit 1

U20 pin H7 Address bit 2

U20 pin J2 Address bit 3

U20 pin J8 Address bit 4

U20 pin J3 Address bit 5

U20 pin J7 Address bit 6

U20 pin K2 Address bit 7

U20 pin K8 Address bit 8

U20 pin K3 Address bit 9

U20 pin H2 Address bit 10

U20 pin K7 Address bit 11

DDR2_DEVB_A0

DDR2_DEVB_A1

DDR2_DEVB_A2

DDR2_DEVB_A3

DDR2_DEVB_A4

DDR2_DEVB_A5

DDR2_DEVB_A6

DDR2_DEVB_A7

DDR2_DEVB_A8

DDR2_DEVB_A9

DDR2_DEVB_A10

DDR2_DEVB_A11

Schematic

Signal Name

Manufacturing

Part Number

I/O

Standard

SSTL-18 class I U22-R27

SSTL-18 class I U22-R29

SSTL-18 class I U22-J31

SSTL-18 class I U22-U32

SSTL-18 class I U22-K34

SSTL-18 class I U22-T23

SSTL-18 class I U22-M34

SSTL-18 class I U22-U31

SSTL-18 class I U22-R24

SSTL-18 class I U22-V31

SSTL-18 class I U22-P34

SSTL-18 class I U22-T29

Manufacturer

Website

Stratix III

Pin Number

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–55

On-Board Memory

Table 2–49. DDR2 Device B Interface I/O (Part 2 of 2)

Board Reference Description

U20 pin L2 Address bit 12

U20 pin L8 Address bit 13

U20 pin L3 Address bit 14

U20 pin G2 Bank address bit 0

U20 pin G3 Bank address bit 1

U20 pin G1 Bank address bit 2

U20 pin C8 Data bit 0

U20 pin C2 Data bit 1

U20 pin D7 Data bit 2

U20 pin D3 Data bit 3

U20 pin D1 Data bit 4

U20 pin D9 Data bit 5

U20 pin B1 Data bit 6

U20 pin B9 Data bit 7

U20 pin A8 Data strobe

U20 pin B7 Data strobe

U20 pin F8 Differential output clock

U20 pin E8 Differential output clock

U20 pin F2 Clock enable

U20 pin G8 Chip select

U20 pin F3 Write enable

U20 pin G7 Column address strobe

U20 pin F7 Row address strobe

U20 pin B3 Data write mask

U20 pin F9 On-die termination control pin

Schematic

Signal Name

DDR2_DEVB_A12

DDR2_DEVB_A13

DDR2_DEVB_A14

DDR2_DEVB_BA0

DDR2_DEVB_BA1

DDR2_DEVB_BA2

DDR2_DEVB_DQ0

DDR2_DEVB_DQ1

DDR2_DEVB_DQ2

DDR2_DEVB_DQ3

DDR2_DEVB_DQ4

DDR2_DEVB_DQ5

DDR2_DEVB_DQ6

DDR2_DEVB_DQ7

DDR2_DEVB_DQS_N

DDR2_DEVB_DQS_P

DDR2_DEVB_CK_N

DDR2_DEVB_CK_P

DDR2_DEVB_CKE

DDR2_DEVB_CSn

DDR2_DEVB_WEn

DDR2_DEVB_CASn

DDR2_DEVB_RASn

DDR2_DEVB_DM

DDR2_DEVB_ODT

I/O

Standard

SSTL-18 class I U22-V32

SSTL-18 class I U22-R28

SSTL-18 class I U22-T30

SSTL-18 class I U22-N32

SSTL-18 class I U22-N33

SSTL-18 class I U22-R30

SSTL-18 class I U22-P29

SSTL-18 class I U22-P32

SSTL-18 class I U22-N30

SSTL-18 class I U22-N31

SSTL-18 class I U22-R26

SSTL-18 class I U22-P28

SSTL-18 class I U22-R25

SSTL-18 class I U22-N29

SSTL-18 class I U22-L34

SSTL-18 class I U22-M33

SSTL-18 class I U22-R32

SSTL-18 class I U22-P31

SSTL-18 class I U22-N34

SSTL-18 class I U22-J32

SSTL-18 class I U22-T26

SSTL-18 class I U22-U25

SSTL-18 class I U22-D33

SSTL-18 class I U22-M31

SSTL-18 class I U22-D34

Stratix III

Pin Number

QDRII+ SRAM

The board uses a burst-of-4 QDRII memory device for high-speed, low-latency memory access. The interface provides addressing for a 72-Mbit device. The actual device used may be 18, 36, or 72 Mbits. Because the Stratix III device supports 18 DQ/DQS group, the board uses a ×18 QDRII or QDRII+ SRAM device. QDRII+ SRAM is needed to support a QDRII rate that is greater than 300 MHz.

QDRII has separate read and write data ports with DDR interfaces operating up to 300 MHz. QDRII+ has separate read and write data ports with DDR interfaces operating up to 350 MHz. Burst-of-2 devices have a DDR address bus allowing for different read and write addresses on every clock (two data words per clock). Burst-of-4 devices have higher data rates due to the longer sequential addressing.

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–56 Chapter 2: Board Components

On-Board Memory

For QDRII devices, the interface supports 10.8 Gbps of throughput at 300 MHz (600 Mbps × 18 pins). The QDRII bandwidth doubles to 21.6 Gbps when considering combined read and write bandwidth. For QDRII+ devices, the interface supports

12.6 Gbps of throughput at 350 MHz (700 Mbps × 18 pins). The QDRII+ bandwidth doubles to 25.2 Gbps when considering combined read and write bandwidth.

Tab le 2– 50 lists the QDRII interface pins.

Table 2–50. QDRII Interface Pins (Part 1 of 2)

Board Reference Description

U15 pin A9 Address bit 0

U15 pin B4 Address bit 1

U15 pin B8 Address bit 2

U15 pin C5 Address bit 3

U15 pin C7 Address bit 4

U15 pin N5 Address bit 5

U15 pin N6 Address bit 6

U15 pin N7 Address bit 7

U15 pin P4 Address bit 8

U15 pin P5 Address bit 9

U15 pin P7 Address bit 10

U15 pin P8 Address bit 11

U15 pin R3 Address bit 12

U15 pin R4 Address bit 13

U15 pin R5 Address bit 14

U15 pin R7 Address bit 15

U15 pin R8 Address bit 16

U15 pin R9 Address bit 17

U15 pin A3 Address bit 18

U15 pin A10 Address bit 19

U15 pin P10 Write data bit 0

U15 pin N11 Write data bit 1

U15 pin M11 Write data bit 2

U15 pin K10 Write data bit 3

U15 pin J11 Write data bit 4

U15 pin G11 Write data bit 5

U15 pin E10 Write data bit 6

U15 pin D11 Write data bit 7

U15 pin C11 Write data bit 8

U15 pin B3 Write data bit 9

U15 pin C3 Write data bit 10

U15 pin D2 Write data bit 11

Schematic Signal

Name

QDRII_A0

QDRII_A1

QDRII_A2

QDRII_A3

QDRII_A4

QDRII_A5

QDRII_A6

QDRII_A7

QDRII_A8

QDRII_A9

QDRII_A10

QDRII_A11

QDRII_A12

QDRII_A13

QDRII_A14

QDRII_A15

QDRII_A16

QDRII_A17

QDRII_A18

QDRII_A19

QDRII_D0

QDRII_D1

QDRII_D2

QDRII_D3

QDRII_D4

QDRII_D5

QDRII_D6

QDRII_D7

QDRII_D8

QDRII_D9

QDRII_D10

QDRII_D11

I/O

Standard

Stratix III

Number

1.5-V HSTL class I C17

1.5-V HSTL class I C14

1.5-V HSTL class I C16

1.5-V HSTL class I A14

1.5-V HSTL class I A15

1.5-V HSTL class I F14

1.5-V HSTL class I F15

1.5-V HSTL class I A13

1.5-V HSTL class I J15

1.5-V HSTL class I G16

1.5-V HSTL class I E14

1.5-V HSTL class I B14

1.5-V HSTL class I J16

1.5-V HSTL class I H16

1.5-V HSTL class I F12

1.5-V HSTL class I D14

1.5-V HSTL class I A10

1.5-V HSTL class I B13

1.5-V HSTL class I C15

1.5-V HSTL class I E17

1.5-V HSTL class I A9

1.5-V HSTL class I B10

1.5-V HSTL class I B11

1.5-V HSTL class I A11

1.5-V HSTL class I E11

1.5-V HSTL class I A12

1.5-V HSTL class I C12

1.5-V HSTL class I D12

1.5-V HSTL class I D13

1.5-V HSTL class I L14

1.5-V HSTL class I K15

1.5-V HSTL class I K13

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–57

On-Board Memory

Table 2–50. QDRII Interface Pins (Part 2 of 2)

Board Reference Description

U15 pin F3 Write data bit 12

U15 pin G2 Write data bit 13

U15 pin J3 Write data bit 14

U15 pin L3 Write data bit 15

U15 pin M3 Write data bit 16

U15 pin N2 Write data bit 17

U15 pin P11 Read data bit 0

U15 pin M10 Read data bit 1

U15 pin L11 Read data bit 2

U15 pin K11 Read data bit 3

U15 pin J10 Read data bit 4

U15 pin F11 Read data bit 5

U15 pin E11 Read data bit 6

U15 pin C10 Read data bit 7

U15 pin B11 Read data bit 8

U15 pin B2 Read data bit 9

U15 pin D3 Read data bit 10

U15 pin E3 Read data bit 11

U15 pin F2 Read data bit 12

U15 pin G3 Read data bit 13

U15 pin K3 Read data bit 14

U15 pin L2 Read data bit 15

U15 pin N3 Read data bit 16

U15 pin P3 Read data bit 17

U15 pin B7 Byte write select bit 0

U15 pin A5 Byte write select bit 1

U15 pin A11 Echo clock

U15 pin A1 Echo clock

U15 pin A6 Write clock

U15 pin B6 Write clock

On-die termination

U15 pin R6

pin for future QDRII devices.

U15 pin P6 Valid output indicator

U15 pin A8 Read port select

U15 pin A4 Write port select

Schematic Signal

Name

QDRII_D12

QDRII_D13

QDRII_D14

QDRII_D15

QDRII_D16

QDRII_D17

QDRII_Q0

QDRII_Q1

QDRII_Q2

QDRII_Q3

QDRII_Q4

QDRII_Q5

QDRII_Q6

QDRII_Q7

QDRII_Q8

QDRII_Q9

QDRII_Q10

QDRII_Q11

QDRII_Q12

QDRII_Q13

QDRII_Q14

QDRII_Q15

QDRII_Q16

QDRII_Q17

QDRII_BWSn0

QDRII_BWSn1

QDRII_CQ_N

QDRII_CQ_P

QDRII_K_N

QDRII_K_P

QDRII_ODT

QDRII_QVLD

QDRII_RPSn

QDRII_WPSn

I/O

Standard

Stratix III

Number

1.5-V HSTL class I K14

1.5-V HSTL class I G13

1.5-V HSTL class I D10

1.5-V HSTL class I F11

1.5-V HSTL class I F13

1.5-V HSTL class I G12

1.5-V HSTL class I A3

1.5-V HSTL class I B4

1.5-V HSTL class I A4

1.5-V HSTL class I A5

1.5-V HSTL class I C6

1.5-V HSTL class I F8

1.5-V HSTL class I G9

1.5-V HSTL class I F9

1.5-V HSTL class I G10

1.5-V HSTL class I J12

1.5-V HSTL class I J11

1.5-V HSTL class I G8

1.5-V HSTL class I G11

1.5-V HSTL class I B2

1.5-V HSTL class I B5

1.5-V HSTL class I F6

1.5-V HSTL class I C5

1.5-V HSTL class I D6

1.5-V HSTL class I C11

1.5-V HSTL class I D11

1.5-V HSTL class I C4

1.5-V HSTL class I H11

1.5-V HSTL class I H14

1.5-V HSTL class I J14

1.5-V HSTL class I C3

1.5-V HSTL class I A2

1.5-V HSTL class I D17

1.5-V HSTL class I K16

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–58 Chapter 2: Board Components

On-Board Memory

Tab le 2– 51 lists the QDRII device component reference and manufacturing

information.

Table 2–51. QDRII Device Component Reference and Manufacturing Information

Board Reference Description Manufacturer

U15

400 MHz QDRII+ burst-of-4 device for 2M × 18

Cypress Semiconductor

P-SRAM

The board features 8 MBytes of P-SRAM memory with a 32-bit data bus. The devices use 1.8-V CMOS signaling and are optimized for low cost and power.

The 32-bit interface comprises two ×16 devices. The Samsung part features a maximum frequency of 104 MHz (104 Mbps). The theoretical bandwidth of the entire interface is 416 Mbps.

The P-SRAM devices are part of a shared bus with connectivity to the MAX II CPLD as well as the flash memory, which is called the FSM bus. All three devices use 1.8-V CMOS signaling. Altera recommends using the 5-Ω OCT setting on the FPGA and the one-half drive setting on the SRAM.

Tab le 2– 52 lists the P-SRAM interface signal name, description, and signal type.

Table 2–52. P-SRAM Device Pin-Out (Part 1 of 4)

Board Reference Description

U4 and U10 pin A3

U4 and U10 pin A4

U4 and U10 pin A5

U4 and U10 pin B3

U4 and U10 pin B4

U4 and U10 pin C3

U4 and U10 pin C4

U4 and U10 pin D4

U4 and U10 pin H2

U4 and U10 pin H3

Address bus shared with flash and P-SRAM bit 1

Address bus shared with flash and P-SRAM bit 2

Address bus shared with flash and P-SRAM bit 3

Address bus shared with flash and P-SRAM bit 4

Address bus shared with flash and P-SRAM bit 5

Address bus shared with flash and P-SRAM bit 6

Address bus shared with flash and P-SRAM bit 7

Address bus shared with flash and P-SRAM bit 8

Address bus shared with flash and P-SRAM bit 9

Address bus shared with flash and P-SRAM bit 10

CY7C1263V18-400BZXCES www.cypress.com

Schematic

Signal Name

FSM_A1

FSM_A2

FSM_A3

FSM_A4

FSM_A5

FSM_A6

FSM_A7

FSM_A8

FSM_A9

FSM_A10

Manufacturing

Part Number

I/O

Standard

1.8 V H23

1.8 V G23

1.8 V F23

1.8 V D27

1.8 V D28

1.8 V F25

1.8 V F26

1.8 V G24

1.8 V F24

1.8 V E26

Stratix III

Device

Number

Manufacturer

Website

Other

Connections

U5 pin T8 and U9

pin B1

U5 pin T9 and U9

pin C1

U5 pin R9 and U9

pin D1

U5 pin P9 and U9

pin D2

U5 pin T10 and

U9 pin A2

U5 pin P13 and

U9 pin C2

U5 pin R10 and

U9 pin A3

U5 pin M10 and

U9 pin B3

U5 pin M11 and

U9 pin C3

U5 pin N10 and

U9 pin C4

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–59

On-Board Memory

Table 2–52. P-SRAM Device Pin-Out (Part 2 of 4)

Stratix III

Board Reference Description

Schematic

Signal Name

I/O

Standard

Device

Other

Connections

Number

U4 and U10 pin H4

U4 and U10 pin H5

U4 and U10 pin G3

U4 and U10 pin G4

U4 and U10 pin F3

U4 and U10 pin F4

U4 and U10 pin E4

U4 and U10 pin D3

U4 and U10 pin H1

U4 and U10 pin G2

U4 and U10 pin H6

U4 pin B6

U4 pin C5

U4 pin C6

U4 pin D5

U4 pin E5

U4 pin F5

U4 pin F6

U4 pin G6

U4 pin B1

U4 pin C1

Address bus shared with flash and P-SRAM bit 11

Address bus shared with flash and P-SRAM bit 12

Address bus shared with flash and P-SRAM bit 13

Address bus shared with flash and P-SRAM bit 14

Address bus shared with flash and P-SRAM bit 15

Address bus shared with flash and P-SRAM bit 16

Address bus shared with flash and P-SRAM bit 17

Address bus shared with flash and P-SRAM bit 18

Address bus shared with flash and P-SRAM bit 19

Address bus shared with flash and P-SRAM bit 20

Address bus shared with flash and P-SRAM bit 21

Data bus shared with flash and P-SRAM bit 0

Data bus shared with flash and P-SRAM bit 1

Data bus shared with flash and P-SRAM bit 2

Data bus shared with flash and P-SRAM bit 3

Data bus shared with flash and P-SRAM bit 4

Data bus shared with flash and P-SRAM bit 5

Data bus shared with flash and P-SRAM bit 6

Data bus shared with flash and P-SRAM bit 7

Data bus shared with flash and P-SRAM bit 8

Data bus shared with flash and P-SRAM bit 9

FSM_A11

FSM_A12

FSM_A13

FSM_A14

FSM_A15

FSM_A16

FSM_A17

FSM_A18

FSM_A19

FSM_A20

FSM_A21

FSM_D0

FSM_D1

FSM_D2

FSM_D3

FSM_D4

FSM_D5

FSM_D6

FSM_D7

FSM_D8

FSM_D9

1.8 V D26

1.8 V A30

1.8 V A33

1.8 V B31

1.8 V A31

1.8 V B32

1.8 V A32

1.8 V M23

1.8 V L23

1.8 V B29

1.8 V C29

1.8 V G27

1.8 V F28

1.8 V E28

1.8 V D30

1.8 V C30

1.8 V F29

1.8 V E29

1.8 V J24

1.8 V J25

1.8 V A24

U5 pin R11 and

U9 pin C4

U5 pin P10 and

U9 pin A12

U5 pin T12 and

U9 pin B5

U5 pin M11 and

U9 pin C5

U5 pin R12 and

U9 pin D7

U5 pin N11 and

U9 pin D8

U5 pin T13 and

U9 pin A7

U5 pin P11 and

U9 pin B7

U5 pin R13 and

U9 pin C7

U5 pin M1 and U9

pin C8

U5 pin R14 and

U9 pin A8

U5 pin P4 and U9

pin E4

U5 pin R1 and U9

pin E5

U5 pin P5 and U9

pin G5

U5 pin T2 and U9

pin G6

U5 pin N5 and U9

pin H7

U5 pin R3 and U9

pin E1

U5 pin P6 and U9

pin E3

U5 pin R4 and U9

pin F3

U5 pin N6 and U9

pin F4

U5 pin T4 and U9

pin F5

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–60 Chapter 2: Board Components

On-Board Memory

Table 2–52. P-SRAM Device Pin-Out (Part 3 of 4)

Stratix III

Board Reference Description

Schematic

Signal Name

I/O

Standard

Device

Other

Connections

Number

U4 pin C2

U4 pin D2

U4 pin E2

U4 pin F2

U4 pin F1

U4 pin G1

U10 pin B6

U10 pin C5

U10 pin C6

U10 pin D5

U10 pin E5

U10 pin F5

U10 pin F6

U10 pin G6

U10 pin B1

U10 pin C1

U10 pin C2

U10 pin D2

U10 pin E2

U10 pin F2

U10 pin F1

Data bus shared with flash and P-SRAM bit 10

Data bus shared with flash and P-SRAM bit 11

Data bus shared with flash and P-SRAM bit 12

Data bus shared with flash and P-SRAM bit 13

Data bus shared with flash and P-SRAM bit 14

Data bus shared with flash and P-SRAM bit 15

Data bus shared with flash and P-SRAM bit 16

Data bus shared with flash and P-SRAM bit 17

Data bus shared with flash and P-SRAM bit 18

Data bus shared with flash and P-SRAM bit 19

Data bus shared with flash and P-SRAM bit 20

Data bus shared with flash and P-SRAM bit 21

Data bus shared with flash and P-SRAM bit 22

Data bus shared with flash and P-SRAM bit 23

Data bus shared with flash and P-SRAM bit 24

Data bus shared with flash and P-SRAM bit 25

Data bus shared with flash and P-SRAM bit 26

Data bus shared with flash and P-SRAM bit 27

Data bus shared with flash and P-SRAM bit 28

Data bus shared with flash and P-SRAM bit 29

Data bus shared with flash and P-SRAM bit 30

FSM_D10

FSM_D11

FSM_D12

FSM_D13

FSM_D14

FSM_D15

FSM_D16

FSM_D17

FSM_D18

FSM_D19

FSM_D20

FSM_D21

FSM_D22

FSM_D23

FSM_D24

FSM_D25

FSM_D26

FSM_D27

FSM_D28

FSM_D29

FSM_D30

1.8 V A26

1.8 V B25

1.8 V A25

1.8 V J20

1.8 V K20

1.8 V K21

1.8 V K22 U5 pin M7

1.8 V C26 U5 pin T6

1.8 V B26 U5 pin P14

1.8 V J22 U5 pin R7

1.8 V J21 U5 pin P8

1.8 V C24 U5 pin T7

1.8 V E25 U5 pin N8

1.8 V D25 U5 pin R8

1.8 V D24 U5 pin F12

1.8 V A27 U5 pin D16

1.8 V A29 U5 pin F13

1.8 V C27 U5 pin D15

1.8 V C28 U5 pin F14

1.8 V E23 U5 pin D14

1.8 V D23 U5 pin E12

U5 pin M6 and U9

pin H5

U5 pin R5 and U9

pin G7

U5 pin P7 and U9

pin E7

U5 pin T5 and U9

pin H5

U5 pin N7 and U9

pin G7

U5 pin R6 and U9

pin E7

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–61

1st

Clock

Address

Data Out

Data In

Data In/Out

Data Out

Latency 4 (Burst Length: 8)

Fixed Latency - A18[0]

Variable Latency - A18[1]

Latency 2 (Burst Length: 8)

2nd 3rd 4th 5th

D0 D1 D2

6th 7th 8th 9th 10th 11th

D3 D4

D5 D6 D7

D0 D1 D2 D3 D4

D5 D6 D7

Q0 Q1 Q2 Q3 Q4

Q5 Q6 Q7

DQ0 DQ1 DQ2 DQ3 DQ4

DQ5 DQ6 DQ7

ADV

On-Board Memory

Table 2–52. P-SRAM Device Pin-Out (Part 4 of 4)

Stratix III

Board Reference Description

Schematic

Signal Name

I/O

Standard

Device

Other

Connections

Number

U10 pin G1

U10 and U4 pin J3 Address valid

U4 pin A1 Byte write select bit 0

U4 pin B2 Byte write select bit 1

U10 pin A1 Byte write select bit 2

U10 pin B2 Byte write select bit 3

U10 and U4 pin J2 Clock

U10 and U4 pin B5 Chip select

U10 and U4 pin A2 Output enable

U10 and U4 pin A6 Power save mode

U4 pin J1 Data wait

U10 pin J1 Data wait

U10 and U4 pin G5 Write enable

Data bus shared with flash and P-SRAM bit 31

FSM_D31

SRAM_ADVn

SRAM_BEn0

SRAM_BEn1

SRAM_BEn2

SRAM_BEn3

SRAM_CLK

SRAM_CSn

SRAM_OEn

SRAM_PSn

SRAM_WAIT0

SRAM_WAIT1

SRAM_WEn

1.8 V B28 U5 pin C15

1.8 V D21 —

1.8 V D22 —

1.8 V E22 —

1.8 V E20 —

1.8 V H20 —

1.8 V C21 —

1.8 V A21 —

1.8 V A22 —

1.8 V AL18 —

1.8 V G20 —

1.8 V F20 —

1.8 V B22 —

Figure 2–17 illustrates the latency for both fixed and variable modes of operation. For

asynchronous accesses, each of the two devices has its own Stratix III device.

f For Samsung SRAM pin definitions, data sheet, and other related documentation,

refer to the Samsung website at www. samsung.com.

Figure 2–17. SRAM Latency Timing Illustration

WAIT

pin wired to the

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–62 Chapter 2: Board Components

On-Board Memory

Tab le 2– 53 lists the Samsung device latency values based on operation frequency.

Table 2–53. SRAM Latency Vs. Frequency

Item

Up to 66 MHz Up to 80 MHz Up to 104 MHz

Fixed Variable Fixed Variable Fixed Variable

Latency set (A11:A10:A9) 4(0:0:1) 2(1:0:0) 5(0:1:0) 3(0:0:0) 7(1:0:1) 4(0:0:1)

Read latency (min) 4 2/4 5 3/5th 7 4/7

First read data fetch clock 5th 3rd/5th 6th 4th/6th 8th 5th/8th

Write latency (min) 223344

First write data loading clock 3rd 3rd 3rd 4th 5th 5th

Figure 2–18 and Figure 2–19 show the Samsung device read and write access

waveforms.

Figure 2–18. SRAM Read Timing Waveforms

0123456789 10 11 12 13 14

CLK

ADV

ADDR

UB, LB

Data Out

WAIT

Figure 2–19. SRAM Write Timing Waveforms

01 2 3 4 5 67 8 9 10 11 12 13 14

CLK

ADV

ADDR

UB, LB

Data In

WAIT

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–63

On-Board Memory

Tab le 2– 54 lists the SRAM device component reference and manufacturing

information.

Table 2–54. SRAM Device Component Reference and Manufacturing Information

Board Reference Description Manufacturer

U4, U10

32 MBytes (2M × 16) of SRAM

Samsung Semiconductor K1B3216B2E-B170 www.samsung.com

Flash Memory

A 512-Mbit Intel P30 flash memory device is used to store configuration files for the FPGA as well as any other necessary data for the development board operation. The target device is a PC48F4400P0VB00 in a BGA package and it supports the common flash interface (CFI) commands. The flash, SSRAM, and the MAX II CPLD all support

1.8-V I/O, and all three devices share a common address and data bus. The default addressing mode is a 16-bit word mode. Byte mode requires driving

Tab le 2– 55 lists the required flash memory signals.

Table 2–55. Flash Interface I/O (Part 1 of 3)

Board

Reference

U9 pin B1

U9 pin C1

U9 pin D1

U9 pin D2

U9 pin A2

U9 pin C2

U9 pin A3

U9 pin B3

U9 pin C3

U9 pin D3

U9 pin C4

U9 pin A5

Description

Address bus shared with flash and P-SRAM bit 1

Address bus shared with flash and P-SRAM bit 2

Address bus shared with flash and P-SRAM bit 3

Address bus shared with flash and P-SRAM bit 4

Address bus shared with flash and P-SRAM bit 5

Address bus shared with flash and P-SRAM bit 6

Address bus shared with flash and P-SRAM bit 7

Address bus shared with flash and P-SRAM bit 8

Address bus shared with flash and P-SRAM bit 9

Address bus shared with flash and P-SRAM bit 10

Address bus shared with flash and P-SRAM bit 11

Address bus shared with flash and P-SRAM bit 12

Schematic Signal

Name

FSM_A1

FSM_A2

FSM_A3

FSM_A4

FSM_A5

FSM_A6

FSM_A7

FSM_A8

FSM_A9

FSM_A10

FSM_A11

FSM_A12

Standard

1.8 V H23

1.8 V G23

1.8 V F23

1.8 V D27

1.8 V D28

1.8 V F25

1.8 V F26

1.8 V G24

1.8 V F24

1.8 V E26

1.8 V D26

1.8 V A30

I/O

Manufacturing

Part Number

Stratix III

Number

Manufacturer

Website

BYTEn

low.

Other Connections

U5 pin T8 and U4 pin A3 and U10 pin A3 and U5 pin T8

U5 pin T9 and U4 pin A4 and U10 pin A4 and U5 pin T9

U5 pin R9 and U4 pin A5 and U10 pin A5 and U5 pin R9

U5 pin P9 and U4 pin B3 and U10 pin B3 and U5 pin P9

U5 pin T10 and U4 pin B4 and U10 pin B4 and U5 pin T10

U5 pin P13 and U4 pin C3 and U10 pin C3 and U5 pin P13

U5 pin R10 and U4 pin C4 and U10 pin C4 and U5 pin R10

U5 pin M10 and U4 pin D4 and U10 pin

D4 and U5 pin M10

U5 pin M11 and U4 pin H2 and U10 pin H2 and U5 pin M11

U5 pin N10 and U4 pin H3 and U10 pin H3 and U5 pin N10

U5 pin R11 and U4 pin H4 and U10 pin H4 and U5 pin R11

U5 pin P10 and U4 pin H5 and U10 pin H5 and U5 pin P10

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–64 Chapter 2: Board Components

On-Board Memory

Table 2–55. Flash Interface I/O (Part 2 of 3)

Board

Reference

U9 pin B5

U9 pin C5

U9 pin D7

U9 pin D8

U9 pin A7

U9 pin B7

U9 pin C7

U9 pin C8

U9 pin A8

U9 pin G1

U9 pin H8

U9 pin B6

U9 pin F2

U9 pin E2

U9 pin G3

U9 pin E4

U9 pin E5

U9 pin G5

U9 pin G6

U9 pin H7

U9 pin E1

U9 pin E3

Description

Address bus shared with flash and P-SRAM bit 13

Address bus shared with flash and P-SRAM bit 14

Address bus shared with flash and P-SRAM bit 15

Address bus shared with flash and P-SRAM bit 16

Address bus shared with flash and P-SRAM bit 17

Address bus shared with flash and P-SRAM bit 18

Address bus shared with flash and P-SRAM bit 19

Address bus shared with flash and P-SRAM bit 20

Address bus shared with flash and P-SRAM bit 21

Address bus shared with flash and P-SRAM bit 22

Address bus shared with flash and P-SRAM bit 23

Address bus shared with flash and P-SRAM bit 24

Data bus shared with flash and P-SRAM bit 0

Data bus shared with flash and P-SRAM bit 1

Data bus shared with flash and P-SRAM bit 2

Data bus shared with flash and P-SRAM bit 3

Data bus shared with flash and P-SRAM bit 4

Data bus shared with flash and P-SRAM bit 5

Data bus shared with flash and P-SRAM bit 6

Data bus shared with flash and P-SRAM bit 7

Data bus shared with flash and P-SRAM bit 8

Data bus shared with flash and P-SRAM bit 9

Schematic Signal

Name

FSM_A13

FSM_A14

FSM_A15

FSM_A16

FSM_A17

FSM_A18

FSM_A19

FSM_A20

FSM_A21

FSM_A22

FSM_A23

FSM_A24

FSM_D0

FSM_D1

FSM_D2

FSM_D3

FSM_D4

FSM_D5

FSM_D6

FSM_D7

FSM_D8

FSM_D9

I/O

Standard

1.8 V A33

1.8 V B31

1.8 V A31

1.8 V B32

1.8 V A32

1.8 V M23

1.8 V L23

1.8 V B29

1.8 V C29

Stratix III

Number

Other Connections

U5 pin T12 and U4 pin G3 and U10 pin G3 and U5 pin T12

U5 pin M11 and U4 pin G4 and U10 pin G4 and U5 pin M11

U5 pin R12 and U4 pin F3 and U10 pin F3 and U5 pin R12

U5 pin N11 and U4 pin F4 and U10 pin F4 and U5 pin N11

U5 pin T13 and U4 pin E4 and U10 pin E4 and U5 pin T13

U5 pin P11 and U4 pin D3 and U10 pin D3 and U5 pin P11

U5 pin R13 and U4 pin H1 and U10 pin H1 and U5 pin R13

U5 pin M1 and U4 pin G2 and U10 pin G2 and U5 pin M1

U5 pin R14 and U4 pin H6 and U10 pin H6 and U5 pin R14

1.8 V C31 U5 pin N12

1.8 V D31 U5 pin T15

1.8 V F27 U5 pin P12

1.8 V G27 U5 pin P4 and U4 pin B6

1.8 V F28 U5 pin R1 and U4 pin C5

1.8 V E28 U5 pin P5 and U4 pin C6

1.8 V D30 U5 pin T2 and U4 pin D5

1.8 V C30 U5 pin N5 and U4 pin E5

1.8 V F29 U5 pin R3 and U4 pin F5

1.8 V E29 U5 pin P6 and U4 pin F6

1.8 V J24 U5 pin R4 and U4 pin G6

1.8 V J25 U5 pin N6 and U4 pin B1

1.8 V A24 U5 pin T4 and U4 pin C1

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–65

On-Board Memory

Table 2–55. Flash Interface I/O (Part 3 of 3)

Board

Reference

U9 pin F3

U9 pin F4

U9 pin F5

U9 pin H5

U9 pin G7

U9 pin E7

Description

Data bus shared with flash and P-SRAM bit 10

Data bus shared with flash and P-SRAM bit 11

Data bus shared with flash and P-SRAM bit 12

Data bus shared with flash and P-SRAM bit 13

Data bus shared with flash and P-SRAM bit 14

Data bus shared with flash and P-SRAM bit 15

U9 pin E6 Clock

U9 pin F6 Address valid

U9 pin B4 Chip enable

U9 pin F8 Output enable

U9 pin F7 Ready/busy

U9 pin D4 Reset

U9 pin G8 Write enable

Schematic Signal

Name

FSM_D10

FSM_D11

FSM_D12

FSM_D13

FSM_D14

FSM_D15

FLASH_CLK

FLASH_ADVn

FLASH_CEn

FLASH_OEn

FLASH_RDYBSYn

FLASH_RESETn

FLASH_WEn

I/O

Standard

Stratix III

Number

Other Connections

1.8 V A26 U5 pin M6 and U4 pin C2

1.8 V B25 U5 pin R5 and U4 pin D2

1.8 V A25 U5 pin P7 and U4 pin E2

1.8 V J20 U5 pin T5 and U4 pin F2

1.8 V K20 U5 pin N7 and U4 pin F1

1.8 V K21 U5 pin R6 and U4 pin G1

1.8 V K24

U5 pin L15

1.8 V C7 U5 pin L13

1.8 V K25 U5 pin K14

1.8 V K23 U5 pin M16

1.8 V L16 U5 pin L11

1.8 V E13 U5 pin M15

1.8 V L22 U5 pin L12

Tab le 2– 56 shows the flash on-board memory map. The memory needs to provide

non-volatile storage of a minimum of eight FPGA bit streams as well as various settings data used for on-board devices such as Ethernet TCP/IP defaults, PFL configuration bits, and data on the board itself. The remaining area is designated as user flash area for storage of software binaries and other data relevant to a user FPGA design.

Table 2–56. Flash Memory Map (Part 1 of 2)

Name Address

PFL option bits

Ethernet option bits

User space (10 MBytes)

0x03FE.0000

0x03FC.0000

0x03FB.FFFF

0x0350.0000

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–66 Chapter 2: Board Components

On-Board Memory

Table 2–56. Flash Memory Map (Part 2 of 2)

Name Address

FPGA design 7

FPGA design 6

FPGA design 5

FPGA design 4

FPGA design 3

FPGA design 2

0x034E.FFFF

0x0000.0000

FPGA design 1

FPGA design 0 (Default)

Factory design

Tab le 2– 57 shows the flash sector map.

Table 2–57. Flash Sector Map–Top and Bottom Parameter Dies

Die Stack

Configuration

Size (KBytes)

(2 × 256 Mbits with 1 CE)

Block Address Range

512-Mbit Flash

32 517

1FFC000–1FFFFFF

... ... ...

256-Mbit Top Parameter Die

32 514

128 513

1FF0000–1FF3FFF

1FE0000–1FEFFFF

... ... ...

256-Mbit Bottom Parameter Die

128 259

128 258

... ...

128 4 ...

32 3

... ...

1000000–100FFFF

770000–77FFFF

760000–76FFFF

010000– 01FFFF

000000–00FFFF

32 0 ...

f For more read and write timing specification, refer to the Intel Corporation website at

www.intel.com.

Tab le 2– 58 lists the flash memory device component reference and manufacturing

information.

Table 2–58. Flash Memory Device Component Reference and Manufacturing Information

Board Reference Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

U9 512 Mbit, 1.7 to 2.0 V core, 64-pin BGA Intel Corporation PC48F4400P0VB00 www.intel.com

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–67

Power Supply

The board’s power is provided through an IBM laptop style DC power input. The input voltage must be in the range of 14 V to 20 V. The DC voltage is then stepped down to the various power rails used by the components on the board and installed into the HSMC connectors.

An on-board, multi-channel A/D converter measures both voltage and current for several specific board rails. The power utilization is displayed on either the graphics display or the dedicated 7-segment display.

Power Distribution System

Figure 2–20 shows the power distribution system, which uses current power rails. The

currents shown reflect the regulator inefficiencies and regulator sharing.

Figure 2–20. Power Distribution System

DC INPUT 14V-20V

5 . 0 V

1.8V_DIMM

1 . 8 V _ DEV

VDDQ_QDRII

Wide Input

Switching Regulator

Module

(LTM4601)

Wide Input

Switching Regulator

Module

(LTM4601)

Wide Input

Switching Regulator

Module

(LTM4601)

Wide Input Switching Regulator

(LT1374)

VLD OIN

MEASURE

5 . 0 V

MEASURE

Linear

(TPS5100)

Linear

(TPS5100)

Linear

(TPS5100)

3 . 3 V

1 . 8 V

1 . 1 V

VREF_DIMM

0 . 9 V

VREF_DEV

0 . 9 V

VREF_QDRI I

0 . 9 V / 0 . 75 V

Linear

(LT1761)

Linear

(LT1761)

BST

Linear

(LT3026)

BST

Linear

(LT3026)

BST

Linear

(LT3026)

BST

Linear

(LT3026)

VCCL

Partial Plane

FPGA VCCL

VTT _ DIMM

Power Net

DIMM Termination

Resistors

VTT _ DEV

Power Net

Device Termination

Resistor s

VTT _ QDRII

Power Net

QDR II Termination

Resistor s

2 . 5 V

1.5/1.8V

1 . 1 V

12V

5.0V

3.0V

3.3V

MEASURE

HSMC Port A, Port B,

and Graphics Display

MEASURE

1 . 5 / 1 . 8 V

1 . 1 V

MEASURE

12 V Power Net

3.0V_CSENSE Power Net

LTC 2402 A/D

ADG 725 MUX

2.5V_A

Power Net

FPGA VCCA PLL

FPGA VCCPT

FPGA VCC_CLKIN

FPGA_VCCPGM

VDDQ_QDRII

Partial Plane

QDRII VDDQ

Partial Plane

ENET PHY DVD D

1 . 8 V

2.5V_B2

Partial Plane

FPGA VCCIO (B2)

1 . 1 V

USB - VCC (FTDI), 14-pin LCD Header

Flash Core, USN (FX2LP)

CPLD VCCIO (B1, B2) Marvell PHY, Graphics

2.5V_B4a_B5_B6

Partial Plane

FPGA VCCIO (B4A, B5, B6)

1.5V_1.8V_B7

Partial Plane

FPGA VCCIO (B7)

FPGA_VCCD_PLL

1.8V_DIMM

Partial Plane

DIMM VDD/VDDQ

1.8V_QDRII

Partial Plane

QDRII VDD

5 V Power Net

3.3V

Power Net

HSMC Port A, B

2.5V

Partial Plane

2.5V_VCCPD

Partial Plane

FPGA VCCPD

1V_VCC

Partial Plane

FPGA VCC

1.8V

Power Net

CPLD VCCINT

CPLD VCCIO (B3, B4)

PSRAM VCC.VCCD

Flash VDDQ

1.8V_S3

Partial Plane

FPGA VCCIO (B3,B4)

FPGA VCCIO (B1, B8)

1.8V_DEV

Partial Plane

DEV VDD/VDDQ

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–68 Chapter 2: Board Components

Power Supply

Power Measurement

Ten power supply rails have on-board voltage and current-sense capabilities. These devices and rails are split from the primary supply plane by a low-value sense resistor for the A/D converter to measure voltage and current.

Tab le 2– 59 shows the targeted rails where Measured Net Name column shows the name

of the rail being measured, and the devices attached to that are listed under Power Pin Name and Description columns. If no subnet is named, then the power is the total output power for that voltage.

Table 2–59. Power Measurement Rails

Number Measured Net Name Power Pin Name Description

21.

32.

VCCL VCCL

1V_VCC

5V_A

2.5V_VCCPD VCCPD

2.5V_VCCPGM VCCPGM

1.8V_S3

2.5V_B2

2.5V_B4A_B5_B6

1.5V_1.8V_B7

VCC

VCCD_PLL

VCCPT

VCCA_PLL

VCCIO1A VCCIO1C VCCIO8A VCCIO8B VCCIO8C

VCCIO3A VCCIO3B VCCIO3C VCCIO4B VCCIO4C

VCCIO2A VCCIO2C

VCCIO4A VCCIO5A VCCIO5C VCCIO6A VCCIO6C

VCCIO7A VCCIO7B VCCIO7C

FPGA core power

FPGA I/O registers power

FPGA PLL digital power

FPGA programmable power technology

FPGA PLL analog power

Pre-driver power for I/Os

Power for configuration I/Os

, , , ,

, ,

FPGA I/O power banks 1, 8

FPGA I/O power banks 3, 4

FPGA I/O power bank 2

FPGA I/O power banks 4a, 5, 6

FPGA I/O power bank 7

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–69

MAX II Device

LTC2402

ADC

Load #1

Load #16

Supply #1

SENSE

feedback

4-Digit Rail

Select

4-Digit 7-Segment or OLED Display (mA)

1A 1B

16A 16B

ADG725

Supply #16

Power Supply

This capability is realized using a 32-channel analog multiplexer to a 2-channel differential A/D converter, with a digital data bus connected to the MAX II CPLD. The CPLD contains a logic design that continually monitors the rails and displays the current in mA on the dedicated four-digit, 7-segment display or graphics display. Because only a single rail can be displayed at any time on the 7-segment display, an octal rotary switch is used to select which rail is currently being displayed. The sense resistor is large enough that it can be easily probed to confirm the display results. To see all of the currents at the same time, you can use the graphics display. Figure 2–21 illustrates the circuit.

Figure 2–21. Power Measurement System

Security Key and Battery Backup

Stratix III devices are protected against copying, reverse engineering, and tampering using configuration bit-stream encryption. Specifically, the Stratix III devices use an advanced encryption standard (AES) algorithm with a 256-bit user-generated key. The key is stored on the Stratix III device and is used to decrypt the incoming configuration data bit-stream before configuration and initialization can begin.

This section discusses the following two methods of storing Stratix III device’s 256-bit encryption key:

■ Vo la t il e

■ Non-volatile

In the volatile scheme, the 256-bit key itself can be reprogrammed as needed. In this case, a 2.5-V battery is required to power the V within the Stratix III device when the system is powered off.

In the non-volatile scheme, the 256-bit key is programmed once into the Stratix III device and cannot be changed. The advantage of the non-volatile scheme is that a battery is not required to power the V

CCBAT

input.

By providing a 2.5-V coin battery connected to the V

May 2013 Altera Corporation Stratix III 3SL150 Development Board

provides support for both volatile and non-volatile keys. A battery socket is also provided to allow battery replacement as needed. Additionally, the V input has a jumper to allow the battery is removed for supporting the non-volatile key mode.

VCCBAT

pin to be tied directly to GND when the

input and maintain the key

CCBAT

power input, the board

CCBAT

power

CCBAT

Reference Manual

2–70 Chapter 2: Board Components

Statement of China-RoHS Compliance

Tab le 2– 60 lists hazardous substances included with the kit.

(Hg)

(1), (2)

Polybrominated

biphenyls (PBB)

Polybrominated diphenyl Ethers

(PBDE)

Table 2–60. Table of Hazardous Substances’ Name and Concentration Notes

Hexavalent

Chromium

(Cr6+)

Mercury

Part Name

Lead

(Pb)

Cadmium

(Cd)

Stratix III development board X* 0 0 0 0 0

12 V power supply 0 0 0 0 0 0

Type A-B USB cable

00 0 0 0 0

User guide 0 0 0 0 0 0

Notes to Table 2–60:

(1) 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the

SJ/T11363-2006 standard.

(2) X* indicates that the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant

threshold of the SJ/T11363-2006 standard, but it is exempted by EU RoHS.

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

This chapter provides additional information about the document and Altera.

Document Revision History

The following table lists the revision history for this document.

Date Version Changes

■ Updated the MAX II pin assignment for

■ Updated the Stratix III pin numbers for

DDR2_DEVA_A12,DDR2_DEVA_A13,DDR2_DEVA_A14,DDR2_DEVA_BA0,DDR2_DEVA_BA

and

May 2013 1.5

1,DDR2_DEVA_BA2,

■ Updated the Stratix III pin numbers for

DDR2_DEVA_CASn

Table 2–49.

■ Updated the document template.

November 2008 1.4

November 2008 1.3

August 2008 1.2

■ Updated QDRII interface pin information in Table 2–50.

■ Updated DDR2 DIMM board memory size.

■ Updated Stratix III pin numbers for the differential output clock signals in Table 2–45.

■ Updated JTAGS settings in Table 2–7.

■ Updated “Power Select Rotary Switch” section.

■ Corrected pin description in Table 2–32.

■ Updated pin description in Table 2–39.

■ Updated “High-Speed Mezzanine Cards” section.

■ Corrected pin description in Table 2–41 and Table 2–42.

■ Corrected pin numbers in Table 2–47 and Table 2–49.

March 2008 1.1 Corrected minor errors and incorporated device errata.

December 2007 1.0 First publication

FSM_A9

signal in Table 2–5.

signals in Table 2–47.

DDR2_DEVB_DQ2

Additional Information

and

DDR2_DEVB_DQ3

signals in

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

Info–2 Additional Information

How to Contact Altera

To locate the most up-to-date information about Altera products, refer to the following table.

Contact

Technical support Website www.altera.com/support

Technical training

Product literature Website www.altera.com/literature

Nontechnical support (general) Email nacomp@altera.com

Note to Table:

(1) You can also contact your local Altera sales office or sales representative.

(1)

(software licensing) Email authorization@altera.com

Contact Method Address

Website www.altera.com/training

Email custrain@altera.com

Typographic Conventions

The following table shows the typographic conventions this document uses.

Visual Cue Meaning

Bold Type with Initial Capital Letters

bold type

Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.

italic type

Initial Capital Letters

“Subheading Title”

Courier type

r An angled arrow instructs you to press the Enter key.

1., 2., 3., and a., b., c., and so on

■ ■ ■ Bullets indicate a list of items when the sequence of the items is not important.

1 The hand points to information that requires special attention.

Indicate command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI.

Indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \qdesigns directory, D: drive, and chiptrip.gdf file.

Indicates variables. For example, n + 1.

Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file.

Indicate keyboard keys and menu names. For example, the Delete key and the Options menu.

Quotation marks indicate references to sections in a document and titles of Quartus II Help topics. For example, “Typographic Conventions.”

Indicates signal, port, register, bit, block, and primitive names. For example,

tdi

, and

input

. The suffix n denotes an active-low signal. For example,

Indicates command line commands and anything that must be typed exactly as it appears. For example,

Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword

TRI

example,

Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure.

c:\qdesigns\tutorial\chiptrip.gdf

SUBDESIGN

), and logic function names (for

resetn

data1

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Additional Information Info–3

Typographic Conventions

Visual Cue Meaning

h The question mark directs you to a software help system with related information. f The feet direct you to another document or website with related information. m The multimedia icon directs you to a related multimedia presentation.

A caution calls attention to a condition or possible situation that can damage or destroy the product or your work.

A warning calls attention to a condition or possible situation that can cause you injury.

The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents.

The feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document.

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

Info–4 Additional Information

Typographic Conventions

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Altera Stratix III Development Board User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Introduction

General Description

1. Overview

Board Component Blocks

Handling the Board

Block Diagram

Introduction

2. Board Components

Board Overview

Featured FPGA (U22)

Device Support

I/O Resources

MAX II CPLD

Configuration, Status, and Setup Elements

Configuration

FPGA Programming Over USB

FPGA Programming from Flash Memory

Flash Programming over USB Interface

Status Elements

Board Specific LEDs

Power Display

Setup Elements

JTAG Control DIP Switch

MAX II Device Control DIP Switch

System Reset and Configuration Switches

Power Select Rotary Switch

PGM Config Select Rotary Switch

Clocking Circuitry

Stratix III FPGA Clock Inputs

Stratix III FPGA Clock Outputs

General User Interfaces

User-Defined Push-Button Switches

User-Defined DIP Switches

User-Defined LEDs

General User-Defined LEDs

HSMC User-Defined LEDs

7-Segment Displays

User 7-Segment Display

Power 7-Segment Display

LCD Displays

Character LCD

Graphics LCD

Speaker Header

Components and Interfaces

USB 2.0 MAC/PHY

10/100/1000 Ethernet

High-Speed Mezzanine Cards

On-Board Memory

DDR2 SDRAM DIMM

DDR2 SDRAM Devices

QDRII+ SRAM

P-SRAM

Flash Memory

Power Supply

Power Distribution System

Power Measurement

Security Key and Battery Backup

Statement of China-RoHS Compliance

Document Revision History

Additional Information

How to Contact Altera

Typographic Conventions