Altera Stratix III Development Board User Manual

Stratix III 3SL150 Development Board Reference Manual

Stratix III 3SL150 Development Board

Reference Manual

101 Innovation Drive San Jose, CA 95134

www.altera.com

MNL-01030-1.5

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© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

Chapter 1. Overview

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Chapter 2. Board Components

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Featured FPGA (U22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

MAX II CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

FPGA Programming Over USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

Flash Programming over USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

Board Specific LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

Power Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

JTAG Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

MAX II Device Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

System Reset and Configuration Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

Power Select Rotary Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

PGM Config Select Rotary Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

Clocking Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

Stratix III FPGA Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

Stratix III FPGA Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

General User Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

User-Defined Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

User-Defined DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29

User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

General User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

HSMC User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31

7-Segment Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31

User 7-Segment Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32

Power 7-Segment Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

LCD Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

Graphics LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

Speaker Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38

Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39

USB 2.0 MAC/PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39

10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39

High-Speed Mezzanine Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–41

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

iv Contents

On-Board Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48

DDR2 SDRAM DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–49

DDR2 SDRAM Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–53

QDRII+ SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–55

P-SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–58

Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–63

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–67

Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–67

Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–68

Security Key and Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–69

Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–70

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Introduction

This document describes the hardware features of the Stratix®III development board, including detailed pin-out information to enable you to create custom FPGA designs that interface with all components of the board.

f For information about setting the Stratix III development board and using the kit’s

demo software, refer to the Stratix III Development Kit User Guide.

General Description

The Stratix III development board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs. The board provides a wide range of peripherals and memory interfaces to facilitate the design and development of Stratix III FPGA designs. Additionally, two high-speed mezzanine card (HSMC) connectors are available to add additional functionality via a variety of HSMCs available from both Altera and various partners.

1. Overview

f To see a list of the latest available HSMC cards and to request a copy of the HSMC

specification, visit www.altera.com.

Design advancements and innovations, such as Programmable Power Technology and selectable core voltage, ensure that designs implemented in Stratix III FPGAs operate faster, but consume less power than previous generation Stratix devices.

f For more information about Stratix III device Programmable Power Technology, refer

to the following documents:

■ Stratix III Programmable Power White Paper

■ PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook

With up to 7,280 KByte of enhanced TriMatrix memory and 384 embedded 18 × 18 multipliers, the on-board Stratix III device supplies internal memory while also providing I/O support for a variety of SDRAM (DDR2 or DDR3) and SRAM (QDRII or RLDRAM II) interfaces. Both DDR2 and QDRII are available on the Stratix III development board providing a high bandwidth, high-speed and low-latency solution.

The Stratix III development board is especially suitable for high-performance, logic-rich applications that require stringent signal and power integrity solutions. For example, the wireless, broadcast, and military markets require advanced signal processing techniques and very low power consumption, while also demanding flexibility and adaptability in the field.

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

1–2 Chapter 1: Overview

General Description

f For more information about:

■ External memory interfaces in Stratix III devices, refer to the External Memory

Interfaces chapter in the Stratix III Device Handbook

■ The Altera DDR and DDR2 SDRAM Controller Compiler MegaCore

function,

refer to the DDR and DDR2 SDRAM Controller Compiler User Guide

■ Power optimization, refer to AN 437: Power Optimization Techniques in Stratix III

FPGAs

■ Altera Video and Image Processing Suite MegaCore functions, refer to the

Video and Image Processing Suite User Guide

Board Component Blocks

The board features the following major component blocks:

■ 1,152-pin Altera Stratix III EP3SL150F FPGA in a ball-grid array (BGA) package

■ 142,000 logic elements (LEs)

■ 5,499 Kbits of memory

■ 384 multiplier blocks

■ Eight phase locked loops (PLLs)

■ 16 global clock networks

■ 736 user I/Os

■ 1.1-V core power

■ 256-pin Altera EPM2210GF256 CPLD in a BGA package

■ 1.8-V core power

■ On-board memory

■ 1-GByte DDR2 SDRAM DIMM

■ 72-Mbit QDRII/+ SRAM

■ 16-MByte DDR2 SDRAM devices

■ Individually addressable

■ 4-MByte SSRAM

■ 64-MByte flash memory

■ FPGA configuration circuitry

■ MAX

II CPLD and flash passive serial configuration

■ On-board USB-Blaster™ circuitry using the Quartus II Programmer

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 1: Overview 1–3

General Description

■ On-board clocking circuitry

■ Two clock oscillators to support Stratix III device user logic

■ 125 MHz

■ 50 MHz

■ SMA connector for external clock input and output

■ General user and configuration interfaces

■ LEDs/displays:

■ Eight user LEDs

■ One configuration-done LED

■ One transmit/receive LED (TX/RX) per HSMC interface

■ One HSMC-present LED per HSMC interface

■ Six Ethernet LEDs

■ User Quad 7-segment display

■ Power consumption display

■ Push-buttons:

■ User reset push-button (CPU reset)

■ Four general user push-buttons

■ System reset push-button (user configuration)

■ One factory push-button switch (factory configuration)

■ DIP switches:

■ MAX II control DIP switch

■ Eight user DIP switches

■ Speaker header

■ Displays

■ 128 × 64 graphics LCD

■ 16 × 2 line character LCD

■ Power supply

■ 14-V – 20-V DC input

■ On-board power measurement circuitry

■ Up to 20 W per HSMC interface

■ Mechanical

■ 7 in. × 8.25 in. board

■ Bench-top design

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

1–4 Chapter 1: Overview

1.5-V HSTL

Statix III

EP3SL1501152

EP3SL340H1152

125-MHz

XTAL

MAX II

Device (x16)

2.5-V CMOS

1.8-V CMOS

Power

Measure/

Display

72-Mbit QDRII/+

18/18

CMOS + LVDS

4-MB SSRAM

(x32)

64-MB Flash

(x16)

1-GByte DDR2

(x72)

USB

2.0

1.8-V SSTL

50-MHz

XTAL

1.8-V CMOS

Quad 7-Seg/

User LEDs,

Buttons,

Switches

SMA Input

1.8-V SSTL

SMA Output

10/100/1000

Ethernet

CMOS + LVDS

2.5-V CMOS

RJ45

Jack

Graphics Display

Header

14-Pin LCD

Header

16-MB

DDR2

(x8)

16-MB

DDR2

(x8)

HSMC Port B

HSMC Port A

Handling the Board

Block Diagram

Figure 1–1 shows the functional block diagram of the Stratix III development board.

Figure 1–1. Stratix III Development Board Block Diagram

Handling the Board

When handling the board, it is important to observe the following precaution:

c Static Discharge Precaution: Without proper anti-static handling, the board can be

damaged. Therefore, use anti-static handling precautions when touching the board.

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Introduction

2. Board Components

This chapter introduces the important components on the Stratix III development board. Figure 2–1 illustrates component locations and Table 2–1 describes component features.

This chapter consists of the following sections:

■ “Featured FPGA (U22)” on page 2–4

■ “MAX II CPLD” on page 2–8

■ “Configuration, Status, and Setup Elements” on page 2–17

■ “Clocking Circuitry” on page 2–25

■ “General User Interfaces” on page 2–28

■ “Components and Interfaces” on page 2–39

■ “On-Board Memory” on page 2–48

■ “Power Supply” on page 2–67

■ “Statement of China-RoHS Compliance” on page 2–70

1 A complete set of board schematics, a physical layout database, and GERBER files for

the Stratix III development board reside in the Stratix III Development Kit documents directory.

f For information about powering up the development board and installing the demo

software, refer to the Stratix III Development Kit User Guide.

Board Overview

This section provides an overview of the Stratix III development board, including an annotated board image and component descriptions.

May 2013 Altera Corporation Stratix III 3SL150 Development Board

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2–2 Chapter 2: Board Components

Stratix III

FPGA (U22)

MAX II

CPLD (U5)

Device Select (J2)

Jumper

24-MHz Crystal (Y2)

6-MHz Crystal (Y3)

125-MHz MAX II Clock (Y1)

Type B USB Connector (J5)

MAX II Control DIP Switch (SW2)

Ethernet PHY LEDs (D6, D7, D8) & Duplex LED (D9)

PGM Config Select Rotary Switch (SW3)

RJ-45 Ethernet Connector (J14)

Clock In/Out SMAs (J16, J17)

Ethernet PHY TX/RX Activity LEDs (D14, D15)

Factory Configuration Push Button (S1)

Power Switch (SW4)

DC Power Jack (J21)

User Push Buttons (S2 through S5)

Reset Configuration Push Button (S7)

Configuration

Done LED (D32)

Board-Specific

LEDs (D33-D36)

User LEDs (D20 through D27)

CPU Reset

Push Button (S6)

Flash Memory Device (U9)

24-MHz Crystal (Y4)

DDR2 SDRAM (U17, U20)

DDR2 SDRAM DIMM Connector (J19)

Power Select

Rotary Switch (SW6)

Power LED (D16)

HSMC Port A (J18)

HSMC Port B (J8)

HSMC Port A

Present LED (D17)

Power Display (U27)

User DIP Switch (SW5)

HSMC Port A

TX/RX Activity

LEDs (D11, D12)

HSMC Port B

Present LED (D10)

Speaker Header (J1)

HSMC Port B

TX/RX Activity LEDs

(D2, D3)

User Display (U28)

QDRII+ SRAM (U15)

(Behind the LCD Screen)

JTAG Control DIP Switch (SW1)

MSEL0 to GND Jumper (J13)

Board Overview

Figure 2–1 shows the top view of the Stratix III development board.

Figure 2–1. Top View of the Stratix III Development Board

Tab le 2– 1 describes the components and lists their corresponding board references.

Table 2–1. Stratix III Development Board (Part 1 of 3)

Board Reference Type Description

Featured Devices

U22 FPGA EP3SL150F1152, 1152-pin BGA package.

U5 CPLD EPM2210GF256, 256-pin device in a BGA package.

Configuration Status and Setup Elements

Device select ( jumper

J5 Input

D32 Configuration done LED Green LED that illuminates when the FPGA is successfully configured.

D11, D12 (Port A)

D2, D3 (Port B)

Channel activity LEDs

J1 Header Speaker header.

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

DEV_SEL

)

Sets target device for JTAG signals when using an external USB Blaster or equivalent.

Type B USB connector that allows for connecting a Type A-B USB cable between a PC and the board.

Green LEDs that indicate the RX and TX activity on the HSMC Ports A or B.

Chapter 2: Board Components 2–3

Board Overview

Table 2–1. Stratix III Development Board (Part 2 of 3)

Board Reference Type Description

D6, D7, D8 Ethernet PHY LEDs

D9 Duplex Ethernet PHY LED

Green Ethernet PHY LEDs. Illuminate when Ethernet PHY is using the 10/100/1000 Mbps (D6, D7, D8) connection speeds.

Green Ethernet PHY LED. Illuminates when Ethernet PHY is both sending and receiving data.

D16 Power LED Blue LED indicates when power is applied to the board.

D14, D15

Ethernet PHY transmit/receive activity LEDs

SW2 MAX II Control DIP switch

SW1 JTAG control DIP switch

Green LEDs. Illuminates when transmit/receive data is active from the Ethernet PHY.

Controls various features of the MAX II device specific to the Stratix III development board.

JTAG control DIP switch used to remove or include devices in the active JTAG chain.

U27 Power display Displays power measured by the MAX II CPLD.

D11, D12

D2, D3

HSMC Port A transmit/receive activity LEDs

HSMC Port B transmit/receive activity LEDs

Illuminates when transmit/receive data is active from the HSMC Port A.

Illuminates when transmit/receive data is active from the HSMC Port B.

Clock Circuitry

Y1 125 MHz MAX II 125-MHz device clock.

Y2 24-MHz crystal Cypress USB PHY.

Y3 6-MHz crystal USB PHY FTDI reference clock.

Y4 24 MHz MAX II 24-MHz device clock.

Y5 125 MHz 125-MHz clock oscillator used for the system clock.

Y6 50 MHz 50-MHz clock oscillator used for data processing.

J16 SMA clock input SMA connector that allows the provision of an external clock input.

J17 SMA clock output SMA connector that allows the provision of an external clock output.

General User Input and Output

S2 through S5 User push-buttons Four 2.5-V push-button switches for user-defined, logic inputs.

S6 CPU reset push-button One 2.5-V push-button switch for FPGA logic and CPU reset.

S1 and S7

Reset and factory configuration push-button

Two 2.5-V push-button switches that control FPGA configuration from flash memory.

D20 through D27 User LEDs Eight user-defined LEDs.

SW3

PGM Config Select rotary switch

Rotary switch to select which FPGA configuration file is loaded from the flash device into the FPGA.

SW6 Power Select rotary switch Power rail select for on-board power monitor.

U28 User display User-defined, green 7-segment display.

SW5 User DIP switch User-defined, eight position DIP switch.

Memory

U9 Flash 512 Mbits of flash memory.

U4, U10 P-SRAM

The P-SRAM devices connect to the MAX II device as well as the flash memory device.

U17, U20 DDR2 SDRAM Two 16M × 8, 1.8-V core devices in 60-pin FBGA packages.

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–4 Chapter 2: Board Components

Featured FPGA (U22)

Table 2–1. Stratix III Development Board (Part 3 of 3)

Board Reference Type Description

U15 QDRII

J19 DDR2 SDRAM DIMM Connector for 1 GByte × 72 DDR2 SDRAM DIMM.

Components and Interfaces

U11 USB device

J14 Ethernet cable jack

J8 and J18 HSMC Port A and Port B HSMC connectors to allow for expansion via the addition of HSMCs.

Power Supply

J21 DC power jack 14–20 V DC power source.

SW4 Input Switches the board’s power on and off.

Burst-of-four, 2M × 18, 400-MHz QDRII memory interface in an FBGA package.

USB device that provides JTAG programming of on-board devices, including the Stratix III device and flash memory device.

The RJ-45 jack is for Ethernet cable connection. The connector is fed by a 10/100/1000 base T PHY device with an RGMII interface to the Stratix III device.

Featured FPGA (U22)

The Stratix III Development Kit features the EP3SL150F1152C2 device (U22) in a 1152-pin BGA package.

f For more information about Stratix III devices, refer to the Stratix III Device Handbook.

Tab le 2– 2 lists the main Stratix III EP3SL150 device features.

Table 2–2. Stratix III EP3SL150 Device Features

ALMs LEs

57 142.5 355 16 2,850 5,499 1,781 7,280 384 8

M9K

Blocks

M144K Blocks

MLAB

Blocks

Total Embedded RAM Kbits

MLAB

Kbits

Tab le 2– 3 lists the Stratix III device component reference and manufacturing

information.

Table 2–3. Stratix III Device Component Reference and Manufacturing Information

Board Reference Description Manufacturer

U22 High-speed, low-power FPGA Altera

Corporation EP3SL150F1152 www.altera.com

Total

Memory

Kbits

Manufacturing

Part Number

18 × 18 Bit Multipliers

Manufacturer

Website

PLLs

Tab le 2– 4 lists the Stratix III device EP3SL150F1152 pin count.

Table 2–4. Stratix III Device Pin Count (Part 1 of 2)

Function I/O Type I/O Count Special Pins

Oscillators and SMAs 1.8-V CMOS 4 Three clock inputs, one output

DDR2 DIMM 1.8-V SSTL 136 18 data strobe signal (DQS) pins

DDR2 devices 1.8-V SSTL 74 Four DQS pins

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–5

Bank 7A 40

Bank 7B 24

Bank 7C 32

Bank 8C 32

Bank 1A 48

Bank 1C

EP3SL150

QDR II

USER PB

1.5 V (73 pins)

2.5 V

(74 pins)

User, FLASH,

SRAM

1.8 V (98 pins)

Bank 2C 40

Bank 2A

Bank 6A

Bank 6C

Bank 5C

Bank 5A 48

Bank 8B 24

Bank 8A 40

Bank 4A 40

Bank 4B 24

Bank 4C 32

Bank 3C 32

Bank 3B 24

Bank 3A 40

LCD,

USER 7-SEG

2.5 V (35 pins)

DDR2 x 72 DIMM

1.8 V (136 pins)

HSMC A

2.5 V

(74 pins)

DDR2 x8

Devices

A & B

1.8 V

(70 pins)

2.5 V

(65 pins)

Ethernet,

Graphics LCD,

USB, Misc

HSMC B

Featured FPGA (U22)

Table 2–4. Stratix III Device Pin Count (Part 2 of 2)

Function I/O Type I/O Count Special Pins

QDRII+ 1.5-V/1.8-V HSTL 66 Two CQ pins

Flash/P-SRAM/MAX 1.8-V CMOS 79 —

Ethernet

2.5-V CMOS

2.5-V LVDS

36 6, 2.5 V LVDS

User I/O (LEDs, etc) 1.8-V/2.5 V 30 —

14-pin LCD header 2.5-V CMOS 11 —

Graphics display 2.5-V CMOS 16 —

USB 2.5-V CMOS 0 —

HSMC Port A

HSMC Port B

2.5-V CMOS

2.5-V LVDS

2.5-V CMOS

2.5-V LVDS

88 3 clock inputs

Device I/O total: 628

Stratix III device I/O total: 736

Figure 2–2 shows the EP3SL150 I/O bank diagram from a system perspective.

Figure 2–2. System I/O Bank Diagram

f For additional information about Altera devices, go to

www.altera.com/products/devices.

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–6 Chapter 2: Board Components

Featured FPGA (U22)

Device Support

Although the target FPGA for the Stratix III development board is the EP3SL150 device, which is the first device in the 65 nm Stratix III FPGA device family, the board is also designed to migrate to the Stratix III EP3SL340H1152 device.

The following list shows the main power rails for the target device:

■ 0.9-V/1.1-V V

■ 1.1-V V

■ 2.5-V V

■ 1.8-V/2.5-V/3.0-V V

■ 2.5-V/3.0-V V

■ 2.5-V V

■ 1.2-V to 3.3-V V

CCL

CCPT

CCPGM

CCPD

CCA_PLL

CC_CLKIN

CCBAT

CCIO

The board’s target device, the EP3SL150F1152C2, comprises the following:

■ 57,000 adaptive logic modules (ALMs)

■ 142,000 LEs

■ 1,775 KBytes of RAM

■ 736 user I/O

■ 8 PLLs

■ 16 global clocks

■ 384 18 × 18 multipliers in finite impulse response (FIR) mode

The board is designed to migrate to the EP3SL340H1152C3 device, which provides the following features in the H1152 package:

■ 135,000 ALMs

■ 338,000 LEs

■ 4,225 KBytes of RAM

■ 736 user I/O

■ 8 PLLs

■ 16 global clocks

■ 576 18 × 18 multipliers in FIR mode

I/O Resources

This section lists specific I/O resources available with the EP3SL150F1152 device, which is from the L family of Stratix III devices.

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–7

Bank 7A 40

Bank 7B 24

Bank 7C 32

Bank 8C 32

Bank 1A 48

Bank 1C

EP3SL150

Bank Name

Number of I/Os

Bank Name

Number of I/Os

Bank 2C 40

Bank 2A

Bank 6A

Bank 6C

Bank 5C

Bank 5A 48

Bank 8B 24

Bank 8A 40

Bank 4A 40

Bank 4B 24

Bank 4C 32

Bank 3C 32

Bank 3B 24

Bank 3A 40

Featured FPGA (U22)

Tab le 2– 3 shows the configuration of the 20 user I/O banks and each bank’s I/O count

for the EP3SL150 device. Incidentally, within the same package, the EP3SL150 and the EP3SL340 devices have the same number of PLLs, user I/O banks, and user I/Os.

Figure 2–3. EP3SL150F1152 Device I/O Bank Resources

Figure 2–4 shows the configuration of the 24 possible user I/O banks and each bank’s

I/O count for the EP3SL340 device in its largest package. Banks 1B, 2B, 5B, and 6B are not available in the F1152 package.

Figure 2–4. EP3SL340F1517 Device I/O Bank Diagram

Number of I/Os

Bank Name

Bank 7A 48

Bank 7B 48

Bank 7C 48

Bank 8C 48

Bank 8B 48

Bank 8A 48

Bank 6A

Bank 6B

Bank 5C

Bank 5C 48

Bank 5B36

Bank 5A48

Bank 4A 48

EP3SL340

Bank 4B 48

Bank 4C 48

Bank 3C 48

Bank 3B 48

Bank 1A 48

Bank 1B

Bank 1C 48

Bank 2C

Bank 2B 36

Bank 2A 48

Bank

Bank 3A 48

Name

Number of I/Os

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–8 Chapter 2: Board Components

MAX II CPLD

The board utilizes an Altera MAX II CPLD (U5) for the following purposes:

■ Power-up configuration of the FPGA from flash memory

■ Embedded USB-Blaster core for USB-based configuration of the FPGA

■ Power consumption monitoring and display

Additionally, the MAX II device is also used to help dual-footprint the FTDI USB device and Cypress USB device. Each device has a shared path between the USB device and the MAX II CPLD. This path then drives to the FPGA separately.

Figure 2–5 illustrates the MAX II device’s functional block diagram.

Figure 2–5. MAX II Device’s Block Diagram

Power Display

JTAG

Header

To FPGA

64-MB

Flash (x16)

8-MB

SRAM (x32)

Stratix III

Device

125 MHz

1.8-V CMOS FSM Bus

24 MHz

PS Config

JTAG Config

USB Data Bus

PGM_CONFIG_SEL

PWR_SEL

Tab le 2– 5 lists the I/O signals present on the MAX II CPLD. The signal names and

functions are relative to the MAX II device (U5).

Table 2–5. MAX II Device Pin-out (Part 1 of 9)

Power

Measure

2.5-V CMOS

MAX II CPLD

CPU_RESET

2.5-V CMOS

RESET_CONFIG

2.5-V CMOS

1.8-V CMOS

FACTORY_CONFIG

Cypress 480 Mb/s

USB (x16)

FTDI

12 Mb/s USB (x8)

MAX II Device

Control DIP Switch

JTAG Control

DIP Switch

Config Status

LEDs

MAX II

Pin Number

Description Schematic Signal Name

Address bus shared with flash and P-SRAM bit 0

Address bus shared with flash and P-SRAM bit 1

Address bus shared with flash and P-SRAM bit 2

FSM_A0

FSM_A1

FSM_A2

I/O

Standard

1.8 V F22 U9 pin A1

1.8 V H23

1.8 V G23

Stratix III

Number

Other Connections

U9 pin B1 and U4 pin A3 and U10 pin A3

U9 pin C1 and U4 pin A4 and U10 pin A4

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–9

MAX II CPLD

Table 2–5. MAX II Device Pin-out (Part 2 of 9)

MAX II

Pin Number

T10

P13

R10

M10

T11

N10

R11

P10

T12

M11

R12

N11

T13

P11

R13

M12

R14

N12

Description Schematic Signal Name

Address bus shared with flash and P-SRAM bit 3

Address bus shared with flash and P-SRAM bit 4

Address bus shared with flash and P-SRAM bit 5

Address bus shared with flash and P-SRAM bit 6

Address bus shared with flash and P-SRAM bit 7

Address bus shared with flash and P-SRAM bit 8

Address bus shared with flash and P-SRAM bit 9

Address bus shared with flash and P-SRAM bit 10

Address bus shared with flash and P-SRAM bit 11

Address bus shared with flash and P-SRAM bit 12

Address bus shared with flash and P-SRAM bit 13

Address bus shared with flash and P-SRAM bit 14

Address bus shared with flash and P-SRAM bit 15

Address bus shared with flash and P-SRAM bit 16

Address bus shared with flash and P-SRAM bit 17

Address bus shared with flash and P-SRAM bit 18

Address bus shared with flash and P-SRAM bit 19.

Address bus shared with flash and P-SRAM bit 20

Address bus shared with flash and P-SRAM bit 21

Address bus shared with flash and P-SRAM bit 22

FSM_A3

FSM_A4

FSM_A5

FSM_A6

FSM_A7

FSM_A8

FSM_A9

FSM_A10

FSM_A11

FSM_A12

FSM_A13

FSM_A14

FSM_A15

FSM_A16

FSM_A17

FSM_A18

FSM_A19

FSM_A20

FSM_A21

FSM_A22

I/O

Standard

Stratix III

Number

Other Connections

U9 pin D1 and U4

1.8 V F23

pin A5 and U10 pin A5

U9 pin D2 and U4

1.8 V D27

pin B3 and U10 pin B3

1.8 V D28

1.8 V F25

1.8 V F26

1.8 V G24

1.8 V F24

1.8 V E26

1.8 V D26

1.8 V A30

1.8 V A33

1.8 V B31

U9 pin A2 and U4 pin B4 and U10 pin B4

U9 pin C2 and U4 pin C3 and U10 pin C3

U9 pin A3 and U4 pin C4 and U10 pin C4

U9 pin B3 and U4 pin D4 and U10 pin D4

U9 pin C3 and U4 pin H2 and U10 pin H2

U9 pin C4 and U4 pin H3 and U10 pin H3

U9 pin C4 and U4 pin H4 and U10 pin H4

U9 pi A12 and U4 pin H5 and U10 pin H5

U9 pin B5 and U4 pin G3 and U10 pin G3

U9 pin C5 and U4 pin G4 and U10 pin G4

U9 pin D7 and U4

1.8 V A31

pin F3 and U10 pin F3

U9 pin D8 and U4

1.8 V B32

pin F4 and U10 pin F4

1.8 V A32

1.8 V M23

1.8 V L23

1.8 V B29

1.8 V C29

U9 pin A7 and U4 pin E4 and U10 pin E4

U9 pin B7 and U4 pin D3 and U10 pin D3

U9 pin C7 and U4 pin H1 and U10 pin H1

U9 pin C8 and U4 pin G2 and U10 pin G2

U9 pin A8 and U4 pin H6 and U10 pin H6

1.8 V C31 U9 pin G1

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–10 Chapter 2: Board Components

MAX II CPLD

Table 2–5. MAX II Device Pin-out (Part 3 of 9)

MAX II

Pin Number

T15

P12

P14

Description Schematic Signal Name

Address bus shared with flash and P-SRAM bit 23

Address bus shared with flash and P-SRAM bit 24

Data bus shared with flash and SRAM bit 0

Data bus shared with flash and SRAM bit 1

Data bus shared with flash and SRAM bit 2

Data bus shared with flash and SRAM bit 3

Data bus shared with flash and SRAM bit 4

Data bus shared with flash and SRAM bit 5

Data bus shared with flash and SRAM bit 6

Data bus shared with flash and SRAM bit 7

Data bus shared with flash and SRAM bit 8

Data bus shared with flash and SRAM bit 9

Data bus shared with flash and SRAM bit 10

Data bus shared with flash and SRAM bit 11

Data bus shared with flash and SRAM bit 12

Data bus shared with flash and SRAM bit 13

Data bus shared with flash and SRAM bit 14

Data bus shared with flash and SRAM bit 15

Data bus shared with flash and SRAM bit 16

Data bus shared with flash and SRAM bit 17

Data bus shared with flash and SRAM bit 18

Data bus shared with flash and SRAM bit 19

FSM_A23

FSM_A24

FSM_D0

FSM_D1

FSM_D2

FSM_D3

FSM_D4

FSM_D5

FSM_D6

FSM_D7

FSM_D8

FSM_D9

FSM_D10

FSM_D11

FSM_D12

FSM_D13

FSM_D14

FSM_D15

FSM_D16

FSM_D17

FSM_D18

FSM_D19

I/O

Standard

Stratix III

Number

Other Connections

1.8 V D31 U9 pin H8

1.8 V F27 U9 pin B6

1.8 V G27

1.8 V F28

1.8 V E28

1.8 V D30

1.8 V C30

1.8 V F29

1.8 V E29

1.8 V J24

1.8 V J25

1.8 V A24

1.8 V A26

1.8 V B25

1.8 V A25

1.8 V J20

1.8 V K20

1.8 V K21

U9 pin F2 and U4 pin B6

U9 pin E2 and U4 pin C5

U9 pin G3 and U4 pin C6

U9 pin E4 and U4 pin D5

U9 pin E5 and U4 pin E5

U9 pin G5 and U4 pin F5

U9 pin G6 and U4 pin F6

U9 pin H7 and U4 pin G6

U9 pin E1 and U4 pin B1

U9 pin E3 and U4 pin C1

U9 pin F3 and U4 pin C2

U9 pin F4 and U4 pin D2

U9 pin F5 and U4 pin E2

U9 pin H5 and U4 pin F2

U9 pin G7 and U4 pin F1

U9 pin E7 and U4 pin G1

1.8 V K22 U10 pin B6

1.8 V C26 U10 pin C5

1.8 V B26 U10 pin C6

1.8 V J22 U10 pin D5

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–11

MAX II CPLD

Table 2–5. MAX II Device Pin-out (Part 4 of 9)

MAX II

Pin Number

F12

D16

F13

D15

F14

D14

E12

C15

Data bus shared with flash and SRAM bit 20

Data bus shared with flash and SRAM bit 21

Data bus shared with flash and SRAM bit 22

Data bus shared with flash and SRAM bit 23

Data bus shared with flash and SRAM bit 24

Data bus shared with flash and SRAM bit 25

Data bus shared with flash and SRAM bit 26

Data bus shared with flash and SRAM bit 27

Data bus shared with flash and SRAM bit 28

Data bus shared with flash and SRAM bit 29

Data bus shared with flash and SRAM bit 30

Data bus shared with flash and SRAM bit 31

Description Schematic Signal Name

L13 Flash address valid

K14 Flash chip enable

L15 Flash clock

M16 Flash output enable

L11 Flash ready/busy

M15 Flash reset

L12 Flash write enable

N13 Flash page select

P15 Flash page select

M14 Flash page select

N16 Flash page select

D3 FPGA configuration complete

D3 FPP configuration data bus bit 0

K4 FPP configuration data bus bit 1

M2 FPP configuration data bus bit 2

K3 FPP configuration data bus bit 3

M2 FPP configuration data bus bit 4

FSM_D20

FSM_D21

FSM_D22

FSM_D23

FSM_D24

FSM_D25

FSM_D26

FSM_D27

FSM_D28

FSM_D29

FSM_D30

FSM_D31

FLASH_ADVn

FLASH_CEn

FLASH_CLK

FLASH_OEn

FLASH_RDYBSYn

FLASH_RESETn

FLASH_WEn

PGM0

PGM1

PGM2

PGM3

FPGA_CONF_DONE

FPGA_DATA0

FPGA_DATA1

FPGA_DATA2

FPGA_DATA3

FPGA_DATA4

I/O

Standard

Stratix III

Number

Other Connections

1.8 V J21 U10 pin E5

1.8 V C24 U10 pin F5

1.8 V E25 U10 pin F6

1.8 V D25 U10 pin G6

1.8 V D24 U10 pin B1

1.8 V A27 U10 pin C1

1.8 V A29 U10 pin C2

1.8 V C27 U10 pin D2

1.8 V C28 U10 pin E2

1.8 V E23 U10 pin F2

1.8 V D23 U10 pin F1

1.8 V B28 U10 pin G1

1.8 V C7 U9 pin F6

1.8 V K25 U9 pin B4

1.8 V K24 U9 pin E6

1.8 V K23 U9 pin F8

1.8 V L16 U9 pin F7

1.8 V E13 U9 pin D4

1.8 V L22 U9 pin G8

1.8 V — SW3 pin 1

1.8 V — SW3 pin 2

1.8 V — SW3 pin 4

1.8 V — SW3 pin 8

2.5 V AH29 —

2.5 V T28 —

2.5 V T27 —

2.5 V R34 —

2.5 V R33 —

2.5 V T25 —

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–12 Chapter 2: Board Components

MAX II CPLD

Table 2–5. MAX II Device Pin-out (Part 5 of 9)

MAX II

Pin Number

Description Schematic Signal Name

L5 FPP configuration data bus bit 5

M3 FPP configuration data bus bit 6

L4 FPP configuration data bus bit 7

C2 FPP configuration clock

E4 FPGA configuration start

C3 FPGA configuration status

E10 USB command/data select

B10

J14

A11

L16

USB empty from MAX II device to Stratix III device

USB data from MAX II to Stratix III bit 0

USB data from MAX II to Stratix III bit 1

USB data from MAX II to Stratix III bit 2

USB data from MAX II to Stratix III bit 3

USB data from MAX II to Stratix III bit 4

USB data from MAX II to Stratix III bit 5

USB data from MAX II to Stratix III bit 6

USB data from MAX II to Stratix III bit 7

USB full from MAX II to Stratix III device

USB clock from MAX II to Stratix III device

USB read enable from MAX II to Stratix III device

USB write enable from MAX II to Stratix III device

Cypress USB pin multiplexed for I/O or FIFO select

Cypress USB pin multiplexed for I/O or FIFO packet commit

Cypress USB pin multiplexed for I/O or gate for other FIFO slaves

C13 Cypress/FTDI USB data bus bit 0

B16 Cypress/FTDI USB data bus bit 1

FPGA_DATA5

FPGA_DATA6

FPGA_DATA7

FPGA_DCLK

FPGA_NCONFIG

FPGA_NSTATUS

USB_CMD_DATA

USB_EMPTY

USB_FD0

USB_FD1

USB_FD2

USB_FD3

USB_FD4

USB_FD5

USB_FD6

USB_FD7

USB_FULL

USB_IFCLK

USB_REN

USB_WEN

USB_PA5_IF0ADR1

USB_PA6_PKTEND

USB_PA7_SLCSn

USB_PHY_FD0

USB_PHY_FD1

I/O

Standard

Stratix III

Number

Other Connections

2.5 V T24 —

2.5 V T32 —

2.5 V R31 —

2.5 V AL3 —

2.5 V AE25 —

2.5 V AH28 —

2.5 V Y28 —

2.5 V AH12 —

2.5 V AE33 —

2.5 V AE31 —

2.5 V AC28 —

2.5 V AA24 —

2.5 V AF34 —

2.5 V AG33 —

2.5 V AA25 —

2.5 V AE32 —

2.5 V AE11 —

2.5 V U1 —

2.5 V N5 —

2.5 V W11 —

2.5 V — U12 pin 38

2.5 V — U12 pin 39

2.5 V — U12 pin 40

2.5 V —

U12 pin 18 and U11 pin 25

U12 pin 19 and U11 pin 24

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–13

MAX II CPLD

Table 2–5. MAX II Device Pin-out (Part 6 of 9)

MAX II

Pin Number

Description Schematic Signal Name

C12 Cypress/FTDI USB data bus bit 2

A15 Cypress/FTDI USB data bus bit 3

D12 Cypress/FTDI USB data bus bit 4

B14 Cypress/FTDI USB data bus bit 5

C11 Cypress/FTDI USB data bus bit 6

B13 Cypress/FTDI USB data bus bit 7

D11 Cypress USB data bus bit 8

A13 Cypress USB data bus bit 9

E11 Cypress USB data bus bit 10

B12 Cypress USB data bus bit 11

C10 Cypress USB data bus bit 12

A12 Cypress USB data bus bit 13

D10 Cypress USB data bus bit 14

B11 Cypress USB data bus bit 15

C7 Cypress USB clock

Cypress USB command/data select

E6 Cypress USB read enable

B4 Cypress USB write enable

D6 Cypress USB empty

C4 Cypress USB full

C6 Cypress USB reset

B3 Cypress USB clock out

C5 Cypress USB wake up

Cypress USB pin multiplexed for I/O or FIFO select

Cypress USB pin multiplexed for I/O or 8051 interrupt

Cypress USB pin multiplexed for

I/O or output enable for the slave FIFOs.

Cypress USB pin multiplexed for I/O or alternate wake up signal

USB_PHY_FD2

USB_PHY_FD3

USB_PHY_FD4

USB_PHY_FD5

USB_PHY_FD6

USB_PHY_FD7

USB_PHY_FD8

USB_PHY_FD9

USB_PHY_FD10

USB_PHY_FD11

USB_PHY_FD12

USB_PHY_FD13

USB_PHY_FD14

USB_PHY_FD15

USB_PHY_IFCLK

USB_PHY_CMD_DATA

USB_PHY_REN

USB_PHY_WEN

USB_PHY_EMPTY

USB_PHY_FULL

USB_RESETn

USB_CLKOUT

USB_WAKEUP

USB_PA4_IF0ADR0

USB_PA0_INT0n

USB_PA1_INT1n

USB_PA2_SLOE

USB_PA3_WU2

I/O

Standard

2.5 V —

Stratix III

Number

Other Connections

U12 pin 20 and U11 pin 23

U12 pin 21 and U11 pin 22

U12 pin 22 and U11 pin 21

U12 pin 23 and U11 pin 20

U12 pin 24 and U11 pin 19

U12 pin 25 and U11 pin 18

2.5 V — U12 pin 45

2.5 V — U12 pin 46

2.5 V — U12 pin 47

2.5 V — U12 pin 48

2.5 V — U12 pin 49

2.5 V — U12 pin 50

2.5 V — U12 pin 51

2.5 V — U12 pin 52

2.5 V — R89

2.5 V — U12 pin 29

2.5 V — U12 pin 30

2.5 V — U12 pin 31

2.5 V — U12 pin 1

2.5 V — U12 pin 29

2.5 V — U12 pin 41

2.5 V — U12 pin 54

2.5 V — U12 pin 44

2.5 V — U12 pin 37

2.5 V —

U12 pin 33 and U11 pin 14

U12 pin 34 and U11 pin 12

2.5 V — U12 pin 35

2.5 V —

U12 pin 36 and U11 pin 11

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–14 Chapter 2: Board Components

MAX II CPLD

Table 2–5. MAX II Device Pin-out (Part 7 of 9)

MAX II

Pin Number

Description Schematic Signal Name

C8 FTDI USB read enable

A6 FTDI USB write enable

A5 FTDI USB reset

D7 FTDI USB reset output

K12 FTDI USB power enable

E10

MAX II output to power seven segment display

MAX II output to power 7-segment display

Chip select to the power monitor A/D

Clock to/from the power monitor A/D

Data from the power monitor A/D

Data to the power monitor multiplexer

Frame synchronization signal to the power monitor multiplexer

J16 Power selection input

J13 Power selection input

USB_RDn

USB_WR

USB_RSTn

USB_RSTOUTn

USB_PWR_ENn

PWR_SEG_A

PWR_SEG_B

PWR_SEG_C

PWR_SEG_D

PWR_SEG_E

PWR_SEG_F

PWR_SEG_G

PWR_SEG_DP

PWR_SEG_MINUS

PWR_DIG_SEL1

PWR_DIG_SEL2

PWR_DIG_SEL3

PWR_DIG_SEL4

PMON_CSN

PMON_CLK

PMON_SDI

PMON_DATA

PMON_SYNC

PWR_SEL0

PWR_SEL1

I/O

Standard

Stratix III

Number

Other Connections

2.5 V — U11 pin 16

2.5 V — U11 pin 15

2.5 V — U11 pin 4

2.5 V — U11 pin 5

1.8 V — U11 pin 10

2.5 V — U27 pin 12

2.5 V — U27 pin 11

2.5 V — U27 pin 3

2.5 V — U27 pin 8

2.5 V — U27 pin 2

2.5 V — U27 pin 9

2.5 V — U27 pin 7

2.5 V — U27 pin 5

2.5 V — U27 pin 13

2.5 V — U27 pin 1

2.5 V — U27 pin 10

2.5 V — U27 pin 4

2.5 V — U27 pin 6

2.5 V — U18 pin 7

2.5 V —

U18 pin 9 and U19, pin 19

2.5 V — U18 pin 8

2.5 V — U19 pin 19

2.5 V — U19 pin 17

1.8 V — SW6 pin P1

1.8 V — SW6 pin P2

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–15

MAX II CPLD

Table 2–5. MAX II Device Pin-out (Part 8 of 9)

MAX II

Pin Number

Description Schematic Signal Name

H16 Power selection input

H13 Power selection input

M4 JTAG master data input signal

N2 JTAG master data output

L16 MAX II chip select

P3 JTAG clock

N4 JTAG mode select

K15 MAX II write enable

K13 MAX II output enable

H1 Connected to Stratix III device

G4 N/A

G1 N/A

G5 N/A

H2 N/A

Synchronous clock for switching regulators

N3 JTAG clock

P2 JTAG mode select

L6 JTAG data input

M5 JTAG data output

Push-button that re-loads the

A10

factory default image into the Stratix III device

B9 JTAG input to HSMC B

D9 JTAG input to HSMC A

C8 FTDI USB read enable

A6 FTDI USB write enable

A5 FTDI USB reset

D7 FTDI USB reset output

K12 FTDI USB power enable

J12 24 MHz clock input

H12 125 MHz clock input

PWR_SEL2

PWR_SEL3

FPGA_JTAG_TDI

FPGA_JTAG_TDO

MAX_CSn

MAX_JTAG_TCK

MAX_JTAG_TMS

MAX_WEn

MAX_OEn

MAX_TO_STRATIX3

MAXGP_JTAG_TCK

MAXGP_JTAG_TDI

MAXGP_JTAG_TDO

MAXGP_JTAG_TMS

LT4601_CLK0

LT4601_CLK90

LT4601_CLK180

FPGA_JTAG_TCK

FPGA_JTAG_TMS

MAX_JTAG_TDI

MAX_JTAG_TDO

FACTORY_CONFIGn

HSMB_JTAG_TDI

HSMA_JTAG_TDI

USB_RDn

USB_WR

USB_RSTn

USB_RSTOUTn

USB_PWR_ENn

CLKIN_24

CLKIN_MAX_125

I/O

Standard

Stratix III

Number

Other Connections

1.8 V — SW6 pin P4

1.8 V — SW6 pin P8

2.5 V G28 U2 pin 13

2.5 V G29 U2 pin 10

1.8 V C20 —

2.5 V F30

U3 pin 2 and U2 pin 2

2.5 V — U3 pin 5, U2 pin 5

1.8 V G21 —

1.8 V D20 —

2.5 V K1 —

2.5 V — U3 pin 3

2.5 V — U3 pin 13

2.5 V — U3 pin 10

2.5 V — U3 pin 6

2.5 V — U32 pin A8

2.5 V — U33 pin A8

2.5 V — U34 pin A8

2.5 V F30

2.5 V H28

2.5 V —

J18 pin 35 and J8 pin 35 and U2 pin 3

J18 pin 36 and J8 pin 36 and U2 pin 6

U3 pin 14 and U2 pin 14

U3 pin 11 and U2 pin 11

2.5 V — S1

2.5 V — J8 pin 38

2.5 V — J18 pin 38

2.5 V — U11 pin 16

2.5 V — U11 pin 15

2.5 V — U11 pin 4

2.5 V — U11 pin 5

1.8 V — U11 pin 10

1.8 V — Y4 pin 3

1.8 V — Y1 pin 4

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

2–16 Chapter 2: Board Components

MAX II CPLD

Table 2–5. MAX II Device Pin-out (Part 9 of 9)

MAX II

Pin Number

Description Schematic Signal Name

G15 JTAG output from HSMC A

F15 JTAG output from HSMC B

F16 HSMC A present

G13 HSMC B present

G14 JTAG control signal

E16 JTAG control signal

F11 JTAG control signal

C14 JTAG control signal

M9 MAX II reset

M8 MAX II enable

H15 MAX II status signal

H14 MAX II status signal

G16 MAX II status signal

G12 MAX II status signal

E15 MAX II status signal

E13 MAX II status signal

E14 Control signal

D13 Control signal

R16 Control signal

N14 PFL enable

M13 N/A

N15 N/A

L14 N/A

K16 N/A

J15 N/A

E7 N/A

N1 N/A

L3 N/A

HSMA_JTAG_TDO

HSMB_JTAG_TDO

HSMA_PSNTn

HSMB_PSNTn

FPGA_BYPASS

HSMA_BYPASS

HSMB_BYPASS

JTAG_SEL

CPU_RESETn

MAX_EN

MAX_ERROR

MAX_LOAD

MAX_FACTORY

MAX_USER

MAX_EMB

DEV_SEL

MWATTS_MAMPS

VOLTS_WATTS

RESET_CONFIGn

MAX_DIP0

MAX_DIP1

MAX_DIP2

MAX_DIP3

MAX_RESERVE0

MAX_RESERVE1

OVERTEMPn

TSENSE_SMB_DATA

TSENSE_SMB_CLK

I/O

Standard

Stratix III

Number

Other Connections

1.8 V — J18 pin 37

1.8 V — J8 pin 37

1.8 V — J18 pin 160

1.8 V — J8 pin 160

1.8 V — SW1 pin 8

1.8 V — SW1 pin 7

1.8 V — SW1 pin 6

1.8 V — U3 pin 1 and J3 pin 1

1.8 V AP5 S6

1.8 V — SW1 pin 5

1.8 V — D34

1.8 V — D33

1.8 V — D36

1.8 V — D35

1.8 V — D1

1.8 V — U2 pin 1 and J2 pin 1

1.8 V — SW2 pin 1

1.8 V — SW2 pin 2

1.8 V — S7

1.8 V — SW2 pin 5

1.8 V — SW2 pin 6

1.8 V — SW2 pin 7

1.8 V — SW2 pin 8

1.8 V — SW2 pin 3

1.8 V — SW2 pin 4

2.5 V — J7 pin 2

2.5 V — U16 pin 7

2.5 V — U16 pin 6

Table 2–6 lists the MAX II component reference and manufacturing information.

Table 2–6. MAX II Component Reference and Manufacturing Information

Board Reference Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

U5 256-pin device in a BGA package Altera Corporation EPM2210GF256C3N www.altera.com

Stratix III 3SL150 Development Board May 2013 Altera Corporation Reference Manual

Chapter 2: Board Components 2–17

Configuration, Status, and Setup Elements

This section describes the board’s configuration, status, and setup elements, and is divided into the following groups:

■ “Configuration” on page 2–17

■ FPGA programming over USB

■ FPGA programming from flash memory

■ Flash programming over USB

■ “Status Elements” on page 2–19

■ Board-specific LEDs

■ Power display

■ “Setup Elements” on page 2–21

■ JTAG control DIP switch

■ MAX II device control DIP switch

■ System reset and configuration push-button switches

■ Power Select rotary switch

■ PGM Config Select rotary switch

Configuration

This section discusses FPGA, flash memory, and MAX II device programming methods supported by the Stratix III development board.

FPGA Programming Over USB

You can configure the FPGA at any time the board is powered on using the USB 2.0 interface and the Quartus II Programmer in JTAG mode.

The JTAG chain is mastered by the embedded USB-Blaster function found in the MAX II device. Only a USB cable is needed to program the Stratix III FPGA. Any device can be bypassed by using the appropriate switch on the JTAG control DIP switch.

1 Board reference SW1 position 4 (SW1.4), labeled

for this feature to work properly.

For more information about:

■ Advanced JTAG settings, refer to Table 2–7.

MAX_ENABLE

must be in the 0 position

May 2013 Altera Corporation Stratix III 3SL150 Development Board

Reference Manual

+ 57 hidden pages

Altera Stratix III Development Board User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Introduction

General Description

1. Overview

Board Component Blocks

Handling the Board

Block Diagram

Introduction

2. Board Components

Board Overview

Featured FPGA (U22)

Device Support

I/O Resources

MAX II CPLD

Configuration, Status, and Setup Elements

Configuration

FPGA Programming Over USB