ALTERA Stratix III Service Manual

Stratix® III Device Family Pin Connection Guidelines

PCG-01004-1.3

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The pin connection guidelines are considered preliminary. These pin connection guidelines should only be used as a recommendation, not as a specification. The use of the pin connection guidelines for any particular design should be verified for device operation, with the datasheet and Altera.

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Disclaimer Page 1 of 1

Stratix® III Device Family Pin Connection Guidelines

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You should create a Quartus II design, enter your device I/O assignments and compile the design. Quartus II will check your pin connections with respect to I/O assignment and placement rules to ensure proper device operation. These rules are dependent on device density, package, I/O assignments, voltage assignments and other factors that are not fully described in this document or the device handbook.

Pin Type (1st,

Pin Name

Supply and Reference Pins

VCCL Power VCCL supplies power to the core voltage power supply pins. Altera recommends that you tie these pins to 1.1 V. However, for low power designs

VCC Power VCC supplies power to the periphery circuitry. Connect these pins to 1.1V power supply. This plane may be shared with the VCCL

RUP[1:8]A

RDN[1:8]A

VCCIO[1:8][A,B,C] Power These are I/O supply voltage pins for banks 1 through 8. Each bank can support a

2nd, & 3rd Function)

I/O, Input Reference pins for I/O banks. The RUP pins share the same VCCIO with the I/O bank

I/O, Input Reference pins for I/O banks. The RDN pins share the same GND with the I/O bank

Pin Description Connection Guidelines

where they are located. The external precision resistor RUP must be connected to the designated RUP pin within the bank. If not required, this pin is a regular I/O pin.

where they are located. The external precision resistor RDN must be connected to the designated RDN pin within the bank. If not required, this pin is a regular I/O pin.

different voltage level. VCCIO supplies power to the output buffers for all LVDS, LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, 3.3 V), HSTL(12, 15, 18), SSTL(15, 18, 2),

3.0-V PCI/PCI-X I/O, and LVTTL(3.0 V, 3.3 V) I/O standards. VCCIO also supplies power to the input buffers used for LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, 3.3 V),

3.0-V PCI/PCI-X and LVTTL(3.0 V, 3.3 V) I/O standards.

using Stratix III -4L speed grade devices, VCCL is powered by 0.9 V. If 1.1 V is used, this plane may be connected to the same power plane as VCC. See note 3.

power plane if VCCL is using 1.1V. With a Proper isolation filter these pins may be shared with VCCD_PLL. For low power designs using Stratix III -4L speed grade devices, VCCL is powered by 0.9 V and VCCPT and VCC must be fully ramped before powering VCCL.

For best jitter performance on your PLL dedicated output clock, it is recommended that you isolate VCC from VCCL and use separate power supply decoupling (see note 2) when all the following design conditions are true:

• Core clock domain frequencies < 100MHz (found in Quartus II output report file)

• Design utilization (in sub-100MHz clock domains) > 40% of total resources (found in Quartus II output report file)

• Combinatorial logic (in sub-100MHz clock domains) with toggle rate > 100%, as reported by Quartus II PowerPlay Power Analyzer See note 3.

When the device does not use this dedicated input for the external precision resistor or as an I/O, Altera recommends that the pin be connected to the VCCIO of the bank in which the Rup pin resides, or GND. When using OCT, tie these pins to the required VCCIO banks through either a 25-Ω or 50-Ω resistor, depending on the desired I/O standard. Refer to the Stratix III data sheet for the desired resistor value of the I/O standard used.

When the device does not use this dedicated input for the external precision resistor or as an I/O it is recommended that the pin be connected to GND. When using OCT tie these pins to GND through either a 25 or 50 resistor depending on the desired I/O standard. Refer to the Stratix III data sheet for the desired resistor value for the I/O standard used. Connect these pins to the desired voltage level required for the I/O standard on these banks. Decoupling depends on the design decoupling requirements of the specific board. See Notes 2 and 3.

VREF[1:8][A,B,C] Power Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O

VCCA_PLL[L[1:4],R[1:4],T[1:2],B[1:2]] Power Analog power for PLLs[L[1:4],R[1:4],T[1:2],B[1:2]]. The designer must connect these

VCCD_PLL[L[1:4],R[1:4],T[1:2],B[1:2]] Power Digital power for PLLs[L[1:4],R[1:4],T[1:2],B[1:2]]. The designer must connect these

standard, then these pins are used as the voltage-reference pins for the bank.

pins to 2.5 V, even if the PLL is not used. Designer is advised to keep isolated from other VCC for better jitter performance.

pins to 1.1 V, even if the PLL is not used.

Pin Connection Guidelines Page 2 of 2

If VREF pins are not used, designers should connect them to either the VCCIO in the bank in which the pin resides or GND. Decoupling depends on the design decoupling requirements of the specific board. See Notes 2 and 3. Connect these pins to 2.5 V, even if the PLL is not used. Use an isolated linear or low noise switching power supply. Power on the PLLs operating at the same frequency should be decoupled. Decoupling depends on the design decoupling requirements of the specific board. See Notes 2 and 3.

Connect these pins to 1.1 V, even if the PLL is not used. Use an isolated linear or low noise switching power supply. With a proper isolation filter these pins may be sourced from the same regulator as VCC and/or VCCL if VCCL requires 1.1V. Decoupling depends on the design decoupling requirements of the specific board. See Notes 2 and 3.

Stratix® III Device Family Pin Connection Guidelines

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Pin Type (1st,

Pin Name

VCCPT Power Power supply for the programmable power technology. Connect to 2.5 V. Connect these pins to 2.5 V. Use an isolated linear or low noise switching power

VCCPGM Power

VCCPD[1:8][A,B,C] Power Dedicated power pins. This supply is used to power the I/O pre-drivers. This can be

VCCBAT Power Battery back-up power supply for design security volatile key register. Connect this pin to a Non-volatile battery power source in the range of 1.0 - 3.3 V when

VCC_CLKIN[3,4,7,8] Power Differential clock input power supply for top and bottom I/O bank. Connect to 2.5 V. Connect these pins to 2.5 V power source. Decoupling depends on the design

GND Ground Device ground pins. All GND pins should be connected to the board ground plane. DNU Do Not Use

NC No Connect Do not drive signals into these pins. When designing for device migration these pins may be connected to power, ground,

Dedicated Configuration/JTAG Pins

nIO_PULLUP Input Dedicated input that chooses whether the internal pull-ups on the user I/O pins and

2nd, & 3rd Function)

Pin Description Connection Guidelines

supply. The voltage on these pins must ramp-up from 0 to 2.5 V within 5 ms to ensure successful configuration. For low power designs using Stratix III -4L speed grade devices, VCCL is powered by 0.9 V and VCCPT and VCC must be fully ramped before powering VCCL. Decoupling depends on the design decoupling requirements of the specific board. See Notes 2 and 3.

Dedicated Configuration power supply. Can be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the particular design.

connected to 3.3 V, 3.0 V, or 2.5 V. VCCPD for 3.3-V I/O standard is 3.3 V, VCCPD for 3.0-V I/O standard is 3.0 V, and VCCPD for 2.5-V/1.8-V/1.2-V I/O standards is

2.5 V.

Do not connect to power or ground or any other signal; must be left floating.

dual-purpose I/O pins (DATA[7:0], CLKUSR, INIT_DONE, DEV_OE, DEV_CLRn, CRC_ERROR) are on or off before and during configuration. A logic high (1.8, 2.5,

3.0, or 3.3 V) turns off the weak pull-up, while a logic low turns them on.

Connect this pin to either 1.8, 2.5, 3.0, or 3.3-V power supply. Decoupling depends on the design decoupling requirements of the specific board. See Notes 2 and 3.

The VCCPD pins require 2.5, 3.0, or 3.3V and must ramp-up from 0 to 2.5, 3.0, or

3.3V within 100 ms to ensure successful configuration. Decoupling depends on the design decoupling requirements of the specific board. See Notes 2 and 3.

using design security volatile key. 3.0 V is the typical power selected for this supply. When not using the volatile key, tie this to a 3.0 V supply or GND. Do not share this source with other FPGA power supplies.

decoupling requirements of the specific board. See Note 2.

These Pins must be left unconnected.

or a signal trace depending on the pin assignment of the devices selected for migration. However, if device migration is not a concern leave these pins floating.

The nIO-PULLUP can be tied directly to VCCPGM, use a 1-kΩ pull-up resistor or tied directly to GND depending on the use desired for the device. Refer to the description column.

TEMPDIODEp Input Pin used in conjunction with the temperature sensing diode (bias-high input) inside the

Stratix III device.

TEMPDIODEn Input Pin used in conjunction with the temperature sensing diode (bias-low input) inside the

Stratix III device.

MSEL[2:0] Input Configuration input pins that set the Stratix III device configuration scheme. These pins are internally connected through a 5-kΩ resistor to GND. Do not leave

nCE Input Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE

is high, the device is disabled.

nCONFIG Input Dedicated configuration control input. Pulling this pin low during user-mode will cause

the FPGA to lose its configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a logic high level will initiate reconfiguration.

If the temperature sensing diode is not used then connect this pin to GND.

these pins floating. When these pins are unused connect them to GND. Depending on the configuration scheme used these pins should be tied to VCCPGM or GND. Refer to chapter 11, "Configuring Stratix III Devices", of the Stratix III Handbook. If only JTAG configuration is used then connect these pins to ground.

In multi-device configuration, nCE of the first device is tied directly to GND while its nCEO pin drives the nCE of the next device in the chain. In single device configuration and JTAG programming, nCE should be connected directly to GND.

If this pin is not used this pin requires a connection directly or through a 10-kΩ resistor to VCCPGM.

Pin Connection Guidelines Page 3 of 3

Stratix® III Device Family Pin Connection Guidelines

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Pin Type (1st,

Pin Name

CONF_DONE Bidirectional

2nd, & 3rd Function)

(open-drain)

Pin Description Connection Guidelines

This is a dedicated configuration Done pin. As a status output, the CONF_DONE pin drives low before and during configuration. Once all configuration data is received without error and the initialization cycle starts, CONF_DONE is released. As a status input, CONF_DONE goes high after all data is received. Then the device initializes and enters user mode. It is not available as a user I/O pin.

Connect this pin to an external 10-kΩ pull-up resistor to a supply that provides an acceptable input signal for the Stratix III device. VCCPGM should be high enough to meet the V

specification of the I/O on the external device.

nCEO Output Output that drives low when device configuration is complete. During multi-device configuration,this pin feeds a subsequent device’s nCE pin. During

nSTATUS Bidirectional

(open-drain)

PORSEL Input Dedicated input which selects between a POR time of 12 ms or 100 ms. A logic high

TCK Input Dedicated JTAG test clock input pin. Connect this pin to a 1-kΩ pull-down resistor to GND. The JTAG circuitry can be

TMS Input Dedicated JTAG test mode input pin. Connect this pin to a 1k - 10kΩ pull-up resistor to VCCPD. To disable the JTAG

TDI Input Dedicated JTAG test data input pin. Connect this pin to a 1k - 10kΩ pull-up resistor to VCCPD. To disable the JTAG

TDO Output Dedicated JTAG test data output pin. The JTAG circuitry can be disabled by leaving TDO unconnected. TDO is powered

TRST Input Dedicated active low JTAG test reset input pin. TRST is used to asynchronously reset

Clock and PLL Pins

CLK[1,3,8,10]p Clock, Input Dedicated high speed clock input pins 1, 3, 8, and 10 that can also be used for data

CLK[1,3,8,10]n Clock, Input Dedicated negative clock input pins for differential clock input that can also be used

CLK[0,2,9,11]p I/O, Clock These pins can be used as I/O pins or clock input pins. OCT Rd is supported on these

CLK[0,2,9,11]n I/O, Clock These pins can be used as I/O pins or negative clock input pins for differential clock

CLK[4:7,12:15]p I/O, Clock These pins can be used as I/O pins or clock input pins. OCT Rd is not supported on

This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after power-up and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during configuration. As a status input, the device enters an error state when nSTATUS is driven low by an external source during configuration or initialization. It is not available as a user I/O pin.

(1.8, 2.5, 3.0, or 3.3 V) selects a POR time of 12 ms and a logic low selects POR time of 100 ms.

the JTAG boundary-scan circuit.

inputs. OCT Rd is not supported on these pins.

for data inputs. OCT Rd is not supported on these pins.

pins.

inputs. OCT Rd is supported on these pins.

these pins.

single device configuration, this pin is left floating. For recommendations on how to connect nCEO in a chain with multiple voltages across the devices in the chain, refer to the Stratix III chapter in Volume 1 of the Stratix III Device Handbook.

Connect this pin to an external 10-kΩ pull-up resistor to a supply that provides an acceptable input signal for the Stratix III device. VCCPGM should be high enough to meet the V

The PORSEL pin should be tied directly to VCCPGM or GND.

disabled by connecting TCK to GND. TCK is powered by VCCPD1A.

circuitry connect TMS to VCCPD. TMS is powered by VCCPD1A.

circuitry connect TDI to VCCPD. TDI is powered by VCCPD1A.

by VCCPD1A. Utilization of TRST is optional. When using the JTAG circuitry but not using TRST tie this pin directly to VCCPD. To disable the JTAG circuitry, tie this pin to GND. TRST is powered by VCCPD1A.

Connect unused pins to GND.

These pins can be tied to GND or left unconnected. If unconnected, use Quartus II software programmable options to internally bias these pins. They can be reserved as inputs tristate with weak pull up resistor enabled, or as outputs driving GND.

specification of the I/O on the external device.

Pin Connection Guidelines Page 4 of 4

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ALTERA Stratix III Service Manual

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