Altera Stratix III User Manual

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Stratix III Development Kit

User Guide

101 Innovation Drive San Jose, CA 95134 www.altera.com

P25-36210-01

Document Version: 1.1 Document Date: August 2008

Copyright © 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services

UG-01028-1.1

Chapter 1. About This Kit

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Kit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Chapter 2. Getting Started

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Before You Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Check the Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Inspect the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Hardware Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

Chapter 3. Software Installation

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Installing the Development Kit CD-ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Installing the Quartus II DVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Installing the USB-Blaster Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Licensing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Chapter 4. Development Board Setup

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Powering Up the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Configuring the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

Chapter 5. Power Measurement

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Power Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Measuring Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

A/D Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

Measuring Core Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

Measuring I/O Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

Measuring Voltage with a DMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

Calculating Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

Changing the Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

Chapter 6. Design Tutorials

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

My First FPGA Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

My First Nios II Software Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

Appendix A. Programming the Flash Device

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1

Creating a Flash File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1

Parallel Flash Loader Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3

Programming the Flash Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3

Preliminary

iv Contents

Restoring the Factory Design to the Flash Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5

Additional Information

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2

Stratix III Development Kit User Guide © August 2008 Altera Corporation

Preliminary

Introduction

1. About This Kit

Welcome to the Altera® Stratix®III Development Kit, which includes a full-featured field-programmable gate array (FPGA) development board, hardware and software development tools, documentation, and accessories needed to begin FPGA development.

The kit provides an integrated control environment that includes a USB command controller, a multi-port SRAM/DDR SDRAM/flash memory controller, Ethernet, an on-board meter, and example designs with demonstration circuitry specified in Verilog HDL code to help you get started quickly with your own designs.

The development board includes an Altera Stratix III FPGA configured with a hardware reference design stored in flash memory. You can use the development board, along with example designs included in the kit, as a platform to prototype complex embedded systems.

The development kit includes these kit features and documentation:

Kit Features

■ Stratix III development board

■ Altera Complete Design Suite DVD containing:

■ Quartus

■ MegaCore

■ Nios

■ Stratix III Development Kit CD-ROM including design examples

■ Accessory daughter cards

■ Power supply, cables, and documentation

II Software, Development Kit Edition (DKE)

IP Library

II Embedded Design Suite

This section briefly describes the following Stratix III Development Kit features:

■ Stratix III Development Board—a prototyping platform that allows you to

develop and prototype hardware designs running on the Stratix III FPGA.

f For specific information about board components and interfaces, refer to

the Stratix III Development Board Reference Manual.

■ Quartus II Software, Development Kit Edition (DKE)—The Quartus II software

(available on the DVD) provides a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software integrates into nearly any design environment, with interfaces to industry-standard EDA tools. The kit includes:

■ The SOPC Builder system development tool

■ A one-year Quartus II software license (Windows platform only)

1–2 Chapter 1: About This Kit

Documentation

f The Quartus II DKE software license allows you to use the product for

12 months. After 12 months, you must purchase a renewal subscription to continue using the software. For more information, refer to the Altera website at www.altera.com.

■ MegaCore IP Library—This library (available on the DVD) contains Altera IP

MegaCore functions. You can evaluate MegaCore functions by using the OpenCore

■ Simulate behavior of a MegaCore function within your system

■ Verify functionality of your design, and quickly and easily evaluate its size and

Plus feature to do the following:

speed

■ Generate time-limited device programming files for designs that include

MegaCore functions

■ Program a device and verify your design in hardware

1 The OpenCore Plus hardware evaluation feature is an evaluation tool for

prototyping only. You must purchase a license to use a MegaCore function in production.

■ Nios II Embedded Design Suite—This full-featured set of tools (available on the

■ Stratix III Development Kit Design Examples—The design examples (available

You only need to purchase a license for a MegaCore function when you are completely satisfied with its functionality and performance, and want to take your design to production.

Documentation

The Stratix III Development Kit CD-ROM contains the following documents:

■ Readme.txt—Contains special instructions and refers to the kit documentation.

■ Stratix III Development Kit User Guide (this document)—Describes how to use the

■ Stratix III Development Board Reference Manual—Provides specific information

f For more information about OpenCore Plus, refer to AN 320: OpenCore

Plus Evaluation of Megafunctions.

DVD) allows you to develop embedded software on the Nios II processor running on Altera FPGAs.

on the CD-ROM) are useful for a variety of hardware applications and let you quickly begin board prototyping and device verification.

kit.

about the board components and interfaces, steps for using the board, and pin-outs and signal specifications.

Stratix III Development Kit User Guide © August 2008 Altera Corporation

Introduction

2. Getting Started

This user guide familiarizes you with the contents of the kit and guides you through the Stratix III development board setup. Using this guide, you can do the following:

■ Inspect the contents of the kit

■ Install the Altera Complete Design Suite Tools

■ Set up licensing

■ Install the Stratix III Development Kit CD-ROM

■ Set up, power up, and verify correct operation of the development board

■ Configure the Stratix III FPGA

■ Find and use the tutorials

■ Set up and run included application examples and demonstrations

f For complete information about the development board, refer to the Stratix III

Development Board Reference Manual.

Before You Begin

Before using the kit or installing the software, check the kit contents and inspect the board to verify that you received all of the items listed in this section. If any of the items are missing, contact Altera before you proceed.

Check the Kit Contents

The Stratix III Development Kit (ordering code: DK-DEV-3SL150N) contains the following items:

■ Stratix III development board with an EP3SL150C3N Stratix III device

■ Altera Complete Design Suite DVD containing:

■ One-year license of Quartus II Software (DKE), Windows platform only

■ MegaCore IP Library

■ Nios II Embedded Design Suite

2–2 Chapter 2: Getting Started

■ Stratix III Development Kit CD-ROM, which includes:

■ Reference designs and demonstrations

■ Stratix III development kit application and device drivers

■ Design examples and tutorials

■ Stratix III Development Board Reference Manual

■ Stratix III Development Kit User Guide (this document)

■ Schematic and board design files

■ USB cable

■ Accessory daughter cards:

■ Two loopback high-speed mezzanine connector (HSMC) cards

■ Debug HSMC card

■ 16 character × 2 line Liquid Crystal Display (LCD)

■ 128 × 64 dot matrix graphics LCD

■ 16-V DC Power supply and adapters for North America, Europe, the United

Before You Begin

Kingdom, and Japan.

f To ensure that you have the most up-to-date information about this product, go to the

Inspect the Board

w Without proper anti-static handling, the Stratix III development board can be

1 In typical applications with the Stratix III development board, a heatsink is not

f For more information about power consumption and thermal modeling, refer to

Altera website at www.altera.com/products/devkits/altera/kit-siii-host.html.

Place the board on an anti-static surface and inspect it to ensure that it has not been damaged during shipment.

damaged.

Verify that all components are on the board and appear intact.

necessary. However, under extreme conditions the board may require additional cooling to stay within operating temperature guidelines. You may wish to perform power consumption and thermal modeling to determine whether your application requires additional cooling.

AN 358: Thermal Management for FPGAs.

Stratix III Development Kit User Guide © August 2008 Altera Corporation

Chapter 2: Getting Started 2–3

References

Hardware Requirements

The Quartus II software has some minimum system requirements. Otherwise, the Stratix III development kit provides all of the hardware needed to use the board.

f For Quartus II software requirements, refer to the Altera website at:

www.altera.com/products/software/products/quartus2web/sofquarwebmain.html.

Software Requirements

This kit requires the following software:

■ Windows XP operating system

■ Quartus II software (refer to the readme.txt file on the CD-ROM for specific

version requirements)

References

For other related information, refer to the following websites:

■ For additional daughter cards available for purchase:

www.altera.com/products/devkits/kit-daughter_boards.jsp

■ For the Stratix III device documentation:

www.altera.com/literature/lit-stx3.jsp

■ For eStore if you want to purchase devices:

www.altera.com/buy/devices/buy-devices.html

■ For Stratix III Orcad symbols:

www.altera.com/support/software/download/pcb/pcb-pcb_index.html

■ For Nios II 32-bit embedded processor solutions:

www.altera.com/technology/embedded/emb-index.html

2–4 Chapter 2: Getting Started

References

Stratix III Development Kit User Guide © August 2008 Altera Corporation

Introduction

The instructions in this section explain how to install the following:

■ Stratix III Development Kit CD-ROM

■ Stratix III Development Kit demo application and drivers

■ The Quartus II Software (DKE) on the DVD, including MegaCore functions from

the MegaCore IP Library

1 Before starting the installation, verify that you have complied with the conditions

described in “Software Requirements” on page 2–3.

Installing the Development Kit CD-ROM

The Stratix III Development Kit CD-ROM contains the following items:

3. Software Installation

■ The sample design and board design files

■ Quick Start Guide

■ My First FPGA Tutorial

■ My First Nios II Software Tutorial

■ Stratix III Development Kit User Guide (this document)

■ Stratix III Development Board Reference Manual

To install the Stratix III Development Kit CD-ROM, perform the following steps:

1. Insert the Stratix III Development Kit CD-ROM into the CD-ROM drive.

1 The CD-ROM should start an auto-install process. If it does not, browse to

the CD-ROM drive and double-click on the setup.exe file.

2. Follow the on-screen instructions to complete the installation process.

The installation program copies the Stratix III development kit files to an installation directory on the computer hard disk and creates a Programs > Altera > Stratix III Development Kit <version#> Windows Start menu shortcut. Use this shortcut later to launch the development kit graphical user interface (GUI).

The installation program creates the directory structure shown in Figure 3–1 for the Stratix III development kit files. In this user guide, <path> refers to <installation directory>\stratixIII_3sl150_dev when locating the development kit files.

3–2 Chapter 3: Software Installation

<path>

stratixIII_3sl150_dev

demos

documents

board_design_files

The default Windows installation directory is C:\altera\

<version#>

\kits.

examples

factory recovery

Installing the Quartus II DVD

Figure 3–1. Stratix III Development Kit Installed Directory Structure

Tab le 3– 1 lists the file directory names and a description of their contents.

Table 3–1. Installed Directory Contents

Directory Name Description of Contents

board_design_files Contains schematic, layout, assembly, and bill of material board design files. Use these files as a

starting point for a new prototype board design.

demos Contains demonstration applications that may change from release to release.

documents Contains the development kit documentation.

examples Contains the sample design files for the Stratix III Development Kit.

factory recovery Contains the original data programmed onto the board before shipment. Use this data to put the

board into the original condition.

1 The examples directory contains a golden top project example with all the pin-out and

pin configuration information included.

Installing the Quartus II DVD

The Quartus II software is the primary FPGA development tool used to create the reference designs in this development kit. Additionally, you may want to install the Nios II Embedded Design Suite found in the Altera Complete Design Suite at

www.altera.com/support/software/download/nios2/dnl-nios2.jsp. The Nios II

embedded processor runs on Altera FPGAs. Some of the reference designs included in this development kit use the Nios II processor.

Insert the Altera Complete Design Suite DVD into the DVD drive, and click Install subscription package on the startup window. Follow the on-screen instructions and accept all default settings. After installing the software, request and install a license to enable it.

f For information about obtaining a license file, refer to “Licensing Considerations” on

page 3–3.

Stratix III Development Kit User Guide © August 2008 Altera Corporation

Chapter 3: Software Installation 3–3

Installing the USB-Blaster Driver

The Stratix III development board includes integrated USB-Blaster™ circuitry for FPGA programming. However, for the host computer and development board to communicate, you must install the USB-Blaster driver on the host computer.

f To download the USB-Blaster driver, go to the Altera support site at

www.altera.com/support/software/drivers/dri-index.html.

To install it, go to www.altera.com/support/software/drivers/usb-blaster/dri-usb-

blaster-xp.html.

Licensing Considerations

Before using the Quartus II software, you must request a license file from the Altera website at www.altera.com/licensing and install it on your computer. When you request a license file, Altera emails you a license.dat file that enables the software.

To license the Quartus II software, you need your network interface card (NIC) ID, which is a 12-digit hexadecimal number that identifies your computer. Networked (or floating-node) licensing requires a NIC ID or server host ID. When obtaining a license file for network licensing, use the NIC ID from the computer that issues the Quartus II licenses to distributed users over a network. You can find the NIC ID for your card by typing ipconfig/all at a command prompt. Your NIC ID is the number on the physical address line, without the dashes.

To obtain a license, perform the following steps.

1. Go to the Altera website at www.altera.com/support/licensing/lic-choose.html.

2. Under Development Kit Licenses Request, click Licenses for RoHS-Compliant Kits.

3. Follow the on-screen instructions to request your license. You will receive a license file through email.

1 Before installing your license, close the following software if it is running

on your computer:

■ Quartus II software

■ MAX+PLUS

■ LeonardoSpectrum

■ Synplify software

■ ModelSim

■ Precision RTL Synthesis Software

II software

simulator

™

synthesis tool

4. To install your license, refer to the Specifying the License File section in the Quartus II

Installation & Licensing for Windows Manual, which is included with the kit.

3–4 Chapter 3: Software Installation

Licensing Considerations

Stratix III Development Kit User Guide © August 2008 Altera Corporation

Introduction

Requirements

1 The Stratix III development board includes integrated USB-Blaster circuitry for FPGA

4. Development Board Setup

The instructions in this chapter explain how to install the development board and configure the FPGA.

Before starting the installation, verify that you have complied with the conditions described in “Hardware Requirements” on page 2–3 and have completed the following requirements:

■ Quartus II software installed on the host computer

■ USB-Blaster driver software installed on the host computer.

programming. Host computer and development board cannot communicate without the USB-Blaster driver software installed. For installation information, refer to

“Installing the USB-Blaster Driver” on page 3–3.

Powering Up the Board

Figure 4–1 shows the Stratix III development board and its components.

4–2 Chapter 4: Development Board Setup

Stratix III

FPGA (U22)

MAX II

CPLD (U5)

Device Select (J2)

Jumper

24 MHz Crystal (Y2)

6 MHz Crystal (Y3)

125 MHz MAX II Clock (Y1)

Type B USB Connector (J5)

MAX II Control DIP Switch (SW2)

Ethernet PHY LEDs (D6, D7, D8) and Duplex LED (D9)

PGM Config Select Rotary Switch (SW3)

RJ-45 Ethernet Connector (J14)

Clock In/Out SMAs (J16, J17)

Ethernet PHY TX/RX Activity LEDs (D14, D15)

Factory Configuration Push Button (S1)

Power Switch (SW4)

DC Power Jack (J21)

User Push Buttons (S2 through S5)

Reset Configuration Push Button (S7)

Configuration

Done LED (D32)

Board-Specific

LEDs (D33-D36)

User LEDs (D20 through D27)

CPU Reset

Push Button (S6)

Flash Memory Device (U9)

24 MHz Crystal (Y4)

DDR2 SDRAM (U17, U20)

DDR2 SDRAM DIMM Connector (J19)

Power Select

Rotary Switch (SW6)

Power LED (D16)

HSMC Port A (J18)

HSMC Port B (J8)

HSMC Port A

Present LED (D17)

Power Display (U27)

User DIP Switch (SW5)

HSMC Port A

TX/RX Activity

LEDs (D11, D12)

HSMC Port B

Present LED (D10)

Speaker Header (J1)

HSMC Port B

TX/RX Activity LEDs

(D2, D3)

User Display (U28)

QDRII+ SRAM (U15)

(Behind the LCD Screen)

JTAG Control DIP Switch (SW1)

MSEL0 to GND

Jumper (J13)

Powering Up the Board

Figure 4–1. Stratix III Development Board Layout and Components

Before powering up, prepare the board as follows:

1. If cards are plugged into the HSMC ports, remove them.

2. Ensure that the POWER switch SW4 is in the OFF (or DOWN) position.

3. Configure the 8-position SW2 DIP switch to the default settings in Table 4–1.

Table 4–1. Switch SW2 Settings (Part 1 of 2)

Function

Switch Name

1 mW/mA mW mA 0

2V/W V W 1

3 RSV0 MAX_RESERVE0 X

4 RSV1 MAX_RESERVE1 X

Stratix III Development Kit User Guide © August 2008 Altera Corporation

Default

PositionPosition 0 Position 1

Chapter 4: Development Board Setup 4–3

Configuring the FPGA

Table 4–1. Switch SW2 Settings (Part 2 of 2)

Function

Switch Name

5 MAX0 PFL Disable PFL Enable 1

6 MAX1 MAX_DIP1 X

7 MAX2 MAX_DIP2 X

8 MAX3 MAX_DIP3 X

Note to Tab le 4–1:

(1) X = don’t care

Default

PositionPosition 0 Position 1

4. Ensure that the 4-position SW1 mini-DIP switches and the two jumpers are set to the default positions shown in Tab le 4 –2 .

Table 4–2. Initial Switch and Jumper Settings

DEV_SEL-J2 JTAG_SEL-J3 SW1.1 SW1.2 SW1.3 SW1.4

ON ON ON OFF OFF OFF

5. Ensure that the J13 MSEL0 GND jumper is ON.

6. Verify that the PGM CONFIG SELECT rotary switch SW3 is set to 0.

At power up, the development board uses a preloaded configuration to demonstrate that the board is operating correctly.

Power up the development board by performing the following steps:

1. Connect the 16-V DC adapter to the development board and to a power source.

w Use only the supplied 16-V power supply. Power regulation circuitry on the board

could be damaged by supplies greater than 16 V.

2. Slide the POWER switch to ON. The nearby blue POWER light-emitting diode (LED) lights up.

3. Confirm that user LEDs 0-7 flash in a scrolling, side-to-side pattern. For customized configurations, the pattern depends on the application.

f For information about custom configurations, refer to “Programming the Flash

Device” on page A–3.

Configuring the FPGA

Before configuring the FPGA, ensure that the Quartus II software and the USB-Blaster driver software are installed on the host computer and the development board is powered on.

f For USB-Blaster driver installation information, refer to “Installing the USB-Blaster

Driver” on page 3–3.

4–4 Chapter 4: Development Board Setup

Configuring the FPGA

To configure the Stratix III FPGA, perform the following steps:

1. Verify that the 4-position SW1 mini-DIP switches and the two jumpers are set to the default positions shown in Tab le 4 –2 .

2. Connect the USB cable to the development board USB port.

3. Cycle the POWER switch OFF then ON.

4. Start the Quartus II software.

5. On the Tools menu, click Programmer. The Quartus II Programmer appears.

6. Click Add File and select <path>\examples\stratixIII_3sl150_dev_my_first_fpga \stratixIII_3sl150_dev_my_first_fpga.sof.

7. Turn on the Program/Configure option for the added file.

8. Click Start to download the selected file to the FPGA. The FPGA is configured when the progress bar reaches 100%.

9. Confirm that user LEDs 0-3 flash in a slow binary counting pattern.

Stratix III Development Kit User Guide © August 2008 Altera Corporation

Introduction

One of the main features of the Stratix III FPGA device is its low power consumption. You can measure the power used by the 3SL150 FPGA device on the Stratix III development board for various conditions with a power design example provided with the kit.

With the power design example, you can control the amount of logic utilized in the FPGA, the clock frequency, and the number of I/Os used, and measure the effect on power used by the Stratix III device.

Power Design Example

The power design example uses a replicated module, stamp.v, that contains combinational logic, randomly filled ROMs, multiplier blocks, and shift registers that change with every clock cycle. The frequency and resource states indicated in

Tab le 5 –2 and Table 5–3 on page 5–2, respectively, represent the percent of full design

used. As compiled, the full example design uses the following FPGA resources:

5. Power Measurement

■ Combinational adaptive look-up tables (ALUTs): 1,872 / 113,600 (2%)

■ Dedicated logic registers: 106,640 / 113,600 (94%)

■ Total registers: 106,640

■ Total pins: 173 / 744 (23%)

■ Total memory bits: 2,621,440 / 5,630,976 (47%)

■ Embedded multiplier 18-bit elements: 320 / 384 (83%)

■ Total PLLs: 1/8 (13%)

Tab le 5 –1 describes the functionality of the four user push buttons that control the

power design example. The on-board 50-MHz oscillator provides the input clock (i_clk, PIN_T33).

Table 5–1. Four Input Button Functionality

User Push

Button FPGA Pin Type Description

User_PB0 B17 Reset Resets the demo to the beginning, i_nrst

User_PB1 A17 Toggle Advances the design example to the next higher frequency, i_nfreq_next

User_PB2 A16 Toggle Advances the design example to the next higher resource utilization,

i_nperc_next

User_PB3 K17 Toggle Enables the outputs to toggle, i_noutput_ena

5–2 Chapter 5: Power Measurement

Power Design Example

The LEDs in Tab le 5 –2 indicate the power-state values of the design example as User_PB1 advances frequency.

Table 5–2. Power State Indicators for Frequency

LED1 (C23) LED0 (F21) Frequency (MHz)

000

0133

1067

1 1 100

The LEDs in Tab le 5 –3 indicate the power-state values of the design example (and number of output pins, when enabled by User_PB3) as User_PB2 advances resource utilization.

Table 5–3. Power State Indicators for Resources

LED6 (F19)

LED5 (C19)

LED4

(D19)

LED3 (A23)

LED2 (B23)

Resources

(%)

Number of

Outputs

0000058

000011016

000101524

000112032

001002540

001013048

001103556

001114064

010004572

010015080

010105588

010116096

0110065104

0110170112

0111075120

0111180128

1000085136

1000190144

1001095152

10011100160

The resource state (Table 5–3) controls the number of I/O pins used. Each resource increment adds eight additional I/O pins (Tabl e 5– 3). Similarly, the overall design frequency (Tab le 5 –2) sets the toggle frequency of these I/O pins.

Stratix III Development Kit User Guide © August 2008 Altera Corporation

Chapter 5: Power Measurement 5–3

Measuring Power

You can measure power by using the analog-to-digital (A/D) circuitry on the development board or by using a digital multimeter (DMM) across on-board sense resistors. However, note that, depending on the DMM accuracy, the on-board A/D measurements tend to produce considerably more accurate results.

A/D Measurements

The POWER SELECT rotary switch SW6 sets the development board to measure and display FPGA core power or I/O output power (Tab le 5 –4 ).

Table 5–4. Switch SW6 Power Selection

Switch Position FPGA Power I/O Bank

0 Core: VCCL, TBD V —

7 I/O: 2.5 V 2

8 I/O: 2.5 V 4, 5, and 6

Measuring Core Power

To measure FPGA core power for various power states, perform the following steps:

1. Ensure that the 8-position SW2 DIP switch is configured to the default settings shown in Table 4–1 on page 4–2.

2. Download the stratixIII_dev_power.sof file as described in “Configuring the

FPGA” on page 4–3. The power design example is in

<path>\demos\stratixIII_3sl150_dev_power.

3. Set the POWER SELECT rotary switch SW6 to 0 to measure the internal V

CC_INT

power in watts.

4. Observe the power on the 4-digit hexadecimal POWER DISPLAY.

5. Using the user input push buttons (Table 5–1 on page 5–1), advance through the power states in Table 5–2 and Table 5–3 on page 5–2. Notice how power increases as frequency and resources increase.

Measuring I/O Power

This example uses FPGA I/O banks 2, 4, 5, and 6. Using the SW6 settings (Tab le 5 –4 ), measure the power for I/O banks 4, 5, and 6, then for I/O bank 2, by performing the following steps:

1. Ensure that the 8-position SW2 DIP switch is configured to the default settings shown in Table 4–1 on page 4–2.

2. Download the stratixIII_dev_power.sof file as described in “Configuring the

FPGA” on page 4–3. The power design example is in

<path>\demos\stratixIII_3sl150_dev_power.

3. Set the POWER SELECT rotary switch SW6 to 8.

4. Observe the 4-digit hexadecimal POWER DISPLAY for the I/O output power in watts on banks 4, 5, and 6.

5–4 Chapter 5: Power Measurement

Measuring Power

6. Press the User_PB3 button to enable the output pins on the HSMC connectors J8 and J18. LED7 (E19), signal o_noutput_ena_state, lights to indicate that the outputs are enabled and toggling. Enabling the outputs further increases power for each resource utilization percentage used by the Stratix III FPGA.

7. Press the User_PB3 button again to disable the outputs. LED7 turns off.

8. Set the POWER SELECT rotary switch SW6 to 7.

9. Repeat steps 4 through 7 to observe the I/O output power in watts on bank 2.

The sum of power results from the two sets of I/O banks provides the total FPGA I/O power.

f For specific information about on-board measurements and the POWER SELECT

rotary switch, refer to the Stratix III Development Board Reference Manual.

Measuring Voltage with a DMM

1 For best results, use a DMM with six-digit or greater accuracy.

Calculating Power

To obtain power values by using a DMM, measure voltage across the sense-resistors, R215, R218, and R214 on the board, then use the voltage measurements to calculate power.

FPGA I/O power is distributed by banks (Table 5–5), for which the sense resistors are components R218 and R214. For the I/O power calculation, use the sum of voltage measurements across these resistors while outputs are enabled. For the FPGA core power calculation, measure the sense resistor voltage across R215.

Table 5–5. Sense Resistors

FPGA Power Voltage

Sense

Resistor

Value

I/O Bank 2 2.5 V R214 0.009 Ω

Banks 4, 5 and 6 2.5 V R218 0.009 Ω

Core: VCCL 1.1 V R215 0.009 Ω

To obtain the power P in watts, measure the voltage across the sense resistors, V

SENSE

and calculate the nominal power as follows:

= Voltage measured across the sense resistor

SENSE

= Current through the sense resistor

SENSE

= FPGA supply voltage

SUPPLY

= Sense resistor value in Ta bl e 5–5 .

SENSE

Chapter 5: Power Measurement 5–5

PVIV

SUPPLYISENSE

SUPPLYVSENSE

SENSE

---------------------------------------------===

Changing the Design Example

then

Equation 5–1.

where

is 1.1 V for the FPGA core and 2.5 V for FPGA I/O.

SUPPLY

Voltage measurements on the DMM should increase as frequency and resource utilization increases according to Tab le 5 –2 and Table 5–3 on page 5–2.

Changing the Design Example

The development kit includes source code for the Stratix III power design example so you can use it as a starting point for your own measurements.

The design example uses 20 stamp.v modules, each with 8 outputs, for a total of 160 output pins. It assigns the pins selected as outputs to the HSMC connectors J8 and J18.

To change the number of outputs, modify the design example and assign the pins appropriately.

1 Power should track linearly with frequency and percentage resources. If you observe

superlinear power measurements, some temperature issue may be the cause.

5–6 Chapter 5: Power Measurement

Changing the Design Example

Introduction

The example designs and tutorials included in the Stratix III Development Kit help familiarize new users with development board features. My First FPGA Tutorial and My First Nios II Software Tutorial provide step-by-step guidance for the first-time user.

My First FPGA Tutorial

My First FPGA Tutorial describes how to create a simple Altera FPGA design. The tutorial takes less than an hour to complete and provides an overview of the design flow using Quartus II software to build a simple logic counter which drives LEDs to flash on the development board.

After installing the Stratix III Development Kit CD-ROM, the My First FPGA Tutorial design and documentation can be found at: <path>\documents\tutorials\hardware_tutorials\my_first_fpga_tutorial.pdf.

6. Design Tutorials

My First Nios II Software Tutorial

My First Nios II Tutorial introduces the basic system development flow for the Nios II processor. This tutorial provides a good starting point if you are new to the Nios II processor or to the general concept of using an embedded processor in an FPGA. In this tutorial, you use a standard, existing Nios II hardware system and create a software program to run on it.

After installing the Stratix III Development Kit CD-ROM, the My First Nios II Software

Tu t or i a l design and documentation can be found at: <path>\documents\tutorials\software_tutorials\my_first_nios2_software_tutorial .pdf.

6–2 Chapter 6: Design Tutorials

My First Nios II Software Tutorial

Overview

A. Programming the Flash Device

There is a Common Flash Interface (CFI) type flash memory device on the Stratix III development board. When you first receive the kit, this CFI flash device arrives programmed with a default factory configuration that was loaded from a Programmer Object File (.pof).

When you power up the board, the CFI flash device configures the FPGA with the default factory configuration using Fast Passive Parallel (FPP) programming. If the configuration loads correctly, the user LEDs on the board flash sequentially from side to side.

As you develop your own project using the Altera tools, you may wish to program the flash device so that, upon power up, it loads the FPGA with your own design. Or you may wish to restore the default factory configuration to your board.

This appendix describes how to program the flash device. You can load an existing design from a .pof, but if your design exists only as an SRAM Object File (.sof), then first you must convert the .sof to a .pof. Programming the flash device also requires the use of the Altera parallel flash loader (PFL). Using this appendix, you can do the following:

■ Create a flash file by converting a .sof to .pof

■ Install the PFL

■ Use the Quartus II Programmer to write a .pof to the flash device

■ Restore the default factory configuration

Creating a Flash File

To create a flash-programmable configuration .pof, perform the following steps:

1. On the File menu in the Quartus II software, click Convert Programming Files.

2. In the Convert Programming Files dialog box, specify the parameter values as shown in the following table:

Parameter Value

Programming file type Programmer Object File (.pof)

Configuration device CFI_512MB

Mode Fast Passive Parallel

File name <output_file.pof>

Memory Map File selected (default)

This is the default file name. Change this to the file name you wish to use for your application. Save the file in <path>\examples\stratixIII_3sl150_dev_pfl.

A–2 Appendix A: Programming the Flash Device

Creating a Flash File

3. Click Options. In the Options dialog box, type 0x3FE0000 then click OK. This sets the option bit base address for the development kit to the required default, 0x3FE0000. The option bit sector stores the start address for each page of memory and also stores the Page Valid bits. The Page Valid bits indicate whether each page is successfully programmed.

f For more information about option bits and Page Mode Implementation

of memory, refer to AN 386: Using the Parallel Flash Loader with the

Quartus II Software.

4. Choose the .sof file you want to convert by selecting the row labeled SOF Data in

the Input files to convert area, and click Add File.

5. Browse to and select the file you wish to convert and click OK.

Figure A–1 shows the Convert Programming Files dialog box updated with the

factory image your_design_name.sof.

1 If you choose to overwrite an existing .pof file, you receive a warning

message.

Figure A–1. Convert Programming Files Settings

Appendix A: Programming the Flash Device A–3

Parallel Flash Loader Instantiation

6. Click Generate. Generation takes a short time and it is confirmed by a

“Generated… pof successfully” message.

You now have a successfully generated .pof that can be programmed to the flash device to automatically configure the FPGA on your Stratix III development board.

Parallel Flash Loader Instantiation

The development kit includes a PFL megafunction design, stratixIII_3sl150_dev_pfl,

in the directory <path>\examples. The Quartus II software uses the PFL to write programming files to the flash device, which then loads the FPGA on power up.

To write to a flash device, you must first program the PFL into the FPGA by using the Quartus II software as described in “Programming the Flash Device” on page A–3, steps 1 through 8.

f For more information about the PFL megafunction, refer to AN 386: Using the Parallel

Flash Loader with the Quartus II Software.

Programming the Flash Device

To program the flash device on the development board, you must first create a .pof flash file as described in “Creating a Flash File” on page A–1. The following procedure describes programming the PFL into the FPGA, then uses the PFL to write the .pof flash file into the flash device.

To download a configuration bit stream into the flash device, perform the following steps:

1. Ensure that the POWER switch SW4 is in the OFF (or DOWN) position.

2. Verify the switch SW1 and jumper settings shown in Table 4–2 on page 4–3.

3. Connect the USB cable to the USB port on the board.

4. Cycle the POWER switch OFF then ON.

5. On the Tools menu in the Quartus II software, click Programmer.

6. Click Add File and select <path>\examples\stratixIII_3sl150_dev_pfl\stratixIII_3sl150_dev_pfl.sof.

7. Turn on the Program/Configure option for the added file.

8. Click Start to download the selected configuration file to FPGA (Figure A–2). The FPGA is configured when the progress bar reaches 100%, after which it is ready to access and program the flash device.

A–4 Appendix A: Programming the Flash Device

Programming the Flash Device

Figure A–2. PFL Programming

9. Click Auto Detect. The EP3SL150 device and a child CFI_512MB device appear in the list of devices to be programmed.

10. Double-click the <File><none> field of the CFI_512MB row. The Select New Programming File dialog box appears. Select the desired .pof, in this example the <output_file>.pof flash file you created earlier, and click Open.

11. Turn on Page_0 and OPTION_BITS options in the Program/Configure column that correspond to the CFI_512MB device (Figure A–3). This results in writes only to the flash page zero and the option bit register.

Appendix A: Programming the Flash Device A–5

Restoring the Factory Design to the Flash Device

Figure A–3. Program/Configure Options

12. Click Start. The message window details the flash writing progress to successful completion. Flash writing to one page, as in this case, can take five to six minutes.

You have now successfully programmed the flash device with a configuration for your board. To configure the board from the flash device, power cycle the board as described in “Powering Up the Board” on page 4–1.

Powering on the board causes the flash device to load a new configuration into the FPGA device. The CONF DONE LED lights up and the hardware functions associated with the design take effect.

Restoring the Factory Design to the Flash Device

To restore the development board to factory conditions, repeat the steps for writing a new .pof to the flash device as described in “Programming the Flash Device” on

page A–3, except select the stratixIII_3sl150_dev_factory_recovery.pof file.

A–6 Appendix A: Programming the Flash Device

Restoring the Factory Design to the Flash Device

Revision History

The following table displays the revision history for this user guide.

Date Version Changes Made

August 2008 1.1

October 2007 1.0 First publication

■ Updated “Introduction” section.

■ Under “Kit Features” and “Software Requirements” sections, removed references to

Quartus II Software Web Edition and added information about the availability of the Quartus II Software Dev Kit Edition where appropriate.

■ Updated directory structure and information about the directory contents in Figure 3–1 and

Table 3–1, respectively.

■ Removed Figure 3-2 and Figure 4-2.

■ Corrected POWER SELECT rotary switch SW4 to SW6 in “Measuring Power” section.

■ Converted document to new frame template and made textual and style changes.

Additional Information

How to Contact Altera

For the most up-to-date information about Altera products, refer to the following table.

Contact Note 1

Technical support Website www.altera.com/support

Technical training Website www.altera.com/training

Product literature Website www.altera.com/literature

Non-technical support (General) Email nacomp@altera.com

Note to Table:

(1) You can also contact your local Altera sales office or sales representative.

Contact Method Address

Email custrain@altera.com

(Software Licensing) Email authorization@altera.com

Info–2 Additional Information

Typographic Conventions

This document uses the typographic conventions shown in the following table.

Visual Cue Meaning

Bold Type with Initial Capital Letters

bold type External timing parameters, directory names, project names, disk drive names, filenames,

Italic Type with Initial Capital Letters

Italic type Internal timing parameters and variables are shown in italic type. Examples: t

Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the

“Subheading Title” References to sections within a document and titles of on-line help topics are shown in

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input.

1., 2., 3., and a., b., c., etc.

■

● • Bullets are used in a list of items when the sequence of the items is not important.

v The checkmark indicates a procedure that consists of one step only. 1 The hand points to information that requires special attention. c The caution calls attention to a condition that could damage the product or design and should

r The angled arrow indicates you should press the Enter key.

f The feet direct you to more information on a particular topic.

Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box.

filename extensions, and software utility names are shown in bold type. Examples: f

MAX

\qdesigns directory, d: drive, chiptrip.gdf file.

Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Design.

, n + 1.

PIA

Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file name>, <project name>.pof file.

Options menu.

quotation marks. Example: “Typographic Conventions.”

Active-low signals are denoted by suffix

n, e.g., resetn.

Anything that must be typed exactly as it appears is shown in Courier type. For example:

c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report

File, references to parts of files (e.g., the AHDL keyword names (e.g.,

TRI) are shown in Courier.

SUBDESIGN), as well as logic function

Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure.

be read prior to starting or continuing with the procedure or process.

The warning calls attention to a condition that could cause injury to the user and should be read prior to starting or continuing the procedure or processes.

Altera Stratix III User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Introduction

1. About This Kit

Kit Features

Documentation

Introduction

2. Getting Started

Before You Begin

Check the Kit Contents

Inspect the Board

References

Hardware Requirements

Software Requirements

Introduction

Installing the Development Kit CD-ROM

3. Software Installation

Installing the Quartus II DVD

Installing the USB-Blaster Driver

Licensing Considerations

Introduction

Requirements

4. Development Board Setup

Powering Up the Board

Configuring the FPGA

Introduction

Power Design Example

5. Power Measurement

Measuring Power

A/D Measurements

Measuring Voltage with a DMM

Calculating Power

Changing the Design Example

Introduction

My First FPGA Tutorial

6. Design Tutorials

My First Nios II Software Tutorial

Overview

Creating a Flash File

Parallel Flash Loader Instantiation

Programming the Flash Device

Restoring the Factory Design to the Flash Device

Revision History

Additional Information

How to Contact Altera

Typographic Conventions