Altera Stratix II GX PCI User Manual

101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.com

Stratix II GX PCI Express

Development Board

Reference Manual

Document Version: 1.0.1 Document Date: April 2007

Copyright © 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Part Number MNL-01002-1.1

ii Development Board Version 1.0.0 Altera Corporation Stratix II GX PCI Express Development Board Reference Manual Preliminary August 2006

Contents

About this Manual

Revision History ......................................................................................................................................... v

How to Contact Altera ............................................................................................................................... v

Typographic Conventions....................................................................................................................... vi

Chapter 1. Introduction

General Description................................................................................................................................ 1-1

Board Features ................................................................................................................................... 1-1

Block Diagram ................................................................................................................................... 1-2

Handling the Board ................................................................................................................................ 1-3

Chapter 2. Board Components & Interfaces

Board Overview...................................................................................................................................... 2-1

Featured Device ...................................................................................................................................... 2-5

Device Support .................................................................................................................................. 2-6

I/O & Clocking Resources ............................................................................................................... 2-6

Clocking Circuitry ................................................................................................................................ 2-11

Configuration Schemes and Status LEDs ..........................................................................................2-12

JTAG Configuration ........................................................................................................................ 2-12

FPP Configuration ........................................................................................................................... 2-14

Flash Memory Configuration File Storage ............................................................................. 2-17

MAX II CPLD Configuration Controller ................................................................................ 2-18

Status and Channel Activity LEDs ............................................................................................... 2-21

General User Interfaces........................................................................................................................ 2-22

Push Button Switches (S1 Through S4) ........................................................................................ 2-22

User-Defined DIP Switch (S5) ....................................................................................................... 2-23

User LEDs (D9 Through D16) ....................................................................................................... 2-23

Configuration DIP Switch .............................................................................................................. 2-24

Board-Specific LEDs ....................................................................................................................... 2-25

FPGA Transceiver Channel Activity LEDs ................................................................................. 2-25

Power, Configuration, and Traffic Activity LEDs ...................................................................... 2-26

Standard Communication Ports ......................................................................................................... 2-27

PCI Express Edge Connector Interface (J9) ................................................................................. 2-27

Gigabit Ethernet (GigE) Interface (RJ1) ........................................................................................2-29

SFP A and B Interfaces (J6 and J7) ................................................................................................ 2-34

High-Speed Mezzanine Connectors A and B Interface ............................................................. 2-36

JTAG Interface ................................................................................................................................. 2-44

Off-Chip Memory ................................................................................................................................. 2-44

DDR2 SDRAM ................................................................................................................................. 2-44

QDRII SRAM .................................................................................................................................... 2-49

Flash Memory .................................................................................................................................. 2-52

Altera Corporation iii

Preliminary

Contents Stratix Device Handbook, Volume 1

Temperature Sensor ............................................................................................................................. 2-54

Heat Sink and Fan ................................................................................................................................ 2-55

Power Supply ........................................................................................................................................ 2-55

Power Supply for Each Component ............................................................................................. 2-55

Components Attached to Each Power Rail ................................................................................. 2-56

Power Distribution System ............................................................................................................ 2-58

Termination ........................................................................................................................................... 2-60

DDR2 Memory ................................................................................................................................. 2-60

QDRII Memory ................................................................................................................................ 2-60

PCI Express ...................................................................................................................................... 2-60

iv Altera Corporation

Preliminary

About this Manual

Revision History

The table below displays the revision history for the chapters in this reference manual.

Chapter Date Version Changes Made

All August 2006 1.0.0 First publication

All April 2007 1.0.1

Added warning not to use external power supply when the Altera

II GX PCI Express development board is powered from the host

Stratix computer chassis

This reference manual provides comprehensive information about the

Stratix®II GX family of devices and the Stratix II GX PCI Express

Altera development board.

How to Contact Altera

For the most up-to-date information about Altera products, go to the Altera world-wide web site at www.altera.com. For technical support on this product, go to www.altera.com/mysupport. For additional information about Altera products, consult the sources shown below.

Information Type USA & Canada All Other Locations

Technical support www.altera.com/mysupport/ www.altera.com/mysupport/

(800) 800-EPLD (3753) (7:00 a.m. to 5:00 p.m. Pacific Time)

Product literature www.altera.com www.altera.com

Altera literature services literature@altera.com literature@altera.com

Non-technical customer service

FTP site ftp.altera.com ftp.altera.com

(800) 767-3753 + 1 408-544-7000

+1 408-544-8767 7:00 a.m. to 5:00 p.m. (GMT -8:00) Pacific Time

7:00 a.m. to 5:00 p.m. (GMT -8:00) Pacific Time

Altera Corporation v August 2006 Preliminary

Typographic Conventions Cyclone FPGA Device Handbook

Typographic

This document uses the typographic conventions shown below.

Conventions

Visual Cue Meaning

Bold Type with Initial Capital Letters

bold type External timing parameters, directory names, project names, disk drive names,

Italic Type with Initial Capital Letters

Italic type Internal timing parameters and variables are shown in italic type.

Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:

“Subheading Title” References to sections within a document and titles of on-line help topics are

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,

1., 2., 3., and a., b., c., etc.

● • Bullets are used in a list of items when the sequence of the items is not important.

■

v The checkmark indicates a procedure that consists of one step only. 1 The hand points to information that requires special attention.

r The angled arrow indicates you should press the Enter key.

f The feet direct you to more information on a particular topic.

Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box.

filenames, filename extensions, and software utility names are shown in bold type. Examples: f

Document titles are shown in italic type with initial capital letters. Example: AN 75:

High-Speed Board Design.

Examples: t

Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file name>, <project name>.pof file.

Delete key, the Options menu.

shown in quotation marks. Example: “Typographic Conventions.”

PIA

, \qdesigns directory, d: drive, chiptrip.gdf file.

MAX

, n + 1.

tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.

Anything that must be typed exactly as it appears is shown in Courier type. For example: actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword Courier.

Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure.

The caution indicates required information that needs special consideration and understanding and should be read prior to starting or continuing with the procedure or process.

The warning indicates information that should be read prior to starting or continuing the procedure or processes

c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an

SUBDESIGN), as well as logic function names (e.g., TRI) are shown in

vi Altera Corporation

Preliminary August 2006

1. Introduction

General Description

The Stratix®II GX PCI Express development board provides a hardware platform for developing and prototyping high-performance PCI Express (PCIe)-based designs as well as to demonstrate the Stratix II GX device’s embedded transceiver and memory circuitry.

With up to 16-integrated transceiver channels and support for high-speed, low-latency memory access (via DDR2 SDRAM and QDRII memory interfaces), the Stratix II GX PCI Express development board provides a fully-integrated solution for multi-channel, high-performance applications, while also using limited board space.

Through the use of Altera

MegaCore® functions (or other intellectual property [IP] cores) and expansion connectors, you can enable the inter-operability of the Stratix II GX embedded transceivers with third-party, application-specific standard products (ASSPs) in either point-to-point or switching and bridging applications.

Because the Stratix II GX embedded transceivers can implement the entire PCIe interface on one device, the StratixIIGX PCIExpress development board offers a high-bandwidth, low-latency, powerefficient PCIe solution with sufficient LEs for your applications.

To simplify the design process, Altera provides a PCIe reference design— available from the Altera website—for use as either a design starting point or an experimental platform. The reference design is designed and tested by Altera engineers and distributed with the PCI Express Development Kit, Stratix II GX Edition (ordering code: DK-PCIE-2SGX90N).

Board Features

The board features the following major component blocks:

■ Off-chip memory

● DDR2 SDRAM

● QDRII SRAM

■ FPGA configuration

● MAX

● JTAG interface

Altera Corporation Reference Manual 1–1 August 2006 Stratix II GX PCI Express Development Board

II CPLD and 16-bit page mode flash memory

General Description

■ User and board-specific interfaces

● Push-button switches

● User DIP switch

● User LEDs

● Board-specific DIP switch

● Board-specific LEDs

■ Power supply

● Power by components

● Power by rail

● Main power source, either:

• PCIe motherboard

• Laptop-style DC power supply via DC input jack

■ Communication ports

● PCIe edge connector

● High-speed Mezzanine cards

● Gigabit Ethernet

● SFP modules

● Joint Test Action Group (JTAG) header

■ Clocking circuitry

● Three high-speed clock oscillators to support Stratix II GX

transceivers and user logic:

• 100 MHz

• 155.52 MHz

• 156.25 MHz

● SMA connector for external clock input and output

Block Diagram

Figure 1–1 shows a functional block diagram of the Stratix II GX

PCI Express development board.

1–2 Reference Manual Altera Corporation Stratix II GX PCI Express Development Board August 2006

Figure 1–1. Stratix II GX PCI Express Development Board

Introduction

MAX II Device

512 MB Flash

256 MB DDR2

SDRAM (x72)

Push-Button

Switches

1.8 V/2.5 V CMOS

100.000 MHz

1.8 V CMOS

1.8 V SSTL

156.250 MHz

HMC Port A

6x XCVR

CMOS/LVDS

Stratix II GX Device

1x XCVR

SFPASFP

HMC Port B

CMOS/LVDS

4x XCVR (1)

REFCLK

8x XCVR

x8 PCIe Edge

Connector

1.8V HSTL

1.8V/2.5V CMOS

155.52 MHz

72 MB QDRII

(x36)

88E1111

GigE PHY+RJ45

TX/RX LEDs

User LEDs

Note to Figure: (1) The 4x XCVR channels are only supported by Stratix II GX EP2SGX130 devices.

Handling the

When handling the board, it is important to observe the following precaution:

Board

w Static Discharge Precaution—Without proper anti-static

handling, the board can be damaged. Therefore, use anti-static handling precaution when touching the board.

Altera Corporation Reference Manual 1–3 August 2006 Stratix II GX PCI Express Development Board

Handling the Board

1–4 Reference Manual Altera Corporation Stratix II GX PCI Express Development Board August 2006

2. Board Components & Interfaces

Board Overview

This chapter provides operational and connectivity detail for the board’s major components and interfaces and is divided into the following major blocks:

■ Featured device

■ Clocking circuitry

■ Configuration

■ User interface components

■ Standard communication ports

■ Off-chip memory

■ Power supply

■ Termination

1 Board schematics, the physical layout database, and

manufacturing files for the Stratix development board are included in the PCI Express Development Kit, Stratix II GX Edition in the following directory:

<install path>/BoardDesignFiles

II GX PCI Express (PCIe)

Altera Corporation Reference Manual 2–1 August 2006 Stratix II GX PCI Express Development Board

Board Overview

Figure 2–1 shows the top view of the Stratix II GX PCIe development

board.

Figure 2–1. Top View of the Stratix II GX PCIe Development Board

High-Speed Mezzanine

Card Interfaces A & B

External Clock Input

SMA Connector (J4)

Configuration Done

LED (D8)

User DIP Switch

Bank (S5)

Ethernet RJ-45

Single Port

(RJ1)

JTAG

Header

(J5)

SFP Ports

A and B

(J6, J7)

User LEDs

(D9 through D16)

HSMC Interface A (J1)

(J1 and J2)

User Push-Button

Switches (S1 - S4)

HSMC Interface B (J2)

Transmit/Receive

Yellow LEDs (D5 and D6)

Power Switch

Power Supply

Input (J3)

MAX II Device

(U4)

(SW1)

Temperature Sensor With Alarm (U7)

DDR2 64 x 8 Mbytes

SDRAM (U2)

QDRII SRAM (U6)

Flash Device (U3)

Stratix II GX Device (U10)

PCI Express x8

Edge Connector

100-MHz Crystal (X1)

155.25-MHz Crystal (X4)

DDR2 32 x 16 Mbytes

SDRAM (U5, U8, U11, U13)

2–2 Reference Manual Altera Corporation Stratix II GX PCI Express Development Board August 2006

Figure 2–2 shows a diagonal view of the Stratix II GX PCIe development

board.

Figure 2–2. Diagonal View of the Stratix II GX PCIe Development Board

Board Components & Interfaces

Altera Corporation Reference Manual 2–3 August 2006 Stratix II GX PCI Express Development Board

Board Overview

Table 2–1 describes the components and lists their corresponding board

references.

Table 2–1. Stratix II GX PCIe Development Board Features

Component/

Interface

Board

Reference

Description Page

Featured Device

Stratix II GX FPGA U10

FF1508 FPGA in a 1508-pin FineLine BGA

package.

2–5

Clocks

100 MHz X1 100-MHz oscillator 2–6

25 MHz X2 25-MHz crystal 2–6

156.25 MHz X3 156.25-MHz oscillator 2–6

155.52 MHz X4 155.52-MHz oscillator 2–6

SMA clock input J4 SMA connector that allows the provision of an external clock

to the Stratix II GX device’s transceivers.

2–6

Configuration and Status

Board configuration DIP switch

Status LEDs D1, D2, D8,

Channel activity LEDs D3-D6, D17,

S6 DIP switch that controls the FPGA configuration settings. 2–23

LEDs that display power and configuration status. 2–25

D19-D22

LEDs that display RX and TX transceiver channel activity. 2–24

D18, D23-D29

User I/O

Push-button switches S1-S4 User-defined push-button switches. 2–21

User LEDs D9-D16 User-defined LEDs. 2–23

8-pin DIP switch S5 User-defined DIP switches. 2–22

JTAG header J5 10-pin header for JTAG-based FPGA communication. 2–12

Interfaces

PCIe edge connector J9 A x8 (8 channel) PCI Express edge connector for insertion

into PCI Express-based host platforms.

Ethernet RJ-45 RJ1 The RJ-45 jack is for Ethernet cable connection. The

connector is fed by a 10/100/1000 base T PHY device with a GMII interface to the Stratix II GX device.

SFP A J6 Small form pluggable cage allows for the connection of SFP

modules.

SFP B J7 Small form pluggable cage allows for the connection of SFP

modules.

2–25

2–28

2–33

2–4 Reference Manual Altera Corporation Stratix II GX PCI Express Development Board August 2006

Table 2–1. Stratix II GX PCIe Development Board Features

Board Components & Interfaces

Component/

Interface

HSMC A J1 High speed mezzanine connector allows for the connection

HSMC B J2 High speed mezzanine connector allows for the connection

Board

Reference

Description Page

2–35

of HSMC daughter cards.

2–35

of HSMC daughter cards.

Memory

QDRII SRAM U6 18 Mybtes (36 bits wide by 512 Kbytes deep) of QDRII

64 x 8 Mbyte DDR2 U2, U5, U8,

U11, U13

Flash U3 512 Mbytes of flash memory. 2–16

SRAM.

256 Mybtes (72 bits wide by 32 Mbytes deep) with error correction coding (ECC) of double data rate (DDR2) synchronous dynamic random access memory (SDRAM).

2–48

2–44

Power

DC power jack J3 DC input connector for the board. 2–55

Power switch SW1 Switches the board’s power on or off. 2–55

Featured Device

The PCI Express Development Kit, Stratix II GX Edition features the FF1508 FPGA (U10) in a 1508-pin FineLine BGA® (FBGA) package. Table 2–2 lists some Stratix II GX device features.

Table 2–2. Stratix II GX Features

Architectural

Feature

The Altera® third-generation FPGA with embedded transceivers

Innovative clock management system

Based on the

1.2-V, 90-nm SRAM process

Altera Corporation Reference Manual 2–5 August 2006 Stratix II GX PCI Express Development Board

● Provides a robust design solution for the most popular high-speed serial interfaces

● Provides optimum jitter performance across the entire operating range of 622 Mbps to

6.375 Gbps

● Provides best-in class signal integrity performance

● Offers enhanced transmit pre-emphasis technology, programmable receiver

equalization, and output voltage control

● Clock signals are automatically routed to the appropriate destination

● Greatly simplifies high-speed board designs

● Internal clock frequency of up to 500 MHz

● Provides up to 6.7 Mbits of on-chip TriMatrix

● Provides up to 63 DSP blocks for efficient implementation of high-performance filters

and other DSP functions

● Supports a wide range of external memory interfaces

Results

™

memory

Featured Device

Device Support

The board support’s device migration within all of the following F1508-packaged Stratix II GX devices:

■ 1.2-V VCCINT

■ 1.2-V to 3.3-V VCCIO

■ 1.2-V to 1.5-V transceiver I/O power

The board’s default device, FF1508 Stratix II GX device, provides the following:

■ 16 transceiver channels

■ 59 source-synchronous channels

■ 90,960 logic elements (LEs)

■ 8 phase-locked loops (PLLs)

■ 650 user I/O

■ 4,520,448 RAM bits

■ 192 18x18 multipliers

The larger EP2SGX130GF1508 Stratix II GX device provides the following:

■ 20 transceiver channels

■ 78 source-synchronous channels

■ 132,540 LEs

■ 8 PLLs

■ 798 user I/O

■ 6,747,840 RAM bits

■ 252 18x18 multipliers

I/O & Clocking Resources

This section lists specific I/O and clocking resources available on both the EP2SGX90FF1508 (default) and the EP2SGX130GF1508 devices.

Figure 2–3 illustrates the available I/O bank resources on both the

EP2SGX90FF1508 and the EP2SGX130GF1508 devices. (The numbers in parentheses represent the EP2SGX130GF1508 device resources.)

2–6 Reference Manual Altera Corporation Stratix II GX PCI Express Development Board August 2006

Board Components & Interfaces

Figure 2–3. Stratix II GX Device I/O Bank Resources

102 I/O

(108)

4 XCVRs

(2SGX130 only)

94 I/O

(104)

B13

B14

B15

B16

B17

B7 B8

95 I/O 100 I/O (104) (106)

Note: Figure is package-top referenced.

B96B11

B106B12

Figure 2–4 illustrates the available I/O mapping on both the

EP2SGX90FF1508 and the EP2SGX130GF1508 devices.

124 I/O (140)

120 I/O (156)

Altera Corporation Reference Manual 2–7 August 2006 Stratix II GX PCI Express Development Board

Featured Device

Figure 2–4. Stratix II GX Device I/O Mapping Resources

SFP Port A SFP Port B

HSMC Port A

HSMC Port B

PCIe Edge

Lanes [0:3]

PCIe Edge

Lanes [4:7]

HSMC Port B

(2SGX130 only)

QDRII (HSTL 18) Flash (CMOS)

1.8V

B13

B14

B15

B16

B17

DDR2 (SSTL 18) Flash (CMOS)

Note: Figure is package-top referenced.

B106B12

B7 B8

1.8 V 1.8 V

B96B11

GigE PHY (CMOS) QDRII (HSTL) Flash (CMOS)

2.5V

DDR2 (SSTL 18) Flash (CMOS)

2.5 V HSMC Port A (LVDS/CMOS)

2.5 V HSMC Port B (LVDS/CMOS)

Figure 2–5 illustrates the clocking resources on both the EP2SGX90FF1508

and the EP2SGX130GF1508 devices. The parenthetical text refers to board-level signals as they relate to specific clock pin names noted in both

the Quartus

II Development Software Handbook and the Stratix II GX Device

Handbook.

2–8 Reference Manual Altera Corporation Stratix II GX PCI Express Development Board August 2006

Figure 2–5. Stratix II GX Device Clocking Resources

PLL5 PLL11

(xaui_refclk)

(pcie_refclk)

(100m_refclk)

REFCLK0(sfp_refclk)

REFCLK1

REFCLK0

REFCLK1

REFCLK0

REFCLK1

REFCLK0

REFCLK1

REFCLK0

REFCLK1

B13

B14

B15

B16

B7 B8

B17

PLL6 PLL12

CLK12 (clk1_p)

CLK13

CLK14

CLK15

Board Components & Interfaces

FPLL7_CLK (hsma_clk1)

PLL7

(hsmca_clk2)

CLK0

CLK1

PLL1

PLL2

PLL8

(hsmca_clk0)

(hsmb_clk1)

CLK2

(hsmb_clk0)

CLK3

FPLL8_CLK

(hsmcb_clk2)

CLK6(ddr2_sync_clk)

CLK7

CLK4

CLK5

(clk2_p)

Altera Corporation Reference Manual 2–9 August 2006 Stratix II GX PCI Express Development Board

Featured Device

Table 2–3 summarizes Stratix II GX device I/O requirements. Clocks are

noted in a separate column because they sometimes use dedicated I/O pins or have special needs.

Table 2–3. Stratix II GX Device I/O Requirements Summarized

Function I/O Type I/O Count Clocks

PCIe edge connector (x8 electrical interface)

Small-form pluggable (SFP) expansion ports (2 expansion connectors)

High-speed mezzanine card, port A (XCVRs, LVDS, CMOS)

High-speed mezzanine card, port B (XCVRs, LVDS, CMOS)

Gigabit Ethernet (GigE) physical (PHY) layer (12-bit,125-MHz Gigabit medium independent interface [GMII])

DDR2 memory (72-bit, 333-MHz interface)

Quad data rate (QDRII) memory (36-bit, 300-MHz interface)

Flash 2.5-V CMOS 70 —

Push buttons 2.5-V CMOS 3 —

DIP switches 2.5-V CMOS 8 —

LEDs 2.5-V CMOS 18 —

EPLL clock inputs 2.5-V CMOS — 2 In

REFCLK inputs LVDS — 3 In

Note to Ta b le 2 – 3 :

(1) High-speed mezzanine card, port B: Four XCVR channels are only available with EP2SGX130GF1508 devices.

1.2-V/1.5-V pseudo current mode logic (PCML)

1.2-V/1.5-V PCML 2 XCVR channels —

1.2-V/1.5-V PCML 6 XCVR channels 1 CMOS in

2.5-V CMOS

2.5-V LVDS

1.2-V/1.5-V PCML 4 XCVR channels

2.5-V CMOS

2.5-V LVDS

2.5-V CMOS 30 1 Out

1.8-V SSTL 122 —

1.8-V HSTL 101 —

8 XCVR channels 1 LVDS in

1 CMOS out 2 LVDS in 2 LVDS out

84 —

(1)

84 —

1 CMOS in 1 CMOS out 2 LVDS in 2 LVDS out

1 In

2–10 Reference Manual Altera Corporation Stratix II GX PCI Express Development Board August 2006

Board Components & Interfaces

Clocking Circuitry

Three oscillators of 100 MHz, 156.25 MHz, and 155.52 MHz are used for clocking the Stratix II GX transceivers and user logic. A fourth oscillator of 25.000 MHz +/- 50 ppm is used as a reference clock for the Marvel 10/100/1000 Ethernet PHY device per manufacturing recommendations.

When the board is not plugged into a host board, the 100-MHz oscillator is used to support the transceiver reference clock for PCIe applications.

Figure 2–6 shows the oscillator driving through a four-output LVDS

buffer to a variety of loads. The buffer can either be driven from the 100-MHz oscillator or from the SMA clock input for custom frequencies. Pin 10 on the board configuration DIP switch controls what clock feeds the buffer (see “Configuration DIP Switch (S6)” on page 2–23).

Figure 2–6. Oscillator Clocking Diagram

25 MHz

SMT OSC

LVTTL

88e1111

GigE PHY

OSC A

SMA

LVTTL

Clock Buffer

LVDS

Translator

LVTTL

LVDS

100 MHz SMT OSC

CLK_SEL

All A/C Coupled

OSC B

LVDS

156.250 MHz SMT OSC

152.520 MHz SMT OSC

LVDS

Stratix II GX

Enhanced PLL

Inputs

MAX II

Configuration

Controller

Stratix II GX

Enhanced PLL

Inputs

Table 2–4 lists the board’s clock distribution system.

Table 2–4. Stratix II GX PCIe Development Board Clock Distribution (Part 1 of 2)

Signal

Frequency Signal Name

Originates

Signal Propagates To

From

100 MHz 100M_OSC_P

100M_OSC_N

User input SMA clock input J4

25 MHz ENET_25M_CLK X2 Ethernet PHY

Altera Corporation Reference Manual 2–11 August 2006 Stratix II GX PCI Express Development Board

X1 U21 (ICS8543 clock buffer), Pins 4 and 5

+ 49 hidden pages

Altera Stratix II GX PCI User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

About this Manual

Revision History

How to Contact Altera

Typographic Conventions Cyclone FPGA Device Handbook

1. Introduction

Board Features

Block Diagram

2. Board Components & Interfaces

Featured Device

Device Support

I/O & Clocking Resources

Clocking Circuitry