Altera Stratix GX Transceiver User Manual

101 Innovation Drive
San Jose, CA 95134
[phone]
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Stratix GX Transceiver User Guide

UG-STXGX-3.0
P25-10021-02

Copyright © 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des­ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al­tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap­plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in­formation and before placing orders for products or services.

Printed on recycled paper

ii Altera Corporation

Contents

About This User Guide ............................................................................ vii

How to Contact Altera ........................................................................................................................... vii

Typographic Conventions .................................................................................................................... viii

Chapter 1. Introduction

Gigabit Transceiver Block Highlights ................................................................................................. 1–1

Transceiver Block Architecture ........................................................................................................... 1–2

Analog Section Overview ............................................................................................................... 1–2

Digital Overview .............................................................................................................................. 1–3

Modes of Operation ............................................................................................................................... 1–5

Basic Mode ........................................................................................................................................ 1–5

SONET Mode .................................................................................................................................... 1–6

XAUI Mode ....................................................................................................................................... 1–7

GigE Mode ......................................................................................................................................... 1–8

Loopback ........................................................................................................................................... 1–9

Built-In Self Test ............................................................................................................................... 1–9

Chapter 2. Stratix GX Analog Description

Introduction ............................................................................................................................................ 2–1

Transmitter Analog ............................................................................................................................... 2–2

Transmitter Buffer ............................................................................................................................ 2–2

Transmitter PLL ................................................................................................................................ 2–5

Serializer (Parallel-to-Serial Converter) ........................................................................................ 2–8

Receiver Analog ..................................................................................................................................... 2–9

Receiver Input Buffer ....................................................................................................................... 2–9

Receiver PLL ................................................................................................................................... 2–12

Clock Recovery Unit ...................................................................................................................... 2–16

Deserializer (Serial-to-Parallel Converter) .................................................................................. 2–19

MegaWizard Analog Features ........................................................................................................... 2–20

MegaWizard Analog Feature Considerations ........................................................................... 2–20

Chapter 3. Basic Mode

Introduction ............................................................................................................................................ 3–1

Basic Mode Receiver Architecture ...................................................................................................... 3–2

Word Aligner .................................................................................................................................... 3–2

8B/10B Decoder ................................................................................................................................ 3–9

Byte Deserializer ............................................................................................................................. 3–13

Receiver Phase Compensation FIFO Buffer ............................................................................... 3–15

Basic Mode Transmitter Architecture ............................................................................................... 3–16

Transmitter Phase Compensation FIFO Buffer .......................................................................... 3–16

Altera Corporation iii

Contents Stratix GX Transceiver User Guide

Byte Serializer ................................................................................................................................. 3–17

8B/10B Encoder .............................................................................................................................. 3–17

Basic Mode Clocking ........................................................................................................................... 3–20

Basic Mode Channel Clocking ...................................................................................................... 3–20

Basic Mode Inter-Transceiver Block Clocking ........................................................................... 3–24

Basic Mode MegaWizard Plug-In ..................................................................................................... 3–29

Basic Mode MegaWizard Plug-In Manager Considerations ................................................... 3–29

Basic Mode altgxb MegaWizard Options ................................................................................... 3–29

Chapter 4. SONET Mode

Introduction ............................................................................................................................................ 4–1

SONET Mode Receiver Architecture .................................................................................................. 4–2

Word Aligner .................................................................................................................................... 4–2

Byte Deserializer ............................................................................................................................... 4–8

Receiver Phase Compensation FIFO Module ............................................................................. 4–10

SONET Mode Transmitter Architecture .......................................................................................... 4–11

Transmitter Phase Compensation FIFO Buffer .......................................................................... 4–11

Byte Serializer ................................................................................................................................. 4–12

SONET Mode Clocking ...................................................................................................................... 4–12

SONET Mode Channel Clocking ................................................................................................. 4–12

SONET Mode Inter-Transceiver Block Clocking ....................................................................... 4–17

SONET Mode MegaWizard Plug-In Manager ................................................................................ 4–23

SONET Mode MegaWizard Considerations .............................................................................. 4–23

SONET Mode altgxb MegaWizard Options ............................................................................... 4–23

Chapter 5. XAUI Mode

Introduction ............................................................................................................................................ 5–1

XAUI Mode Receiver Architecture ..................................................................................................... 5–5

Word Aligner .................................................................................................................................... 5–6

Channel Aligner ............................................................................................................................... 5–9

Rate Matcher ................................................................................................................................... 5–11

8B/10B Decoder .............................................................................................................................. 5–11

PCS - XGMII Code Conversion .................................................................................................... 5–15

Byte Deserializer ............................................................................................................................. 5–15

Receiver Phase Compensation FIFO Module ............................................................................. 5–18

XAUI Mode Transmitter Architecture .............................................................................................. 5–18

Transmitter Phase Compensation FIFO Module ....................................................................... 5–18

Byte Serializer ................................................................................................................................. 5–19

XGMII Character to PCS Code-Group Mapping ....................................................................... 5–20

8B/10B Encoder .............................................................................................................................. 5–21

XAUI Mode Clocking .......................................................................................................................... 5–24

XAUI Mode Channel Clocking .................................................................................................... 5–24

XAUI Inter-Transceiver Block Clocking ..................................................................................... 5–28

XAUI Mode MegaWizard Plug-In Manager ................................................................................... 5–34

XAUI Mode MegaWizard Considerations ................................................................................. 5–34

XAUI Mode altgxb MegaWizard Options .................................................................................. 5–34

iv Altera Corporation

Contents Contents

Chapter 6. GigE Mode

Introduction ............................................................................................................................................ 6–1

Word Aligner .................................................................................................................................... 6–4

Rate Matcher ..................................................................................................................................... 6–9

8B/10B Decoder .............................................................................................................................. 6–11

Receiver Phase Compensation FIFO Buffer ............................................................................... 6–14

GigE Mode Transmitter Architecture ............................................................................................... 6–14

Transmitter Phase Compensation FIFO Buffer .......................................................................... 6–15

GigE Transmitter Synchronization .............................................................................................. 6–16

Idle Generation ............................................................................................................................... 6–16

8B/10B Encoder .............................................................................................................................. 6–17

GigE Mode Clocking ........................................................................................................................... 6–20

GigE Mode Channel Clocking ......................................................................................................6–20

GigE Mode Inter-Transceiver Clocking ...................................................................................... 6–25

GigE Mode MegaWizard Considerations ................................................................................... 6–31

GigE Mode altgxb MegaWizard Options ................................................................................... 6–31

Design Example ................................................................................................................................... 6–38

Design Description ......................................................................................................................... 6–38

Simulation Waveform & Hardware Verification Results ......................................................... 6–44

Chapter 7. Loopback Modes

Introduction ............................................................................................................................................ 7–1

Serial Loopback ...................................................................................................................................... 7–1

Parallel Loopback .................................................................................................................................. 7–2

Reverse Serial Loopback ....................................................................................................................... 7–3

Chapter 8. Stratix GX Built-In Self Test (BIST)

Introduction ............................................................................................................................................ 8–1

Pattern Generator .................................................................................................................................. 8–2

PRBS Mode Generator ..................................................................................................................... 8–2

Incremental Mode Generator ......................................................................................................... 8–3

High-Frequency Mode Generator .................................................................................................. 8–3

Low-Frequency Mode Generator ................................................................................................... 8–4

Mix-Frequency Mode Generator .................................................................................................... 8–5

Pattern Verifier ....................................................................................................................................... 8–5

PRBS Mode Verifier ......................................................................................................................... 8–5

Incremental Mode Verifier .............................................................................................................. 8–6

Design Examples ................................................................................................................................... 8–7

Design 1: PRBS BIST Generator & Verification Design .............................................................. 8–7

Design 2: Incremental BIST Generator & Verification Design ................................................. 8–11

Design 3: High-Frequency Transmitter Generator Design ...................................................... 8–16

Design 4: Low-Frequency Transmitter Generator Design ....................................................... 8–18

Design 5: Mix-Frequency Transmitter Generator Design ........................................................ 8–20

Altera Corporation v

Contents Stratix GX Transceiver User Guide

Chapter 9. Reset Control &
Power Down

Introduction ............................................................................................................................................ 9–1

Power On Reset (POR) .......................................................................................................................... 9–1

USER Reset & Enable Signals .............................................................................................................. 9–1

Recommended Resets ........................................................................................................................... 9–4

Receiver & Transmitter Reset ......................................................................................................... 9–4

Receiver Reset ................................................................................................................................. 9–32

Transmitter Reset ........................................................................................................................... 9–52

Power Down ......................................................................................................................................... 9–57

Appendix A. Data & Control Codes

8B/10B Code ......................................................................................................................................... A–1

Code Notation .................................................................................................................................. A–1

Disparity Calculation ...................................................................................................................... A–1

Supported Codes ............................................................................................................................. A–3

Appendix B. Ports & Parameters

Input Ports ............................................................................................................................................. B–1

Output Ports .......................................................................................................................................... B–5

Parameter Descriptions ........................................................................................................................ B–9

Appendix C. REFCLKB Pin Constraints

Known Issues ........................................................................................................................................ C–1

Quartus II Software Messages ....................................................................................................... C–3

Recommendations ........................................................................................................................... C–5

vi Altera Corporation

About This User Guide

How to Contact Altera

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Product literature www.altera.com www.altera.com

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Altera Corporation vii

Preliminary

Typographic Conventions Stratix GX Transceiver User Guide

Typographic

This document uses the typographic conventions shown below.

Conventions

Visual Cue Meaning

Bold Type with Initial
Capital Letters

bold type External timing parameters, directory names, project names, disk drive names,

Italic Type with Initial Capital
Letters

Italic type Internal timing parameters and variables are shown in italic type.

Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:

“Subheading Title” References to sections of a document and titles of on-line help topics are shown

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,

1., 2., 3., and
a., b., c., etc.

● • Bullets are used in a list of items when the sequence of the items is not important.

■

v The checkmark indicates a procedure that consists of one step only.
1 The hand points to information that requires special attention.

r The angled arrow indicates you should press the Enter key.

f The feet direct you to more information on a particular topic.

Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.

filenames, filename extensions, and software utility names are shown in bold
type. Examples: f

Document titles are shown in italic type with initial capital letters. Example: AN

75: High-Speed Board Design.

Examples: t

Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.

Delete key, the Options menu.

in quotation marks. Example: “Typographic Conventions.”

PIA

, \qdesigns directory, d: drive, chiptrip.gdf file.

MAX

, n + 1.

tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.

Anything that must be typed exactly as it appears is shown in Courier type. For
example:
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword
Courier.

Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.

c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an

SUBDESIGN), as well as logic function names (e.g., TRI) are shown in

viii Altera Corporation

Preliminary

1. Introduction

Introduction

Gigabit Transceiver Block Highlights

Stratix®GX devices combine highly advanced 3.1875-gigabit-per-second
(Gbps) four-channel gigabit transceiver blocks with one of the industry’s
most advanced FPGA architectures. Stratix GX devices are manufactured
on a 1.5-V, 0.13-µm, all-layer copper CMOS process technology with 1.5­V PCML I/O standard support.

Historically, designers have used high-speed transceivers in strictly
structured, line-side applications. Now, with the new gigabit transceiver
blocks embedded in FPGAs, you can use transceivers in a host of new
systems that require flexibility, increased time-to-market, high
performance, and top-of-the-line features.

Stratix GX devices are organized into four-channel blocks with four

3.1875 Gbps full-duplex channels per block and up to 20 channels (in five
blocks) per device. Each self-contained Stratix GX gigabit transceiver
block supports a variety of embedded functions and does the following:

■ Supports frequencies from 500 megabits per second (Mbps) to

3.1875 Gbps

■ Integrates serializer/deserializer (SERDES), clock data recovery

(CDR), word aligner, channel aligner, rate matcher, 8B/10B
encoder/decoder, byte serializer/deserializer, and phase
compensation first-in first-out (FIFO) modules

■ Supports flexible reference clock generation capabilities, including a

dedicated transmitter phase-locked loop (PLL) and four receiver
PLLs per gigabit transceiver block

■ Supports programmable pre-emphasis, equalization, and

programmable VOD settings in I/O buffers, and dynamic
reprogrammability for each of these features

■ Implements XAUI physical media attachment (PMA) and physical

coding sublayer (PCS) functionality for 10GBASE-X systems

■ Provides built-in Gigabit Ethernet (GigE) physical coding sublayer

functionality

■ Provides individual transmitter and receiver power-down capability

for reduced power consumption during non-operation

■ Includes built-in self test (BIST) capability, including embedded

Pseudo Random Binary Sequence (PRBS) pattern generation and
verification

■ Includes three independent loopback paths for system verification

Altera Corporation 1–1
January 2005

Transceiver Block Architecture

Transceiver
Block
Architecture

Figure 1–1 shows a block diagram of the gigabit transceiver block (GXB).

You can bypass various modules if desired. Refer to“Modes of

Operation” on page 1–5 for a description of the supported features in

each mode. You can divide the transceiver block into an analog section
and a digital section, as shown in Figure 1–1.

Figure 1–1. Block Diagram of a Stratix GX Gigabit Transceiver Block

Digital SectionAnalog Section

Word

Aligner

Channel

Aligner

8B/10B
Encoder

Rate

Matcher

Reference

Clock

Reference

Clock

Receiver

Transmitter

Deserializer

Clock

Recovery

Unit

Receiver

PLL

Transmitter

PLL

Serializer

8B/10B

Decoder

Serializer

Byte

Byte

Deserializer

Compensation

FIFO Buffer

Phase

Compensation

FIFO Buffer

Phase

Analog Section Overview

This section describes the various components within the analog section
of the transceiver block.

Transmitter Differential I/O Buffers

The gigabit transmitter block differential I/O buffers support the 1.5-V
PCML I/O standard, and contain features that improve system signal
integrity. These features include programmable pre-emphasis, which
helps compensate for high frequency losses, and a variety of
programmable V

Receiver Differential I/O Buffers

The gigabit transceiver block differential I/O buffers support the 1.5-V
PCML I/O standard, and contain a variety of features that improve
system signal integrity. Programmable equalization capabilities are used
to compensate for signal degradation across transmission mediums.

1–2 Altera Corporation
Stratix GX Transceiver User Guide January 2005

settings that support noise margin tuning.

OD

Introduction

Transmitter & Receiver PLLs

Each gigabit transceiver block contains one dedicated transmitter PLL
and four dedicated receiver PLLs. These PLLs provide clocking flexibility
and support a range of incoming data streams. For data transmission and
recovery, these PLLs generate the required clock frequencies based upon
the synthesis of an input reference clock. Each transmitter PLL supports
multiplication factors of 2, 4, 5, 8, 10, 16, or 20. Either external reference
clocks or a variety of clock sources within the Stratix GX device drive the
PLLs.

Clock Recovery Unit

The gigabit transceiver block clock recovery unit (CRU) performs analog
Clock Data Recovery (CDR). The CRU uses an external reference clock to
extract a recovered clock that is frequency and phase aligned with the
incoming data, thereby eliminating any clock-to-data skew. This
recovered clock then clocks the data through the rest of the gigabit
transceiver block.

Serializer Deserializer (SERDES)

The transmitter serializer converts the incoming lower speed parallel
signal to a high-speed serial signal on the transmit side. The SERDES
supports a variety of conversion factors, ensuring implementation
flexibility. For example, the SERDES supports 10- and 20-bit serialization
factors, typically required for 8B/10B encoded data, as well as 8- and
16-bit factors.

The receiver deserializer converts the incoming data stream from a
high-speed serial signal to a lower-speed parallel signal that can be
processed in the FPGA logic array on the receive side. The SERDES
supports a variety of conversion factors, ensuring implementation
flexibility. For example, the SERDES supports both 10-bit and 8-bit
serialization and deserialization factors.

Digital Overview

This section describes the various components in the digital section of the
transceiver block.

Altera Corporation 1–3
January 2005 Stratix GX Transceiver User Guide

Transceiver Block Architecture

Transmitter & Receiver Phase Compensation FIFO Buffer

The transmitter and receiver data path has a dedicated phase
compensation FIFO buffer that decouples phase variations between the
FPGA and transceiver clock domains. These FIFO buffers ensure a
consistent, reliable interface to the logic array and simplify system design
and timing analysis.

Byte Serializer/Deserializer

The byte serializer converts a 16- or 20-bit data bus into two 8- or 10-bit
data buses, respectively, at double the data rate. The byte serializer
converts an 8- or 10-bit data bus into 16- or 20-bit data buses, allowing
maximum throughput of the transceiver without burdening the FPGA
logic array.

The byte deserializer converts an 8- or 10-bit data bus into 16- or 20-bit
data buses, allowing maximum throughput of the transceiver without
burdening the FPGA logic array.

8B/10B Encoder/Decoder

8B/10B encoding/decoding is the backbone of many transceiver
protocols, and it is often used in proprietary implementations. The
gigabit transceiver block has dedicated circuitry to perform 8B/10B
encoding in the transmitter and decoding in the receiver. This coding
technique ensures sufficient data transitions and a DC balanced stream in
the data signal for successful data recovery at the receiver.

Word Aligner

The word aligner module contains a fully programmable pattern detector
to identify specific patterns within the incoming data stream. The pattern
detector includes recognition support /K28.5/ comma characters for
8B/10B encoded data and A1 or A2 frame alignment patterns for
scrambled signals. Additionally, you can specify a custom alignment
pattern in lieu of the /K28.5/ comma.

The word aligner in the gigabit transceiver block also creates words from
the incoming serial data stream by realigning the data based on identified
byte boundaries. The realignment function uses a barrel shifter and
works with the pattern detector. Additionally, the word aligner has a
manual data realignment mode that lets you control the data realignment
in user mode without consistent alignment characters.

1–4 Altera Corporation
Stratix GX Transceiver User Guide January 2005

Introduction

Channel Aligner

An embedded channel aligner aligns byte boundaries across multiple
channels and synchronizes the data entering the logic array from the
gigabit transceiver block’s four channels. The Stratix GX channel aligner
is optimized for a 10-Gigabit Ethernet XAUI 4-channel implementation.
The channel aligner includes the control circuitry and channel alignment
character detection defined by the XAUI protocol. The channel aligner is
only available in XAUI mode.

Rate Matcher

In multi-crystal environments, the clock frequencies of the transmitting
and receiving devices do not match. This mismatch can cause the data to
transmit at a rate slightly faster or slower than the receiving device can
interpret. The Stratix GX rate matcher resolves the frequency differences
between the recovered clock and the FPGA logic array clock by inserting
or deleting removable characters from the data stream, as defined by the
transmission protocol, without compromising transmitted data. If the
functional mode is XAUI, the rate matcher is based on the 10-Gigabit
Ethernet protocol. If the functional mode is GigE, the rate matcher is
based on the Gigabit Ethernet protocol.

Modes of Operation

You can bypass various modules of the gigabit transceiver block based on
the configured mode of operation. Stratix GX transceivers currently
support basic mode, SONET mode, and XAUI mode. This section
provides an overview of each supported mode of operation.

Basic Mode

Basic mode enables a subset of the transceiver blocks so you can perform
customizable configuration. Channel aligner and the rate matcher
features are not available in this mode. Refer to the Basic Mode chapter for
more details on the configurability of this mode. Figure 1–2 shows a block
diagram of a duplex channel configured in basic mode.

Altera Corporation 1–5
January 2005 Stratix GX Transceiver User Guide

Modes of Operation

Figure 1–2. Block Diagram of a Duplex Channel Configured in Basic Mode

Digital SectionAnalog Section

Reference

Clock

Reference

Clock

Receiver

Transmitter

Deserializer

Clock

Recovery

Unit

Receiver

PLL

Transmitter

PLL

Serializer

Word

Aligner

Channel

Aligner

8B/10B
Encoder

Rate

Matcher

8B/10B

Decoder

Serializer

Byte

Byte

Deserializer

Compensation

FIFO Buffer

Phase

Compensation

FIFO Buffer

Phase

SONET Mode

SONET mode lets you to select a subset of the transceiver blocks to
perform SONET-like configuration. SONET-like implies that the data
width can either be 8 or 16 bits and that the 8B/10B encoder/decoder,
channel aligner, and the rate matcher features are not available. Refer to
the SONET Mode chapter for more details on the configurability of this
mode. Figure 1–3 shows a block diagram of a duplex channel configured
in SONET mode.

1–6 Altera Corporation
Stratix GX Transceiver User Guide January 2005

Figure 1–3. Block Diagram of a Duplex Channel Configured in SONET Mode

Digital SectionAnalog Section

Introduction

Reference

Clock

Reference

Clock

Receiver

Transmitter

Deserializer

Clock

Recovery

Unit

Receiver

PLL

Transmitter

PLL

Serializer

Word

Aligner

Channel

Aligner

8B/10B
Encoder

Rate

Matcher

8B/10B

Decoder

Serializer

Byte

Byte

Deserializer

Compensation

FIFO Buffer

Phase

Compensation

FIFO Buffer

Phase

XAUI Mode

Stratix GX transceivers contain embedded macros dedicated to
supporting the XAUI protocol, specified in clause 47 of the IEEE 802.3ae
specification. These macros includes synchronization, channel deskew,
rate matching, XGXS to XGMII, and XGMII to XGXS code-group
conversion. Refer to the XAUI Mode chapter for more details on the
configurability of this mode. Figure 1–4 shows a block diagram of a
duplex channel configured in XAUI mode.

Altera Corporation 1–7
January 2005 Stratix GX Transceiver User Guide

Modes of Operation

Figure 1–4. Block Diagram of a Duplex Channel Configured in XAUI Mode

Digital SectionAnalog Section

Reference

Clock

Reference

Clock

Receiver

Transmitter

Deserializer

Clock

Recovery

Unit

Receiver

PLL

Transmitter

PLL

Serializer

Word

Aligner

Channel

Aligner

8B/10B
Encoder

Rate

Matcher

8B/10B

Decoder

Serializer

Byte

Byte

Deserializer

Compensation

FIFO Buffer

Phase

Compensation

FIFO Buffer

Phase

GigE Mode

Stratix GX devices in GigE mode can use the 8B/10B encoder/decoder,
rate matcher, synchronizer, and byte serializer/deserializer built-in hard
macros. Refer to the GigE Mode chapter for more information about this
mode. The rate matcher and word aligner each have a dedicated state
machine governing their functions. These state machines are active only
in GigE mode. Figure 1–5 shows a block diagram of a duplex channel
configured in GigE mode.

1–8 Altera Corporation
Stratix GX Transceiver User Guide January 2005

Figure 1–5. Block Diagram of a Duplex Channel Configured in GigE Mode

Digital SectionAnalog Section

Introduction

Reference

Clock

Reference

Clock

Receiver

Transmitter

Deserializer

Clock

Recovery

Unit

Receiver

PLL

Transmitter

PLL

Serializer

Word

Aligner

Channel

Aligner

8B/10B
Encoder

Rate

Matcher

8B/10B

Decoder

Byte

Serializer

Byte

Deserializer

Phase

Compensation

FIFO Buffer

Phase

Compensation

FIFO Buffer

Loopback

There are three different loopback modes to use in the gigabit transceiver
block to allow for a complete method of in-system verification. The
loopback modes are versatile and robust enough to accommodate all
protocols and let you to choose whether to retime the data.

Built-In Self Test

The gigabit transceiver block contains several features that simplify
design verification. An embedded PRBS pattern generator provides a
bitstream pattern that you can use to test the device and board
connections. The PRBS pattern generator works with a PRBS receiver to
implement a full self-test path. Additionally, serial and parallel loopback
paths let you test the FPGA logic without monitoring external signals.
The reverse loopback path enables external system testing with minimal
device interaction.

Altera Corporation 1–9
January 2005 Stratix GX Transceiver User Guide

Modes of Operation

1–10 Altera Corporation
Stratix GX Transceiver User Guide January 2005

2. Stratix GX Analog Description

Introduction

This chapter describes how to serialize the parallel data for transmission
and convert received data into parallel data. Data transmission and
reception is performed by pseudo current mode logic (PCML) buffers.
These transceiver buffers support programmable pre-emphasis,
equalization, and programmable V

The programmable pre-emphasis setting is available on transmit buffers
to maximize the eye opening on the far-end receiver by boosting the
high-frequency component of the data signal. Similarly, programmable
equalization is available for receive buffers to reduce the high-frequency
losses and inter-symbol interference. These features are useful in lossy
transmission lines. Transceivers also support flexible reference clock
generation capabilities, including a dedicated transmitter phase-locked
loop (PLL) and four receiver PLLs per transceiver block.

The clock recovery unit (CRU) is the main part of each receive analog
section; it recovers the clock from the serial data stream (see Figure 2–1).

You can set the CRU to automatically or manually alter the receiver PLL
phase and frequency to match the bit transition on the incoming data
stream. This is to eliminate any clock-to-data skew or to keep the receiver
PLL locked to the reference clock (lock-to-data or lock-to-reference
mode).

During the clock recovery phase, the receiver PLL initially locks to the
reference clock and then attempts to lock on to the incoming data by first
recovering the clock from the incoming serial data.

settings in I/O buffers.

OD

Altera Corporation 2–1
January 2005

Transmitter Analog

Figure 2–1. Block Diagram Analog Components

Digital SectionAnalog Section

Deserializer

Clock

Recovery

Unit

Reference

Clock

Reference

Clock

Receiver

Transmitter

Receiver

PLL

Transmitter

PLL

Serializer

Transmitter

Word

Aligner

Channel

Aligner

This section describes the transmitter buffer, the transmitter PLL, and the
serializer. Figure 2–2 shows the transmitter analog components.

Analog

Figure 2–2. Transmitter Analog Components

Digital SectionAnalog Section

Reference

Clock

Transmitter

PLL

8B/10B

Encoder

Rate

Matcher

8B/10B

Decoder

Serializer

Byte

Byte

Deserializer

Compensation

FIFO Buffer

Phase

Compensation

FIFO Buffer

Phase

Transmitter

Serializer

8B/10B

Encoder

Byte

Serializer

Phase

Compensation

FIFO Buffer

Transmitter Buffer

The Stratix®GX transceiver buffers support the 1.5-V PCML standard at
speeds up to 3.1875 gigabits per second (Gbps) and are capable of driving
40 inches of FR4 trace across two connectors. In addition, the buffer
contains programmable output voltage, programmable pre-emphasis
circuitry, and internal termination circuitry.

2–2 Altera Corporation
Stratix GX Transceiver User Guide January 2005

Programmable Voltage Output Differential (VOD)

Stratix GX transceivers let you customize the differential output voltage

) to handle different length, backplane, and receiver requirements

(V

OD

(see Figure 2–3). You can select the VOD (differential) from a range of 400
to 1,600 mV, as shown in Table 2–1.

Figure 2–3. VOD (Differential) Signal Level

Single-Ended Waveform

V

CM

Differential Waveform (VOD (Differential) = 2 x VOD (single-ended))

V

OD

Stratix GX Analog Description

Positive Channel (p) = V

V

OD

Negative Channel (n) = V

Ground

p − n = 0 V

V

OD

OH

OL

Table 2–1 shows the differential output voltage (VOD) setting per current

level for each of the on-chip transmitter programmable termination
values.

Table 2–1. Programmable VOD (Differential)

100 Ω (mV) 120 Ω (mV) 150 Ω (mV)

400 480 600

800 960 1,200

1,000 1,200 1,500

1,200 1,440

1,400

1,600

Altera Corporation 2–3
January 2005 Stratix GX Transceiver User Guide

Transmitter Analog

You can set the differential VOD values statically during configuration or
dynamically adjust them in user mode. You select the static V
through a list in the altgxb MegaWizard
the appropriate V

setting in the configuration file. The disadvantage of

OD

®

Plug-In Manager, which sets

OD

value

the static mode setting is that the VOD is set on a per transceiver block
basis and cannot be changed unless you regenerate another
programming file.

Alternatively, if you enable dynamic adjustment in the altgxb
MegaWizard Plug-In, you can dynamically configure the V

setting by

OD

the device during user mode. This configuration is done by asserting
encoded values on the tx_vodctrl bus, which is instantiated in the
altgxb module when you select the dynamic adjustment option. This
option lets you make quick performance evaluations of the various
settings without having to recompile and regenerate multiple
configuration files. Another advantage of this option is that it allows the

of each channel to be configured independently. Refer to the section

V

OD

“MegaWizard Analog Features” on page 2–20 for further details.

Programmable Pre-Emphasis

The programmable pre-emphasis module in each transmit buffer boosts
the high frequencies in the transmit data signal, which may be attenuated
in the transmission media. This maximizes the data eye opening at the
far-end receiver. Pre-emphasis is particularly useful in lossy transmission
mediums.

The transfer function of a transmission line can be represented in the
frequency domain as a low-pass filter. Any frequency components below
the –3 dB frequency pass through with minimal losses. Frequency
components that are greater than the –3-dB frequency are attenuated.
This variation in frequency response yields data-dependant jitter and
other ISI effects. By applying pre-emphasis, the high frequency
components are boosted, or in other words, pre-emphasized. This
pre-emphasis equalizes the frequency response as seen at the receiver so
that the delta between the low-frequency and high-frequency
components is reduced, which in return minimizes the ISI effects from the
transmission medium.

In Stratix GX transceivers, the programmable pre-emphasis settings can
have one of six values (0 to 5). You should experiment with the
pre-emphasis values to determine the optimal setting based on your
system variables.

2–4 Altera Corporation
Stratix GX Transceiver User Guide January 2005

Stratix GX Analog Description

As with the VOD settings, you can set the pre-emphasis settings statically
during configuration or adjust them dynamically in user mode. You can
set the static pre-emphasis value through a drop-down menu in the
altgxb MegaWizard Plug-In, which sets the appropriate pre-emphasis
setting in the configuration file. The disadvantage of the static mode
setting is that the pre-emphasis is set on a per-transceiver-block basis and
cannot be changed without regenerating another programming file.

On the other hand, if you select dynamic adjustment in the altgxb
MegaWizard Plug-In, the pre-emphasis setting can be configured
dynamically by the device during user mode. This configuration is done
by asserting encoded values on the tx_preemphasisctrl bus, which
is instantiated in the altgxb module when you select the dynamic
adjustment option. This option lets you make quick performance
evaluations of the various settings without having to recompile and
regenerate multiple configuration files. Another advantage of this option
is that it allows the pre-emphasis of each channel to be configured
independently. For further details, refer to “MegaWizard Analog

Features” on page 2–20.

Avoid pre-emphasis and V

settings that yield a value greater than

OD

1,600 mV. Settings beyond this value do not damage the buffer, but they
prevent accurate device operation. Verify that the combination of V

OD

and pre-emphasis settings do not exceed the 1,600-mV limit.

Programmable Transmitter Termination

The Stratix GX transmitter buffer includes a 100-, 120-, or 150-Ω
programmable on-chip differential termination resistor. The Stratix GX
transmitter buffers are current-mode drivers, so the resultant V

OD

is a
function of the transmitter termination value. For more information on
resultant V

values, see “Programmable Voltage Output Differential

OD

(VOD)” on page 2–3.

Transmitter PLL

Each transceiver block contains a transmitter PLL and a slow-speed
reference clock. The transmitter PLL receives the reference clock and
generates the high-speed serial clock used by the serializer. The slow­speed reference clock is used for the transceiver logic. Figure 2–4 shows
the transmitter PLL’s block diagram. The pll_locked signal indicates
when the transmitter PLL is locked to the reference clock. A high signal
indicates that the PLL is locked to the reference clock; a low signal
indicates that the PLL is not locked to the reference clock.

Altera Corporation 2–5
January 2005 Stratix GX Transceiver User Guide

Transmitter Analog

Figure 2–4. Transmitter PLL Block Diagram

Inter Quad Routing (IQ1)
Inter Quad Routing (IQ0)

Global Clocks, I/O Bus, General Routing

/4, 8, 10, 16, 20

/m

Up

PFD CP+LF

DownINCLK

VCO

Clock
Driver

High Speed

TX_PLL_CLK

Low Speed

TX_PLL_CLK

Dedicated Local

REFCLKB

/2

Table 2–2 lists some of the transmitter PLL specifications.

Table 2–2. Transmitter PLL Specifications

Parameter Specifications

Input reference frequency range 25 MHz to 650 MHz

Data rate support 500 Mbps to 3.1875 Gbps

Multiplication factor (W) 2, 4, 5, 8, 10, 16, or 20 (1)

Note to Ta b l e 2 – 2:

(1) Multiplication factors 2 and 5 can only be achieved with the use of the pre-divider

on the REFCLKB.

Clock Synthesis

The maximum input frequency of the phase frequency detector (PFD) is
325 MHz. To achieve reference clock frequency above this limitation, the
/2 pre-divider on the dedicated local REFCLKB path can be enabled
automatically by the Quartus
reference clock frequency by a factor of 2 and then the /m factor
compensates the frequency difference. An example would be a data rate
of 2,488 Mbps with a 622-MHz reference clock. In this scenario, the
reference clock must be assigned to the REFCLKB port where the 622­MHz reference clock is divided by 2, yielding a 311-MHz clock at the PFD.
This 311-MHz reference clock is then multiplied by a factor of 8 to achieve
the 2,488-MHz clock at the VCO.

®

II software. The /2 pre-divider divides the

2–6 Altera Corporation
Stratix GX Transceiver User Guide January 2005

Stratix GX Analog Description

If the reference clock exceeds 325 MHz, the clock must be fed by the
dedicated local reference clock pin, REFCLKB. By default, the Quartus II
software assigns pins to be LVTTL, so you must assign the 1.5-V PCML
I/O standard to the I/O pins to select the REFCLKB port as the reference
source. The Quartus II software prompts a fitter error if the reference
clock exceeds 325 MHz and the reference clock source is not on the
REFCLKB port.

You can also use the pre-divider on the REFCLKB path to support
additional multiplication factors. The block diagram in Figure 2–4 shows
that /m can only support multiplication factors of 4, 8, 10, 16, and 20, but

Table 2–3 shows that the additional multiplication factors of 2 and 5 are

also achievable. You can achieve these multiplication factors by using the
pre-divider. A multiplication factor of 2 is achieved by pre-dividing the
reference clock by 2 and then multiplying the resultant frequency by 4,
which yields a multiplication factor of 2. A multiplication factor of 5 is
achieved in the same manner by pre-dividing the reference clock by 2 and
then multiplying the resultant frequency by 10, which yields a
multiplication factor of 5.

Table 2–3 lists the possible multiplication values as a function of the

source to the transmitter PLL. Table 2–3 assumes that the reference clock
is directly fed from the source listed and does not factor any pre-clock
synthesis (that is, the Stratix GX PLL driving a global clock that is used for
the transmitter PLL reference clock source).

Table 2–3. Multiplication Values as a Function of the Reference Clock
Source to the Transmitter PLL

Transmitter PLL Reference Clock

Source

Global clock, I/O bus, general routing 4, 8, 10, 16, 20

Inter-transceiver routing 2, 4, 5, 8, 10, 16, 20

Dedicated local REFCLKB 2, 4, 5, 8, 10, 16, 20

Multiplication Factors

You must specify the data rate of the channel and input clock period of
the reference clock. The data rate divided by the input clock period must
equal one of the multiplication factors listed in Table 2–3.

Transmitter PLL Bandwidth Setting

The Stratix GX transmitter PLL in the transceiver block offers a
programmable bandwidth setting. The PLL bandwidth is the measure of
its ability to track the input clock and jitter. The bandwidth is determined
by the –3-dB frequency of the closed-loop gain of the PLL.

Altera Corporation 2–7
January 2005 Stratix GX Transceiver User Guide

Transmitter Analog

A high-bandwidth setting provides a faster lock time and tracks more
jitter on the input clock source which passes it through the PLL. This
helps reject noise from the VCO and power supplies. A low-bandwidth
setting, on the other hand, filters out more high frequency input clock
jitter, but increases lock time.

You can set the bandwidth for Stratix GX devices to either low or high.
The –3-dB frequencies for these settings can vary due to the non-linear
nature and frequency dependencies of the circuit. As a result, you can
vary the bandwidth to customize the performance on specific systems.

Serializer (Parallel-to-Serial Converter)

The serializer converts parallel data to serial data at the transmitter
output buffer. The serializer can support 8- or 10-bit words when used
with the transmitter multiplexer. The 8-bit serializer drives the serial data
to the output buffer, as shown in Figure 2–5. The serializer can drive the
serial bit-stream at a data rate range of 500 Mbps to 3.1875 Gbps. The
serializer outputs the least significant bit (LSB) of the word first.

Figure 2–5. Example of 8-Bit Serialization

Serializer

D7

D8

D6

D4

D3

D2

D1

D0

Serial Data Out

(I/O Output Buffer)

Parallel Data

D7

D8

D6

8

D4

D3

D2

D1

D0

Low-Speed

Parallel Clock

High-Speed

Serial Clock

Figure 2–6 shows the serial bit order of the serializer output. In this

example, a constant 8’h6a (01010110) value is serialized.

1 The serial data is transmitted from LSB to most significant bit

(MSB).

2–8 Altera Corporation
Stratix GX Transceiver User Guide January 2005

Figure 2–6. Serializer Bit Order

Parallel Clock

Serial Clock

Parallel Data (in Hex)

Serial Data Out

(x) 56

Stratix GX Analog Description

011 01 010

Receiver Analog

This section describes the receiver input buffer, the receiver PLL, the clock
recovery unit, and the deserializer. Figure 2–7 shows the receiver analog
components.

Figure 2–7. Highlighted Block Diagram of the Receiver Analog Components

Digital SectionAnalog Section

Word

Aligner

Channel

Aligner

Rate

Matcher

8B/10B

Decoder

Reference

Clock

Receiver

Deserializer

Clock

Recovery

Unit

Receiver

PLL

Receiver Input Buffer

The receiver input buffer contains internal termination and internal
equalization. Figure 2–8 shows the structure of the input buffer. The input
buffer has programmable equalization that you can apply to increase the
signal integrity of the transmission line. The internal termination in the
receiver buffer can support AC and DC coupling with programmable
differential termination settings of 100, 120, or 150 Ω..

Byte

Deserializer

Phase

Compensation

FIFO Buffer

Altera Corporation 2–9
January 2005 Stratix GX Transceiver User Guide

Receiver Analog

Figure 2–8. Receiver Input Buffer

Input Buffer

Programmable

Termination

Input Pins

Programmable

Equalizer

Internal Loopback

from Transmitter

To PLD

Programmable Receiver Termination

The Stratix GX receiver buffer includes programmable on-chip
differential termination of 100, 120, or 150 Ω..

This assignment must be made per pin through the Assignment Editor in
the Quartus II software. Select Assignment Organizer > Options for
Individual Nodes Only > Stratix GX Termination Value (Assignments
menu).

1 The proper termination settings should be selected and verified

accordingly before compilation.

The transmitter PLL input signal (inclk) drives the termination
resistance calibration circuit. The Quartus II software allows
receiver-only configurations in Stratix GX devices. However, if you use
the Quartus II software to remove the transmitter PLL in a receiver-only
configuration, you will see an incorrect value or unpredictable behavior
with the receiver input pin termination. If the rx_cruclk signal is
globally routed, the Quartus II software handles this automatically. If the
rx_cruclk signal is not globally routed or routed using the inter­quadrant line (IQ2), the Quartus II software returns a no-fit. In this
situation, you must add a transmitter PLL to your design.

If the pll_areset (analog reset) signal goes high, the RX_Vcm value is
less than the 1.1 V. This value varies unpredictably because the circuit is
tristated. RX_Vcm is referenced from the Stratix GX receiver analog power
supply.

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Stratix GX Transceiver User Guide January 2005

Stratix GX Analog Description

If external termination is used, the receiver must be externally terminated
and biased to 1.1 V. Figure 2–9 shows an example of an external
termination and biasing circuit.

Figure 2–9. External Termination & Biasing Circuit

50/60/75­Termination

Resistance

Transmission

Receiver External Termination
and Biasing

Ω

R1/R2 = 1K

V

× {R2/(R1 + R 2)} = 1.1 V

DD

Receiver External Termination

Line

V

DD

C1

and Biasing

R1

R2

Stratix GX Device

Receiver

RXIP

RXIN

Enable Stratix GX-to-Stratix GX Receiver DC Coupling

You can configure the Stratix GX receiver buffers so that DC-coupled
Stratix GX-to-Stratix GX communication is possible. The Stratix GX
transmitter’s common-mode is typically around 750 mV, while the
receiver common mode by default is approximately 1.1 V. However, by
enabling DC coupling, the receiver common mode is biased to allow
interoperability with the Stratix GX transmitter.

Equalizer Mode

Stratix GX transceivers offer an equalization circuit in each receiver
channel to increase noise margins and help reduce the effects of high
frequency losses. The programmable equalizer compensates for
inter-symbol interference (ISI) and high frequency losses that distort the
signal and reduce the noise margin of the transmission medium by
equalizing the frequency response.

The transfer function of a transmission line can be represented in the
frequency domain as a low-pass filter. Any frequency components below
the –3-dB frequency pass through with minimal losses. Frequency
components that are greater than the –3-dB frequency are attenuated.

Altera Corporation 2–11
January 2005 Stratix GX Transceiver User Guide

Receiver Analog

This variation in frequency response yields data-dependant jitter and
other ISI effects. By applying equalization, the low frequency components
are attenuated. This equalizes the frequency response so that the delta
between the low frequency and high frequency components are reduced,
which minimizes the ISI effects from the transmission medium.

In Stratix GX transceivers, the programmable equalizer settings can have
one of five values (0 through four). You should experiment with the
equalization values to determine the optimal setting based on your
system variables.

As with the V

settings, you can set the equalization settings statically

OD

during configuration or adjust them dynamically in user mode. You can
select the static equalization value through a drop-down menu in the
altgxb MegaWizard Plug-In. This action sets the appropriate
equalization setting in the configuration file. The disadvantage of this
mode is that the equalization is set on a per-transceiver block basis and
cannot be changed without regenerating another programming file.

On the other hand, if you select the dynamic adjustment in the altgxb
MegaWizard Plug-In, the equalization setting can be configured
dynamically by the device during user mode. This configuration is
accomplished by asserting encoded values on the rx_equalizerctrl
signal, which is instantiated in the altgxb module when this option is
selected. This feature lets you make quick performance evaluations of the
various settings without having to recompile and regenerate multiple
configuration files. Another advantage is that this option allows the
equalization of each channel to be configured independently. Refer to

“MegaWizard Analog Features” on page 2–20 for more details.

Receiver PLL

Each transceiver block contains four receiver PLLs and a slow-speed
reference clock. The receiver PLLs receive the reference clock and
generate the high-speed serial clock used by the CR. The slow-speed
reference clock is used for the transceiver logic. Figure 2–10 shows the
block diagram for the lock-to-reference portion of the receiver PLL.

This section focuses on the receiver PLL in Lock-to-Reference mode. The
lock-to-data circuit has been omitted. Refer to the “Lock-to-Reference

Mode & Lock-to-Data Mode” on page 2–16 for more information on the

operation between the two modes.

2–12 Altera Corporation
Stratix GX Transceiver User Guide January 2005