ALTERA Stratix GX Service Manual
Stratix GX Device Handbook, Volume 1
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
www.altera.com
SGX5V1-1.2
Copyright © 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as
expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for
products or services.
ii Altera Corporation
Contents
Chapter Revision Dates .......................................................................... vii
About This Handbook .............................................................................. ix
How to Contact Altera ............................................................................................................................. ix
Typographic Conventions ....................................................................................................................... ix
Section I. Stratix GX Device Family Data Sheet
Revision History ....................................................................................................................... Section I–2
Chapter 1. Introduction to the Stratix GX Device Data Sheet
Overview ................................................................................................................................................. 1–1
Features ................................................................................................................................................... 1–1
High-Speed I/O Interface Functional Description ........................................................................... 1–4
FPGA Functional Description .............................................................................................................. 1–5
Chapter 2. Stratix GX Transceivers
Transmitter Path ............................................................................................................................... 2–5
Receiver Path ................................................................................................................................... 2–13
Loopback Modes ............................................................................................................................ 2–26
BIST (Built-In Self Test) ................................................................................................................. 2–28
Stratix GX Clocking ........................................................................................................................ 2–30
Other Transceiver Features ................................................................................................................ 2–37
Individual Power-Down & Reset for the Transmitter & Receiver .......................................... 2–37
Voltage Reference Capabilities ..................................................................................................... 2–38
Hot-Socketing Capabilities ........................................................................................................... 2–39
Applications & Protocols Supported with Stratix GX Devices ..................................................... 2–39
Stratix GX Example Application Support ................................................................................... 2–39
High-Speed Serial Bus Protocols .................................................................................................. 2–40
Chapter 3. Source-Synchronous Signaling With DPA
Introduction ............................................................................................................................................ 3–1
Stratix GX I/O Banks ....................................................................................................................... 3–1
Principles of SERDES Operation .................................................................................................... 3–1
DPA Block Overview ....................................................................................................................... 3–5
DPA Operation ............................................................................................................................... 3–10
Altera Corporation iii
Contents
Chapter 4. Stratix GX Architecture
Logic Array Blocks ................................................................................................................................ 4–1
LAB Interconnects ............................................................................................................................ 4–1
LAB Control Signals ......................................................................................................................... 4–2
Logic Elements ....................................................................................................................................... 4–3
LUT Chain & Register Chain .......................................................................................................... 4–5
addnsub Signal ................................................................................................................................. 4–5
LE Operating Modes ........................................................................................................................ 4–5
Clear & Preset Logic Control ........................................................................................................ 4–10
MultiTrack Interconnect ..................................................................................................................... 4–11
TriMatrix Memory ............................................................................................................................... 4–18
Memory Modes ............................................................................................................................... 4–19
Parity Bit Support ........................................................................................................................... 4–21
Shift Register Support .................................................................................................................... 4–21
Memory Block Size ......................................................................................................................... 4–22
Independent Clock Mode .............................................................................................................. 4–40
Input/Output Clock Mode ........................................................................................................... 4–42
Read/Write Clock Mode ............................................................................................................... 4–44
Single-Port Mode ............................................................................................................................ 4–45
Digital Signal Processing Block ......................................................................................................... 4–46
Multiplier Block .............................................................................................................................. 4–52
Adder/Output Blocks ................................................................................................................... 4–56
Modes of Operation ....................................................................................................................... 4–59
DSP Block Interface ........................................................................................................................ 4–65
PLLs & Clock Networks ..................................................................................................................... 4–68
Global & Hierarchical Clocking ................................................................................................... 4–68
Enhanced & Fast PLLs ................................................................................................................... 4–76
Enhanced PLLs ............................................................................................................................... 4–82
Fast PLLs .......................................................................................................................................... 4–93
I/O Structure ........................................................................................................................................ 4–96
Double-Data Rate I/O Pins ......................................................................................................... 4–103
External RAM Interfacing ........................................................................................................... 4–107
Programmable Drive Strength ................................................................................................... 4–110
Open-Drain Output ...................................................................................................................... 4–111
Slew-Rate Control ........................................................................................................................ 4–112
Bus Hold ........................................................................................................................................ 4–112
Programmable Pull-Up Resistor ................................................................................................ 4–113
Advanced I/O Standard Support .............................................................................................. 4–113
Differential On-Chip Termination ............................................................................................. 4–118
MultiVolt I/O Interface ............................................................................................................... 4–120
Power Sequencing & Hot Socketing ............................................................................................... 4–121
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support ........................................................................ 4–122
Chapter 5. Configuration & Testing
SignalTap Embedded Logic Analyzer ................................................................................................ 5–1
Configuration ......................................................................................................................................... 5–1
Operating Modes .............................................................................................................................. 5–1
iv Altera Corporation
Stratix GX Device Handbook, Volume 1
Contents
Configuration Schemes ................................................................................................................... 5–2
Partial Reconfiguration .................................................................................................................... 5–3
Remote Update Configuration Modes .......................................................................................... 5–3
Stratix GX Automated Single Event Upset (SEU) Detection ........................................................... 5–7
Custom-Built Circuitry .................................................................................................................... 5–8
Software Interface ............................................................................................................................. 5–8
Temperature-Sensing Diode ................................................................................................................ 5–8
Chapter 6. DC & Switching Characteristics
Operating Conditions ........................................................................................................................... 6–1
Power Consumption ........................................................................................................................... 6–22
Timing Model ....................................................................................................................................... 6–22
Preliminary & Final Timing .......................................................................................................... 6–23
Performance .................................................................................................................................... 6–23
Internal Timing Parameters .......................................................................................................... 6–26
External Timing Parameters ......................................................................................................... 6–35
External I/O Delay Parameters .................................................................................................... 6–44
Maximum Input & Output Clock Rates ...................................................................................... 6–54
High-Speed I/O Specification ........................................................................................................... 6–58
PLL Timing ...................................................................................................................................... 6–62
DLL Jitter ............................................................................................................................................... 6–68
Chapter 7. Reference & Ordering Information
Software .................................................................................................................................................. 7–1
Device Pin-Outs ..................................................................................................................................... 7–1
Ordering Information ........................................................................................................................... 7–1
Altera Corporation v
Stratix GX Device Handbook, Volume 1
Contents
vi Altera Corporation
Stratix GX Device Handbook, Volume 1
Chapter Revision Dates
The chapters in this book, Stratix GX Device Handbook, Volume 1, were revised on the following dates.
Where chapters or groups of chapters are available separately, part numbers are listed.
Chapter 1. Introduction to the Stratix GX Device Data Sheet
Revised: February 2005
Part number: SGX51001-1.0
Chapter 2. Stratix GX Transceivers
Revised: June 2006
Part number: SGX51002-1.1
Chapter 3. Source-Synchronous Signaling With DPA
Revised: August 2005
Part number: SGX51003-1.1
Chapter 4. Stratix GX Architecture
Revised: February 2005
Part number: SGX51004-1.0
Chapter 5. Configuration & Testing
Revised: February 2005
Part number: SGX51005-1.0
Chapter 6. DC & Switching Characteristics
Revised: June 2006
Part number: SGX51006-1.2
Chapter 7. Reference & Ordering Information
Revised: February 2005
Part number: SGX51007-1.0
Altera Corporation vii
Chapter Revision Dates Stratix GX Device Handbook, Volume 1
viii Altera Corporation
About This Handbook
This handbook provides comprehensive information about the Altera®
Stratix®GX family of devices.
How to Contact Altera
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at www.altera.com. For technical support on
this product, go to www.altera.com/mysupport. For additional
information about Altera products, consult the sources shown below.
Information Type USA & Canada All Other Locations
Technical support www.altera.com/mysupport/ www.altera.com/mysupport/
(800) 800-EPLD (3753)
(7:00 a.m. to 5:00 p.m. Pacific Time)
Product literature www.altera.com www.altera.com
Altera literature services literature@altera.com literature@altera.com
Non-technical customer
service
FTP site ftp.altera.com ftp.altera.com
Typographic
(800) 767-3753 + 1 408-544-7000
This document uses the typographic conventions shown below.
+1 408-544-8767
7:00 a.m. to 5:00 p.m. (GMT -8:00)
Pacific Time
7:00 a.m. to 5:00 p.m. (GMT -8:00)
Pacific Time
Conventions
Visual Cue Meaning
Bold Type with Initial
Capital Letters
bold type External timing parameters, directory names, project names, disk drive names,
Italic Type with Initial Capital
Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
filenames, filename extensions, and software utility names are shown in bold
type. Examples: f
Document titles are shown in italic type with initial capital letters. Example: AN
75: High-Speed Board Design.
, \qdesigns directory, d: drive, chiptrip.gdf file.
MAX
Altera Corporation ix
Preliminary
Typographic Conventions Stratix GX Device Handbook, Volume 1
Visual Cue Meaning
Italic type Internal timing parameters and variables are shown in italic type.
Examples: t
Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.
Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title” References to sections within a document and titles of on-line help topics are
shown in quotation marks. Example: “Typographic Conventions.”
PIA
, n + 1.
Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,
tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example:
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword
Courier.
1., 2., 3., and
a., b., c., etc.
● • Bullets are used in a list of items when the sequence of the items is not important.
■
v The checkmark indicates a procedure that consists of one step only.
1 The hand points to information that requires special attention.
c
w
r The angled arrow indicates you should press the Enter key.
f The feet direct you to more information on a particular topic.
Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
The caution indicates required information that needs special consideration and
understanding and should be read prior to starting or continuing with the
procedure or process.
The warning indicates information that should be read prior to starting or
continuing the procedure or processes
c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
x Altera Corporation
Preliminary
Section I. Stratix GX
Device Family Data Sheet
This section provides the data sheet specifications for Stratix® GX
devices. It contains feature definitions of the internal architecture,
configuration information, testing information, DC operating conditions,
and AC timing parameters.
This section includes the following chapters:
■ Chapter 1, Introduction to the Stratix GX Device Data Sheet
■ Chapter 2, Stratix GX Transceivers
■ Chapter 3, Source-Synchronous Signaling With DPA
■ Chapter 4, Stratix GX Architecture
■ Chapter 5, Configuration & Testing
■ Chapter 6, DC & Switching Characteristics
■ Chapter 7, Reference & Ordering Information
Altera Corporation Section I–1
Preliminary
Stratix GX Device Family Data Sheet Stratix GX Device Handbook, Volume 1
Revision History
The table below shows the revision history for Chapters 1 through 7.
Chapter(s) Date / Version Changes Made Comments
1 February 2005,
v1.0
2 June 2006, v1.1
February 2005,
v1.0
3 August 2005,
v1.1
4 February 2005,
v1.0
5 February 2005,
v1.0
6 June 2006, v1.2
August 2005,
v1.1
7 February 2005,
v1.0
Initial Release.
● Updated “Serial Loopback” section.
● Updated Figures 2–1 through 2–3.
● Updated Figure 2–13.
● Updated Figures 2–26 and 2–27.
Initial Release.
Added Note (3) to Figure 3-7.
Initial Release.
Initial Release.
● Updated “Operating Conditions” section.
● Updated Table 6–4.
● Updated note 3 in Table 6–6.
● Added note 12 in Table 6–7.
● Updated Figure 6–1.
● Added Figure 6–2.
● Updated Tables 6–13 through 6–16.
Updated Tables 6-7 and 6-50.
Initial Release.
● Changed V
OD
receiver input voltage and
refclkb input voltage in
Table 6–4.
● Changed value for
undershoot during transition
from -0.5 V to -2.0 V in note 3
of Ta bl e 6 – 6.
● Changed value of V
mV to V in Table 6–15.
● Changed unit value of W to
Ω..
to VID for
OCM
from
Section I–2 Altera Corporation
Preliminary
SGX51001-1.0
1. Introduction to the
Stratix GX Device Data Sheet
Overview
Features
The Stratix®GX family of devices is Altera’s second FPGA family to
combine high-speed serial transceivers with a scalable, high-performance
logic array. Stratix GX devices include 4 to 20 high-speed transceiver
channels, each incorporating clock data recovery (CDR) technology and
embedded SERDES capability at data rates of up to 3.1875 gigabits per
second (Gbps). These transceivers are grouped by four-channel
transceiver blocks, and are designed for low power consumption and
small die size. The Stratix GX FPGA technology is built upon the Stratix
architecture, and offers a 1.5-V logic array with unmatched performance,
flexibility, and time-to-market capabilities. This scalable,
high-performance architecture makes Stratix GX devices ideal for
high-speed backplane interface, chip-to-chip, and communications
protocol-bridging applications.
■ Transceiver block features are as follows:
● High-speed serial transceiver channels with CDR provides
500-megabits per second (Mbps) to 3.1875-Gbps full-duplex
operation
● Devices are available with 4, 8, 16, or 20 high-speed serial
transceiver channels providing up to 127.5 Gbps of full-duplex
serial bandwidth
● Support for transceiver-based protocols, including 10 Gigabit
Ethernet attachment unit interface (XAUI), Gigabit Ethernet
(GigE), and SONET/SDH
● Compatible with PCI Express, SMPTE 292M, Fibre Channel, and
Serial RapidIO I/O standards
● Programmable differential output voltage (V
), pre-emphasis,
OD
and equalization settings for improved signal integrity
● Individual transmitter and receiver channel power-down
capability implemented automatically by the Quartus
®
II
software for reduced power consumption during non-operation
● Programmable transceiver-to-FPGA interface with support for
8-, 10-, 16-, and 20-bit wide data paths
● 1.5-V pseudo current mode logic (PCML) for 500 Mbps to
3.1875 Gbps
● Support for LVDS, LVPECL, and 3.3-V PCML on reference
clocks and receiver input pins (AC-coupled)
● Built-in self test (BIST)
● Hot insertion/removal protection circuitry
Altera Corporation 1–1
February 2005
Features
● Pattern detector and word aligner supports programmable
patterns
● 8B/10B encoder/decoder performs 8- to 10-bit encoding and 10-
to 8-bit decoding
● Rate matcher compliant with IEEE 802.3-2002 for GigE mode
and with IEEE 802-3ae for XAUI mode
● Channel bonding compliant with IEEE 802.3ae (for XAUI mode
only)
● Device can bypass some transceiver block features if necessary
■ FPGA features are as follows:
● 10,570 to 41,250 logic elements (LEs); see Table 1–1
● Up to 3,423,744 RAM bits (427,968 bytes) available without
reducing logic resources
● TriMatrix
™
memory consisting of three RAM block sizes to
implement true dual-port memory and first-in-out (FIFO)
buffers
● Up to 16 global clock networks with up to 22 regional clock
networks per device region
● High-speed DSP blocks provide dedicated implementation of
multipliers (faster than 300 MHz), multiply-accumulate
functions, and finite impulse response (FIR) filters
● Up to eight general usage phase-locked loops (four enhanced
PLLs and four fast PLLs) per device provide spread spectrum,
programmable bandwidth, clock switchover, real-time PLL
reconfiguration, and advanced multiplication and phase
shifting
● Support for numerous single-ended and differential I/O
standards
● High-speed source-synchronous differential I/O support on up
to 45 channels for 1-Gbps performance
● Support for source-synchronous bus standards, including
10-Gigabit Ethernet XSBI, Parallel RapidIO, UTOPIA IV,
Network Packet Streaming Interface (NPSI), HyperTransport
technology, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4
● Support for high-speed external memory, including zero bus
turnaround (ZBT) SRAM, quad data rate (QDR and QDRII)
SRAM, double data rate (DDR) SDRAM, DDR fast cycle RAM
(FCRAM), and single data rate (SDR) SDRAM
● Support for multiple intellectual property megafunctions from
Altera® MegaCore® functions and Altera Megafunction Partners
Program (AMPPSM) megafunctions
● Support for remote configuration updates
● Dynamic phase alignment on LVDS receiver channels
TM
1–2 Altera Corporation
Stratix GX Device Handbook, Volume 1 February 2005
Table 1–1. Stratix GX Device Features
Introduction to the Stratix GX Device Data Sheet
Feature
LEs 10,570 25,660 41,250
Transceiver channels 4, 8 4, 8, 16 8, 20
Source-synchronous channels 22 39 45
M512 RAM blocks (32
M4K RAM blocks (128
M-RAM blocks (4K
Total RAM bits 920,448 1,944,576 3,423,744
Digital signal processing (DSP) blocks 6 10 14
Embedded multipliers (1) 48 80 112
PLLs 4 4 8
Note to Ta b le 1 –1 :
(1) This parameter lists the total number of 9- × 9-bit multipliers for each device. For the total number of 18- × 18-bit
multipliers per device, divide the total number of 9- × 9-bit multipliers by 2. For the total number of 36- × 36-bit
multipliers per device, decide the total number of 9- × 9-bit multipliers by 8.
× 18 bits) 94 224 384
× 36 bits) 60 138 183
×144 bits) 1 2 4
EP1SGX10C
EP1SGX10D
EP1SGX25C
EP1SGX25D
EP1SGX25F
EP1SGX40D
EP1SGX40G
Stratix GX devices are available in space-saving FineLine BGA® packages
(refer to Tables 1–2 and 1–3), and in multiple speed grades (refer to
Table 1–4). Stratix GX devices support vertical migration within the same
package (that is, you can migrate between the EP1SGX10C and
EP1SGX25C devices in the 672-pin FineLine BGA package). See the
Stratix GX device pin tables for more information. Vertical migration
means that you can migrate to devices whose dedicated pins,
configuration pins, and power pins are the same for a given package
across device densities. For I/O pin migration across densities, you must
cross-reference the available I/O pins using the device pin-outs for all
planned densities of a given package type, to identify which I/O pins it
is possible to migrate. The Quartus II software can automatically cross
reference and place all pins for migration when given a device migration
list.
Table 1–2. Stratix GX Package Options & I/O Pin Counts (Part 1
of 2) Note (1)
Device 672-Pin FineLine BGA 1,020-Pin FineLine BGA
EP1SGX10C 362
EP1SGX10D 362
EP1SGX25C 455
Altera Corporation 1–3
February 2005 Stratix GX Device Handbook, Volume 1
High-Speed I/O Interface Functional Description
Table 1–2. Stratix GX Package Options & I/O Pin Counts (Part 2
of 2) Note (1)
Device 672-Pin FineLine BGA 1,020-Pin FineLine BGA
EP1SGX25D 455 607
EP1SGX25F 607
EP1SGX40D 624
EP1SGX40G 624
Note to Ta b l e 1 – 2:
(1) The number of I/O pins listed for each package includes dedicated clock pins and
dedicated fast I/O pins. However, these numbers do not include high-speed or
clock reference pins for high-speed I/O standards.
Table 1–3. Stratix GX FineLine BGA Package Sizes
Dimension 672 Pin 1,020 Pin
Pitch (mm) 1.00 1.00
Area (mm
Length
2
)
× width (mm × mm) 27 × 27 33 × 33
729 1,089
Table 1–4. Stratix GX Device Speed Grades
Device 672-Pin FineLine BGA 1,020-pin FineLine BGA
EP1SGX10 -5, -6, -7
EP1SGX25 -5, -6, -7 -5, -6, -7
EP1SGX40 -5, -6, -7
High-Speed I/O
Interface
Functional
Description
The Stratix GX device family supports high-speed serial transceiver
blocks with CDR circuitry as well as source-synchronous interfaces. The
channels on the right side of the device use an embedded circuit
dedicated for receiving and transmitting high-speed serial data streams
to and from the system board. These channels are clustered in a
four-channel serial transceiver building block and deliver high-speed
bidirectional point-to-point data transmissions to provide up to
3.1875 Gbps of full-duplex data transmission per channel. The channels
on the left side of the device support source-synchronous data transfers
at up to 1 Gbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport
technology I/O standards. Figure 1–1 shows the Stratix GX I/O blocks.
The differential source-synchronous serial interface and the high-speed
serial interface are described in the Stratix GX Transceivers chapter of the
Stratix GX Device Handbook, Volume 1.
1–4 Altera Corporation
Stratix GX Device Handbook, Volume 1 February 2005
Introduction to the Stratix GX Device Data Sheet
Figure 1–1. Stratix GX I/O Blocks Note (1)
DQST9 DQST8 DQST7 DQST6 DQST5 DQST4 DQST3 DQST2 DQST1 DQST0
VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3 VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4
PLL7
Bank 2
(4)
Bank 3 Bank 4
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (3)
PLL5
910
I/O Banks 3, 4, 9 & 10 Support
All Single-Ended I/O Standards (2)
PLL11
I/O Bank 13 (5)
I/O Bank 14 (5)
VREF1B2 VREF2B2 VREF3B2 VREF4B2VREF1B1 VREF2B1 VREF3B1 VREF4B1
PLL1
PLL2
(4)
Bank 1
PLL8
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (3)
VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7
DQSB9 DQSB8 DQSB7 DQSB6 DQSB5 DQSB4 DQSB3 DQSB2 DQSB1 DQSB0
I/O Banks 1 and 2 Support All
Single-Ended I/O Standards Except
Differential HSTL Output Clocks,
Differential SSTL-2 Output Clocks,
HSTL Class II, GTL, SSTL-18 Class II,
PCI, PCI-X, and AGP 1
×/2×
I/O Banks 7, 8, 11 & 12 Support
All Single-Ended I/O Standards (2)
11 12Bank 8 Bank 7
PLL6
PLL12
1.5-V PCML (5)
I/O Bank 17 (5)
I/O Bank 16 (5)
I/O Bank 15 (5)
Notes to Figure 1–1:
(1) Figure 1–1 is a top view of the Stratix GX silicon die.
(2) Banks 9 through 12 are enhanced PLL external clock output banks.
(3) If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the
I/O standards except HSTL class I and II, GTL, SSTL-18 Class II, PCI, PCI-X, and AGP 1×/2×.
(4) For guidelines for placing single-ended I/O pads next to differential I/O pads, see the Selectable I/O Standards in
Stratix & Stratix GX Devices chapter of the Stratix GX Device Handbook, Volume 2.
(5) These I/O banks in Stratix GX devices also support the LVDS, LVPECL, and 3.3-V PCML I/O standards on
reference clocks and receiver input pins (AC coupled).
FPGA Functional Description
Stratix GX devices contain a two-dimensional row- and column-based
architecture to implement custom logic. A series of column and row
interconnects of varying length and speed provide signal interconnects
between logic array blocks (LABs), memory block structures, and DSP
blocks.
Altera Corporation 1–5
February 2005 Stratix GX Device Handbook, Volume 1
FPGA Functional Description
The logic array consists of LABs, with 10 logic elements (LEs) in each
LAB. An LE is a small unit of logic providing efficient implementation of
user logic functions. LABs are grouped into rows and columns across the
device.
M512 RAM blocks are simple dual-port memory blocks with 512 bits plus
parity (576 bits). These blocks provide dedicated simple dual-port or
single-port memory up to 18-bits wide at up to 318 MHz. M512 blocks are
grouped into columns across the device in between certain LABs.
M4K RAM blocks are true dual-port memory blocks with 4K bits plus
parity (4,608 bits). These blocks provide dedicated true dual-port, simple
dual-port, or single-port memory up to 36-bits wide at up to 291 MHz.
These blocks are grouped into columns across the device in between
certain LABs.
M-RAM blocks are true dual-port memory blocks with 512K bits plus
parity (589,824 bits). These blocks provide dedicated true dual-port,
simple dual-port, or single-port memory up to 144-bits wide at up to
269 MHz. Several M-RAM blocks are located individually or in pairs
within the device’s logic array.
Digital signal processing (DSP) blocks can implement up to either eight
full-precision 9 × 9-bit multipliers, four full-precision 18 × 18-bit
multipliers, or one full-precision 36 × 36-bit multiplier with add or
subtract features. These blocks also contain 18-bit input shift registers for
digital signal processing applications, including FIR and infinite impulse
response (IIR) filters. DSP blocks are grouped into two columns in each
device.
Each Stratix GX device I/O pin is fed by an I/O element (IOE) located at
the end of LAB rows and columns around the periphery of the device.
I/O pins support numerous single-ended and differential I/O standards.
Each IOE contains a bidirectional I/O buffer and six registers for
registering input, output, and output-enable signals. When used with
dedicated clocks, these registers provide exceptional performance and
interface support with external memory devices such as DDR SDRAM,
FCRAM, ZBT, and QDR SRAM devices.
High-speed serial interface channels support transfers at up to 840 Mbps
using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O
standards.
Figure 1–2 shows an overview of the Stratix GX device.
1–6 Altera Corporation
Stratix GX Device Handbook, Volume 1 February 2005
Figure 1–2. Stratix GX Block Diagram
M512 RAM Blocks for
Dual-Port Memory, Shift
Registers, & FIFO Buffers
DSP Blocks for
Multiplication and Full
Implementation of FIR Filters
Introduction to the Stratix GX Device Data Sheet
M4K RAM Blocks
for True Dual-Port
Memory & Other Embedded
Memory Functions
IOEs Support DDR, PCI, GTL+, SSTL-3,
SSTL-2, HSTL, LVDS, LVPECL, PCML,
HyperTransport & other I/O Standards
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
DSP
Block
IOEs IOEs
LABs LABs
LABs
LABs LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
M-RAM Block
The number of M512 RAM, M4K RAM, and DSP blocks varies by device
along with row and column numbers and M-RAM blocks. Table 1–5 lists
the resources available in Stratix GX devices.
Table 1–5. Stratix GX Device Resources
Device
M512 RAM
Columns/Blocks
EP1SGX10 4 / 94 2 / 60 1 2 / 6 40 30
EP1SGX25 6 / 224 3 / 138 2 2 / 10 62 46
EP1SGX40 8 / 384 3 / 183 4 2 / 14 77 61
Altera Corporation 1–7
February 2005 Stratix GX Device Handbook, Volume 1
M4K RAM
Columns/Blocks
M-RAM
Blocks
DSP Block
Columns/Blocks
LAB
Columns
LAB Rows
FPGA Functional Description
1–8 Altera Corporation
Stratix GX Device Handbook, Volume 1 February 2005
SGX51002-1.1
2. Stratix GX Transceivers
Transceiver Blocks
Stratix®GX devices incorporate dedicated embedded circuitry on the
right side of the device, which contains up to 20 high-speed 3.1875-Gbps
serial transceiver channels. Each Stratix GX transceiver block contains
four full-duplex channels and supporting logic to transmit and receive
high-speed serial data streams. The transceiver block uses the channels to
deliver bidirectional point-to-point data transmissions with up to
3.1875 Gbps of data transition per channel.
There are up to 20 transceiver channels available on a single Stratix GX
device. Ta bl e 2 –1 shows the number of transceiver channels available on
each Stratix GX device.
Table 2–1. Stratix GX Transceiver Channels
Device Number of Transceiver Channels
EP1SGX10C 4
EP1SGX10D 8
EP1SGX25C 4
EP1SGX25D 8
EP1SGX25F 16
EP1SGX40D 8
EP1SGX40G 20
Figure 2–1 shows the elements of the transceiver block, including the four
channels, supporting logic, and I/O buffers. Each transceiver channel
consists of a receiver and transmitter. The supporting logic contains a
transmitter PLL to generate a high-speed clock used by the four
transmitters. The receiver PLL within each transceiver channel generates
the receiver reference clocks. The supporting logic also contains state
machines to manage rate matching for XAUI and GIGE applications, in
addition to channel bonding for XAUI applications.
Altera Corporation 2–1
June 2006
Figure 2–1. Stratix GX Transceiver Block Note (1)
PLD
Logic
Array
PLD
Logic
Array
PLD
Logic
Array
PLD
Logic
Array
XAUI
Receiver
State
Machine
Receiver Channel 0
Channel 0
Transmitter Channel 0
Receiver Channel 1
Channel 1
Transmitter Channel 1
XAUI
Transmitter
State
Machine
Receiver Channel 2
Channel 2
Transmitter Channel 2
Channel
Aligner
State
Machine
Transmitter
PLL
Receiver Pins
Transmitter Pins
Receiver Pins
Transmitter Pins
PLD
Logic
Array
(2)
Receiver Pins
Transmitter Pins
Receiver Pins
Transmitter Pins
PLD
Logic
Array
Receiver Channel 3
Channel 3
Transmitter Channel 3
Notes to Figure 2–1:
(1) Each receiver channel has its own PLL and CRU, which are not shown in this diagram. For more information, refer
to the section “Receiver Path” on page 2–13.
(2) For possible transmitter PLL clock inputs, refer to the section “Transmitter Path” on page 2–5.
2–2 Altera Corporation
Stratix GX Device Handbook, Volume 1 June 2006
Stratix GX Transceivers
Each Stratix GX transceiver channel consists of a transmitter and receiver.
The transmitter contains the following:
■ Transmitter PLL
■ Transmitter phase compensation FIFO buffer
■ Byte serializer
■ 8B/10B encoder
■ Serializer (parallel to serial converter)
■ Transmitter output buffer
The receiver contains the following:
■ Input buffer
■ Clock recovery unit (CRU)
■ Deserializer
■ Pattern detector and word aligner
■ Rate matcher and channel aligner
■ 8B/10B decoder
■ Receiver logic array interface
You can set all the Stratix GX transceiver functions through the Quartus II
software. You can set programmable pre-emphasis, programmable
equalizer, and programmable V
dynamically as well. Each Stratix GX
OD
transceiver channel is also capable of BIST generation and verification in
addition to various loopback modes. Figure 2–2 shows the block diagram
for the Stratix GX transceiver channel.
Stratix GX transceivers provide physical coding sublayer (PCS) and
physical media attachment (PMA) implementation for protocols such as
10-gigabit XAUI and GIGE. The PCS portion of the transceiver consists of
the logic array interface, 8B/10B encoder/decoder, pattern detector, word
aligner, rate matcher, channel aligner, and the BIST and pseudo-random
binary sequence pattern generator/verifier. The PMA portion of the
transceiver consists of the serializer/deserializer, the CRU, and the I/O
buffers.
Altera Corporation 2–3
June 2006 Stratix GX Device Handbook, Volume 1
Figure 2–2. Stratix GX Transceiver ChanneL Note (1)
FIFO
Phase
Compensation
Byte
Deserializer
8B/10B
Decoder
Rate
Matcher
FIFO
Phase
Compensation
Byte
Serializer
8B/10B
Encoder
Aligner
Channel
Word
Aligner
Unit
Channel 0
Clock
Recovery
Deserializer
Receiver
PLL
Receiver
Transmitter
Clock
Receiver
Reference
To Channels 1-3
Serializer
PLL
Transmitter
Reference
Transmitter
Clock
Note to Figure 2–2:
(1) There are four transceiver channels in a transceiver block.
2–4 Altera Corporation
Stratix GX Device Handbook, Volume 1 June 2006
Stratix GX Transceivers
Transmitter Path
This section describes the data path through the Stratix GX transmitter
(see Figure 2–2). Data travels through the Stratix GX transmitter via the
following modules:
■ Transmitter PLL
■ Transmitter phase compensation FIFO buffer
■ Byte serializer
■ 8B/10B encoder
■ Serializer (parallel to serial converter)
■ Transmitter output buffer
Transmitter PLL
Each transceiver block has one transmitter PLL, which receives the
reference clock and generates the following signals:
■ High-speed serial clock used by the serializer
■ Slow-speed reference clock used by the receiver
■ Slow-speed clock used by the logic array (divisible by two for
double-width mode)
The INCLK clock is the input into the transmitter PLL. There is one INCLK
clock per transceiver block. This clock can be fed by either the REFCLKB
pin, PLD routing, or the inter-transceiver routing line. See the section
“Stratix GX Clocking” on page 2–30 for more information about the inter-
transceiver lines.
The transmitter PLL in each transceiver block clocks the circuits in the
transmit path. The transmitter PLL is also used to train the receiver PLL.
If no transmit channels are used in the transceiver block, the transmitter
PLL can be turned off. Figure 2–3 is a block diagram of the transmitter
PLL.
Altera Corporation 2–5
June 2006 Stratix GX Device Handbook, Volume 1
Figure 2–3. Transmitter PLL Block Diagram Note (1)
k
Low Speed Clock
High Speed Cloc
Clock
Driver
÷m
VCO
Charge Pump +
Loop Filter
Up
Down
PFD
INCLK
÷2
Inter Quad Routing (IQ1)
Inter Quad Routing (IQ0)
Global Clks, IO Bus, Gen Routing
Dedicated
Local
REFCLKB
Note to Figure 2–3:
(1) The divider in the PLL divides by 4, 8, 10, 16, or 20.
2–6 Altera Corporation
Stratix GX Device Handbook, Volume 1 June 2006
Stratix GX Transceivers
The transmitter PLL can support up to 3.1875 Mbps. The input clock
frequency for –5 and –6 speed grade devices is limited to 650 MHz if you
use the REFCLKB pin or to 325 MHz if you use the other clock routing
resources. For –7 speed grade devices, the maximum input clock
frequency is 312.5 MHz with the REFCLKB pin, and the maximum is
156.25 MHz for all other clock routing resources. An optional
PLL_LOCKED port is available to indicate whether the transmitter PLL is
locked to the reference clock. The transmitter PLL has a programmable
loop bandwidth that can be set to low or high. The loop bandwidth
parameter can be statically set in the Quartus II software.
Table 2–2 lists the adjustable parameters in the transmitter PLL.
Table 2–2. Transmitter PLL Specifications
Parameter Specifications
Input reference frequency range 25 MHz to 650 MHz
Data rate support 500 Mbps to 3.1875 Gbps
Multiplication factor (W) 2, 4, 5, 8, 10, 16, or 20 (1)
Bandwidth Low, high
Note to Ta b l e 2 – 2:
(1) Multiplication factors 2 and 5 can only be achieved with the use of the pre-divider
on the REFCLKB pin.
Transmitter Phase Compensation FIFO Buffer
The transmitter phase compensation FIFO buffer resides in the
transceiver block at the PLD boundary. This FIFO buffer compensates for
the phase differences between the transmitter reference clock (inclk)
and the PLD interface clock (tx_coreclk). The phase difference
between the two clocks must be less than 360°. The PLD interface clock
must also be frequency locked to the transmitter reference clock. The
phase compensation FIFO buffer is four words deep and cannot be
bypassed.
Byte Serializer
The byte serializer takes double-width words (16 or 20 bits) from the PLD
interface and converts them to a single width word (8 or 10 bits) for use
in the transceiver. The transmit data path after the byte serializer is single
width (8 or 10 bits). The byte serializer is bypassed when single width
mode (8 or 10 bits) is used at the PLD interface.
Altera Corporation 2–7
June 2006 Stratix GX Device Handbook, Volume 1
8B/10B Encoder
t
The 8B/10B encoder translates 8-bit wide data + 1 control enable bit into
a 10-bit encoded data. The encoded data has a maximum run length of 5.
The 8B/10B encoder can be bypassed. Figure 2–4 diagrams the encoding
process.
Figure 2–4. Encoding Process
+
76543210
HGFED CB A
8b-10b conversion
jhgfiedcba
9876543210
ctrl
MSB sent last
LSB sent firs
Transmit State Machine
The transmit state machine operates in either XAUI mode or in GIGE
mode, depending on the protocol used.
GIGE Mode
In GIGE mode, the transmit state machines convert all idle ordered sets
(/K28.5/, /Dx.y/) to either /I1/ or /I2/ ordered sets. /I1/ consists
of a negative-ending disparity /K28.5/ (denoted by /K28.5/-)
followed by a neutral /D5.6/. /I2/ consists of a positive-ending
disparity /K28.5/ (denoted by /K28.5/+) and a negative-ending
disparity /D16.2/ (denoted by /D16.2/-). The transmit state machines
do not convert any of the ordered sets to match /C1/ or /C2/, which are
the configuration ordered sets. (/C1/ and /C2/ are defined by
(/K28.5/, /D21.5/) and (/K28.5/, /D2.2/), respectively.) Both the
/I1/ and /I2/ ordered sets guarantee a negative-ending disparity after
each ordered set. The GIGE transmit state machine can be statically
disabled in the Quartus II software, even if using the GIGE protocol
mode.
2–8 Altera Corporation
Stratix GX Device Handbook, Volume 1 June 2006
Stratix GX Transceivers
XAUI Mode
The transmit state machine translates the XAUI XGMII code group to the
XAUI PCS code group. Table 2–3 shows the code conversion.
Table 2–3. Code Conversion
XGMII TXC XGMII TXD PCS Code-Group Description
0 00 through FF Dxx.y Normal data
1 07 K28.0 or K28.3 or
K28.5
1 07 K28.5 Idle in ||T||
1 9C K28.4 Sequence
1 FB K27.7 Start
1 FD K29.7 Terminate
1 FE K30.7 Error
1 See IEEE 802.3
reserved code
groups
1 Other value K30.7 Invalid XGMII character
See IEEE 802.3
reserved code groups
Idle in ||I||
Reserved code groups
The XAUI PCS idle code groups, /K28.0/ (/R/) and /K28.5/ (/K/), are
7+x6
automatically randomized based on a PRBS7 pattern with an x
+1
polynomial. The /K28.3/ (/A/) code group is automatically generated
between 16 and 31 idle code groups. The idle randomization on the /A/,
/K/, and /R/ code groups are done automatically by the transmit state
machine.
Serializer (Parallel-to-Serial Converter)
The serializer converts the parallel 8-bit or 10-bit data into a serial stream,
transmitting the LSB first. The serialized stream is then fed to the transmit
buffer. Figure 2–5 is a diagram of the serializer.
Altera Corporation 2–9
June 2006 Stratix GX Device Handbook, Volume 1
Figure 2–5. Serializer
Low-speed
parallel clock
High-speed
serial clock
Transmit Buffer
D9
D8
D7
D6
10
D5
D4
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Serial data
out (to output
buffer)
The Stratix GX transceiver buffers support the 1.5-V pseudo current
mode logic (PCML) I/O standard at a rate up to 3.1875 Gbps, across up to
40 inches of FR4 trace, and across 2 connectors. Additional I/O standards,
LVDS, 3.3-V PCML, LVPECL, can be supported when AC coupled. The
common mode of the output driver is 750 mV.
The output buffer, as shown in Figure 2–6, consists of a programmable
output driver and a programmable pre-emphasis circuit.
2–10 Altera Corporation
Stratix GX Device Handbook, Volume 1 June 2006
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