ALTERA Stratix EP1S25 Service Manual

Pin Information For The Stratix™ EP1S25 Device, ver 3.6

Page 1 of 27

Bank Number

B2 VREF0B2 IO DIFFIO_RX38p C1 C1 F31 HIGH B2 VREF0B2 IO DIFFIO_RX38n D2 D2 F32 HIGH B2 VREF0B2 IO DIFFIO_TX38p E3 E3 G28 HIGH B2 VREF0B2 IO DIFFIO_TX38n E4 E4 G27 HIGH B2 VREF0B2 IO DIFFIO_RX37p E1 E1 G29 HIGH B2 VREF0B2 IO DIFFIO_RX37n E2 E2 G30 HIGH B2 VREF0B2 IO DIFFIO_TX37p F3 F3 F24 H28 HIGH B2 VREF0B2 IO DIFFIO_TX37n F4 F4 F23 H27 HIGH B2 VREF0B2 IO DIFFIO_RX36p F1 F1 C27 H30 HIGH B2 VREF0B2 IO DIFFIO_RX36n F2 F2 C28 H29 HIGH B2 VREF0B2 IO DIFFIO_TX36p G5 G5 G23 J27 HIGH B2 VREF0B2 IO DIFFIO_TX36n G6 G6 G24 J28 HIGH B2 VREF0B2 IO DIFFIO_RX35p G1 G1 D27 G31 HIGH B2 VREF0B2 IO DIFFIO_RX35n G2 G2 D28 G32 HIGH B2 VREF0B2 IO DIFFIO_TX35p G3 G3 H24 H25 HIGH B2 VREF0B2 IO DIFFIO_TX35n G4 G4 H23 H26 HIGH B2 VREF0B2 IO DIFFIO_RX34p H1 H1 E27 H31 HIGH B2 VREF0B2 IO DIFFIO_RX34n H2 H2 E28 H32 HIGH B2 VREF0B2 IO DIFFIO_TX34p H3 H3 H22 J25 HIGH B2 VREF0B2 IO DIFFIO_TX34n H4 H4 H21 J26 HIGH B2 VREF0B2 VREF0B2 H8 H8 E24 F27 B2 VREF0B2 IO DIFFIO_RX33p F25 J29 HIGH B2 VREF0B2 IO DIFFIO_RX33n F26 J30 HIGH B2 VREF0B2 IO DIFFIO_TX33p H6 H6 J24 K28 HIGH B2 VREF0B2 IO DIFFIO_TX33n H5 H5 J23 K27 HIGH B2 VREF0B2 IO DIFFIO_RX32p F27 K30 HIGH B2 VREF0B2 IO DIFFIO_RX32n F28 K29 HIGH B2 VREF0B2 IO DIFFIO_TX32p J7 J7 K23 K26 HIGH B2 VREF0B2 IO DIFFIO_TX32n H7 H7 K24 K25 HIGH B2 VREF0B2 IO DIFFIO_RX31p J4 J4 G26 J32 HIGH B2 VREF0B2 IO DIFFIO_RX31n J3 J3 G25 J31 HIGH B2 VREF0B2 IO DIFFIO_TX31p J21 L27 HIGH B2 VREF0B2 IO DIFFIO_TX31n J22 L26 HIGH B2 VREF0B2 IO DIFFIO_RX30p J2 J2 G27 K31 HIGH B2 VREF0B2 IO DIFFIO_RX30n J1 J1 G28 L32 HIGH B2 VREF0B2 IO DIFFIO_TX30p J6 J6 K21 M26 HIGH B2 VREF0B2 IO DIFFIO_TX30n J5 J5 K22 M27 HIGH B2 VREF0B2 IO DIFFIO_RX29p/RUP2 K4 K4 H26 M28 HIGH B2 VREF0B2 IO DIFFIO_RX29n/RDN2 K3 K3 H25 M29 HIGH B2 VREF0B2 IO DIFFIO_TX29p L22 M24 HIGH B2 VREF0B2 IO DIFFIO_TX29n L21 M25 HIGH B2 VREF1B2 IO DIFFIO_RX28p H27 L30 HIGH B2 VREF1B2 IO DIFFIO_RX28n H28 L31 HIGH B2 VREF1B2 IO DIFFIO_TX28p L23 N24 HIGH B2 VREF1B2 IO DIFFIO_TX28n L24 N23 HIGH B2 VREF1B2 IO DIFFIO_RX27p K2 K2 J25 M31 HIGH B2 VREF1B2 IO DIFFIO_RX27n K1 K1 J26 M30 HIGH B2 VREF1B2 IO DIFFIO_TX27p K9 K9 L20 N27 HIGH B2 VREF1B2 IO DIFFIO_TX27n J8 J8 L19 N28 HIGH B2 VREF1B2 IO DIFFIO_RX26p K6 K6 J27 N29 HIGH B2 VREF1B2 IO DIFFIO_RX26n K5 K5 J28 N30 HIGH B2 VREF1B2 IO DIFFIO_TX26p K8 K8 M22 P23 HIGH B2 VREF1B2 IO DIFFIO_TX26n K7 K7 M21 P24 HIGH B2 VREF1B2 IO DIFFIO_RX25p L3 L3 K26 N31 HIGH B2 VREF1B2 IO DIFFIO_RX25n L2 L2 K25 N32 HIGH B2 VREF1B2 IO DIFFIO_TX25p L5 L5 M24 N25 HIGH B2 VREF1B2 IO DIFFIO_TX25n L4 L4 M23 N26 HIGH B2 VREF1B2 IO DIFFIO_RX24p K27 P29 HIGH B2 VREF1B2 IO DIFFIO_RX24n K28 P30 HIGH B2 VREF1B2 IO DIFFIO_TX24p L7 L7 M20 P28 HIGH B2 VREF1B2 IO DIFFIO_TX24n L6 L6 M19 P27 HIGH B2 VREF1B2 VREF1B2 L8 L8 K20 L25 B2 VREF1B2 IO DIFFIO_RX23p M6 M6 L25 P31 HIGH B2 VREF1B2 IO DIFFIO_RX23n M7 M7 L26 P32 HIGH B2 VREF1B2 IO DIFFIO_TX23p N26 R28 HIGH B2 VREF1B2 IO DIFFIO_TX23n N25 R27 HIGH B2 VREF1B2 IO DIFFIO_RX22p M4 M4 L27 R32 HIGH B2 VREF1B2 IO DIFFIO_RX22n M5 M5 L28 R31 HIGH B2 VREF1B2 IO DIFFIO_TX22p N24 P25 HIGH B2 VREF1B2 IO DIFFIO_TX22n N23 P26 HIGH B2 VREF1B2 IO DIFFIO_RX21p N6 N6 M25 R30 HIGH B2 VREF1B2 IO DIFFIO_RX21n N7 N7 M26 R29 HIGH

VREF Bank Pin Name/Function Optional Function(s) Configuration

Function

B672 F672 F780 F1020 DQS for x16 DQS for x32

DIFFIO Speed (1)

Pin List

Pin Information For The Stratix™ EP1S25 Device, ver 3.6

Page 2 of 27

Bank Number

B2 VREF1B2 IO DIFFIO_TX21p M8 M8 N22 R23 HIGH B2 VREF1B2 IO DIFFIO_TX21n M9 M9 N21 R24 HIGH B2 VREF1B2 IO DIFFIO_RX20p M27 T32 HIGH B2 VREF1B2 IO DIFFIO_RX20n N28 T31 HIGH B2 VREF1B2 IO DIFFIO_TX20p P8 P8 N20 R25 HIGH B2 VREF1B2 IO DIFFIO_TX20n N8 N8 N19 R26 HIGH B2 VREF1B2 CLK0n N2 N2 N27 T30 B2 VREF1B2 CLK0p N3 N3 P27 T29 B2 VREF1B2 IO CLK1n P26 T28 B2 VREF1B2 CLK1p M1 M1 P25 T27

B1 VREF0B1 CLK2p R1 R1 R27 U31 B1 VREF0B1 CLK2n R2 R2 T27 U32 B1 VREF0B1 CLK3p R3 R3 R25 U29 B1 VREF0B1 IO CLK3n R26 U30 B1 VREF0B1 IO DIFFIO_RX19p T28 U28 HIGH B1 VREF0B1 IO DIFFIO_RX19n U27 U27 HIGH B1 VREF0B1 IO DIFFIO_TX19p P6 P6 T21 V26 HIGH B1 VREF0B1 IO DIFFIO_TX19n P7 P7 T22 V25 HIGH B1 VREF0B1 IO DIFFIO_RX18p R6 R6 U26 V32 HIGH B1 VREF0B1 IO DIFFIO_RX18n R7 R7 U25 V31 HIGH B1 VREF0B1 IO DIFFIO_TX18p R8 R8 T19 V28 HIGH B1 VREF0B1 IO DIFFIO_TX18n R9 R9 T20 V27 HIGH B1 VREF0B1 IO DIFFIO_RX17p R4 R4 V27 V30 HIGH B1 VREF0B1 IO DIFFIO_RX17n R5 R5 V28 V29 HIGH B1 VREF0B1 IO DIFFIO_TX17p T23 W25 HIGH B1 VREF0B1 IO DIFFIO_TX17n T24 W26 HIGH B1 VREF0B1 VREF0B1 T8 T8 R19 V21 B1 VREF0B1 IO DIFFIO_RX16p T3 T3 V26 W32 HIGH B1 VREF0B1 IO DIFFIO_RX16n T2 T2 V25 W31 HIGH B1 VREF0B1 IO DIFFIO_TX16p T26 W27 HIGH B1 VREF0B1 IO DIFFIO_TX16n T25 W28 HIGH B1 VREF0B1 IO DIFFIO_RX15p W28 W30 HIGH B1 VREF0B1 IO DIFFIO_RX15n W27 W29 HIGH B1 VREF0B1 IO DIFFIO_TX15p T7 T7 U19 V24 HIGH B1 VREF0B1 IO DIFFIO_TX15n T6 T6 U20 V23 HIGH B1 VREF0B1 IO DIFFIO_RX14p T5 T5 W26 Y32 HIGH B1 VREF0B1 IO DIFFIO_RX14n T4 T4 W25 Y31 HIGH B1 VREF0B1 IO DIFFIO_TX14p U6 U6 U24 Y26 HIGH B1 VREF0B1 IO DIFFIO_TX14n U5 U5 U23 Y25 HIGH B1 VREF1B1 IO DIFFIO_RX13p U2 U2 Y28 Y30 HIGH B1 VREF1B1 IO DIFFIO_RX13n U1 U1 Y27 Y29 HIGH B1 VREF1B1 IO DIFFIO_TX13p U8 U8 U21 Y28 HIGH B1 VREF1B1 IO DIFFIO_TX13n U7 U7 U22 Y27 HIGH B1 VREF1B1 IO DIFFIO_RX12p U4 U4 Y26 AA31 HIGH B1 VREF1B1 IO DIFFIO_RX12n U3 U3 Y25 AA30 HIGH B1 VREF1B1 IO DIFFIO_TX12p U9 U9 V19 W23 HIGH B1 VREF1B1 IO DIFFIO_TX12n V8 V8 V20 W24 HIGH B1 VREF1B1 IO DIFFIO_RX11p AA28 AB31 HIGH B1 VREF1B1 IO DIFFIO_RX11n AA27 AB30 HIGH B1 VREF1B1 IO DIFFIO_TX11p V24 Y23 HIGH B1 VREF1B1 IO DIFFIO_TX11n V23 Y24 HIGH B1 VREF1B1 IO DIFFIO_RX10p/RUP1 V6 V6 AA25 AA28 HIGH B1 VREF1B1 IO DIFFIO_RX10n/RDN1 V5 V5 AA26 AA29 HIGH B1 VREF1B1 IO DIFFIO_TX10p V22 AA25 HIGH B1 VREF1B1 IO DIFFIO_TX10n V21 AA24 HIGH B1 VREF1B1 VREF1B1 V7 V7 W20 AA23 B1 VREF1B1 IO DIFFIO_RX9p AB28 AB32 HIGH B1 VREF1B1 IO DIFFIO_RX9n AB27 AC31 HIGH B1 VREF1B1 IO DIFFIO_TX9p W23 AA27 HIGH B1 VREF1B1 IO DIFFIO_TX9n W24 AA26 HIGH B1 VREF1B1 IO DIFFIO_RX8p V1 V1 AB26 AD32 HIGH B1 VREF1B1 IO DIFFIO_RX8n V2 V2 AB25 AD31 HIGH

VREF Bank Pin Name/Function Optional Function(s) Configuration

Function

VCCA_PLL1 M3 M3 P23 T25 GND GNDA_PLL1 N5 N5 P24 T26 VCCG_PLL1 M2 M2 P21 R22 GNDG_PLL1 N4 N4 P22 T22 VCCA_PLL2 P5 P5 R23 U25 GND GNDA_PLL2 P3 P3 R24 U26 VCCG_PLL2 P4 P4 R21 U24 GNDG_PLL2 P2 P2 R22 T24

B672 F672 F780 F1020 DQS for x16 DQS for x32

DIFFIO Speed (1)

Pin List

Pin Information For The Stratix™ EP1S25 Device, ver 3.6

Page 3 of 27

Bank Number

B1 VREF1B1 IO DIFFIO_TX8p W5 W5 W21 AB27 HIGH B1 VREF1B1 IO DIFFIO_TX8n W6 W6 W22 AB26 HIGH B1 VREF1B1 IO DIFFIO_RX7p V3 V3 AC28 AC29 HIGH B1 VREF1B1 IO DIFFIO_RX7n V4 V4 AC27 AC30 HIGH B1 VREF1B1 IO DIFFIO_TX7p W7 W7 Y21 AC25 HIGH B1 VREF1B1 IO DIFFIO_TX7n W8 W8 Y22 AC26 HIGH B1 VREF2B1 IO DIFFIO_RX6p W1 W1 AD28 AD30 HIGH B1 VREF2B1 IO DIFFIO_RX6n W2 W2 AD27 AD29 HIGH B1 VREF2B1 IO DIFFIO_TX6p Y24 AC27 HIGH B1 VREF2B1 IO DIFFIO_TX6n Y23 AC28 HIGH B1 VREF2B1 IO DIFFIO_RX5p AE28 AE32 HIGH B1 VREF2B1 IO DIFFIO_RX5n AE27 AE31 HIGH B1 VREF2B1 IO DIFFIO_TX5p Y3 Y3 AA23 AD28 HIGH B1 VREF2B1 IO DIFFIO_TX5n Y4 Y4 AA24 AD27 HIGH B1 VREF2B1 IO DIFFIO_RX4p W3 W3 AF28 AE30 HIGH B1 VREF2B1 IO DIFFIO_RX4n W4 W4 AF27 AE29 HIGH B1 VREF2B1 IO DIFFIO_TX4p Y6 Y6 AA21 AD26 HIGH B1 VREF2B1 IO DIFFIO_TX4n Y5 Y5 AA22 AD25 HIGH B1 VREF2B1 IO DIFFIO_RX3p Y2 Y2 AF32 HIGH B1 VREF2B1 IO DIFFIO_RX3n Y1 Y1 AF31 HIGH B1 VREF2B1 IO DIFFIO_TX3p AA6 AA6 AB23 AE28 HIGH B1 VREF2B1 IO DIFFIO_TX3n AA5 AA5 AB24 AE27 HIGH B1 VREF2B1 VREF2B1 Y7 Y7 AE26 AB25 B1 VREF2B1 IO DIFFIO_RX2p AA2 AA2 AF30 HIGH B1 VREF2B1 IO DIFFIO_RX2n AA1 AA1 AF29 HIGH B1 VREF2B1 IO DIFFIO_TX2p AA4 AA4 AE25 HIGH B1 VREF2B1 IO DIFFIO_TX2n AA3 AA3 AE26 HIGH B1 VREF2B1 IO DIFFIO_RX1p AB2 AB2 AG31 HIGH B1 VREF2B1 IO DIFFIO_RX1n AB1 AB1 AG32 HIGH B1 VREF2B1 IO DIFFIO_TX1p AB4 AB4 AF27 HIGH B1 VREF2B1 IO DIFFIO_TX1n AB3 AB3 AF28 HIGH B1 VREF2B1 IO DIFFIO_RX0p AC2 AC2 AG30 HIGH B1 VREF2B1 IO DIFFIO_RX0n AD1 AD1 AG29 HIGH B1 VREF2B1 IO DIFFIO_TX0p AC4 AC4 AF26 HIGH B1 VREF2B1 IO DIFFIO_TX0n AC3 AC3 AF25 HIGH B8 VREF0B8 IO AC24 AB24 B8 VREF0B8 IO DQ9B7 AD5 AD5 AG26 AH28 DQ3B15 DQ1B31 B8 VREF0B8 IO AC5 AC5 AC23 AC24 B8 VREF0B8 IO DQ9B6 AD2 AD2 AH26 AK30 DQ3B14 DQ1B30 B8 VREF0B8 IO DQ9B5 AE2 AE2 AG25 AJ28 DQ3B13 DQ1B29 B8 VREF0B8 IO DQ9B4 AD3 AD3 AH25 AJ29 DQ3B12 DQ1B28 B8 VREF0B8 IO AB22 AC23 B8 VREF0B8 IO DQ9B3 AE4 AE4 AF25 AK29 DQ3B11 DQ1B27 B8 VREF0B8 IO AD24 B8 VREF0B8 IO DQS9B AD4 AD4 AF24 AK28 B8 VREF0B8 IO DQ9B2 AE3 AE3 AG24 AL30 DQ3B10 DQ1B26 B8 VREF0B8 IO AE25 AD23 B8 VREF0B8 IO DQ9B1 AB5 AB5 AE24 AL29 DQ3B9 DQ1B25 B8 VREF0B8 IO AE24 B8 VREF0B8 IO DQ9B0 AF3 AF3 AH24 AM29 DQ3B8 DQ1B24 B8 VREF0B8 IO AB6 AB6 AD24 AE23 B8 VREF0B8 IO AC6 AC6 AF24 B8 VREF0B8 IO DQ8B7 AC7 AC7 AG23 AH26 DQ3B7 DQ1B23 B8 VREF0B8 VREF0B8 AE5 AE5 AD22 AH27 B8 VREF0B8 IO DQ8B6 AD6 AD6 AD23 AJ27 DQ3B6 DQ1B22 B8 VREF0B8 IO DQ8B5 AE7 AE7 AF23 AL28 DQ3B5 DQ1B21 B8 VREF0B8 IO AF5 AF5 AB21 AC22 B8 VREF0B8 IO DQ8B4 AB7 AB7 AH23 AK27 DQ3B4 DQ1B20 B8 VREF0B8 IO DQ8B3 AD7 AD7 AE22 AJ26 DQ3B3 DQ1B19 B8 VREF0B8 IO AG24 B8 VREF0B8 IO DQS8B AE6 AE6 AE23 AL27 DQS3B B8 VREF0B8 IO DQ8B2 AA7 AA7 AF22 AM27 DQ3B2 DQ1B18 B8 VREF0B8 IO AB20 AB22 B8 VREF0B8 IO DQ8B1 AF7 AF7 AH22 AM28 DQ3B1 DQ1B17 B8 VREF0B8 IO DQ8B0 AF6 AF6 AG22 AK26 DQ3B0 DQ1B16 B8 VREF0B8 IO AF23 B8 VREF1B8 IO Y20 AA21 B8 VREF1B8 IO DQ7B7 AC8 AC8 AD21 AH24 DQ2B15 DQ1B15 B8 VREF1B8 IO AB21 B8 VREF1B8 IO DQ7B6 AB8 AB8 AE21 AJ24 DQ2B14 DQ1B14 B8 VREF1B8 IO DQ7B5 AD8 AD8 AG21 AJ25 DQ2B13 DQ1B13 B8 VREF1B8 IO AC22 AD22

VREF Bank Pin Name/Function Optional Function(s) Configuration

Function

B672 F672 F780 F1020 DQS for x16 DQS for x32

DIFFIO Speed (1)

Pin List

Pin Information For The Stratix™ EP1S25 Device, ver 3.6

Page 4 of 27

Bank Number

B8 VREF1B8 IO DQ7B4 AE8 AE8 AF21 AK25 DQ2B12 DQ1B12 B8 VREF1B8 IO DQ7B3 AF8 AF8 AE20 AL25 DQ2B11 DQ1B11 B8 VREF1B8 IO AC21 B8 VREF1B8 IO DQS7B Y9 Y9 AG20 AL26 DQS1B B8 VREF1B8 IO DQ7B2 Y8 Y8 AF20 AK24 DQ2B10 DQ1B10 B8 VREF1B8 IO AC20 AG23 B8 VREF1B8 IO DQ7B1 W9 W9 AH21 AM25 DQ2B9 DQ1B9 B8 VREF1B8 IO AD21 B8 VREF1B8 IO DQ7B0 AA8 AA8 AH20 AM26 DQ2B8 DQ1B8 B8 VREF1B8 IO DQ6B7 AC9 AC9 AE19 AJ23 DQ2B7 DQ1B7 B8 VREF1B8 IO FCLK3 AD9 AD9 AC21 AE21 B8 VREF1B8 IO FCLK2 AB9 AB9 AC19 AF21 B8 VREF1B8 VREF1B8 AE9 AE9 AD20 AH25 B8 VREF1B8 IO DQ6B6 AF9 AF9 AD19 AL24 DQ2B6 DQ1B6 B8 VREF1B8 IO DQ6B5 AD10 AD10 AF19 AH22 DQ2B5 DQ1B5 B8 VREF1B8 IO AF22 B8 VREF1B8 IO DQ6B4 AE10 AE10 AG19 AM24 DQ2B4 DQ1B4 B8 VREF1B8 IO PGM2 AA9 AA9 AB19 AA20 B8 VREF1B8 IO DQ6B3 AC10 AC10 AH19 AK23 DQ2B3 DQ1B3 B8 VREF1B8 IO AB20 B8 VREF1B8 IO DQS6B Y10 Y10 AF18 AJ22 DQS2B B8 VREF1B8 IO DQ6B2 AA10 AA10 AD18 AL23 DQ2B2 DQ1B2 B8 VREF1B8 IO CRC_ERROR W10 W10 AA20 AF20 B8 VREF1B8 IO DQ6B1 AB10 AB10 AE18 AK22 DQ2B1 DQ1B1 B8 VREF1B8 IO DQ6B0 AF10 AF10 AG18 AL22 DQ2B0 DQ1B0 B8 VREF1B8 IO RDN8 AB11 AB11 Y19 AC20 B8 VREF1B8 IO RUP8 AE11 AE11 W19 AH19 B8 VREF1B8 IO DQ5B7 AF17 AM22 B8 VREF1B8 IO AG22 B8 VREF1B8 IO DQ5B6 AG17 AJ21 B8 VREF1B8 IO DQ5B5 AE17 AK21 B8 VREF2B8 IO AB19 B8 VREF2B8 IO DQ5B4 AD17 AL21 B8 VREF2B8 IO RDYnBSY AC11 AC11 AA19 AA19 B8 VREF2B8 IO DQ5B3 AG16 AH20 B8 VREF2B8 IO AB18 AD20 B8 VREF2B8 IO DQS5B AH16 AJ20 B8 VREF2B8 IO DQ5B2 AD16 AK20 B8 VREF2B8 IO nCS Y11 Y11 Y18 AC19 B8 VREF2B8 IO DQ5B1 AF16 AL20 B8 VREF2B8 IO DQ5B0 AE16 AM20 B8 VREF2B8 IO AD11 AD11 AG21 B8 VREF2B8 IO AG20 B8 VREF2B8 IO V18 AE20 B8 VREF2B8 IO W18 AD19 B8 VREF2B8 IO CS AA11 AA11 AA18 AG19 B8 VREF2B8 IO AJ18 B8 VREF2B8 IO AH18 B8 VREF2B8 IO AK18 B8 VREF2B8 VREF2B8 W11 W11 AH18 AH23 B8 VREF2B8 IO CLK5n AD12 AD12 Y17 AJ19 B8 VREF2B8 CLK5p AC12 AC12 AA17 AK19 B8 VREF2B8 IO CLK4n AF12 AF12 AB17 AL19 B8 VREF2B8 CLK4p AE12 AE12 AC17 AM19 B8 VREF2B8 PLL_ENA PLL_ENA W12 W12 AC18 AF19 B8 VREF2B8 MSEL0 MSEL0 Y12 Y12 AC16 AG18 B8 VREF2B8 MSEL1 MSEL1 Y13 Y13 W17 AE18 B8 VREF2B8 MSEL2 MSEL2 W13 W13 AB15 AE19 B12 VREF2B8 IO PLL6_OUT3n Y16 AM18 B12 VREF2B8 IO PLL6_OUT3p W16 AL18 B12 VREF2B8 IO PLL6_OUT2n AG15 AK17 B12 VREF2B8 IO PLL6_OUT2p AF15 AJ17 B11 VREF2B8 IO PLL6_FBn AB12 AB12 AA15 AM17 B11 VREF2B8 IO PLL6_FBp AA12 AA12 AA14 AL17 B11 VREF2B8 IO PLL6_OUT1n AB14 AB14 W15 AK16 B11 VREF2B8 IO PLL6_OUT1p AA14 AA14 W14 AJ16 B11 VREF2B8 IO PLL6_OUT0n AB13 AB13 AE15 AM16 B11 VREF2B8 IO PLL6_OUT0p AA13 AA13 AD15 AL16 B12 VCC_PLL6_OUTB AB16 AB17 B11 VCC_PLL6_OUTA AC14 AE17 B11 VCC_PLL6_OUTA AE13 AE13

VREF Bank Pin Name/Function Optional Function(s) Configuration

Function

VCCA_PLL6 AD14 AD14 AG14 AG17

B672 F672 F780 F1020 DQS for x16 DQS for x32

DIFFIO Speed (1)

Pin List

Pin Information For The Stratix™ EP1S25 Device, ver 3.6

Page 5 of 27

Bank Number

B7 VREF0B7 CLK7p AE15 AE15 W13 AM15 B7 VREF0B7 IO CLK7n Y13 AL15 B7 VREF0B7 CLK6p AF15 AF15 AD14 AK15 B7 VREF0B7 IO CLK6n AE14 AJ15 B7 VREF0B7 nCE nCE Y14 Y14 AB13 AF18 B7 VREF0B7 nCEO nCEO W14 W14 AC13 AH15 B7 VREF0B7 IO AA18 B7 VREF0B7 IO AB15 B7 VREF0B7 IO PGM0 W15 W15 W12 AD18 B7 VREF0B7 nIO_PULLUP nIO_PULLUP AA15 AA15 Y12 AF15 B7 VREF0B7 VCCSEL VCCSEL Y15 Y15 AA12 AJ14 B7 VREF0B7 PORSEL PORSEL W16 W16 AC12 AG15 B7 VREF0B7 IO AA15 B7 VREF0B7 IO AD15 B7 VREF0B7 IO AC15 B7 VREF0B7 IO AK14 B7 VREF0B7 IO AC18 B7 VREF0B7 IO AL14 B7 VREF0B7 VREF0B7 AB15 AB15 AD11 AH12 B7 VREF0B7 IO INIT_DONE AC15 AC15 W11 AE15 B7 VREF0B7 IO V11 AB14 B7 VREF0B7 IO DQ4B7 AD13 AL13 B7 VREF0B7 IO DQ4B6 AE13 AM13 B7 VREF0B7 IO nRS Y16 Y16 AC11 AB18 B7 VREF0B7 IO DQ4B5 AF13 AH13 B7 VREF0B7 IO Y11 AA14 B7 VREF0B7 IO DQ4B4 AD12 AJ13 B7 VREF0B7 IO DQ4B3 AG13 AK13 B7 VREF0B7 IO RUnLU AD15 AD15 W10 AF14 B7 VREF0B7 IO DQS4B AH13 AJ12 B7 VREF0B7 IO AA16 AA16 AB12 AE14 B7 VREF1B7 IO DQ4B2 AE12 AK12 B7 VREF1B7 IO DQ4B1 AF12 AL12 B7 VREF1B7 IO PGM1 AC16 AC16 AA11 AG14 B7 VREF1B7 IO DQ4B0 AG12 AM11 B7 VREF1B7 IO RDN7 AB16 AB16 AC10 AC14 B7 VREF1B7 IO RUP7 AD16 AD16 AB11 AF13 B7 VREF1B7 IO DQ3B7 W17 W17 AG11 AL10 DQ1B15 DQ0B31 B7 VREF1B7 IO AD14 B7 VREF1B7 IO DQ3B6 AE16 AE16 AH11 AK11 DQ1B14 DQ0B30 B7 VREF1B7 IO DQ3B5 Y17 Y17 AE11 AL11 DQ1B13 DQ0B29 B7 VREF1B7 IO DEV_CLRn AF17 AF17 AC9 AH14 B7 VREF1B7 IO DQ3B4 AA17 AA17 AF11 AK10 DQ1B12 DQ0B28 B7 VREF1B7 IO DQ3B3 Y18 Y18 AE10 AM9 DQ1B11 DQ0B27 B7 VREF1B7 IO AB13 B7 VREF1B7 IO DQS3B AE17 AE17 AG10 AJ11 DQS1B B7 VREF1B7 IO Y10 AG13 B7 VREF1B7 IO DQ3B2 W18 W18 AH10 AL9 DQ1B10 DQ0B26 B7 VREF1B7 IO DQ3B1 AB17 AB17 AF10 AJ10 DQ1B9 DQ0B25 B7 VREF1B7 VREF1B7 AB18 AB18 AD9 AH10 B7 VREF1B7 IO DQ3B0 AA18 AA18 AD10 AH11 DQ1B8 DQ0B24 B7 VREF1B7 IO Y19 Y19 AC13 B7 VREF1B7 IO AA10 AE13 B7 VREF1B7 IO DQ2B7 AF18 AF18 AG9 AL8 DQ1B7 DQ0B23 B7 VREF1B7 IO FCLK5 AC17 AC17 AC8 AM14 B7 VREF1B7 IO FCLK4 AD17 AD17 AB10 AF12 B7 VREF1B7 IO DQ2B6 AE18 AE18 AF9 AJ9 DQ1B6 DQ0B22 B7 VREF1B7 IO DQ2B5 AF19 AF19 AE9 AK9 DQ1B5 DQ0B21 B7 VREF1B7 IO AB9 AD13 B7 VREF1B7 IO DQ2B4 Y20 Y20 AH8 AM8 DQ1B4 DQ0B20 B7 VREF1B7 IO DQ2B3 AA19 AA19 AH9 AH9 DQ1B3 DQ0B19 B7 VREF1B7 IO AD18 AD18 AG12 B7 VREF2B7 IO DQS2B AB19 AB19 AE8 AK8 DQS0B B7 VREF2B7 IO DQ2B2 AD19 AD19 AD8 AM7 DQ1B2 DQ0B18 B7 VREF2B7 IO AC18 AC18 AA9 AE12 B7 VREF2B7 IO DQ2B1 AC19 AC19 AF8 AJ8 DQ1B1 DQ0B17 B7 VREF2B7 IO DQ2B0 AE19 AE19 AG8 AL7 DQ1B0 DQ0B16 B7 VREF2B7 IO AC12

VREF Bank Pin Name/Function Optional Function(s) Configuration

Function

GND GNDA_PLL6 AC14 AC14 AF14 AH17 VCCG_PLL6 AD13 AD13 AA13 AD16 GNDG_PLL6 AE14 AE14 AB14 AB16

B672 F672 F780 F1020 DQS for x16 DQS for x32

DIFFIO Speed (1)

Pin List

Pin Information For The Stratix™ EP1S25 Device, ver 3.6

Page 6 of 27

Bank Number

B7 VREF2B7 IO AF20 AF20 AB8 AA12 B7 VREF2B7 IO DQ1B7 AE20 AE20 AF6 AL6 DQ0B15 DQ0B15 B7 VREF2B7 IO DQ1B6 AA20 AA20 AG7 AM6 DQ0B14 DQ0B14 B7 VREF2B7 IO AC7 AD12 B7 VREF2B7 IO DQ1B5 AB20 AB20 AH7 AJ7 DQ0B13 DQ0B13 B7 VREF2B7 IO DQ1B4 AF21 AF21 AF7 AM5 DQ0B12 DQ0B12 B7 VREF2B7 IO AB11 B7 VREF2B7 IO DQ1B3 AC20 AC20 AD6 AK7 DQ0B11 DQ0B11 B7 VREF2B7 IO DQS1B AA21 AA21 AE7 AH7 DQS0B B7 VREF2B7 IO AB21 AB21 AD5 AE11 B7 VREF2B7 IO DQ1B2 AE21 AE21 AH6 AL5 DQ0B10 DQ0B10 B7 VREF2B7 IO DQ1B1 AD20 AD20 AG6 AK6 DQ0B9 DQ0B9 B7 VREF2B7 VREF2B7 AD21 AD21 AD7 AH8 B7 VREF2B7 IO DQ1B0 AC21 AC21 AE6 AJ6 DQ0B8 DQ0B8 B7 VREF2B7 IO Y9 AF10 B7 VREF2B7 IO AG10 B7 VREF2B7 IO DQ0B7 AE25 AE25 AF5 AL3 DQ0B7 DQ0B7 B7 VREF2B7 IO AE4 AG11 B7 VREF2B7 IO DQ0B6 AF22 AF22 AH5 AL4 DQ0B6 DQ0B6 B7 VREF2B7 IO AC6 AD9 B7 VREF2B7 IO DQ0B5 AF24 AF24 AF4 AM4 DQ0B5 DQ0B5 B7 VREF2B7 IO DQ0B4 AE22 AE22 AG4 AJ4 DQ0B4 DQ0B4 B7 VREF2B7 IO AD23 AD23 AG9 B7 VREF2B7 IO DQ0B3 AB22 AB22 AG5 AJ5 DQ0B3 DQ0B3 B7 VREF2B7 IO DQS0B AE23 AE23 AH3 AK5 B7 VREF2B7 IO AD24 AD24 AC5 AC9 B7 VREF2B7 IO DQ0B2 AC23 AC23 AG3 AH5 DQ0B2 DQ0B2 B7 VREF2B7 IO DQ0B1 AC22 AC22 AE5 AK3 DQ0B1 DQ0B1 B7 VREF2B7 IO AD22 AD22 AB7 AE9 B7 VREF2B7 IO DQ0B0 AE24 AE24 AH4 AK4 DQ0B0 DQ0B0 B7 VREF2B7 IO AF9 B6 VREF0B6 IO DIFFIO_TX77n AD25 AD25 AF8 HIGH B6 VREF0B6 IO DIFFIO_TX77p AC24 AC24 AF7 HIGH B6 VREF0B6 IO DIFFIO_RX77n AD26 AD26 AG4 HIGH B6 VREF0B6 IO DIFFIO_RX77p AC25 AC25 AG3 HIGH B6 VREF0B6 IO DIFFIO_TX76n AB24 AB24 AF5 HIGH B6 VREF0B6 IO DIFFIO_TX76p AB23 AB23 AF6 HIGH B6 VREF0B6 IO DIFFIO_RX76n AB26 AB26 AG1 HIGH B6 VREF0B6 IO DIFFIO_RX76p AB25 AB25 AG2 HIGH B6 VREF0B6 IO DIFFIO_TX75n AA24 AA24 AE7 HIGH B6 VREF0B6 IO DIFFIO_TX75p AA23 AA23 AE8 HIGH B6 VREF0B6 IO DIFFIO_RX75n AA26 AA26 AF4 HIGH B6 VREF0B6 IO DIFFIO_RX75p AA25 AA25 AF3 HIGH B6 VREF0B6 VREF0B6 Y21 Y21 AE3 AG6 B6 VREF0B6 IO DIFFIO_TX74n AA22 AA22 AB5 AD6 HIGH B6 VREF0B6 IO DIFFIO_TX74p Y22 Y22 AB6 AD5 HIGH B6 VREF0B6 IO DIFFIO_RX74n Y26 Y26 AF2 HIGH B6 VREF0B6 IO DIFFIO_RX74p Y25 Y25 AF1 HIGH B6 VREF0B6 IO DIFFIO_TX73n Y24 Y24 AA7 AE6 HIGH B6 VREF0B6 IO DIFFIO_TX73p Y23 Y23 AA8 AE5 HIGH B6 VREF0B6 IO DIFFIO_RX73n W23 W23 AF2 AE4 HIGH B6 VREF0B6 IO DIFFIO_RX73p W24 W24 AF1 AE3 HIGH B6 VREF0B6 IO DIFFIO_TX72n W21 W21 AA5 AD8 HIGH B6 VREF0B6 IO DIFFIO_TX72p W22 W22 AA6 AD7 HIGH B6 VREF0B6 IO DIFFIO_RX72n AE2 AE2 HIGH B6 VREF0B6 IO DIFFIO_RX72p AE1 AE1 HIGH B6 VREF0B6 IO DIFFIO_TX71n Y6 AC5 HIGH B6 VREF0B6 IO DIFFIO_TX71p Y5 AC6 HIGH B6 VREF0B6 IO DIFFIO_RX71n W25 W25 AD2 AC3 HIGH B6 VREF0B6 IO DIFFIO_RX71p W26 W26 AD1 AC4 HIGH B6 VREF1B6 IO DIFFIO_TX70n W19 W19 Y7 AC7 HIGH B6 VREF1B6 IO DIFFIO_TX70p W20 W20 Y8 AC8 HIGH B6 VREF1B6 IO DIFFIO_RX70n V23 V23 AC2 AD3 HIGH B6 VREF1B6 IO DIFFIO_RX70p V24 V24 AC1 AD4 HIGH B6 VREF1B6 IO DIFFIO_TX69n V21 V21 W7 AB7 HIGH B6 VREF1B6 IO DIFFIO_TX69p V22 V22 W8 AB6 HIGH B6 VREF1B6 IO DIFFIO_RX69n V25 V25 AB4 AD2 HIGH B6 VREF1B6 IO DIFFIO_RX69p V26 V26 AB3 AD1 HIGH B6 VREF1B6 IO DIFFIO_TX68n W5 AA6 HIGH B6 VREF1B6 IO DIFFIO_TX68p W6 AA7 HIGH B6 VREF1B6 IO DIFFIO_RX68n AB2 AC2 HIGH B6 VREF1B6 IO DIFFIO_RX68p AB1 AB1 HIGH

VREF Bank Pin Name/Function Optional Function(s) Configuration

Function

B672 F672 F780 F1020 DQS for x16 DQS for x32

DIFFIO Speed (1)

Pin List

Pin Information For The Stratix™ EP1S25 Device, ver 3.6

Page 7 of 27

Bank Number

B6 VREF1B6 VREF1B6 V20 V20 W9 AB8 B6 VREF1B6 IO DIFFIO_TX67n V8 AA9 HIGH B6 VREF1B6 IO DIFFIO_TX67p V7 AA8 HIGH B6 VREF1B6 IO DIFFIO_RX67n/RDN6 U24 U24 AA3 AA4 HIGH B6 VREF1B6 IO DIFFIO_RX67p/RUP6 U23 U23 AA4 AA5 HIGH B6 VREF1B6 IO DIFFIO_TX66n V6 Y5 HIGH B6 VREF1B6 IO DIFFIO_TX66p V5 Y6 HIGH B6 VREF1B6 IO DIFFIO_RX66n AA2 AB3 HIGH B6 VREF1B6 IO DIFFIO_RX66p AA1 AB2 HIGH B6 VREF1B6 IO DIFFIO_TX65n V19 V19 V9 Y7 HIGH B6 VREF1B6 IO DIFFIO_TX65p U20 U20 V10 Y8 HIGH B6 VREF1B6 IO DIFFIO_RX65n U26 U26 Y4 AA3 HIGH B6 VREF1B6 IO DIFFIO_RX65p U25 U25 Y3 AA2 HIGH B6 VREF1B6 IO DIFFIO_TX64n U19 U19 U7 W5 HIGH B6 VREF1B6 IO DIFFIO_TX64p U18 U18 U8 W6 HIGH B6 VREF1B6 IO DIFFIO_RX64n U22 U22 Y2 Y4 HIGH B6 VREF1B6 IO DIFFIO_RX64p U21 U21 Y1 Y3 HIGH B6 VREF2B6 IO DIFFIO_TX63n T21 T21 U6 Y10 HIGH B6 VREF2B6 IO DIFFIO_TX63p T20 T20 U5 Y9 HIGH B6 VREF2B6 IO DIFFIO_RX63n T25 T25 W4 Y2 HIGH B6 VREF2B6 IO DIFFIO_RX63p T24 T24 W3 Y1 HIGH B6 VREF2B6 IO DIFFIO_TX62n T19 T19 U9 W10 HIGH B6 VREF2B6 IO DIFFIO_TX62p R19 R19 U10 W9 HIGH B6 VREF2B6 IO DIFFIO_RX62n W2 W4 HIGH B6 VREF2B6 IO DIFFIO_RX62p W1 W3 HIGH B6 VREF2B6 IO DIFFIO_TX61n T6 V9 HIGH B6 VREF2B6 IO DIFFIO_TX61p T5 V10 HIGH B6 VREF2B6 IO DIFFIO_RX61n T23 T23 V4 W2 HIGH B6 VREF2B6 IO DIFFIO_RX61p T22 T22 V3 W1 HIGH B6 VREF2B6 VREF2B6 R18 R18 R10 AA10 B6 VREF2B6 IO DIFFIO_TX60n T10 V5 HIGH B6 VREF2B6 IO DIFFIO_TX60p T9 V6 HIGH B6 VREF2B6 IO DIFFIO_RX60n R22 R22 V1 V4 HIGH B6 VREF2B6 IO DIFFIO_RX60p R23 R23 V2 V3 HIGH B6 VREF2B6 IO DIFFIO_TX59n P20 P20 T7 V8 HIGH B6 VREF2B6 IO DIFFIO_TX59p P21 P21 T8 V7 HIGH B6 VREF2B6 IO DIFFIO_RX59n R20 R20 U4 V2 HIGH B6 VREF2B6 IO DIFFIO_RX59p R21 R21 U3 V1 HIGH B6 VREF2B6 IO DIFFIO_TX58n P19 P19 T4 W8 HIGH B6 VREF2B6 IO DIFFIO_TX58p N19 N19 T3 W7 HIGH B6 VREF2B6 IO DIFFIO_RX58n U2 U5 HIGH B6 VREF2B6 IO DIFFIO_RX58p T1 U6 HIGH B6 VREF2B6 IO CLK8n R3 U3 B6 VREF2B6 CLK8p P24 P24 R4 U4 B6 VREF2B6 CLK9n P25 P25 T2 U1 B6 VREF2B6 CLK9p R26 R26 R2 U2

B5 VREF0B5 CLK10p M26 M26 P4 T6 B5 VREF0B5 IO CLK10n P3 T5 B5 VREF0B5 CLK11p M24 M24 P2 T4 B5 VREF0B5 CLK11n M25 M25 N2 T3 B5 VREF0B5 IO DIFFIO_TX57n N20 N20 N10 R7 HIGH B5 VREF0B5 IO DIFFIO_TX57p N21 N21 N9 R8 HIGH B5 VREF0B5 IO DIFFIO_RX57n M2 T2 HIGH B5 VREF0B5 IO DIFFIO_RX57p N1 T1 HIGH B5 VREF0B5 IO DIFFIO_TX56n M18 M18 N5 P7 HIGH B5 VREF0B5 IO DIFFIO_TX56p M19 M19 N6 P8 HIGH B5 VREF0B5 IO DIFFIO_RX56n M20 M20 M3 R1 HIGH B5 VREF0B5 IO DIFFIO_RX56p M21 M21 M4 R2 HIGH B5 VREF0B5 IO DIFFIO_TX55n N7 R5 HIGH B5 VREF0B5 IO DIFFIO_TX55p N8 R6 HIGH B5 VREF0B5 IO DIFFIO_RX55n M22 M22 L1 R3 HIGH B5 VREF0B5 IO DIFFIO_RX55p M23 M23 L2 R4 HIGH

VREF Bank Pin Name/Function Optional Function(s) Configuration

Function

GNDG_PLL3 R25 R25 R7 U11 VCCG_PLL3 P23 P23 R8 V11 GNDA_PLL3 R24 R24 R5 U7 GND VCCA_PLL3 P22 P22 R6 U8 GNDG_PLL4 N22 N22 P7 U9 VCCG_PLL4 N24 N24 P8 T9 GNDA_PLL4 N23 N23 P5 T7 GND VCCA_PLL4 N25 N25 P6 T8

B672 F672 F780 F1020 DQS for x16 DQS for x32

DIFFIO Speed (1)

Pin List

Pin Information For The Stratix™ EP1S25 Device, ver 3.6

Page 8 of 27

Bank Number

B5 VREF0B5 IO DIFFIO_TX54n N4 R10 HIGH B5 VREF0B5 IO DIFFIO_TX54p N3 R9 HIGH B5 VREF0B5 IO DIFFIO_RX54n L22 L22 L3 P1 HIGH B5 VREF0B5 IO DIFFIO_RX54p L23 L23 L4 P2 HIGH B5 VREF0B5 VREF0B5 L19 L19 P10 R12 B5 VREF0B5 IO DIFFIO_TX53n L21 L21 M10 P6 HIGH B5 VREF0B5 IO DIFFIO_TX53p L20 L20 M9 P5 HIGH B5 VREF0B5 IO DIFFIO_RX53n K1 P3 HIGH B5 VREF0B5 IO DIFFIO_RX53p K2 P4 HIGH B5 VREF0B5 IO DIFFIO_TX52n K20 K20 M6 N7 HIGH B5 VREF0B5 IO DIFFIO_TX52p K19 K19 M5 N8 HIGH B5 VREF0B5 IO DIFFIO_RX52n L25 L25 K4 N1 HIGH B5 VREF0B5 IO DIFFIO_RX52p L24 L24 K3 N2 HIGH B5 VREF0B5 IO DIFFIO_TX51n K22 K22 M8 P9 HIGH B5 VREF0B5 IO DIFFIO_TX51p K21 K21 M7 P10 HIGH B5 VREF0B5 IO DIFFIO_RX51n K24 K24 J1 N3 HIGH B5 VREF0B5 IO DIFFIO_RX51p K23 K23 J2 N4 HIGH B5 VREF0B5 IO DIFFIO_TX50n J20 J20 L10 N5 HIGH B5 VREF0B5 IO DIFFIO_TX50p J19 J19 L9 N6 HIGH B5 VREF0B5 IO DIFFIO_RX50n K26 K26 J3 M2 HIGH B5 VREF0B5 IO DIFFIO_RX50p K25 K25 J4 M3 HIGH B5 VREF0B5 IO DIFFIO_TX49n L5 N10 HIGH B5 VREF0B5 IO DIFFIO_TX49p L6 N9 HIGH B5 VREF0B5 IO DIFFIO_RX49n H1 L2 HIGH B5 VREF0B5 IO DIFFIO_RX49p H2 L3 HIGH B5 VREF1B5 IO DIFFIO_TX48n L8 M8 HIGH B5 VREF1B5 IO DIFFIO_TX48p L7 M9 HIGH B5 VREF1B5 IO DIFFIO_RX48n/RDN5 J22 J22 H3 M4 HIGH B5 VREF1B5 IO DIFFIO_RX48p/RUP5 J21 J21 H4 M5 HIGH B5 VREF1B5 IO DIFFIO_TX47n H20 H20 K7 M6 HIGH B5 VREF1B5 IO DIFFIO_TX47p H19 H19 K8 M7 HIGH B5 VREF1B5 IO DIFFIO_RX47n J26 J26 G1 L1 HIGH B5 VREF1B5 IO DIFFIO_RX47p J25 J25 G2 K2 HIGH B5 VREF1B5 IO DIFFIO_TX46n J7 L6 HIGH B5 VREF1B5 IO DIFFIO_TX46p J8 L7 HIGH B5 VREF1B5 IO DIFFIO_RX46n J24 J24 G4 J2 HIGH B5 VREF1B5 IO DIFFIO_RX46p J23 J23 G3 J1 HIGH B5 VREF1B5 IO DIFFIO_TX45n H22 H22 K5 K5 HIGH B5 VREF1B5 IO DIFFIO_TX45p H21 H21 K6 K6 HIGH B5 VREF1B5 IO DIFFIO_RX45n F1 K4 HIGH B5 VREF1B5 IO DIFFIO_RX45p F2 K3 HIGH B5 VREF1B5 IO DIFFIO_TX44n H24 H24 J6 K8 HIGH B5 VREF1B5 IO DIFFIO_TX44p H23 H23 J5 K7 HIGH B5 VREF1B5 IO DIFFIO_RX44n F3 J3 HIGH B5 VREF1B5 IO DIFFIO_RX44p F4 J4 HIGH B5 VREF1B5 VREF1B5 J18 J18 K9 L8 B5 VREF1B5 IO DIFFIO_TX43n G21 G21 H8 J5 HIGH B5 VREF1B5 IO DIFFIO_TX43p G22 G22 H7 J6 HIGH B5 VREF1B5 IO DIFFIO_RX43n H25 H25 E1 H1 HIGH B5 VREF1B5 IO DIFFIO_RX43p H26 H26 E2 H2 HIGH B5 VREF1B5 IO DIFFIO_TX42n G23 G23 H6 J7 HIGH B5 VREF1B5 IO DIFFIO_TX42p G24 G24 H5 J8 HIGH B5 VREF1B5 IO DIFFIO_RX42n G25 G25 D1 G1 HIGH B5 VREF1B5 IO DIFFIO_RX42p G26 G26 D2 G2 HIGH B5 VREF1B5 IO DIFFIO_TX41n F23 F23 G5 H5 HIGH B5 VREF1B5 IO DIFFIO_TX41p F24 F24 G6 H6 HIGH B5 VREF1B5 IO DIFFIO_RX41n F25 F25 C1 H3 HIGH B5 VREF1B5 IO DIFFIO_RX41p F26 F26 C2 H4 HIGH B5 VREF1B5 IO DIFFIO_TX40n E23 E23 F6 H8 HIGH B5 VREF1B5 IO DIFFIO_TX40p E24 E24 F5 H7 HIGH B5 VREF1B5 IO DIFFIO_RX40n E25 E25 F1 HIGH B5 VREF1B5 IO DIFFIO_RX40p E26 E26 F2 HIGH B5 VREF1B5 IO DIFFIO_TX39n D24 D24 G6 HIGH B5 VREF1B5 IO DIFFIO_TX39p C25 C25 G5 HIGH B5 VREF1B5 IO DIFFIO_RX39n D25 D25 G3 HIGH B5 VREF1B5 IO DIFFIO_RX39p C26 C26 G4 HIGH B4 VREF0B4 IO F7 B4 VREF0B4 IO DQ0T0 B24 B24 A4 D5 DQ0T0 DQ0T0 B4 VREF0B4 IO B25 B25 G7 K9 B4 VREF0B4 IO DQ0T1 D23 D23 A3 C3 DQ0T1 DQ0T1 B4 VREF0B4 IO DQ0T2 D22 D22 B3 E5 DQ0T2 DQ0T2 B4 VREF0B4 IO DQS0T C24 C24 D5 C5

VREF Bank Pin Name/Function Optional Function(s) Configuration

Function

B672 F672 F780 F1020 DQS for x16 DQS for x32

DIFFIO Speed (1)

Pin List

Pin Information For The Stratix™ EP1S25 Device, ver 3.6

Page 9 of 27

Bank Number

B4 VREF0B4 IO B23 B23 F7 F8 B4 VREF0B4 IO DQ0T3 E22 E22 B5 C4 DQ0T3 DQ0T3 B4 VREF0B4 IO C23 C23 J9 B4 VREF0B4 IO DQ0T4 B22 B22 B4 D4 DQ0T4 DQ0T4 B4 VREF0B4 IO DQ0T5 A24 A24 C4 A4 DQ0T5 DQ0T5 B4 VREF0B4 IO G8 M10 B4 VREF0B4 IO DQ0T6 A22 A22 A5 B4 DQ0T6 DQ0T6 B4 VREF0B4 IO F8 G9 B4 VREF0B4 IO DQ0T7 C22 C22 C5 B3 DQ0T7 DQ0T7 B4 VREF0B4 IO H9 B4 VREF0B4 IO J9 L9 B4 VREF0B4 IO DQ1T0 C20 C20 E6 D6 DQ0T8 DQ0T8 B4 VREF0B4 VREF0B4 F22 F22 E7 E6 B4 VREF0B4 IO DQ1T1 D21 D21 A6 C6 DQ0T9 DQ0T9 B4 VREF0B4 IO DQ1T2 D20 D20 B7 B5 DQ0T10 DQ0T10 B4 VREF0B4 IO B21 B21 K11 B4 VREF0B4 IO DQS1T A21 A21 B6 E7 DQS0T B4 VREF0B4 IO H9 L11 B4 VREF0B4 IO DQ1T3 C21 C21 D6 C7 DQ0T11 DQ0T11 B4 VREF0B4 IO DQ1T4 B20 B20 A7 A5 DQ0T12 DQ0T12 B4 VREF0B4 IO J11 B4 VREF0B4 IO DQ1T5 E21 E21 D7 D7 DQ0T13 DQ0T13 B4 VREF0B4 IO G9 F9 B4 VREF0B4 IO DQ1T6 A20 A20 C6 A6 DQ0T14 DQ0T14 B4 VREF0B4 IO DQ1T7 F21 F21 C7 B6 DQ0T15 DQ0T15 B4 VREF0B4 IO C19 C19 F9 G10 B4 VREF0B4 IO F10 B4 VREF0B4 IO DQ2T0 D19 D19 D8 B7 DQ1T0 DQ0T16 B4 VREF0B4 IO DQ2T1 E20 E20 C8 D8 DQ1T1 DQ0T17 B4 VREF0B4 IO B19 B19 H10 L12 B4 VREF0B4 IO DQ2T2 E19 E19 E8 B8 DQ1T2 DQ0T18 B4 VREF1B4 IO DQS2T A19 A19 C9 A7 DQS0T B4 VREF1B4 IO H11 B4 VREF1B4 IO DQ2T3 C18 C18 D9 E9 DQ1T3 DQ0T19 B4 VREF1B4 IO DQ2T4 B18 B18 B9 A8 DQ1T4 DQ0T20 B4 VREF1B4 IO DQ2T5 D18 D18 B8 C9 DQ1T5 DQ0T21 B4 VREF1B4 IO DQ2T6 F20 F20 A8 C8 DQ1T6 DQ0T22 B4 VREF1B4 IO FCLK6 G19 G19 G10 G12 B4 VREF1B4 IO FCLK7 E18 E18 F10 A14 B4 VREF1B4 IO DQ2T7 G20 G20 A9 D9 DQ1T7 DQ0T23 B4 VREF1B4 IO J12 B4 VREF1B4 IO A18 A18 J10 K12 B4 VREF1B4 IO DQ3T0 F19 F19 E10 E11 DQ1T8 DQ0T24 B4 VREF1B4 VREF1B4 F18 F18 E9 E8 B4 VREF1B4 IO DQ3T1 C17 C17 A10 B9 DQ1T9 DQ0T25 B4 VREF1B4 IO F11 H12 B4 VREF1B4 IO DQ3T2 G18 G18 C10 D10 DQ1T10 DQ0T26 B4 VREF1B4 IO K10 K13 B4 VREF1B4 IO DQS3T B17 B17 D10 D11 DQS1T B4 VREF1B4 IO DQ3T3 E17 E17 B10 C10 DQ1T11 DQ0T27 B4 VREF1B4 IO F12 B4 VREF1B4 IO DQ3T4 F17 F17 A11 A9 DQ1T12 DQ0T28 B4 VREF1B4 IO DQ3T5 D17 D17 C11 B11 DQ1T13 DQ0T29 B4 VREF1B4 IO DEV_OE G17 G17 J11 L13 B4 VREF1B4 IO DQ3T6 A17 A17 D11 C11 DQ1T14 DQ0T30 B4 VREF1B4 IO DQ3T7 H18 H18 B11 B10 DQ1T15 DQ0T31 B4 VREF1B4 IO RUP4 D16 D16 H11 G13 B4 VREF1B4 IO RDN4 C16 C16 G11 J13 B4 VREF1B4 IO DQ4T0 B12 A11 B4 VREF1B4 IO nWS E16 E16 K11 D14 B4 VREF1B4 IO DQ4T1 C12 B12 B4 VREF1B4 IO DQ4T2 D12 C12 B4 VREF2B4 IO B16 B16 G12 F13 B4 VREF2B4 IO DQS4T A13 D12 B4 VREF2B4 IO DATA0 F16 F16 H12 E14 B4 VREF2B4 IO DQ4T3 B13 C13 B4 VREF2B4 IO DQ4T4 E12 D13 B4 VREF2B4 IO L11 L14 B4 VREF2B4 IO DQ4T5 C13 E13 B4 VREF2B4 IO DATA1 C15 C15 F12 F14 B4 VREF2B4 IO DQ4T6 D13 A13 B4 VREF2B4 IO DQ4T7 E13 B13

VREF Bank Pin Name/Function Optional Function(s) Configuration

Function

B672 F672 F780 F1020 DQS for x16 DQS for x32

DIFFIO Speed (1)

Pin List

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ALTERA Stratix EP1S25 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Pin List