Altera SerialLite III Streaming MegaCore Function User Manual

SerialLite III Streaming MegaCore

Function User Guide

Last updated for Altera Complete Design Suite: 15.0

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TOC-2

SerialLite III Streaming MegaCore Function Quick Reference.........................1-1

About the SerialLite III Streaming IP Core........................................................2-1

Getting Started ....................................................................................................3-1

SerialLite III Streaming Protocol...............................................................................................................2-1

SerialLite III Streaming Protocol Operating Modes................................................................... 2-2

Performance and Resource Utilization.....................................................................................................2-3

Installing and Licensing IP Cores..............................................................................................................3-1

OpenCore Plus IP Evaluation.................................................................................................................... 3-1

Specifying IP Core Parameters and Options............................................................................................3-2

SerialLite III Parameter Editor.......................................................................................................3-2

Arria 10 Designs...............................................................................................................................3-3

SerialLite III Streaming IP Core Parameters............................................................................................3-3

Transceiver Reconfiguration Controller for Stratix V and Arria V GZ Designs................................3-5

Files Generated for Altera IP Cores...........................................................................................................3-6

Files Generated for Altera IP Cores (Legacy Parameter Editor)...........................................................3-8

Simulating.....................................................................................................................................................3-9

Simulating Altera IP Cores in other EDA Tools..........................................................................3-9

Simulation Parameters..................................................................................................................3-10

Arria 10 Simulation Testbench....................................................................................................3-12

Simulating and Verifying the Design..........................................................................................3-13

SerialLite III Streaming IP Core Functional Description..................................4-1

Altera Corporation

IP Core Architecture....................................................................................................................................4-1

SerialLite III Streaming Source Core.............................................................................................4-3

SerialLite III Streaming Sink Core.................................................................................................4-6

SerialLite III Streaming Duplex Core............................................................................................4-9

Arria 10 versus Stratix V and Arria V GZ Variations.................................................................4-9

Clock Domains...........................................................................................................................................4-10

Core Clocking.................................................................................................................................4-11

Core Latency...................................................................................................................................4-14

Transmission Overheads and Lane Rate Calculations......................................................................... 4-15

Reset.............................................................................................................................................................4-16

Link-Up Sequence......................................................................................................................................4-16

CRC-32 Error Injection ........................................................................................................................... 4-17

FIFO ECC Protection ...............................................................................................................................4-17

User Data Interface Waveforms.............................................................................................................. 4-17

Signals..........................................................................................................................................................4-19

TOC-3

SerialLite III Streaming IP Core Design Guidelines..........................................5-1

SerialLite III Streaming IP Core Design Example for Stratix V Devices..............................................5-1

Design Example Components........................................................................................................5-3

Design Setup ....................................................................................................................................5-4

Design Example Compilation and Download............................................................................. 5-5

Design Example Operation.............................................................................................................5-6

SerialLite III Streaming Link Debugging..................................................................................................5-6

Source Core Link Debugging......................................................................................................... 5-7

Sink Core Link Debugging............................................................................................................. 5-9

Error Handling...........................................................................................................................................5-10

Additional Information...................................................................................... 6-1

Document Revision History ......................................................................................................................6-1

How to Contact Altera................................................................................................................................ 6-1

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SerialLite III Streaming MegaCore Function

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The Altera® SerialLite III Streaming MegaCore® IP function is a lightweight protocol suitable for high bandwidth streaming data in chip-to-chip, board-to-board, and backplane applications.

The SerialLite III Streaming IP core is part of the MegaCore IP Library, which is distributed with the Quartus® II software and is downloadable from the Altera website at www.altera.com.

Note:

For system requirements and installation instructions, refer to the Altera Software Installation and Licensing Manual.

Table 1-1: SerialLite III Streaming MegaCore Function

Item Description

Version 15.0

Release Date May 2015

Release Information

IP Catalog Name

Ordering

• Arria 10 SerialLite III Streaming (Arria 10 devices)

• SerialLite III Streaming (Stratix V and Arria V GZ devices)

IP-SLITE3/ST

Code

Quick Reference

Product ID 010A

Vendor ID 6AF7

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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1-2

SerialLite III Streaming MegaCore Function Quick Reference

Item Description

Core Features • Up to 17.4 Gbps lane data rates for Arria 10 devices.

• Supports 1–24 serial lanes in configurations that provide nominal bandwidths from 3.125 gigabits per second (Gbps) to over 300 Gbps.

• Avalon® Streaming (Avalon-ST) user interfaces on the transmit and receive datapaths.

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IP Core Information

Protocol Features

• Simplex and duplex operations

• Support for single or multiple lanes

• 64B/67B physical layer encoding

• Payload and idle scrambling

• Error detection

• Low overhead framing

• Low point-to-point transfer latency

Typical Application

• High resolution video

• Radar processing

• Medical imaging

• Baseband processing in wireless infrastructure

Device Family Support

Arria 10, Arria V GZ, and Stratix V FPGA devices. Refer to the What’s New in Altera IP page of the Altera website for

detailed information.

Design Tools • Parameter editor in the Quartus II software for IP design instantiation

and compilation

• TimeQuest timing analyzer in the Quartus II software for timing analysis

• ModelSim-Altera software, MATLAB, or third-party tool using NativeLink for design simulation or synthesis

Related Information

• Altera Software Installation and Licensing

• What's New in Altera IP

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SerialLite III Streaming MegaCore Function Quick Reference

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SerialLite III

Streaming

MegaCore

Function

SerialLite III

Streaming MegaCore

Function

FPGA FPGA

User

Logic

User

Logic

Serial Data

(Up to

24 Channels)

Transmission Media Support:

- PCB (Chip-to-Chip)

- Backplane (Board-to-Board)

Data Processing

Management Board

ADC

System Board

Control Board

Interface Board

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About the SerialLite III Streaming IP Core

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The SerialLite III Streaming IP core is a high-speed serial communication protocol for chip-to-chip, board-to-board, and backplane application data transfers. This protocol offers high bandwidth, low overhead frames, low I/O count, and supports scalability in both number of lanes and lane speed.

The SerialLite III Streaming IP core incorporates a physical coding sublayer (PCS), a physical media attachment (PMA), and a media access control (MAC) block. The IP core transmits and receives streaming data through the Avalon-ST interface on its FPGA fabric interface.

Figure 2-1: Typical System Application

SerialLite III Streaming Protocol

The SerialLite III Streaming IP core implements a protocol which supports the transfer of high bandwidth streaming data over a unidirectional or bidirectional, high-speed serial link.

The SerialLite III Streaming IP core has the following protocol features:

• Simplex and duplex operations

• Support for single or multiple lanes

• 64B/67B physical layer encoding

• Payload and idle scrambling

• Error detection

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SerialLite III Streaming Protocol Operating Modes

• Low protocol overhead

• Low point-to-point transfer latency

• Uses the hardened Native PHY IP core (Arria 10 devices) or Interlaken PHY IP core (Stratix V and Arria V GZ devices) to reduce soft logic resource utilization

SerialLite III Streaming Protocol Operating Modes

The protocol defines two operating modes for different applications: continuous and burst mode. This section defines these two operating modes, and describes the targeted application models and their key characteristics. The following table shows the key differences of the two operating modes.

Table 2-1: Continuous vs. Burst Mode Characteristics

Characteristics Continuous Mode Burst Mode

Buffering Minimal Burst size

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Can connect directly to a data converter (ADC,

Yes No

DAC) Asynchronous clock and data recovery support No Yes

The IP core that you generate can be in either mode. There is no parameter option to select between continuous and burst modes. The selection depends on how you provide data at the Avalon-ST TX interface.

Continuous Mode

A SerialLite III Streaming link operating in continuous mode accepts and transmits user data over the link, and presents it on the user interface at the receiving link at the same rate and without gaps in the stream. When operating in this mode, a link implementing the protocol looks like a data pipe that can transparently forward all data presented on the user interface to the far end of the link.

Continuous mode is appropriate for applications that require a simple interface to transmit a single, high bandwidth data stream. An example of this application is sensor data links for radar and wireless infrastructure. With this mode, data converters can connect to either end of the link with minimal interface logic. This mode requires both ends of the link to operate from a common transceiver reference clock.

Burst Mode

A SerialLite III Streaming link operating in burst mode accepts bursts of data across the user interface and transmits each burst across the link as a discrete data burst.

Burst mode is appropriate for applications where the data stream is divided into bursts of data. An example of this application is uncompressed digital video where the data stream is divided into lines of display raster. This mode provides more flexibility to the clocking and also supports multiplexing of multiple data streams across the link.

Note:

Altera Corporation

The minimum required gap between bursts is 2 user clock cycles in standard and advanced clocking modes on the transmit side. Therefore, the user must provide two extra user clock cycles between an end of burst and the start of the next burst.

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Related Information

Performance and Resource Utilization

• Standard Clocking Mode on page 4-12

• Advanced Clocking Mode on page 4-13

Performance and Resource Utilization

The following table lists the resources and expected performance for different SerialLite III Streaming IP core variations. These results are obtained using the Quartus II software targeting the Stratix V GX (5SGXMA7H2F35C2), the Arria V GZ (5AGZME7K2F40I3L), and the Arria 10 (10AX115S1F45I1SGES) FPGA device.

Note:

The numbers of ALMs and logic registers in the following table are rounded up to the nearest 100.

Table 2-2: SerialLite III Streaming IP Core FPGA Performance and Resource Utilization

2-3

Device Direction

Source Standard 24 17400 Disabled 1984 3937 259 48

Sink Standard 24 17400 Disabled 2930 7409 373 48

Arria 10

Duplex Standard 24 17400 Disabled 4226 10838 561 96

Clocking

Mode

Number of Lanes

Parameters Per-Lane

Data Rate

(Mbps)

ECC Primary Secondary

ALMs

Logic Registers

Standard 24 17400 Enabled 2818 5696 902 72 Advanced 24 17400 Disabled 2378 4009 219 87 Advanced 24 17400 Enabled 4003 8412 910 121

Standard 24 17400 Enabled 3673 9047 1052 72 Advanced 24 17400 Disabled 4060 7363 452 0 Advanced 24 17400 Enabled 3860 9084 1083 72

Standard 24 17400 Enabled 5775 14442 1726 144 Advanced 24 17400 Disabled 6032 10836 623 87 Advanced 24 17400 Enabled 7266 16808 1996 193

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Performance and Resource Utilization

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Device Direction

Source Standard 24 10312.50 Disabled 6257 4511 142 48

Stratix

Sink Standard 24 10312.50 Disabled 5159 7962 267 48

V GX and Arria V GZ

Duplex Standard 24 10312.50 Disabled 4680 11819 482 96

Clocking

Mode

Number of Lanes

Parameters Per-Lane

Data Rate

(Mbps)

ECC Primary Secondary

ALMs

Logic Registers

Standard 24 10312.50 Enabled 7191 6636 459 72 Advanced 24 10312.50 Disabled 6265 4482 196 87 Advanced 24 10312.50 Enabled 8038 9013 761 121

Standard 24 10312.50 Enabled 3779 9761 802 72 Advanced 24 10312.50 Disabled 6058 7995 258 0 Advanced 24 10312.50 Enabled 5891 9789 905 72

Standard 24 10312.50 Enabled 6419 15829 1249 144 Advanced 24 10312.50 Disabled 5582 11779 514 87 Advanced 24 10312.50 Enabled 7018 18393 1410 193

M20K

Related Information

Fitter Resources Reports

More information about Quartus II resource utilization reporting.

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acds

quartus - Contains the Quartus II software ip - Contains the Altera IP Library and third-party IP cores

altera - Contains the Altera IP Library source code

<IP core name> - Contains the IP core source files

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Installing and Licensing IP Cores

The Altera IP Library provides many useful IP core functions for your production use without purchasing an additional license. Some Altera MegaCore® IP functions require that you purchase a separate license for production use. However, the OpenCore® feature allows evaluation of any Altera® IP core in simulation and compilation in the Quartus® II software. After you are satisfied with functionality and perfformance, visit the Self Service Licensing Center to obtain a license number for any Altera product.

Figure 3-1: IP Core Installation Path

Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is

<home directory>/altera/ <version number>.

Related Information

• Altera Licensing Site

• Altera Software Installation and Licensing Manual

OpenCore Plus IP Evaluation

Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and hardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to take your design to production. OpenCore Plus supports the following evaluations:

• Simulate the behavior of a licensed IP core in your system.

• Verify the functionality, size, and speed of the IP core quickly and easily.

• Generate time-limited device programming files for designs that include IP cores.

• Program a device with your IP core and verify your design in hardware.

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Specifying IP Core Parameters and Options

OpenCore Plus evaluation supports the following two operation modes:

• Untethered—run the design containing the licensed IP for a limited time.

• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a connection between your board and the host computer.

Note: All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times

out.

Specifying IP Core Parameters and Options

Follow these steps to specify IP core parameters and options.

1. In the Qsys IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears.

2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in your project. If prompted, also specify the target Altera device family and output file HDL preference. Click OK.

3. Specify parameters and options for your IP variation:

• Optionally select preset parameter values. Presets specify all initial parameter values for specific

applications (where provided).

• Specify parameters defining the IP core functionality, port configurations, and device-specific

features.

• Specify options for generation of a timing netlist, simulation model, testbench, or example design

(where applicable).

• Specify options for processing the IP core files in other EDA tools.

4. Click Finish to generate synthesis and other optional files matching your IP variation specifications. The parameter editor generates the top-level .qsys IP variation file and HDL files for synthesis and simulation. Some IP cores also simultaneously generate a testbench or example design for hardware testing.

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The top-level IP variation is added to the current Quartus II project. Click Project > Add/Remove Files in Project to manually add a .qsys file to a project. Make appropriate pin assignments to connect ports.

SerialLite III Parameter Editor

Based on the values you set, the SerialLite III streaming parameter editor automatically calculates the rest of the parameters, and provides you with the following values or information:

• Input data rate per lane

• Transceiver data rate per lane

• A list of feasible transceiver reference clock frequencies, one of which you select to provide to the core

• Information related to the core overheads

Important:

Related Information

SerialLite III Streaming IP Core Parameters on page 3-3

Altera Corporation

If your design targets Stratix V or Arria V GZ devices, you cannot migrate your design to Arria 10 devices automatically. For Arria 10 devices, the transceiver reconfiguration functionality is embedded inside the transceivers. Therefore, you must re-instantiate the IP core to target Arria 10 devices.

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Arria 10 Designs

If your design targets Arria 10 devices:

• The parameter editor displays a message about the required output clock frequency of the external TX

• For source only Arria 10 implementations, the parameter editor does not provide the transceiver

• The SerialLite IP core expects the user to provide the transmitter's serial clock. If you compile the IP

• When generating the example testbench, the SerialLite IP core instantiates an external transceiver ATX

• To generate the SerialLite III Arria 10 example testbench using the parameter editor, select Generate >

Arria 10 Designs

3-3

PLL IP clock. For source or duplex modes, connect the Transceiver PHY Reset Controller to the TX PLL to ensure the appropriate HSSI power-up sequence.

reference clock frequency because the user is expected to provide the transmit serial clock. If you use an on-chip PLL to generate the transmit serial clock, you can use the same PLL reference clock frequency that you provide to the core in the sink direction, operating at the same user clock frequency (or equivalent transceiver lane data rate).

without the proper serial clock, the Quartus II Compiler issues a compilation error. Refer to Arria 10

Simulation Testbench for an example design.

PLL for the transmit serial clock based on the required user clock only when configured in sink or duplex mode. The Arria 10 simulation testbench uses the external transceiver ATX PLL. The transceiver ATX PLL core is configured with the transceiver reference clock specified in the parameter editor and transmit serial clock.

Example Designs > seriallite_iii_a10_0 - example (alternatively, turn on the Example Design option in the parameter editor). Altera recommends that you generate the Arria 10 simulation testbench for the sink or duplex direction.

Related Information

• SerialLite III Streaming IP Core Parameters on page 3-3

• Arria 10 Simulation Testbench on page 3-12

• Arria 10 versus Stratix V and Arria V GZ Variations on page 4-9

SerialLite III Streaming IP Core Parameters

Table 3-1: SerialLite III Streaming IP Core Parameters

Parameter

General Design Options Direction Source, Sink,

Duplex

Lanes 1–24 4

Device speed

1–4 2 Specifies the device speed grade (Stratix V and

grade

Value Default Description

Duplex Indicates the direction of the core's variant.

Specifies the number of lanes (equal to physical transceiver links) that are used to transfer the streaming data.

Arria V GZ devices only).

PLL type ATX, CMU CMU Selects the transceiver PLL type. (Stratix V and

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SerialLite III Streaming IP Core Parameters

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Parameter

Meta frame

200–8191 8191 Specifies the metaframe length in 8-byte words.

length ECC

Yes/No No Select to use error correcting code (ECC)

Protection

Clocking and Data Rates Advanced

Yes/No No Select to use the advanced clocking mode for your

clocking mode

Required user clock frequency

Minimum: 50 MHz Maximum: Limited

by the supported transceiver data rates

Generated user clock frequency

Minimum: 50 MHz Maximum: Limited

(1)

by the supported transceiver data rates

Value Default Description

protection to strengthen the FIFO buffers from single-event upset (SEU) changes.

design. The default setting is standard clocking mode.

146.484375 MHz

Specifies the clock generator’s fractional PLL (fPLL) output frequency used to drive the user_

clock signal. This range is device-specific and is

tied with the lane data rate and fPLL minimal clocking constraints.

In advanced clocking mode, this signal specifies the frequency required for the user_clock input.

146.484375 MHz

Specifies the actual user clock frequency as produced by the fPLL and is ideally the same as the required clock frequency. In certain very high precision situations where the desired user clock is provided up to higher decimal places, this value can vary slightly due to the fPLL constraints. Change the required clock frequency to correct the issue if the minute variation is intolerable.

Interface clock frequency

Core clock frequency

(1)

The parameter editor automatically calculates this parameter value based on the general design options.

Altera Corporation

Lane rate/64 Lane rate/40

(1)

See description

(Lane rate/64) to

(1)

(Lane rate/67) (Lane rate/40)–to

(Lane rate/67) See description

205.078125 MHz

Specifies the clock frequency of the source, sink, or duplex user interface in advanced clocking mode.

Arria 10 15.625 Gbps ≤ lane rate ≤ 17.4 Gbps: Lane rate/64

Arria 10 < 15.625 Gbps, and all Stratix V and Arria V GZ: Lane rate/40

The core clock is used internally between the user domain and the Native PHY IP core (Arria 10 devices) or Interlaken PHY IP core (Stratix V and Arria V GZ devices).

Arria 10 15.625 Gbps ≤ lane rate ≤ 17.4 Gbps: (Lane rate/64) to (Lane rate/67)

Arria 10 < 15.625 Gbps, and all Stratix V and Arria V GZ: (Lane rate/40) to (Lane rate/67)

(2)

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Transceiver Reconfiguration Controller for Stratix V and Arria V GZ...

3-5

Parameter

fPLL reference clock frequency

(1)

Transceiver reference clock frequency

Input data rate per lane

Value Default Description

Lane rate/64 Lane rate/40 See description

Range supported by the transceiver PLLs (Lane rate/N)

64 × (User clock

(1)

frequency)

257.812500 MHz

Specifies the fPLL reference clock frequency in standard clocking mode.

Arria 10 15.625 Gbps ≤ lane rate ≤ 17.4 Gbps: lane rate/64

Arria 10 < 15.625 Gbps, and all Stratix V and Arria

(2)

644.53125 MHz

V GZ: Lane rate/40

Specifies the transceiver reference clock frequency. The default value for the Input clock frequency is lane rate/16. Sample values of N include 80, 64, 50, 40, 32, 25, 20, 16, 12.5, 10, and 8.

Altera recommends that you select the highest frequency among the available options in the drop-down list.

For Arria 10 source designs, set this parameter to none.

9.375 Gbps Input data rate that the core can support.

Transceiver data rate per

(1)

lane

Input data rate × Overheads

10.3125 Gbps The effective data rate at the output of the transceivers, incorporating transmission and other overheads.

The parameter editor automatically calculates this value by adding the input data rate with transmis‐ sion overheads to provide you with a selection of

(2)

Aggregate input data

(1)

rate

Related Information

Lanes × Input data rate

36.6210938

Gbps

user clock frequency.

Aggregate input data rate that the core can support.

SerialLite III Parameter Editor on page 3-2

Transceiver Reconfiguration Controller for Stratix V and Arria V GZ Designs

If your design targets Stratix V or Arria V GZ devices, the transceiver reconfiguration controller is not included in the generated IP core. To create a complete system, refer to the design example block diagram on how to connect the transceiver reconfiguration controller.

(2)

The clock frequency value is useful if you want to simulate designs at different data rates. You should apply the displayed value in your testbench parameters.

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<your_testbench>_tb.csv <your_testbench>_tb.spd

<your_ip>.cmp - VHDL component declaration file

<your_ip>.ppf - XML I/O pin information file <your_ip>.qip - Lists IP synthesis files <your_ip>.sip - Contains assingments for IP simulation files

<your_ip>.v or .vhd

Top-level IP synthesis file

<your_ip>.v or .vhd Top-level simulation file

<simulator_setup_scripts>

<your_ip>.qsys - System or IP integration file

<your_ip>_bb.v - Verilog HDL black box EDA synthesis file <your_ip>_inst.v or .vhd - Sample instantiation template

<your_ip>_generation.rpt - IP generation report <your_ip>.debuginfo - Contains post-generation information

<your_ip>.html - Connection and memory map data <your_ip>.bsf - Block symbol schematic <your_ip>.spd - Combines simulation scripts for multiple cores

<your_ip>_tb.qsys

Testbench system file

<your_ip>.sopcinfo - Software tool-chain integration file

<EDA tool setup

scripts>

<your_ip>

IP variation files

<testbench>_tb

testbench system

sim

Simulation files

synth

IP synthesis files

sim

simulation files

Simulator scripts

<testbench>_tb

<ip subcores> n

Subcore libraries

sim

Subcore

Simulation files

synth

Subcore

synthesis files

<your_ip> n

IP variation files

testbench files

3-6

Files Generated for Altera IP Cores

Note: If your design targets Arria 10 devices, the transceiver reconfiguration functionality is embedded

inside the transceivers. The phy_mgmt bus interface connects directly to the Avalon-MM dynamic reconfiguration interface of the embedded Arria 10 Native PHY IP core. This interface is provided at the top level.

Files Generated for Altera IP Cores

The Quartus II software generates the following IP core output file structure:

Figure 3-2: IP Core Generated Files

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Table 3-2: IP Core Generated Files

<my_ip>.qsys

File Name Description

The Qsys system or top-level IP variation file. <my_ip> is the name that you give your IP variation.

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Files Generated for Altera IP Cores

File Name Description

<system>.sopcinfo Describes the connections and IP component parameterizations in

your Qsys system. You can parse its contents to get requirements when you develop software drivers for IP components.

Downstream tools such as the Nios II tool chain use this file. The .sopcinfo file and the system.h file generated for the Nios II tool chain include address map information for each slave relative to each master that accesses the slave. Different masters may have a different address map to access a particular slave component.

<my_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that

contains local generic and port definitions that you can use in VHDL design files.

3-7

<my_ip>.html

A report that contains connection information, a memory map showing the address of each slave with respect to each master to which it is connected, and parameter assignments.

<my_ip>_generation.rpt IP or Qsys generation log file. A summary of the messages during IP

generation.

<my_ip>.debuginfo Contains post-generation information. Used to pass System Console

and Bus Analyzer Toolkit information about the Qsys interconnect. The Bus Analysis Toolkit uses this file to identify debug components in the Qsys interconnect.

<my_ip>.qip

Contains all the required information about the IP component to integrate and compile the IP component in the Quartus II software.

<my_ip>.csv Contains information about the upgrade status of the IP component. <my_ip>.bsf A Block Symbol File (.bsf) representation of the IP variation for use

in Quartus II Block Diagram Files (.bdf).

<my_ip>.spd

Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with information about memories that you can initialize.

<my_ip>.ppf The Pin Planner File (.ppf) stores the port and node assignments for

<my_ip>_bb.v You can use the Verilog black-box (_bb.v) file as an empty module

<my_ip>.sip Contains information required for NativeLink simulation of IP

<my_ip>_inst.v or _inst.vhd HDL example instantiation template. You can copy and paste the

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IP components created for use with the Pin Planner.

declaration for use as a black box.

components. You must add the .sip file to your Quartus project.

contents of this file into your HDL file to instantiate the IP variation.

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Files Generated for Altera IP Cores (Legacy Parameter Editor)

File Name Description

<my_ip>.regmap If the IP contains register information, the .regmap file generates.

The .regmap file describes the register map information of master and slave interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This enables register display views and user customizable statistics in System Console.

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<my_ip>.svd

<my_ip>.v

<my_ip>.vhd

mentor/

aldec/

/synopsys/vcs

/synopsys/vcsmx

Allows HPS System Debug tools to view the register maps of peripherals connected to HPS within a Qsys system.

During synthesis, the .svd files for slave interfaces visible to System Console masters are stored in the .sof file in the debug section. System Console reads this section, which Qsys can query for register map information. For system slaves, Qsys can access the registers by name.

HDL files that instantiate each submodule or child IP core for synthesis or simulation.

Contains a ModelSim® script msim_setup.tcl to set up and run a simulation.

Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a simulation.

Contains a shell script vcs_setup.sh to set up and run a VCS

simulation. Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to

set up and run a VCS MX® simulation.

/cadence

Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM simulation.

/submodules Contains HDL files for the IP core submodule. <child IP cores>/ For each generated child IP core directory, Qsys generates /synth and /

sim sub-directories.

Files Generated for Altera IP Cores (Legacy Parameter Editor)

The Quartus II generates the following output for IP cores that use the legacy MegaWizard parameter editor.

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Notes:

1. If supported and enabled for your IP variation

2. If functional simulation models are generated

3. Ignore this directory

<your_ip>.v or .vhd - Top-level IP synthesis file

<your_ip>_inst.v or .vhd - Sample instantiation template

<your_ip>.bsf - Block symbol schematic file

<your_ip>.vo or .vho - IP functional simulation model

<your_ip>_syn.v or .vhd - Timing & resource estimation netlist1

<your_ip>_bb.v - Verilog HDL black box EDA synthesis file

<your_ip>.qip - Quartus II IP integration file

greybox_tmp 3

<your_ip>.cmp - VHDL component declaration file

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Figure 3-3: IP Core Generated Files

Simulating

3-9

Simulating

Simulating Altera IP Cores in other EDA Tools

The Quartus II software supports RTL and gate-level design simulation of Altera IP cores in supported EDA simulators. Simulation involves setting up your simulator working environment, compiling simulation model libraries, and running your simulation.

You can use the functional simulation model and the testbench or example design generated with your IP core for simulation. The functional simulation model and testbench files are generated in a project subdirectory. This directory may also include scripts to compile and run the testbench. For a complete list of models or libraries required to simulate your IP core, refer to the scripts generated with the testbench. You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts. NativeLink launches your preferred simulator from within the Quartus II software.

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Post-fit timing

simulation netlist

Post-fit timing simulation (3)

Post-fit functional

simulation netlist

Post-fit functional

simulation

Analysis & Synthesis

Fitter

(place-and-route)

TimeQuest Timing Analyzer

Device Programmer

Quartus II Design Flow

Gate-Level Simulation

Post-synthesis

functional

simulation

Post-synthesis functional

simulation netlist

(Optional) Post-fit timing simulation

RTL Simulation

Design Entry

(HDL, Qsys, DSP Builder)

Altera Simulation

Models

EDA Netlist Writer

3-10

Simulation Parameters

Figure 3-4: Simulation in Quartus II Design Flow

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Note: Post-fit timing simulation is supported only for Stratix IV and Cyclone IV devices in the current

version of the Quartus II software. Altera IP supports a variety of simulation models, including simulation-specific IP functional simulation models and encrypted RTL models, and plain text RTL models. These are all cycle-accurate models. The models support fast functional simulation of your IP core instance using industry-standard VHDL or Verilog HDL simulators. For some cores, only the plain text RTL model is generated, and you can simulate that model. Use the simulation models only for simulation and not for synthesis or any other purposes. Using these models for synthesis creates a nonfunctional design.

Related Information

Simulating Altera Designs

Simulation Parameters

After design generation, simulation files are available for you to simulate your design. To simulate your design, ensure that the SerialLite III Streaming IP core source and sink cores are both generated with the same parameters or are duplex cores.

• Stratix V and Arria V GZ files are located in the <variation name>_sim directory

• Arria 10 files are located in the <variation name> directory The example testbench simulates the core using the user-specified configuration

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Table 3-3: Stratix V and Arria V GZ Testbench Default Simulation Parameters

Parameter Default Value Comments

Simulation Parameters

3-11

Generated user clock frequency (user_clock_

frequency)

Standard clocking: 145.98375 MHz

Advanced clocking:

—

146.484375

Lanes (lanes) 2 — Transceiver reference clock

644.53125 MHz —

frequency (pll_ref_freq) Transceiver data rate per

10312.5 Mbps —

lane (data_rate) Meta frame length (meta_

frame_length)

fPLL reference clock

200 —

257.8125 MHz Not used in advanced clocking mode.

frequency (reference_

clock_frequency)

Core clock frequency

205.078125 MHz Not used in advanced clocking mode.

(coreclkin_frequency) Simulation-specific parameters Total samples to transfer

2000 Total samples to transfer during simulation.

(total_samples_to_

transfer)

Mode (mode) Continuous/burst The testbench environment may automati‐

cally choose one of the modes depending on the random seed with which it is provided. Refer to the simulation scripts listed in

Table 3-4 for details.

Skew insertion enable (skew_insertion_enable)

Yes Skew testing is enabled. The testbench

environment randomly inserts skew in the lanes within the range 0 - 107 UI.

ECC protection enabled (ecc_enable)

0 When set, the core is simulated with the

ECC-enabled variant. Use the ECC-enabled variant in the test environment.

When ECC mode is disabled, the two most significant bits of the error buses in the source or sink direction are don't care.

For more information about Altera simulation models, refer to the Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook.

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Simulating Altera Designs

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Testbench

Traffic

Generator

Traffic

Checker

Source

Absorber

Source

Application

Source

Adaptation

Sink

Application

Sink

Adaptation

Sink

Alignment

Source

Clock

Generator

Sink

Clock

Generator

Native PHY IP

Duplex -

Interlaken

Mode

Transceiver

TX PLL

Skew

Insertion

Loopback

Device Under Test (Duplex Mode)

Test Environment

3-12

Arria 10 Simulation Testbench

If your design targets Arria 10 devices, the generated example testbench is dynamic and has the same configuration as the IP (except for the metaframe length). When you choose the sink or duplex direction, the parameter editor generates an external transceiver ATX PLL for use in the Arria 10 testbench. Therefore, Altera recommends that you generate the Arria 10 simulation testbench for designs using the sink or duplex direction.

Note: The Arria 10 example testbench includes the external transceiver PLL; the IP core does not include

the transceiver PLL for these devices.

Figure 3-5: SerialLite III Streaming Example Testbench (Duplex) for Arria 10 Devices

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+ 47 hidden pages

Altera SerialLite III Streaming MegaCore Function User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

About the SerialLite III Streaming IP Core

SerialLite III Streaming Protocol

SerialLite III Streaming Protocol Operating Modes

Continuous Mode

Burst Mode

Performance and Resource Utilization

Getting Started

Installing and Licensing IP Cores

OpenCore Plus IP Evaluation

Specifying IP Core Parameters and Options

SerialLite III Parameter Editor

Arria 10 Designs

SerialLite III Streaming IP Core Parameters

Transceiver Reconfiguration Controller for Stratix V and Arria V GZ Designs

Files Generated for Altera IP Cores

Files Generated for Altera IP Cores (Legacy Parameter Editor)

Simulating

Simulating Altera IP Cores in other EDA Tools

Simulation Parameters

Arria 10 Simulation Testbench