ALLNET ALLNET 182897 Datasheet

Page 1

1 Introduction

PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Rev. 3.5 — 18 October 2017 Product data sheet 317435 COMPANY PUBLIC

This document describes the functionality and electrical specification of the NFC Controller PN7150. Specifically it describes the features of the product PN7150

Additional documents describing the product functionality further are available for designin support. Refer to the references listed in this document to get access to the full documentation provided by NXP.

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NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

2 General description

Best plug´n play and high-performance full NFC solution PN7150 is a full NFC controller solution with integrated firmware and NCI interface designed for contactless communication at 13.56 MHz. It is compatible with NFC forum requirements.

PN7150 is designed based on learnings from previous NXP NFC device generation. It is the ideal solution for rapidly integrating NFC technology in any application, especially those running O/S environment like Linux and Android, reducing Bill of Material (BOM) size and cost, thanks to:

• Full NFC forum compliancy (see [1]) with small form factor antenna

• Embedded NFC firmware providing all NFC protocols as pre-integrated feature

• Direct connection to the main host or microcontroller, by I2C-bus physical and NCI

protocol

• Ultra-low power consumption in polling loop mode

• Highly efficient integrated power management unit (PMU) allowing direct supply from a

battery

PN7150 embeds a new generation RF contactless front-end supporting various transmission modes according to NFCIP-1 and NFCIP-2, ISO/IEC 14443, ISO/IEC 15693, MIFARE and FeliCa specifications. It embeds an ARM Cortex-M0 microcontroller core loaded with the integrated firmware supporting the NCI 1.0 host communication. It also allows to provide a higher output power by supplying the transmitter output stage from 3.0 V to 4.75 V.

PN7150

The contactless front-end design brings a major performance step-up with on one hand a higher sensitivity and on the other hand the capability to work in active load modulation communication enabling the support of small antenna form factor.

Supported transmission modes are listed in Figure 1. For contactless card functionality, the PN7150 can act autonomously if previously configured by the host in such a manner.

PN7150 integrated firmware provides an easy integration and validation cycle as all the NFC real-time constraints, protocols and device discovery (polling loop) are being taken care internally. In few NCI commands, host SW can configure the PN7150 to notify for card or peer detection and start communicating with them.

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 2 / 61

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NXP Semiconductors

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CARD

(PICC)

T4T - ISO/IEC 14443 A

T4T - ISO/IEC 14443 B

READER

(PCD - VCD)

ISO/IEC 14443 A

ISO/IEC 14443 B

ISO/IEC 15693

MIFARE Classic 1K/4K

MIFARE DESFire

Sony FeliCa

(1)

NFC FORUM

NFC-IP MODES

P2P ACTIVE

106 TO 424 kbps

INITIATOR AND TARGET

P2P PASSIVE

106 TO 424 kbps

INITIATOR AND TARGET

NFC FORUM T3T

READER FOR NFC FORUM

Tag Types 1 TO 5

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

1. According to ISO/IEC 18092 (Ecma 340) standard.

Fig 1. PN7150 transmission modes

PN7150

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 3 / 61

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NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

3 Features and benefits

• Includes NXP ISO/IEC14443-A and Innovatron ISO/IEC14443-B intellectual property

licensing rights

• ARM Cortex-M0 microcontroller core

• Highly integrated demodulator and decoder

• Buffered output drivers to connect an antenna with minimum number of external

components

• Integrated RF level detector

• Integrated Polling Loop for automatic device discovery

• RF protocols supported – NFCIP-1, NFCIP-2 protocol (see [8] and [11]) – ISO/IEC 14443A, ISO/IEC 14443B PICC, NFC Forum T4T modes via host interface

(see [3])

– NFC Forum T3T via host interface – ISO/IEC 14443A, ISO/IEC 14443B PCD designed according to NFC Forum digital

protocol T4T platform and ISO-DEP (see [1])

– FeliCa PCD mode – MIFARE PCD encryption mechanism (MIFARE Classic 1K/4K) – NFC Forum tag 1 to 5 (MIFARE Ultralight, Jewel, Open FeliCa tag, MIFARE

DESFire) (see [1])

– ISO/IEC 15693/ICODE VCD mode (see [9])

• Supported host interfaces – NCI protocol interface according to NFC Forum standardization (see [2]) – I2C-bus High-speed mode (see [4])

• Integrated power management unit – Direct connection to a battery (2.3 V to 5.5 V voltage supply range) – Support different Hard Power-Down/Standby states activated by firmware – Autonomous mode when host is shut down

• Automatic wake-up via RF field, internal timer and I2C-bus interface

• Integrated non-volatile memory to store data and executable code for customization

PN7150

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 4 / 61

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NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

4 Applications

• All devices requiring NFC functionality especially those running in an Android or Linux

environment

• TVs, set-top boxes, blu-ray decoders, audio devices

• Home automation, gateways, wireless routers

• Home appliances

• Wearables, remote controls, healthcare, fitness

• Printers, IP phones, gaming consoles, accessories

PN7150

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 5 / 61

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NXP Semiconductors

PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

5 Quick reference data

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

BAT

battery supply voltage

Card Emulation and Passive Target; VSS = 0 V

[1]

2.3 - 5.5 VV

[2]

DD(PAD)

BAT

O(VDDPAD)

th(Ilim)

tot

amb

Reader, Active Initiator and Active Target; VSS = 0 V

[1]

2.7 - 5.5 V

[2]

supply voltage internal supply voltage 1.65 1.8 1.95 V

DD(PAD)

supply voltage

supply voltage for host interface

[1]

1.65 1.8 1.95 V

[1]

3.0 - 3.6 V

[3]

- 10 14 μA

battery supply current

• 1.8 V host supply;VSS = 0 V

• 3 V host supply; VSS = 0 V

in Hard Power Down state;V

= 3.6 V; T

BAT

= 25 °C

in Standby state;V

in Monitor state;V

in low-power polling loop;V

= 3.6 V; T = 25 °C - 20 - μA

BAT

= 2.75 V; T = 25 °C - - 14 μA

BAT

= 3.6 V; T =

BAT

[4]

- 150 - μA

25 °C;loop time = 500 ms

[2]

- - 190 mA

- - 15 mA

output current on pin V

DD(PAD)

PCD mode at typical 3 V

total current which can be pulled on V

DD(PAD)

referenced

outputs

current limit threshold current

current limiter on V V

total power dissipation Reader; I

VDD(TX)

pin;V

DD(TX)

= 100 mA;V

= 3.3

DD(TX)

= 5.5 V - - 420 mW

BAT

[2]

- 180 - mA

ambient temperature JEDEC PCB-0.5 -30 - +85 °C

[1] VSS represents V

SS(PAD)

and V

SS(TX)

[2] The antenna should be tuned not to exceed this current limit (the detuning effect when coupling with another device must be taken into account).

[3] External clock on NFC_CLK_XTAL1 must be LOW.

[4] See [10] for computing the power consumption as it depends on several parameters.

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 6 / 61

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NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

6 Ordering information

Table 2. Ordering information

PN7150B0HN/C110xx

[1] xx = firmware code variant.

PackageType number

Name Description Version

[1]

HVQFN40 plastic thermal enhanced very thin quad

flat package; no leads; 40 terminals; body; 6 × 6 × 0.85 mm

PN7150

SOT618-1

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 7 / 61

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NXP Semiconductors

0 5

Terminal 1 index area

A :7

B1 : 6

aaa-007965

B2 : 6

C : 8

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

7 Marking

Fig 2. PN7150 package marking (top view)

PN7150

Table 3. Marking codes

Type number Marking code

Line A 7 characters used: basic type number:PN7150x

where x is the FW variant

Line B1 6 characters used: diffusion batch sequence

number

Line B2 6 characters used: assembly ID number

Line C 7 characters used: manufacturing code

including:

• diffusion center code: – Z: SSMC – S: Powerchip (PTCT)

• assembly center code: – S: ATKH

• RoHS compliancy indicator: – D: Dark Green; fully compliant RoHS

and no halogen and antimony

• manufacturing year and week, 3 digits: – Y: year – WW: week code

• product life cycle status code: – X: means not qualified product – nothing means released product

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RF DETECTRF DETECT

CLESS

INTERFACE UNIT

SENSOR

DEMOD ADC

DRIVER TxCtrl

PLL BG

VMID

MISCELLANEOUS

TIMERS

CRC

COPROCESSOR

RANDOM NUMBER

GENERATOR

CLOCK MANAGEMENT UNIT

OSCILLATOR

380 kHz

FRACN

PLL

OSCILLATOR

40 MHz

QUARTZ

OSCILLATOR

CLESS UART

AHB to APB

RX CODEC

SIGNAL

PROCESSING

TX CODEC

DATA

MEMORY

SRAM

EEPROM

CODE

MEMORY

ROM

EEPROM

HOST INTERFACE

ARM

CORTEX M0

MEMORY

CONTROL

I2C-bus

POWER

MANAGEMENT UNIT

BATTERY MONITOR

4.5 V

TX-LDO

1.8 V

DSLDO

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

8 Block diagram

PN7150

Fig 3. PN7150 block diagram

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 9 / 61

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PN7150

Transparent top view

terminal 1

index area

I2CADR0

i.c.

I2CADR1

SS(PAD)

I2CSDA

DD(PAD)

I2CSCL

IRQ

VEN

DDD

DDA

BAT

i.c.

DD(TX_IN)

TX1

n.c.

SS(TX)

TX2

DD(MID)

RXP

RXN

DD(TX)

BAT1VBAT2

i.c.

NFC

CLK

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

9 Pinning information

9.1 Pinning

PN7150

Fig 4. Pinning

Table 4. Pin description

Symbol Pin

I2CADR0 1 I V

Type

[1]

Refer Description

DD(PAD)

I2C-bus address 0

i.c. 2 - - internally connected; must be connected to

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 10 / 61

I2CADR1 3 I V

SS(PAD)

I2CSDA 5 I/O V

DD(PAD)

I2CSCL 7 I V

IRQ 8 O V

VEN 10 I V

i.c. 11 - - internally connected; leave open

4 G n/a pad ground

6 P n/a pad supply voltage

9 G n/a ground

DD(PAD)

BAT

GND

I2C-bus address 1

I2C-bus data line

I2C-bus clock line

interrupt request output

reset pin. Set the device in Hard Power Down

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NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

PN7150

Symbol Pin

BAT2

BAT1

DD(TX)

12 P n/a battery supply voltage; must be connected to

13 P n/a battery supply voltage; must be connected to

14 P n/a transmitter supply voltage

RXN 15 I V

RXP 16 I V

DD(MID)

17 P n/a receiver reference input supply voltage

TX2 18 O V

SS(TX)

19 G n/a contactless transmitter ground

Type

[1]

Refer Description

BAT

DD(TX)

negative receiver input

positive receiver input

antenna driver output

n.c. 20 - - not connected

TX1 21 O V

DD(TX_IN)

22 P n/a transmitter input supply voltage; must be

DD(TX)

antenna driver output

connected to V

DD(TX)

i.c. 23 - - internally connected; leave open

i.c. 24 - - internally connected; leave open

i.c. 25 - - internally connected; leave open

BAT

DDA

DDD

26 P n/a battery supply voltage

27 G n/a ground

28 P n/a analog supply voltage; must be connected to

29 P n/a supply voltage

30 P n/a digital supply voltage; must be connected to

n.c. 31 - - not connected

n.c. 32 - - not connected

n.c. 33 - - not connected

n.c. 34 - - not connected

n.c. 35 - - not connected

NFC_CLK_XTAL1 36 I V

NFC_CLK_XTAL2 37 O V

oscillator input/PLL input

oscillator output

i.c. 38 - - internally connected; leave open

i.c. 39 - - internally connected; leave open

CLK_REQ 40 O V

DD(PAD)

clock request pin

[1] P = power supply; G = ground; I = input, O = output; I/O = input/output.

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 11 / 61

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NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

10 Functional description

PN7150 can be connected on a host controller through I2C-bus. The logical interface towards the host baseband is NCI-compliant [2] with additional command set for NXPspecific product features. This IC is fully user controllable by the firmware interface described in [5].

Moreover, PN7150 provides flexible and integrated power management unit in order to preserve energy supporting Power Off mode.

In the following chapters you will find also more details about PN7150 with references to very useful application note such as:

• PN7150 User Manual ([5]):

User Manual describes the software interfaces (API) based on the NFC forum NCI standard. It does give full description of all the NXP NCI extensions coming in addition to NCI standard ([2]).

• PN7150 Hardware Design Guide ([6]):

Hardware Design Guide provides an overview on the different hardware design options offered by the IC and provides guidelines on how to select the most appropriate ones for a given implementation. In particular, this document highlights the different chip power states and how to operate them in order to minimize the average NFC-related power consumption so to enhance the battery lifetime.

PN7150

• PN7150 Antenna and Tuning Design Guide ([7]):

Antenna and Tuning Design Guide provides some guidelines regarding the way to design an NFC antenna for the PN7150 chip. It also explains how to determine the tuning/matching network to place between this antenna and the PN7150. Standalone antenna performances evaluation and final RF system validation (PN7150 + tuning/matching network + NFC antenna within its final environment) are also covered by this document.

• PN7150 Low-Power Mode Configuration ([10]):

Low-Power Mode Configuration documentation provides guidance on how PN7150 can be configured in order to reduce current consumption by using Low-power polling mode.

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 12 / 61

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NXP Semiconductors

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NFCC

host interface

control

HOST

CONTROLLER

BATTERY/PMU

ANTENNA

MATCHING

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Fig 5. PN7150 connection

PN7150

10.1 System modes

10.1.1 System power modes

PN7150 is designed in order to enable the different power modes from the system.

2 power modes are specified: Full power mode and Power Off mode.

Table 5. System power modes description

System power mode Description

Full power mode the main supply (V

Power Off mode the system is kept Hard Power Down (HPD)

) as well as the host interface supply (V

BAT

available, all use cases can be executed

DD(PAD)

) is

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 13 / 61

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[VEN = Off]

BAT

= On && V

DD(PAD)

= On

VEN = On]

BAT

= Off || VEN = Off]

Full power mode

Power Off mode

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Fig 6. System power mode diagram

Table 6 summarizes the system power mode of the PN7150 depending on the status of the external supplies available in the system:

PN7150

Table 6. System power modes configuration

BAT

VEN Power mode

Off X Power Off mode

On Off Power Off mode

On On Full power mode

Depending on power modes, some application states are limited:

Table 7. System power modes description

System power mode Allowed communication modes

Power Off mode no communication mode available

Full power mode Reader/Writer, Card Emulation, P2P modes

10.1.2 PN7150 power states

Next to system power modes defined by the status of the power supplies, the power states include the logical status of the system thus extend the power modes.

4 power states are specified: Monitor, Hard Power Down (HPD), Standby, Active.

Table 8. PN7150 power states

Power state name Description

Monitor The PN7150 is supplied by V

critical level, VEN voltage > 1.1 V and the Monitor state is enabled. The system power mode is Power Off mode.

which voltage is below its programmable

BAT

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 14 / 61

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NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Power state name Description

Hard Power Down The PN7150 is supplied by V

Standby The PN7150 is supplied by V

Active The PN7150 is supplied by V

At application level, the PN7150 will continuously switch between different states to optimize the current consumption (polling loop mode). Refer to Table 1 for targeted current consumption in here described states.

PN7150

which voltage is above its programmable

BAT

critical level when Monitor state is enabled and PN7150 is kept in Hard Power Down (VEN voltage is kept low by host or SW programming) to have the minimum power consumption. The system power mode is in Power Off.

which voltage is above its programmable

BAT

critical level when the Monitor state is enabled, VEN voltage is high (by host or SW programming) and minimum part of PN7150 is kept supplied to

enable configured wake-up sources which allow to switch to Active state; RF

field,Host interface. The system power mode is Full power mode.

which voltage is above its programmable

BAT

critical level when Monitor state is enabled, VEN voltage is high (by host or SW programming) and the PN7150 internal blocks are supplied. 3 functional modes are defined: Idle, Target and Initiator. The system power mode is Full power mode.

The PN7150 is designed to allow the host controller to have full control over its functional states, thus of the power consumption of the PN7150 based NFC solution and possibility to restrict parts of the PN7150 functionality.

10.1.2.1 Monitor state

In Monitor state, the PN7150 will exit it only if the battery voltage recovers over the critical level. Battery voltage monitor thresholds show hysteresis behavior as defined in Table

27.

10.1.2.2 Hard Power Down (HPD) state

The Hard Power Down state is entered when V voltage < 0.4 V. As these signals are under host control, the PN7150 has no influence on entering or exiting this state.

10.1.2.3 Standby state

Active state is PN7150’s default state after boot sequence in order to allow a quick configuration of PN7150. It is recommended to change the default state to Standby state after first boot in order to save power. PN7150 can switch to Standby state autonomously (if configured by host).

In this state, PN7150 most blocks including CPU are no more supplied. Number of wakeup sources exist to put PN7150 into Active state:

DD(PAD)

and V

are high by setting VEN

BAT

• I2C-bus interface wake-up event

• Antenna RF level detector

• Internal timer event when using polling loop (380 kHz Low-power oscillator is enabled)

If wake-up event occurs, PN7150 will switch to Active state. Any further operation depends on software configuration and/or wake-up source.

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 15 / 61

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NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

10.1.2.4 Active state

Within the Active state, the system is acting as an NFC device. The device can be in 3 different functional modes: Idle, Poller and Target.

Table 9. Functional modes in active state

Functional modes Description

Idle the PN7150 is active and allows host interface communication. The RF

Listener the PN7150 is active and is configured for listening to external device.

Poller the PN7150 is active and is configured in Poller mode. It polls external

PN7150

interface is not activated.

device

Poller mode

Listener mode

10.1.2.5 Polling loop

The polling loop will sequentially set PN7150 in different power states (Active or Standby). All RF technologies supported by PN7150 can be independently enabled within this polling loop.

There are 2 main phases in the polling loop:

• Listening phase. The PN7150 can be in Standby power state or Listener mode

• Polling phase. The PN7150 is in Poller mode

In this mode, PN7150 is acting as Reader/Writer or NFC Initiator, searching for or communicating with passive tags or NFC target. Once RF communication has ended, PN7150 will switch to active battery mode (that is, switch off RF transmitter) to save energy. Poller mode shall be used with 2.7 V < V

1.1 V. Poller mode shall not be used with V V

DD(PAD)

is within its operational range (see Table 1).

< 5.5 V and VEN voltage >

BAT

< 2.7 V.

In this mode, PN7150 is acting as a card or as an NFC Target. Listener mode shall be used with 2.3 V < V

BAT

5.5 V and VEN voltage > 1.1 V.

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 16 / 61

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Emulation

Pause

Type A

Type B

Type F @424

Type F @212

ISO15693

Listening phase

Polling phase

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

PN7150

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 17 / 61

Fig 7. Polling loop: all phases enabled

Listening phase uses Standby power state (when no RF field) and PN7150 goes to Listener mode when RF field is detected. When in Polling phase, PN7150 goes to Poller mode.

To further decrease the power consumption when running the polling loop, PN7150 features a low-power RF polling. When PN7150 is in Polling phase instead of sending regularly RF command, PN7150 senses with a short RF field duration if there is any NFC Target or card/tag present. If yes, then it goes back to standard polling loop. With 500 ms (configurable duration, see [5]) listening phase duration, the average power consumption is around 150 μA.

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Listening phase

Emulation

Pause

Polling phase

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

PN7150

Fig 8. Polling loop: low-power RF polling

Detailed description of polling loop configuration options is given in [5].

10.2 Microcontroller

PN7150 is controlled via an embedded ARM Cortex-M0 microcontroller core.

PN7150 features integrated in firmware are referenced in [5].

10.3 Host interface

PN7150 provides the support of an I2C-bus Slave Interface, up to 3.4 MBaud.

The host interface is waken-up on I2C-bus address.

To enable and ensure data flow control between PN7150 and host controller, additionally a dedicated interrupt line IRQ is provided which Active state is programmable. See [5] for more information.

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 18 / 61

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High performance NFC controller with integrated firmware, supporting all NFC Forum modes

10.3.1 I2C-bus interface

The I2C-bus interface implements a slave I2C-bus interface with integrated shift register, shift timing generation and slave address recognition.

I2C-bus Standard mode (100 kHz SCL), Fast mode (400 kHz SCL) and High-speed mode (3.4 MHz SCL) are supported.

The mains hardware characteristics of the I2C-bus module are:

• Support slave I2C-bus

• Standard, Fast and High-speed modes supported

• Wake-up of PN7150 on its address only

• Serial clock synchronization can be used by PN7150 as a handshake mechanism to

suspend and resume serial transfer (clock stretching)

The I2C-bus interface module meets the I2C-bus specification [4] except General call, 10bit addressing and Fast mode Plus (Fm+).

10.3.1.1 I2C-bus configuration

PN7150

The I2C-bus interface shares four pins with I2C-bus interface also supported by PN7150. When I2C-bus is configured in EEPROM settings, functionality of interface pins changes to one described in Table 10.

Table 10. Functionality for I2C-bus interface

Pin name Functionality

I2CADR0 I2C-bus address 0

I2CADR1 I2C-bus address 1

I2CSCL

I2CSDA

[1]

[1] I2CSCL and I2CSDA are not fail-safe and V

I2C-bus clock line

I2C-bus data line

shall always be available when

DD(pad)

using the SCL and SDA lines connected to these pins.

PN7150 supports 7-bit addressing mode. Selection of the I2C-bus address is done by 2pin configurations on top of a fixed binary header: 0, 1, 0, 1, 0, I2CADR1, I2CADR0, R/W.

Table 11. I2C-bus interface addressing

I2CADR1 I2CADR0 I2C-bus address

(R/W = 0, write)

0 0 0x50 0x51

0 1 0x52 0x53

1 0 0x54 0x55

1 1 0x56 0x57

I2C-bus address (R/W = 1, read)

10.4 PN7150 clock concept

There are 4 different clock sources in PN7150:

• 27.12 MHz clock coming either/or from:

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 19 / 61

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PN7150

NFC_CLK_XTAL1 NFC_CLK_XTAL2

crystal

27.12 MHz

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

– Internal oscillator for 27.12 MHz crystal connection – Integrated PLL unit which includes a 1 GHz VCO, taking is reference clock on pin

• 13.56 MHz RF clock recovered from RF field

• Low-power oscillator 40 MHz

• Low-power oscillator 380 kHz

10.4.1 27.12 MHz quartz oscillator

When enabled, the 27.12 MHz quartz oscillator applied to PN7150 is the time reference for the RF front end when PN7150 is behaving in Reader mode or NFCIP-1 initiator.

Therefore stability of the clock frequency is an important factor for reliable operation. It is recommended to adopt the circuit shown in Figure 9.

PN7150

NFC_CLK_XTAL1

Fig 9. 27.12 MHz crystal oscillator connection

Table 12 describes the levels of accuracy and stability required on the crystal.

Table 12. Crystal requirements

Symbol Parameter Conditions Min Typ Max Unit

xtal

crystal frequency ISO/IEC and FCC

- 27.12 - MHz

compliancy

Δf

xtal

crystal frequency accuracy

full operating range

all V

range;T = 20

BAT

[1]

-100 - +100 ppm

[1]

-50 - +50 ppm

°C

all temperature range;V

BAT

= 3.6 V

[1]

-50 - +50 ppm

ESR equivalent series resistance - 50 100 Ω

xtal

load capacitance - 10 - pF

crystal power dissipation - - 100 μW

[1] This requirement is according to FCC regulations requirements. To meet only ISO/IEC 14443 and ISO/IEC 18092, then ± 14 kHz apply.

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Input reference

noise floor

-140 dBc/Hz

dBc/Hz

-20dBc/Hz

Input reference noise corner

50 kHz

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

10.4.2 Integrated PLL to make use of external clock

When enabled, the PLL is designed to generate a low noise 27.12 MHz for an input clock 13 MHz, 19.2 MHz, 24 MHz, 26 MHz, 38.4 MHz and 52 MHz.

The 27.12 MHz of the PLL is used as the time reference for the RF front end when PN7150 is behaving in Reader mode or ISO/IEC 18092 Initiator as well as in Target when configured in Active Communication mode.

The input clock on NFC_CLK_XTAL1 shall comply with the.following phase noise requirements for the following input frequency: 13 MHz, 19.2 MHz, 24 MHz, 26 MHz,

38.4 MHz and 52 MHz:

PN7150

Fig 10. Input reference phase noise characteristics

This phase noise is equivalent to an RMS jitter of 6.23 ps from 10 Hz to 1 MHz. For configuration of input frequency, refer to [9]. There are 6 pre-programmed and validated frequencies for the PLL: 13 MHz, 19.2 MHz, 24 MHz, 26 MHz, 38.4 MHz and 52 MHz.

Table 13. PLL input requirements

Coupling: single-ended, AC coupling;

Symbol Parameter Conditions Min Typ Max Unit

clk

i(ref)acc

clock frequency ISO/IEC and FCC

compliancy

reference input frequency accuracy

full operating range;frequencies typical values:13 MHz, 26 MHz and

52 MHz

full operating range;frequencies typical values:19.2 MHz, 24 MHz and

38.4 MHz

- 13 - MHz

- 19.2 - MHz

- 24 - MHz

- 26 - MHz

- 38.4 - MHz

- 52 - MHz

[1]

-25 - +25 ppmf

[1]

-50 - +50 ppm

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 21 / 61

Page 22

NXP Semiconductors

PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Symbol Parameter Conditions Min Typ Max Unit

Sinusoidal shape

i(p-p)

i(clk)

Square shape

i(clk)

phase noise input noise floor at 50 kHz -140 - - dB/

peak-to-peak input voltage

clock input voltage 0 - 1.8 V

clock input voltage 0 - 1.8 ± 10 % V

0.2 - 1.8 V

[1] This requirement is according to FCC regulations requirements. To meet only ISO/IEC 14443 and ISO/IEC 18092, then ± 400 ppm limits apply.

For detailed description of clock request mechanisms, refer to [5] and [6].

10.4.3 Low-power 40 MHz ± 2.5 % oscillator

Low-power OSC generates a 40 MHz internal clock. This frequency is divided by two to make the system clock.

10.4.4 Low-power 380 kHz oscillator

A Low Frequency Oscillator (LFO) is implemented to drive a counter (WUC) wakingup PN7150 from Standby state. This allows implementation of low-power reader polling loop at application level. Moreover, this 380 kHz is used as the reference clock for write access to EEPROM memory.

10.5 Power concept

10.5.1 PMU functional description

The Power Management Unit of PN7150 generates internal supplies required by PN7150 out of V

• VDD: internal supply voltage

• V

DD(TX)

The Figure 11 describes the main blocks available in PMU:

input supply voltage:

BAT

: output supply voltage for the RF transmitter

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 22 / 61

Page 23

NXP Semiconductors

aaa-016748

BAT

NFCC

BANDGAP

DSLDO

TXLDO

BAT1

and V

BAT2

DD(TX)

aaa-017002

BAT1

NFCC

DD(TX)

DD(TX_IN)

BAT2

BATTERY

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Fig 11. PMU functional diagram

PN7150

10.5.2 DSLDO: Dual Supply LDO

The input pin of the DSLDO is V

The Low drop-out regulator provides VDD required in PN7150.

BAT

10.5.3 TXLDO

Transmitter voltage can be generated by internal LDO (V supply source V

DD(TX)

The regulator has been designed to work in 2 configurations:

10.5.3.1 Configuration 1: supply connection in case the battery is used to generate RF field

The Low drop Out Regulator has been designed to generate a 3.0 V, 3.3 V or 3.6 V supply voltage to a transmitter with a current load up to 180 mA.

The output is called V connected to V

BAT1

pin.

. The input supply voltage of this regulator is a battery voltage

DD(TX)

) or come from an external

DD(TX)

Fig 12. V

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 23 / 61

BAT1

= V

(between 2.3 V and 5.5 V)

BAT2

Page 24

NXP Semiconductors

aaa-014174

5.0 V

2.8 V

3.6 V

3.3 V

3.0 V

4.5 V 3.6 V 3.3 V 3.0 V 2.8 V

Drop = 1 Ω * load

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

PN7150

value shall be chosen according to the minimum targeted V

DD(TX)

reader mode shall work.

• If V

is above 3.0 V plus the regulator voltage dropout, then V

BAT

chosen:

• If V

is above 3.3 V plus the regulator voltage dropout, then V

BAT

chosen:

• If V

is above 3.6 V plus the regulator voltage dropout, then V

BAT

chosen:

value for which

BAT

= 3.0 V shall be

DD(TX)

= 3.3 V shall be

DD(TX)

= 3.6 V shall be

DD(TX)

Fig 13. V

offset behavior

DD(TX)

Figure 13 shows V

offset disabled behavior for both cases of V

DD(TX)

programmed

DD(TX)

for 3.0 V, 3.3 V or 3.6 V.

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 24 / 61

Page 25

NXP Semiconductors

aaa-009463

BAT

2.5 V

aaa-017003

NFCC

EXTERNAL 5 V

BAT1

BAT2

BATTERY

DD(TX)

DD(TX_IN)

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

PN7150

In Standby state, whenever V

is configured for 3.0 V, 3.3 V or 3.6 V, V

DD(TX)

regulated at 2.5 V.

Fig 14. V

behavior when PN7150 is in Standby state

DD(TX)

Figure 14 shows the case where the PN7150 is in standby state.

10.5.3.2 Configuration 2: supply connection in case a 5 V supply is used to generate RF field with the use of TXLDO

TXLDO has also the possibility to generate 4.75 V or 4.5 V supply in case the supply of this regulator is an external 5 V supply.

Fig 15. V

BAT1

= 5 V, V

between 2.3 V and 5.5 V

BAT2

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 25 / 61

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NXP Semiconductors

aaa-017004

BAT1

Drop = 1 * load

4.75 V

5.5 V

4.5 V

DD(TX)

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Fig 16. V

behavior when PN7150 is supply using external supply on V

DD(TX)

PN7150

BAT1

Figure 16 shows the behavior of V

10.5.3.3 TXLDO limiter

The TXLDO includes a current limiter to avoid too high current within TX1, TX2 when in reader or initiator modes.

The current limiter block compares an image of the TXLDO output current to a reference. Once the reference is reached, the output current gets limited which is equivalent to a typical output current of 220 mA whatever V

5.5 V.

10.5.4 Battery voltage monitor

The PN7150 features low-power V battery from being discharged below critical levels. When V V

BATcritical

principle schematic of the battery monitor.

The battery voltage monitor is enabled via an EEPROM setting.

At the first start-up, V configured in EEPROM. The PN7150 monitors battery voltage continuously.

threshold, then the PN7150 goes in Monitor state. Refer to Figure 17 for

BAT

depending on V

DD(TX)

or V

BAT

voltage monitor which protects mobile device

BAT

BAT1

value.

BAT1

value in the range of 2.3 V to

voltage goes below

BAT

voltage monitor functionality is OFF and then enabled if properly

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 26 / 61

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SYSTEM

MANAGEMENT

low power

DVDD_CPU

DDD

power off

VBAT

MONITOR

REGISTERS

enable

threshold selection

POWER SWITCHES

POWER

MANAGEMENT

DIGITAL

(memories, cpu,

etc,...)

BAT

EEPROM

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

PN7150

Fig 17. Battery voltage monitor principle

The value of the critical level can be configured to 2.3 V or 2.75 V by an EEPROM setting. This value has a typical hysteresis around 150 mV.

10.6 Reset concept

10.6.1 Resetting PN7150

To enter reset, there are 2 ways:

• Pulling VEN voltage low (Hard Power Down state)

• if V

Reset means resetting the embedded FW execution and the registers values to their default values. Part of these default values is defined from EEPROM data loaded values, others are hardware defined. See [5] to know which ones are accessible to tune PN7150 to the application environment.

To get out of reset:

• Pulling VEN voltage high with V

Figure 18 shows reset done via VEN pin.

monitor is enabled: lowering V

BAT

VEN voltage is kept above 1.1 V)

above V

BAT

below the monitor threshold (Monitor state, if

BAT

monitor threshold if enabled

BAT

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 27 / 61

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NXP Semiconductors

aaa-015878

host

communication

possible

boot

w(VEN)

DD(PAD)

BAT

aaa-015879

host

communication

possible

boot

t(VDD(PAD)-VEN)

DD(PAD)

BAT

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Fig 18. Resetting PN7150 via VEN pin

See Section 14.2.2 for the timings values.

10.6.2 Power-up sequences

PN7150

10.6.2.1 V

There are 2 different supplies for PN7150. PN7150 allows these supplies to be set up independently, therefore different power-up sequences have to be considered.

is set up before V

BAT

This is at least the case when V PN7150 V

is always supplied as soon the system is supplied.

BAT

As VEN pin is referred to V

Fig 19. V

is set up before V

BAT

DD(PAD)

pin is directly connected to the battery and when

BAT

pin, VEN voltage shall go high after V

BAT

DD(PAD)

has been set.

BAT

See Section 14.2.3 for the timings values.

10.6.2.2 V

DD(PAD)

It is at least the case when V V

DD(PAD)

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 28 / 61

and V

are set up in the same time

BAT

pin is connected to a PMU/regulator which also supply

BAT

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NXP Semiconductors

aaa-015881

host

communication

possible

boot

t(VBAT-VEN)

DD(PAD)

BAT

boot

W(VEN)

DD(PAD)

BAT

t(VDD(PAD)-VEN)

aaa-015884

host

communication

possible

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Fig 20. V

See Section 14.2.3 for the timings values.

DD(PAD)

and V

are set up in the same time

BAT

PN7150

10.6.2.3 PN7150 has been enabled before V off

This can be the case when V V

DD(PAD)

is generated from a PMU. When the battery voltage is too low, then the PMU

pin is directly connected to the battery and when

BAT

might no more be able to generate V V

DD(PAD)

is set up again.

As the pins to select the interface are biased from V the pins might not be correctly biased internally and the information might be lost. Therefore it is required to make the IC boot after V

DD(PAD)

is set up or before V

DD(PAD)

has been cut

. When the device gets charged again, then

DD(PAD)

, when V

DD(PAD)

is set up again.

disappears

Fig 21. V

is set up or cut-off after PN7150 has been enabled

DD(PAD)

See Section 14.2.3 for the timings values.

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 29 / 61

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VBAT(L)

t > 0 mst > 0 ms

(nice to have)

BAT

DD(PAD)

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

10.6.3 Power-down sequence

PN7150Fig 22. power-down sequence

PN7150

10.7 Contactless Interface Unit

PN7150 supports various communication modes at different transfer speeds and modulation schemes. The following chapters give more detailed overview of selected communication modes.

Remark: all indicated modulation index and modes in this chapter are system parameters. This means that beside the IC settings a suitable antenna tuning is required to achieve the optimum performance.

10.7.1 Reader/Writer communication modes

Generally 5 Reader/Writer communication modes are supported:

• PCD Reader/Writer for ISO/IEC 14443A/MIFARE

• PCD Reader/Writer for Jewel/Topaz

• PCD Reader/Writer for FeliCa

• PCD Reader/Writer for ISO/IEC 14443B

• VCD Reader/Writer for ISO/IEC 15693/ICODE

10.7.1.1 ISO/IEC 14443A/MIFARE and Jewel/Topaz PCD communication mode

The ISO/IEC 14443A/MIFARE PCD communication mode is the general reader to card communication scheme according to the ISO/IEC 14443A specification. This modulation scheme is as well used for communications with Jewel/Topaz cards.

Figure 23 describes the communication on a physical level, the communication table describes the physical parameters (the numbers take the antenna effect on modulation depth for higher data rates).

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 30 / 61

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NFCC

ISO/IEC 14443A - MIFARE

PCD mode

PICC (Card)

ISO/IEC 14443A - MIFARE

PCD to PICC 100 % ASK at 106 kbit/s > 25 % ASK at 212, 424 or 848 kbit/s Modified Miller coded

PICC to PCD, subcarrier load modulation Manchester coded at 106 kbit/s BPSK coded at 212, 424 or 848 kbit/s

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Fig 23. ISO/IEC 14443A/MIFARE Reader/Writer communication mode diagram

Table 14. Overview for ISO/IEC 14443A/MIFARE Reader/Writer communication mode

Communication direction

PN7150 → PICC

card)

PICC → PN7150

(data received by PN7150 from a card)

ISO/IEC 14443A/ MIFARE/ Jewel/ Topaz

Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s

Bit length (128/13.56) μs (64/13.56) μs (32/13.56) μs (16/13.56) μs

modulation on

100 % ASK > 25 % ASK > 25 % ASK > 25 % ASK(data sent by PN7150 to a

PN7150 side

bit coding Modified Miller Modified Miller Modified Miller Modified Miller

modulation on PICC side

subcarrier

subcarrier load modulation

13.56 MHz/16 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16

frequency

bit coding Manchester BPSK BPSK BPSK

ISO/IEC 14443A higher transfer speeds

subcarrier load modulation

PN7150

subcarrier load modulation

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 31 / 61

The contactless coprocessor and the on-chip CPU of PN7150 handle the complete ISO/ IEC 14443A/MIFARE RF-protocol, nevertheless a dedicated external host has to handle the application layer communication.

Page 32

NXP Semiconductors

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NFCC

ISO/IEC 18092 - FeliCa

PCD mode

PICC (Card)

FeliCa card

PCD to PICC, 8 - 12 % ASK at 212 or 424 kbits/s Manchester coded

PICC to PCD, load modulation Manchester coded at 212 or 424 kbits/s

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

10.7.1.2 FeliCa PCD communication mode

The FeliCa communication mode is the general Reader/Writer to card communication scheme according to the FeliCa specification. Figure 24 describes the communication on a physical level, the communication overview describes the physical parameters.

Fig 24. FeliCa Reader/Writer communication mode diagram

PN7150

Table 15. Overview for FeliCa Reader/Writercommunication mode

Communication direction

FeliCa FeliCa higher transfer speeds

Transfer speed 212 kbit/s 424 kbit/s

Bit length (64/13.56) μs (32/13.56) μs

PN7150 → PICC

modulation on

8 % - 12 % ASK 8 % - 12 % ASK(data sent by PN7150 to a card)

PN7150 side

bit coding Manchester Manchester

PICC → PN7150

(data received by PN7150 from a card)

modulation on PICC

load modulation load modulation

side

subcarrier frequency no subcarrier no subcarrier

bit coding Manchester Manchester

The contactless coprocessor of PN7150 and the on-chip CPU handle the FeliCa protocol. Nevertheless a dedicated external host has to handle the application layer communication.

10.7.1.3 ISO/IEC 14443B PCD communication mode

The ISO/IEC 14443B PCD communication mode is the general reader to card communication scheme according to the ISO/IEC 14443B specification. Figure 25 describes the communication on a physical level, the communication table describes the physical parameters.

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 32 / 61

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NFCC

ISO/IEC 14443 Type B

PCD mode

PICC (Card)

ISO/IEC 14443 Type B

PCD to PICC, 8 - 14 % ASK at 106, 212, 424 or 848 kbit/s NRZ coded

PICC to PCD, subcarrier load modulation BPSK coded at 106, 212, 424 or 848 kbit/s

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Fig 25. ISO/IEC 14443B Reader/Writer communication mode diagram

Table 16. Overview for ISO/IEC 14443B Reader/Writer communication mode

Communication direction

PN7150 → PICC

card)

PICC → PN7150

(data received by PN7150 from a card)

Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s

Bit length (128/13.56) μs (64/13.56) μs (32/13.56) μs (16/13.56) μs

modulation on PN7150 side

bit coding NRZ NRZ NRZ NRZ

modulation on PICC side

subcarrier frequency

bit coding BPSK BPSK BPSK BPSK

ISO/IEC 14443B ISO/IEC 14443B higher transfer speeds

8 % - 14 % ASK 8 % - 14 % ASK 8 % - 14 % ASK 8 % - 14 % ASK(data sent by PN7150 to a

subcarrier load modulation

13.56 MHz/16 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16

subcarrier load modulation

PN7150

subcarrier load modulation

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 33 / 61

The contactless coprocessor and the on-chip CPU of PN7150 handles the complete ISO/IEC 14443B RF-protocol, nevertheless a dedicated external host has to handle the application layer communication.

10.7.1.4 R/W mode for NFC forum Type 5 Tag

The R/W mode for NFC forum Type 5 Tag (T5T) is the general reader to card communication scheme according to the ISO/IEC 15693 specification. PN7150 will communicate with VICC (Type 5 Tag) using only the 26.48 kbit/s with single subcarrier data rate of the VICC.

Page 34

NXP Semiconductors

aaa-016752

NFCC

ISO/IEC 15693

VCD mode

Card

(VICC/TAG)

ISO/IEC 15693

VCD to VICC, 100 % ASK at 26.48 kbit/s pulse position coded

VICC to VCD, subcarrier load modulation Manchester coded at 26.48 kbit/s

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Fig 26. R/W mode for NFC forum T5T communication diagram

Figure 26 and Table 17 show the communication schemes used.

Table 17. Communication overview for NFC forum T5T R/W mode

Communication direction

PN7150 → VICC

(data sent by PN7150 to a tag)

VICC → PN7150

(data received by PN7150 from a tag)

transfer speed 26.48 kbit/s

bit length (512/13.56) μs

modulation on PN7150 side 100 % ASK

bit coding pulse position modulation 1 out of 4 mode

transfer speed 26.48 kbit/s

bit length (512/13.56) μs

modulation on VICC side subcarrier load modulation

subcarrier frequency single subcarrier

bit coding Manchester

PN7150

10.7.2 ISO/IEC 18092, Ecma 340 NFCIP-1 communication modes

An NFCIP-1 communication takes place between 2 devices:

• NFC Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication.

• NFC Target: responds to NFC Initiator command either in a load modulation scheme in

Passive communication mode or using a self-generated and self-modulated RF field for Active communication mode.

The NFCIP-1 communication differentiates between Active and Passive communication modes.

• Active communication mode means both the NFC Initiator and the NFC Target are

using their own RF field to transmit data

• Passive communication mode means that the NFC Target answers to an NFC

Initiator command in a load modulation scheme. The NFC Initiator is active in terms of generating the RF field.

PN7150 supports the Active Target, Active Initiator, Passive Target and Passive Initiator

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 34 / 61

communication modes at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the NFCIP-1 standard.

Page 35

NXP Semiconductors

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NFCC

BATTERY

NFC Target: Passive or Active Communication modesNFC Initiator: Passive or Active Communication modes

HOST

NFCC

BATTERY

HOST

aaa-016756

1. NFC Initiator starts the communication at selected transfer speed

2. NFC Target answers at the same transfer speed

NFCC

NFC Target

host

power for digital processing

NFCC

NFC Target

host

power for digital processing

NFC Initiator

host

power to generate the field

NFC Initiator

host

power to generate the field

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Fig 27. NFCIP-1 communication mode

Nevertheless a dedicated external host has to handle the application layer communication.

10.7.2.1 ACTIVE communication mode

Active communication mode means both the NFC Initiator and the NFC Target are using their own RF field to transmit data.

PN7150

Fig 28. Active communication mode

The following table gives an overview of the Active communication modes:

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 35 / 61

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1. NFC Initiator starts the communication at selected transfer speed

2. NFC Target answers using load modulation at the same transfer speed

host

power for digital processing

NFCC

NFC Target

host

power for digital processing

NFC Initiator

host

power to generate the field

NFC Initiator

host

power to generate the field

NFCC

NFC Target

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Table 18. Overview for Active communication mode

Communication direction

Baud rate 106 kbit/s 212 kbit/s 424 kbit/s

Bit length (128/13.56) μs (64/13.56) μs (32/13.56) μs

NFC Initiator to NFC Target

modulation 100 % ASK

bit coding Modified Miller Manchester Manchester

NFC Target to NFC Initiator

modulation 100 % ASK

bit coding Miller Manchester Manchester

[1] This modulation index range is according to NFCIP-1 standard. It might be that some NFC forum type 3 cards does not withstand the full range as based on FeliCa range which is narrow (8 % to 14 % ASK).

ISO/IEC 18092, Ecma 340, NFCIP-1

8 % - 30 % ASK

[1]

8 % - 30 % ASK

[1]

8 % - 30 % ASK

PN7150

[1]

10.7.2.2 Passive communication mode

Passive communication mode means that the NFC Target answers to an NFC Initiator command in a load modulation scheme.

Fig 29. Passive communication mode

Table 19 gives an overview of the Passive communication modes:

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 36 / 61

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NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Table 19. Overview for Passive communication mode

Communication direction

Baud rate 106 kbit/s 212 kbit/s 424 kbit/s

Bit length (128/13.56) μs (64/13.56) μs (32/13.56) μs

NFC Initiator to NFC Target

modulation 100 % ASK

bit coding Modified Miller Manchester Manchester

NFC Target to NFC Initiator

modulation subcarrier load

subcarrier frequency 13.56 MHz/16 no subcarrier no subcarrier

bit coding Manchester Manchester Manchester

ISO/IEC 18092, Ecma 340, NFCIP-1

8 % - 30 % ASK

load modulation load modulation

modulation

[1]

8 % - 30 % ASK

PN7150

[1]

10.7.2.3 NFCIP-1 framing and coding

The NFCIP-1 framing and coding in Active and Passive communication modes are defined in the NFCIP-1 standard: ISO/IEC 18092 or Ecma 340.

10.7.2.4 NFCIP-1 protocol support

The NFCIP-1 protocol is not completely described in this document. For detailed explanation of the protocol, refer to the ISO/IEC 18092 or Ecma 340 NFCIP-1 standard. However the datalink layer is according to the following policy:

• Transaction includes initialization, anticollision methods and data transfer. This

sequence must not be interrupted by another transaction

• PSL shall be used to change the speed between the target selection and the data

transfer, but the speed should not be changed during a data transfer

10.7.3 Card communication modes

PN7150 can be addressed as NFC forum T3T and T4T tags. This means that PN7150 can generate an answer in a load modulation scheme according to the ISO/IEC 14443A, ISO/IEC 14443B and the Sony FeliCa interface description.

Remark: PN7150 does not support a complete card protocol. This has to be handled by the host controller.

Table 20, Table 21 and Table 22 describe the physical parameters.

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 37 / 61

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NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

10.7.3.1 NFC forum T4T, ISO/IEC 14443Acard mode

Table 20. Overview for NFC forum T4T, ISO/IEC 14443A card mode

Communication direction

PCD ® PN7150

from a card)

PN7150 ® PCD

(data sent by PN7150 to a card)

Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s

Bit length (128/13.56) μs (64/13.56) μs (32/13.56) μs

modulation on PCD side

bit coding Modified Miller Modified Miller Modified Miller

modulation on PN7150 side

subcarrier frequency

bit coding Manchester BPSK BPSK

ISO/IEC 14443A ISO/IEC 14443A higher transfer speeds

100 % ASK > 25 % ASK > 25 % ASK(data received by PN7150

subcarrier load modulation subcarrier load

13.56 MHz/16 13.56 MHz/16 13.56 MHz/16

modulation

PN7150

subcarrier load modulation

10.7.3.2 NFC forum T4T, ISO/IEC 14443B card mode

Table 21. Overview for NFC forum T4T, ISO/IEC 14443B card mode

Communication direction

PCD ® PN7150

from a Reader)

PN7150 ® PCD

(data sent by PN7150 to a Reader)

Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s

Bit length (128/13.56) μs (64/13.56) μs (32/13.56) μs

modulation on PCD side

bit coding NRZ NRZ NRZ

modulation on PN7150 side

subcarrier frequency

bit coding BPSK BPSK BPSK

ISO/IEC 14443B ISO/IEC 14443B higher transfer speeds

8 % - 14 % ASK 8 % - 14 % ASK 8 % - 14 % ASK(data received by PN7150

subcarrier load modulation

13.56 MHz/16 13.56 MHz/16 13.56 MHz/16

subcarrier load modulation

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 38 / 61

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NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

10.7.3.3 NFC forum T3T, Sony FeliCa card mode

Table 22. Overview for NFC forum T3T, Sony FeliCa card mode

Communication direction

Transfer speed 212 kbit/s 424 kbit/s

Bit length (64/13.56) μs (32/13.56) μs

PCD ® PN7150

modulation on PN7150 side

bit coding Manchester Manchester

PN7150 ® PCD

(data sent by PN7150 to a Reader)

modulation on PICC side

subcarrier frequency no subcarrier no subcarrier

bit coding Manchester Manchester

PN7150

FeliCa FeliCa higher transfer speeds

8 % - 12 % ASK 8 % - 12 % ASK(data received by PN7150 from a Reader)

load modulation load modulation

10.7.4 Frequency interoperability

When in communication, PN7150 is generating some RF frequencies. PN7150 is also sensitive to some RF signals as it is looking from data in the field.

In order to avoid interference with others RF communication, it is required to tune the antenna and design the board according to [6].

Although ISO/IEC 14443 and ISO/IEC 18092/Ecma 340 allows an RF frequency of 13.56 MHz ± 7 kHz, FCC regulation does not allow this wide spread and limits the dispersion to ± 50 ppm, which is in line with PN7150 capability.

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 39 / 61

Page 40

NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

11 Limiting values

Table 23. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

DD(PAD)VDD(PAD)

BAT

ESD

stg

tot

PN7150

supply voltage supply voltage for host

interface

battery supply voltage - 6 V

electrostatic discharge voltage

HBM; 1500 Ω, 100 pF;EIA/ JESD22-A114-D

CDM; field induced model;EIA/JESC22-C101-C

storage temperature -55 +150 °C

total power dissipation all modes

- 4.35 V

- 1.5 kVV

- 500 V

[1]

- 600 mW

RXN(i)

RXP(i)

RXN input voltage 0 2.5 V

RXP input voltage 0 2.5 V

[1] The design of the solution shall be done so that for the different use cases targeted the power to be dissipated from the field or generated by PN7150 does not exceed this value.

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 40 / 61

Page 41

NXP Semiconductors

PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

12 Recommended operating conditions

Table 24. Operating conditions

Symbol Parameter Conditions Min Typ Max Unit

amb

BAT

ambient temperature JEDEC PCB-0.5 -30 +25 +85 °C

battery supply voltage

battery monitor enabled;VSS =

[1]

2.3 - 5.5 V

0 V

Card Emulation and Passive Target;VSS = 0 V

[1]

2.3 - 5.5 V

[2]

DD(PAD)

tot

BAT

th(Ilim)

Reader, Active Initiator and Active Target;VSS = 0 V

DD(PAD)

supply voltage

supply voltage for host interface

• 1.8 V host supply;VSS = 0 V

• 3 V host supply;VSS = 0 V

total power dissipation Reader;I

= 5.5 V

battery supply current

in Hard Power Down state; V

in Standby state;V T = 25 °C

in Monitor state;V T = 25 °C

in low-power polling loop; V 25 °C;loop time = 500 ms

PCD mode at typical 3 V

current limit threshold current

current limiter on V pin; V

DD(TX)

= 100 mA;V

VDD(TX)

= 3.6 V;T = 25 °C

BAT

= 3.6 V; T =

BAT

DD(TX)

= 3.3 V

BAT

= 3.6 V;

= 2.75 V;

[1]

2.7 - 5.5 V

[2]

[1]

1.65 1.8 1.95 V

[1]

3.0 - 3.6 V

- - 420 mW

[3]

- 10 14 μA

- 20 - μA

- - 14 μA

[4]

- 150 - μA

[5]

- - 190 mA

[5]

- 180 - mA

[1] VSS represents V

SS(PAD)

and V

SS(TX)

[2] The antenna should be tuned not to exceed this current limit (the detuning effect when coupling with another device must be taken into account).

[3] External clock on NFC_CLK_XTAL1 must be LOW.

[4] See [10] for computing the power consumption as it depends on several parameters.

[5] The antenna shall be tuned not to exceed the maximum of I

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 41 / 61

BAT

Page 42

NXP Semiconductors

PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

13 Thermal characteristics

Table 25. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

th(j-a)

thermal resistance from junction to ambient

in free air with exposed pad soldered on a 4 layer JEDEC PCB

- 40 - K/W

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 42 / 61

Page 43

NXP Semiconductors

PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

14 Characteristics

14.1 Current consumption characteristics

Table 26. Current consumption characteristics for operating ambient temperature range

Symbol Parameter Conditions Min Typ Max Unit

BAT

battery supply current

in Hard Power Down state; V

= 3.6 V; VEN

BAT

voltage = 0 V

in Standby state;V

BAT

= 3.6 V;

- 10 20 μA

[1]

- 20 35 μA

in Idle and Listener modes; V

in Poller mode;V

in Monitor state;V

BAT

= 3.6 V

= 3.6 V - 150 - mA

BAT

= 2.75 V

BAT

[1] Refer to Section 10.1.2 for the description of the power modes.

[2] This is the same value for V

= 2.3 V when the monitor threshold is set to 2.3 V.

BAT

14.2 Functional block electrical characteristics

14.2.1 Battery voltage monitor characteristics

Table 27. Battery voltage monitor characteristics

Symbol Parameter Conditions Min Typ Max Unit

hys

14.2.2 Reset via VEN

threshold voltage

hysteresis voltage 100 150 200 mV

set to 2.3 V 2.15 2.3 2.45 VV

set to 2.75 V 2.6 2.75 2.9 V

- 4.55 - mA

[2]

- 10 20 μA

Table 28. Reset timing

Symbol Parameter Conditions Min Typ Max Unit

W(VEN)

boot

VEN pulse width to reset 10 - - μs

boot time - - 2.5 ms

14.2.3 Power-up timings

Table 29. Power-up timings

Symbol Parameter Conditions Min Typ Max Unit

t(VBAT-VEN)

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 43 / 61

transition time from pin V to pin VEN

BAT

voltage = HIGH

, VEN

0 0.5 - ms

Page 44

NXP Semiconductors

aaa-017006

I2CSDA

I2CSCL

r(I2CSDA)

HD;DAT

SU;DAT

LOW

HIGH

HD;STA

SU;STA

f(I2CSDA)

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Symbol Parameter Conditions Min Typ Max Unit

t(VDDPAD-VEN)

t(VBAT-VDDPAD)

14.2.4 Power-down timings

Table 30. Power-down timings

Symbol Parameter Conditions Min Typ Max Unit

VBAT(L)

14.2.5 I2C-bus timings

Here below are timings and frequency specifications.

transition time from pin V

DD(PAD)

to pin VEN

transition time from pin V to pin V

DD(PAD)

time V

LOW 20 - - ms

BAT

DD(PAD)

voltage = HIGH

BAT

BAT,VDD(PAD)

HIGH

, VEN

PN7150

0 0.5 - ms

Fig 30. I2C-bus timings

Table 31. High-speed mode I2C-bus timings specification

Symbol Parameter Conditions Min Max Unit

clk(I2CSCL)

SU;STA

clock frequency on pin I2CSCL

set-up time for a repeated

I2C-bus SCL;Cb < 100

0 3.4 MHz

Cb < 100 pF 160 - ns

START condition

HD;STA

hold time (repeated) START

Cb < 100 pF 160 - ns

condition

LOW

HIGH

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 44 / 61

SU;DAT

HD;DAT

LOW period of the SCL clock Cb < 100 pF 160 - ns

HIGH period of the SCL clock Cb < 100 pF 60 - ns

data set-up time Cb < 100 pF 10 - ns

data hold time Cb < 100 pF 0 - ns

Page 45

NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Symbol Parameter Conditions Min Max Unit

r(I2CSDA)

f(I2CSDA)

hys

Table 32. Fast mode I2C-bus timings specification

Symbol Parameter Conditions Min Max Unit

clk(I2CSCL

SU;STA

HD;STA

LOW

HIGH

SU;DAT

HD;DAT

hys

PN7150

rise time on pin I2CSDA I2C-bus SDA;Cb < 100

fall time on pin I2CSDA I2C-bus SDA;Cb < 100

hysteresis voltage Schmitt trigger

inputs;Cb < 100 pF

) clock frequency on pin I2CSCL I2C-bus SCL;Cb < 400

set-up time for a repeated

Cb < 400 pF 600 - ns

START condition

hold time (repeated) START

Cb < 400 pF 600 - ns

condition

LOW period of the SCL clock Cb < 400 pF 1.3 - μs

HIGH period of the SCL clock Cb < 400 pF 600 - ns

data set-up time Cb < 400 pF 100 - ns

data hold time Cb < 400 pF 0 900 ns

hysteresis voltage Schmitt trigger

inputs;Cb < 400 pF

10 80 ns

0.1V

DD(PAD)

- V

0 400 kHz

0.1V

DD(PAD)

- V

14.3 Pin characteristics

14.3.1 NFC_CLK_XTAL1 and NFC_CLK_XTAL2 pins characteristics

Table 33. Input clock characteristics on NFC_CLK_XTAL1 when using PLL

Symbol Parameter Conditions Min Typ Max Unit

i(p-p)

δ duty cycle 35 - 65 %

Table 34. Pin characteristics for NFC_CLK_XTAL1 when PLL input

Symbol Parameter Conditions Min Typ Max Unit

i(clk)(p-p)

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 45 / 61

peak-to-peak input voltage 0.2 - 1.8 V

HIGH-level input current VI = V

-1 - +1 μA

LOW-level input current VI = 0 V -1 - +1 μA

input voltage - - V

peak-to-peak clock input

200 - - mV

voltage

input capacitance all power modes - 2 - pF

Page 46

NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Table 35. Pin characteristics for 27.12 MHz crystal oscillator

Symbol Parameter Conditions Min Typ Max Unit

i(NFC_CLK_XTAL1)

i(NFC_CLK_XTAL2)

Table 36. PLL accuracy

Symbol Parameter Conditions Min Typ Max Unit

o(acc)

14.3.2 VEN input pin characteristics

NFC_CLK_XTAL1 input capacitance

NFC_CLK_XTAL2 input capacitance

output frequency accuracy

VDD = 1.8 V - 2 - pF

deviation added to NFC_CLK_XTAL1

frequency on RF frequency generated;worst case whatever input frequency

PN7150

- 2 - pF

-50 - +50 ppm

Table 37. VEN input pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

HIGH-level input voltage 1.1 - V

LOW-level input voltage 0 - 0.4 V

HIGH-level input current VEN voltage = V

LOW-level input current VEN voltage = 0 V -1 - +1 μA

input capacitance - 5 - pF

14.3.3 Pin characteristics for IRQ and CLK_REQ

Table 38. pin characteristics for IRQ and CLK_REQ

Symbol Parameter Conditions Min Typ Max Unit

HIGH-level output

IOH < 3 mA V

voltage

LOW-level output

IOL < 3 mA 0 - 0.4 V

voltage

load capacitance - - 20 pF

fall time

CL = 12 pF max

• high speed 1 - 3.5 ns

• slow speed 2 - 10 ns

rise time

CL = 12 pF max

• high speed 1 - 3.5 ns

• slow speed 2 - 10 ns

pull-down resistance

BAT

DD(PAD)

[1]

0.35 - 0.85 MΩ

-1 - +1 μA

- 0.4 - V

DD(PAD)

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 46 / 61

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NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

[1] Activated in HPD and Monitor states.

14.3.4 Input pin characteristics for RXN and RXP

Table 39. Input pin characteristics for RXN and RXP

Symbol Parameter Conditions Min Typ Max Unit

RXN(i)

RXP(i)

i(RXN)

i(RXP)

i(RXN-

VDDMID)

i(RXP-

VDDMID)

i(dyn)(RXN)

i(dyn)(RXP)

i(dyn)(RXN)

i(dyn)(RXP)

i(dyn)(RXN)

i(dyn)(RXP)

i(RF)

PN7150

RXN input voltage 0 - VDDV

RXP input voltage 0 - VDDV

RXN input capacitance - 12 - pF

RXP input capacitance - 12 - pF

input impedance between RXN and V

DD(MID)

input impedance between RXP and V

DD(MID)

RXN dynamic input voltage

RXP dynamic input voltage

RXN dynamic input voltage Manchester, NRZ

RXP dynamic input voltage Manchester, NRZ

RXN dynamic input voltage All data coding;106

RXP dynamic input voltage All data coding;106

RF input voltage RF input voltage

Reader, Card and

0 - 15 kΩ

P2P modes

Reader, Card and

0 - 15 kΩ

P2P modes

Miller coded

• 106 kbit/s - 150 200 mV(p-p)

• 212 kbit/s to

- 150 200 mV(p-p)

424 kbit/s

Miller coded

• 106 kbit/s - 150 200 mV(p-p)

• 212 kbit/s to

- 150 200 mV(p-p)

424 kbit/s

- 150 200 mV(p-p)

or BPSK coded;106

kbit/s to 848 kbit/s

- 150 200 mV(p-p)

or BPSK coded;106

kbit/s to 848 kbit/s

VDD- - V(p-p)

kbit/s to 848 kbit/s

VDD- - V(p-p)

kbit/s to 848 kbit/s

100 - mV(p-p) detected; Initiator modes

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 47 / 61

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NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

14.3.5 Output pin characteristics for TX1 and TX2

Table 40. Output pin characteristics for TX1 and TX2

Symbol Parameter Conditions Min Typ Max Unit

Table 41. Output resistance for TX1 and TX2

Symbol Parameter Conditions Min Typ Max Unit

HIGH-level output voltage

LOW-level output voltage

LOW-level output resistance

HIGH-level output

resistance

= 3.3 V and

DD(TX)

IOH = 30 mA;PMOS driver fully on

= 3.3 V and

DD(TX)

IOL = 30 mA;NMOS driver fully on

- 100

DD(TX)

mV;CWGsN = 01h

- 100

DD(TX)

mV;CWGsN = 0Fh

- 100 mV - - 4 Ω

DD(TX)

PN7150

- 150 - - mV

DD(TX)

- - 200 mV

- - 85 Ω

- - 5 Ω

14.3.6 Input pin characteristics for I2CADR0 and I2CADR1

Table 42. Input pin characteristics for I2CADR0 and I2CADR1

Symbol Parameter Conditions Min Typ Max Unit

HIGH-level input

0.65V

DD(PAD)

- V

DD(PAD)

voltage

LOW-level input

0 - 0.35V

DD(PAD)

voltage

HIGH-level input

VI = V

DD(PAD)

-1 - +1 μA

current

LOW-level input

VI = 0 V -1 - +1 μA

current

input capacitance - 5 - pF

14.3.7 Pin characteristics for I2CSDA and I2CSCL

Table 43. Pin characteristics for I2CSDA and I2CSCL

Symbol Parameter Conditions Min Typ Max Unit

LOW-level output

IOL < 3 mA

voltage

load capacitance - - 10 pF

[1]

0 - 0.4 V

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 48 / 61

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NXP Semiconductors

PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Symbol Parameter Conditions Min Typ Max Unit

fall time CL = 100 pF;Rpull-up = 2

kΩ;Standard and Fast mode

fall time CL = 100 pF;Rpull-up = 1

kΩ;High-speed mode

rise time

CL = 100 pF;Rpull-up = 2 kΩ;Standard and Fast mode

CL = 100 pF; Rpull-up = 1 kΩ; High-speed mode

HIGH-level input voltage

LOW-level input voltage

HIGH-level input

VI = V

;high impedance -1 - +1 μA

DD(PAD)

current

LOW-level input

VI = 0 V;high impedance -1 - +1 μA

current

input capacitance - 5 - pF

[1]

30 - 250 ns

[1]

80 - 110 ns

[1]

30 - 250 nst

[1]

10 - 100 ns

0.7V

DD(PAD)

0 - 0.3V

- V

DD(PAD)

[1] Only for pin I2CSDA as I2CSCL is only used as input.

14.3.8 VDD pin characteristic

Table 44. Electrical characteristic of V

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage VSS = 0 V 1.65 1.8 1.95 V

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 49 / 61

Page 50

NXP Semiconductors

References

Outline version

European projection

Issue date

IEC JEDEC JEITA

SOT618-1

MO-220

sot618-1_po

02-10-22 13-11-05

Unit

max nom

min

1.00 0.05 0.2 6.1 4.25 6.1

0.4

(1)

Dimensions (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm

SOT618-1

A1b

0.30

c D

(1)

DhE

(1)

4.10

e e1e2L v w

0.05y0.05

0.1

0.85 0.02 6.0 4.10 6.00.21

0.33.950.80 0.00 5.9 3.95 5.90.18

0.5 4.5 0.54.25 4.5 0.1

1/2 e

terminal 1 index area

11 20

40 31

terminal 1 index area

0 2.5 5 mm

scale

ACCBv

detail X

B A

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

15 Package outline

PN7150

Fig 31. Package outline, HVQFN40, SOT618-1, MSL3

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 50 / 61

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NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

16 Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

16.2 Wave and reflow soldering

PN7150

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

16.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are exposed to the wave

• Solder bath specifications, including temperature and impurities

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 51 / 61

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NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

16.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads

to higher minimum peak temperatures (see Figure 32) than a SnPb process, thus reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board

is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 45 and 46

Table 45. SnPb eutectic process (from J-STD-020D)

Package thickness (mm)

< 2.5 235 220

≥ 2.5 220 220

PN7150

Package reflow temperature (°C)

Volume (mm3)

< 350 ≥ 350

Table 46. Lead-free process (from J-STD-020D)

Package thickness (mm)

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Package reflow temperature (°C)

Volume (mm3)

< 350 350 to 2 000 > 2 000

Moisture sensitivity precautions, as indicated on the packing, must be respected at all times.

Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 32.

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 52 / 61

Page 53

NXP Semiconductors

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

MSL: Moisture Sensitivity Level

Fig 32. Temperature profiles for large and small components

PN7150

For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 53 / 61

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High performance NFC controller with integrated firmware, supporting all NFC Forum modes

17 Abbreviations

Table 47. Abbreviations

Acronym Description

API Application Programming Interface

ASK Amplitude Shift keying

ASK modulation index

Automatic device discovery

BPSK Bit Phase Shift Keying

Card Emulation The IC is capable of handling a PICC emulation on the RF interface including

DEP Data Exchange Protocol

DSLDO Dual Supplied LDO

FW FirmWare

HPD Hard Power Down

LDO Low Drop Out

LFO Low Frequency Oscillator

MOSFET Metal Oxide Semiconductor Field Effect Transistor

MSL Moisture Sensitivity Level

NCI NFC Controller Interface

NFC Near Field Communication

NFCC NFC Controller, PN7150 in this data sheet

NFC Initiator Initiator as defined in ISO/IEC 18092 or ECma 340: NFCIP-1 communication

NFCIP NFC Interface and Protocol

NFC Target Target as defined in ISO/IEC 18092 or ECma 340: NFCIP-1 communication

NRZ Non-Return to Zero

P2P Peer to Peer

PCD Proximity Coupling Device. Definition for a Card reader/writer device

PCD -> PICC Communication flow between a PCD and a PICC according to the

PICC Proximity Interface Coupling Card. Definition for a contactless Smart Card

PICC-> PCD Communication flow between a PICC and a PCD according to the

PMOS P-channel MOSFET

PMU Power Management Unit

PN7150

The ASK modulation index is defined as the voltage ratio (Vmax - Vmin)/ (Vmax + Vmin) × 100%

Detect and recognize any NFC peer devices (initiator or target) like: NFC initiator or target, ISO/IEC 14443-3, -4 Type A&B PICC, MIFARE Classic and MIFARE Ultralight PICC, ISO/IEC 15693 VICC

part of the protocol management. The application handling is done by the host controller

according to the ISO/IEC 14443 specification or MIFARE

ISO/IEC 14443 specification or MIFARE

according to the ISO/IEC 14443 specification or MIFARE

ISO/IEC 14443 specification or MIFARE

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 54 / 61

Page 55

NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Acronym Description

PSL Parameter SeLection

TXLDO Transmitter LDO

UM User Manual

VCD Vicinity Coupling Device. Definition for a reader/writer device according to the

VCO Voltage Controlled Oscillator

VICC Vicinity Integrated Circuit Card

WUC Wake-Up Counter

PN7150

ISO/IEC 15693 specification

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 55 / 61

Page 56

NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

18 References

[1] NFC Forum Device Requirements V1.3 [2] NFC Controller Interface (NCI) Technical Specification V1.0 [3] ISO/IEC 14443 parts 2: 2001 COR 1 2007 (01/11/2007), part 3: 2001 COR 1 2006

[4] I2C Specification, UM10204 rev4 (13/02/2012) [5] UM10936 PN7150 User Manual [6] AN11756 PN7150 Hardware Design Guide [7] AN11755 PN7150 Antenna design and matching guide [8] ISO/IEC 18092 (NFCIP-1) edition, 15/032013. This is similar to Ecma 340. [9] ISO/IEC 15693 part 2: 2nd edition (15/12/2006), part 3: 1st edition (01/04/2001) [10] AN11757 PN7150 Low-Power Mode Configuration [11] ISO/IEC 21481 (NFCIP-2) edition, 01/07/2012. This is similar to Ecma 352.

PN7150

(01/09/2006) and part 4: 2nd edition 2008 (15/07/2008)

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 56 / 61

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High performance NFC controller with integrated firmware, supporting all NFC Forum modes

19 Revision history

Table 48. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PN7150 v3.5 20171018 Product data sheet - PN7150 v3.4

Modifications: • Table 17(Communication overview for NFC Forum T5T R/W mode) updated.

PN7150 v3.4 20171004 Product data sheet - PN7150 v3.3

Modifications: • Descriptive title updated

• Section 2: Figure 1 updated

• MIFARE branding upated

PN7150 v3.3 20160704 Product data sheet - PN7150 v3.2

Modifications: • Figure 1: updated.

• Section 10.7.1.4: updated.

• Section 10.7.3: updated.

PN7150 v3.2 201600525 Product data sheet - PN7150 v3.1

PN7150 v3.1 20160511 Product data sheet - PN7150 v3.0

PN7150 v3.0 20151209 Product data sheet - PN7150 v2.1

PN7150 v2.1 20151127 Preliminary data sheet - PN7150 v2.0

PN7150 v2.0 20150701 Preliminary data sheet - PN7150 v1.2

PN7150 v1.2 20150625 Objective data sheet - PN7150 v1.1

PN7150 v1.1 20150212 Objective data sheet - PN7150 v1.0

PN7150 v1.0 20150129 Objective data sheet - -

Modifications: • Initial version

PN7150

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 57 / 61

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High performance NFC controller with integrated firmware, supporting all NFC Forum modes

20 Legal information

20.1 Data sheet status

PN7150

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

[1][2]

Product status

20.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

20.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

[3]

Definition

development.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 58 / 61

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NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.

PN7150

20.4 Licenses

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

Purchase of NXP ICs with ISO/IEC 14443 type B functionality

This NXP Semiconductors IC is ISO/IEC 14443 Type B software enabled and is licensed under Innovatron’s Contactless Card patents license for ISO/IEC 14443 B.

RATP/Innovatron Technology

Purchase of NXP ICs with NFC technology

Purchase of an NXP Semiconductors IC that complies with one of the Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/ IEC 21481 does not convey an implied license under any patent right infringed by implementation of any of those standards. Purchase of NXP Semiconductors IC does not include a license to any NXP patent (or other IP right) covering combinations of those products with other products, whether hardware or software.

The license includes the right to use the IC in systems and/or end-user equipment.

20.5 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

MIFARE — is a trademark of NXP B.V.

DESFire — is a trademark of NXP B.V.

ICODE and I-CODE — are trademarks of NXP B.V.

MIFARE Ultralight — is a trademark of NXP B.V.

MIFARE Classic — is a trademark of NXP B.V.

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High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Tables

PN7150

Tab. 1. Quick reference data .........................................6

Tab. 2. Ordering information ..........................................7

Tab. 3. Marking codes ...................................................8

Tab. 4. Pin description .................................................10

Tab. 5. System power modes description ................... 13

Tab. 6. System power modes configuration ................ 14

Tab. 7. System power modes description ................... 14

Tab. 8. PN7150 power states ......................................14

Tab. 9. Functional modes in active state .....................16

Tab. 10. Functionality for I2C-bus interface ...................19

Tab. 11. I2C-bus interface addressing .......................... 19

Tab. 12. Crystal requirements ....................................... 20

Tab. 13. PLL input requirements ................................... 21

Tab. 14. Overview for ISO/IEC 14443A/MIFARE

Reader/Writer communication mode ............... 31

Tab. 15. Overview for FeliCa Reader/

Writercommunication mode .............................32

Tab. 16. Overview for ISO/IEC 14443B Reader/

Writer communication mode ............................33

Tab. 17. Communication overview for NFC forum

T5T R/W mode ................................................34

Tab. 18. Overview for Active communication mode .......36

Tab. 19. Overview for Passive communication mode ....37

Tab. 20. Overview for NFC forum T4T, ISO/IEC

14443A card mode ..........................................38

Tab. 21. Overview for NFC forum T4T, ISO/IEC

14443B card mode ..........................................38

Tab. 22. Overview for NFC forum T3T, Sony FeliCa

card mode ....................................................... 39

Tab. 23. Limiting values ................................................ 40

Tab. 24. Operating conditions ....................................... 41

Tab. 25. Thermal characteristics ................................... 42

Tab. 26. Current consumption characteristics for

operating ambient temperature range ............. 43

Tab. 27. Battery voltage monitor characteristics ............43

Tab. 28. Reset timing .................................................... 43

Tab. 29. Power-up timings ............................................ 43

Tab. 30. Power-down timings ........................................ 44

Tab. 31. High-speed mode I2C-bus timings

specification .....................................................44

Tab. 32. Fast mode I2C-bus timings specification ......... 45

Tab. 33. Input clock characteristics on

NFC_CLK_XTAL1 when using PLL ................ 45

Tab. 34. Pin characteristics for NFC_CLK_XTAL1

when PLL input ............................................... 45

Tab. 35. Pin characteristics for 27.12 MHz crystal

oscillator .......................................................... 46

Tab. 36. PLL accuracy .................................................. 46

Tab. 37. VEN input pin characteristics .......................... 46

Tab. 38. pin characteristics for IRQ and CLK_REQ .......46

Tab. 39. Input pin characteristics for RXN and RXP ......47

Tab. 40. Output pin characteristics for TX1 and TX2 .....48

Tab. 41. Output resistance for TX1 and TX2 .................48

Tab. 42. Input pin characteristics for I2CADR0 and

I2CADR1 ......................................................... 48

Tab. 43. Pin characteristics for I2CSDA and I2CSCL ....48

Tab. 44. Electrical characteristic of VDD ....................... 49

Tab. 45. SnPb eutectic process (from J-STD-020D) ..... 52

Tab. 46. Lead-free process (from J-STD-020D) ............ 52

Tab. 47. Abbreviations ...................................................54

Tab. 48. Revision history ............................................... 57

Product data sheet Rev. 3.5 — 18 October 2017 COMPANY PUBLIC 317435 60 / 61

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NXP Semiconductors

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

PN7150

1 Introduction ......................................................... 1

2 General description ............................................ 2

3 Features and benefits .........................................4

4 Applications .........................................................5

5 Quick reference data .......................................... 6

6 Ordering information .......................................... 7

7 Marking .................................................................8

8 Block diagram ..................................................... 9

9 Pinning information .......................................... 10

9.1 Pinning ............................................................. 10

10 Functional description ......................................12

10.1 System modes .................................................13

10.1.1 System power modes ...................................... 13

10.1.2 PN7150 power states ......................................14

10.1.2.1 Monitor state ....................................................15

10.1.2.2 Hard Power Down (HPD) state ........................15

10.1.2.3 Standby state ...................................................15

10.1.2.4 Active state ...................................................... 16

10.1.2.5 Polling loop ...................................................... 16

10.2 Microcontroller ................................................. 18

10.3 Host interface .................................................. 18

10.3.1 I2C-bus interface ............................................. 19

10.3.1.1 I2C-bus configuration .......................................19

10.4 PN7150 clock concept .....................................19

10.4.1 27.12 MHz quartz oscillator ............................. 20

10.4.2 Integrated PLL to make use of external clock ...21

10.4.3 Low-power 40 MHz ± 2.5 % oscillator ............. 22

10.4.4 Low-power 380 kHz oscillator ..........................22

10.5 Power concept .................................................22

10.5.1 PMU functional description .............................. 22

10.5.2 DSLDO: Dual Supply LDO .............................. 23

10.5.3 TXLDO .............................................................23

10.5.3.1 Configuration 1: supply connection in case

the battery is used to generate RF field ...........23

10.5.3.2 Configuration 2: supply connection in case a 5 V supply is used to generate RF field with

the use of TXLDO ........................................... 25

10.5.3.3 TXLDO limiter .................................................. 26

10.5.4 Battery voltage monitor ....................................26

10.6 Reset concept ..................................................27

10.6.1 Resetting PN7150 ............................................27

10.6.2 Power-up sequences ....................................... 28

10.6.2.1 VBAT is set up before VDD(PAD) ................... 28

10.6.2.2 VDD(PAD) and VBAT are set up in the same

time .................................................................. 28

10.6.2.3 PN7150 has been enabled before VDD(PAD) is set up or before VDD(PAD)

has been cut off .............................................. 29

10.6.3 Power-down sequence .................................... 30

10.7 Contactless Interface Unit ............................... 30

10.7.1 Reader/Writer communication modes ..............30

10.7.1.1 ISO/IEC 14443A/MIFARE and Jewel/Topaz

PCD communication mode .............................. 30

10.7.1.2 FeliCa PCD communication mode ...................32

10.7.1.3 ISO/IEC 14443B PCD communication mode ... 32

10.7.1.4 R/W mode for NFC forum Type 5 Tag .............33

10.7.2 ISO/IEC 18092, Ecma 340 NFCIP-1

communication modes .....................................34

10.7.2.1 ACTIVE communication mode .........................35

10.7.2.2 Passive communication mode .........................36

10.7.2.3 NFCIP-1 framing and coding ........................... 37

10.7.2.4 NFCIP-1 protocol support ................................37

10.7.3 Card communication modes ............................ 37

10.7.3.1 NFC forum T4T, ISO/IEC 14443Acard mode ... 38

10.7.3.2 NFC forum T4T, ISO/IEC 14443B card mode ...38

10.7.3.3 NFC forum T3T, Sony FeliCa card mode ........ 39

10.7.4 Frequency interoperability ............................... 39

11 Limiting values ..................................................40

12 Recommended operating conditions .............. 41

13 Thermal characteristics .................................... 42

14 Characteristics .................................................. 43

14.1 Current consumption characteristics ................43

14.2 Functional block electrical characteristics ........43

14.2.1 Battery voltage monitor characteristics ............ 43

14.2.2 Reset via VEN ................................................. 43

14.2.3 Power-up timings ............................................. 43

14.2.4 Power-down timings ........................................ 44

14.2.5 I2C-bus timings ................................................44

14.3 Pin characteristics ............................................45

14.3.1 NFC_CLK_XTAL1 and NFC_CLK_XTAL2

pins characteristics .......................................... 45

14.3.2 VEN input pin characteristics ...........................46

14.3.3 Pin characteristics for IRQ and CLK_REQ .......46

14.3.4 Input pin characteristics for RXN and RXP ...... 47

14.3.5 Output pin characteristics for TX1 and TX2 ..... 48

14.3.6 Input pin characteristics for I2CADR0 and

I2CADR1 ..........................................................48

14.3.7 Pin characteristics for I2CSDA and I2CSCL .... 48

14.3.8 VDD pin characteristic ..................................... 49

15 Package outline .................................................50

16 Soldering of SMD packages .............................51

16.1 Introduction to soldering .................................. 51

16.2 Wave and reflow soldering .............................. 51

16.3 Wave soldering ................................................51

16.4 Reflow soldering .............................................. 52

17 Abbreviations .................................................... 54

18 References ......................................................... 56

19 Revision history ................................................ 57

20 Legal information ..............................................58

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 18 October 2017

Document number: 317435

ALLNET ALLNET 182897 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

2 General description

3 Features and benefits

4 Applications

5 Quick reference data

6 Ordering information

7 Marking

8 Block diagram

9 Pinning information

9.1 Pinning

10 Functional description

10.1 System modes

10.1.1 System power modes

10.1.2 PN7150 power states

10.1.2.1 Monitor state

10.1.2.2 Hard Power Down (HPD) state

10.1.2.3 Standby state

10.1.2.4 Active state

10.1.2.5 Polling loop

10.2 Microcontroller

10.3 Host interface

10.3.1 I2C-bus interface

10.3.1.1 I2C-bus configuration

10.4 PN7150 clock concept

10.4.1 27.12 MHz quartz oscillator

10.4.2 Integrated PLL to make use of external clock

10.4.3 Low-power 40 MHz ± 2.5 % oscillator

10.4.4 Low-power 380 kHz oscillator

10.5 Power concept

10.5.1 PMU functional description

10.5.2 DSLDO: Dual Supply LDO

10.5.3 TXLDO

10.5.3.1 Configuration 1: supply connection in case the battery is used to generate RF field

10.5.3.2 Configuration 2: supply connection in case a 5 V supply is used to generate RF field with the use of TXLDO

10.5.3.3 TXLDO limiter

10.5.4 Battery voltage monitor

10.6 Reset concept

10.6.1 Resetting PN7150

10.6.2 Power-up sequences

10.6.3 Power-down sequence

10.7 Contactless Interface Unit

10.7.1 Reader/Writer communication modes

10.7.1.1 ISO/IEC 14443A/MIFARE and Jewel/Topaz PCD communication mode

10.7.1.2 FeliCa PCD communication mode

10.7.1.3 ISO/IEC 14443B PCD communication mode

10.7.1.4 R/W mode for NFC forum Type 5 Tag

10.7.2 ISO/IEC 18092, Ecma 340 NFCIP-1 communication modes

10.7.2.1 ACTIVE communication mode

10.7.2.2 Passive communication mode

10.7.2.3 NFCIP-1 framing and coding

10.7.2.4 NFCIP-1 protocol support

10.7.3 Card communication modes

10.7.3.1 NFC forum T4T, ISO/IEC 14443Acard mode

10.7.3.2 NFC forum T4T, ISO/IEC 14443B card mode

10.7.3.3 NFC forum T3T, Sony FeliCa card mode

10.7.4 Frequency interoperability

11 Limiting values

12 Recommended operating conditions

13 Thermal characteristics

14 Characteristics

14.1 Current consumption characteristics

14.2 Functional block electrical characteristics

14.2.1 Battery voltage monitor characteristics

14.2.2 Reset via VEN

14.2.3 Power-up timings

14.2.4 Power-down timings

14.2.5 I2C-bus timings

14.3 Pin characteristics

14.3.1 NFC_CLK_XTAL1 and NFC_CLK_XTAL2 pins characteristics

14.3.2 VEN input pin characteristics

14.3.3 Pin characteristics for IRQ and CLK_REQ

14.3.4 Input pin characteristics for RXN and RXP

14.3.5 Output pin characteristics for TX1 and TX2

14.3.6 Input pin characteristics for I2CADR0 and I2CADR1

14.3.7 Pin characteristics for I2CSDA and I2CSCL

14.3.8 VDD pin characteristic