Alliance Semiconductor Corporation AS7C31024A-20TJI, AS7C31024A-20TJC, AS7C31024A-20TI, AS7C31024A-20TC, AS7C31024A-20JI Datasheet
...
January 2001
Advance Information
5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout)
Features
• AS7C1024A (5V version)
• AS7C31024A (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,012 words x 8 bits
• High speed
- 10/12/15/20 ns address access time
- 3/3/4/5 ns output enable access time
• Low power consumption: ACTIVE
- 660 mW (AS7C1024A) / max @ 10 ns
- 324 mW (AS7C31024A) / max @ 10 ns
• Low power consumption: STANDBY
- 55 mW (AS7C1024A) / max CMOS
- 36 mW (AS7C31024A) / max CMOS
AS7C1024A
AS7C31024A
®
• Latest 6T 0.25u CMOS technology
• 2.0V data retention
• Easy memory expansion with CE1
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
-300 mil SOJ
-400 mil SOJ
- 8 × 20mm TSOP I
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
, CE2, OE inputs
Logic block diagram
V
CC
GND
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
Row decoder
512×256×8
(1,048,576)
Column decoder
A9
A10
A11
Array
A12
I/O7
Sense amp
I/O0
Control
circuit
A13
A14
A15
A16
WE
OE
CE1
CE2
Pin arrangement
32-pin TSOP I
(8 x 20mm)
A11 OE
1
2
A9
3
A8
4
A13
5
WE
6
CE2
7
A15
8
V
CC
9
NC
10
A16
11
A14
12
A12
13
A7
14
A6
15
A5
16
A4 A3
AS7C1024A
AS7C31024A
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AS7C1024A
32
31
30
29
28
27
26
25
24
23
22
AS7C31024A
21
20
19
18
17
Selection guide
AS7C1024A-10
AS7C31024A-10
AS7C1024A-12
AS7C31024A-12
Maximum address access time 10 12 15 20 ns
Maximum output enable access time 3 3 4 5 ns
Maximum
operating current
Maximum CMOS
standby current
ASAS7C1024A 120 110 100 100 mA
AS7C31024A 90 80 80 80 mA
AS7C1024A 10 10 10 15 mA
AS7C31024A 10 10 10 15 mA
AS7C1024A-15
AS7C31024A-15
AS7C1024A-20
AS7C31024A-20 Unit
V
CC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
2/6/01; V.0.9 Alliance Semiconductor P. 1 of 8
Copyright © Alliance Semiconductor. All rights reserved.
AS7C1024A
AS7C31024A
®
Functional description
The AS7C1024A and AS7C31024A are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as
131,012 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 3/3/4/5 ns are ideal for high
performance applications. Active high and low chip enables (CE1
When CE1
static, then full standby power is reached (I
conditions. All devices in this family will retain data when VCC is reduced as low as 2.0V.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written
on the rising edge of WE
should drive I/O pins only after outputs have been disabled with output enable (OE
A read cycle is accomplished by asserting output enable (OE
I/O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is
active, output drivers stay in high-impedance mode.
is high or CE2 is low the devices enter standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is
). For example, the AS7C31024A is guaranteed not to exceed 36mW under nominal full standby
SB1
(write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices
Absolute maximum ratings
Parameter Symbol Min Max Unit
Vo l ta ge o n V
Voltage on any pin relative to GND Both V
Power dissipation Both P
Storage temperature (plastic) Both T
Ambient temperature with V
DC current into outputs (low) Both I
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
relative to GND
CC
applied Both T
CC
, CE2) permit easy memory expansion with multiple-bank systems.
) or write enable (WE).
) and both chip enables (CE1, CE2), with write enable (WE) high. The chips drive
AS7C1024A V
AS7C31024A V
t1
t1
t2
D
stg
bias
OUT
–0.50 +7.0 V
-0.50 +5.0 V
–0.50 VCC +0.50 V
–1.0W
–65 +150 °C
–55 +125 °C
–20mA
Truth table
CE1
HXXX High Z Standby (I
XLXX High Z Standby (I
L H H H High Z Output disable (I
LHHL D
LHLX D
Key: X = Don’t Care, L = Low, H = High
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CE2 WE OE Data Mode
OUT
IN
Read (ICC)
Write (
SB
SB
ICC
, I
, I
SB1
SB1
)
CC
)
)
)
Recommended operating conditions
Parameter Device Symbol Min Nominal Max Unit
Supply voltage
Input voltage
Ambient operating temperature
†
VILmin. = –3.0V for pulse width less than t
AS7C1024A V
AS7C31024A V
ASAS7C1024A V
AS7C31024A V
commercial T
industrial T
.
RC/2
CC
CC
IH
IH
V
IL
A
A
DC operating characteristics (over the operating range)1
Parameter Sym Test conditions Device
®
4.5 5.0 5.5 V
3.0 3.3 3.6 V
2.2 – VCC + 0.5 V
2.0 – VCC + 0.5 V
†
–0.5 – 0.8 V
0–70°C
–40 – 85 °C
-10 -12 -15 -20
Min Max Min Max Min Max Min Max
AS7C1024A
AS7C31024A
Unit
Input leakage
current
Output leakage
current
Operating power
supply current
Standby power
supply current
Output voltage
Data retention
current
|VCC = Max, VIN = GND to V
|I
LI
V
= Max, CE1 = VIH or
CC
|
|I
LO
CE2 = V
, V
IL
= GND to V
OUT
VCC = Max, CE1 = VIL,
CE2 = V
I
CC
IH
, f = f
Max
mA
VCC = Max, CE1 ≥ VIH and/or
I
SB
I
SB1
V
OL
V
OH
ICCDR
CE2 ≤ V
VCC = Max, CE1
IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – 2.4 – V
, VIN = VIH or VIL,
IL
, I
f = f
Max
OUT
≥
≤ GND + 0.2V or
V
IN
≥ VCC –0.2V, f = 0
V
IN
IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 V
= 2.0V
V
CC
CE1
≥ VCC–0.2V or
CE2 ≤ 0.2V
V
≥
V
CC
≤ 0.2V
IN
–0.2V or
V
IN
, I
OUT
= 0mA
V
–0.2V
CC
CC
Both –1–1–1–1µA
Both –1–1–1–1µA
CC
AS7C1024A – 120 – 110 – 100 – 100
= 0
AS7C31024A – 90 – 80 – 80 – 80
AS7C1024A – 30 – 25 – 20 – 20
AS7C31024A – 30 – 25 – 20 – 20
AS7C1024A – 10 – 10 – 10 – 15
AS7C31024A – 10 – 10 – 10 – 15
AS7C1024A - 1 - 1 - 1 - 5 mA
AS7C31024A - 1 - 1 - 1 - 5 mA
mA
mA
mA
Capacitance (f = 1 MHz, T
= 25 °C, V
a
= NOMINAL)
CC
2
Parameter Symbol Signals Test conditions Max Unit
Input capacitance C
I/O capacitance C
2/6/01; V.0.9 Alliance Semiconductor P. 3 of 8
IN
I/O
A, CE1, CE2, WE, OE VIN = 0V 5 pF
I/O VIN = V
= 0V 7 pF
OUT
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