Alliance Semiconductor Corporation AS4C4M4E1Q-60TC, AS4C4M4E1Q-60JC, AS4C4M4E1Q-50TC, AS4C4M4E1Q-50JC, 4C4M4EOQ-60TC Datasheet

March 2001

Copyright © Alliance Semiconductor. All rights reserved.

®

AS4C4M4EOQ

AS4C4M4E1Q

4M ✕ 4 CMOS QuadCAS DRAM (EDO) family

3/22/01; v.1.0

Alliance Semiconductor

P. 1 of 16

Features

• Organization: 4,194,304 words × 4 bits

• High speed

- 50/60 ns RAS

access time

- 25/30 ns column address access time

- 12/15 ns CAS

access time

• Low power consumption

- Active: 495 mW max

- Standby: 5.5 mW max, CMOS I/O

• Extended data out

•Refresh

- 4096 refresh cycles, 64 ms refresh interval for
4C4M4EOQ

- 2048 refresh cycles, 32 ms refresh interval for

AS4C4M4E1Q

-RAS

-only and hidden refresh or CAS-before-RAS refresh

or self-refresh

• TTL-compatible

•4 separate CAS

pins allow for separate I/O operation

• JEDEC standard package

- 300 mil, 28-pin SOJ

- 300 mil, 28-pin TSOP

• 5V power supply

• Latch-up current ≥ 200 mA

• ESD protection ≥ 2000 mV

Pin arrangement

A8
A7
A6
A5
A4

A10

A0
A1
A2
A3

V

CC

GND

GND
I/O3
I/O2
CAS

3

OE

V

CC

I/O0
I/O1

WE

RAS

1
2
3
4
5

28
27
26
25
24

*NC/A11 A9623

9
10
11
12
13

20
19
18
17
16

14 15

SOJ

AS4C4M4E0

A8
A7
A6
A5
A4

A10

A0
A1
A2
A3

V

CC

GND

GND
I/O3
I/O2
CAS

3

OE

V

CC

I/O0
I/O1

WE

RAS

1
2
3
4
5

28
27
26
25
24

*NC/A11 A9

623

9

10

11
12
13

20
19
18
17
16

14 15

TSOP

AS4C4M4E0

* NC on 2K refresh version; A11 on 4K refresh version

CAS0
CAS

1

7
8

CAS2

22
21

NC

CAS0
CAS

1

7
8

NC

22
21

CAS

2

Pin designation

Pin(s) Description

A0 to A11 Address inputs

RAS

Row address strobe

CAS

Column address strobe

WE

Write enable

I/O0 to I/O3 Input/output

OE

Output enable

V

CC

Power

GND Ground

NC No Connection

Selection guide

Symbol 4C4M4EOQ/E1Q-50 4C4M4EOQ/E1-60 Unit

Maximum RAS

access time t

RAC

50 60 ns

Maximum column address access time t

CAA

25 30 ns

Maximum CAS

access time t

CAC

12 15 ns

Maximum output enable (OE

) access time t

OEA

13 15 ns

Minimum read or write cycle time t

RC

85 100 ns

Minimum hyper page mode cycle time t

PC

20 24 ns

Maximum operating current I

CC1

110 100 mA

Maximum CMOS standby current I

CC5

1.0 1.0 mA

AS4C4M4EOQ

AS4C4M4E1Q

®

3/22/01; v.1.0

Alliance Semiconductor

P. 2 of 16

Functional description

The 4C4M4EOQ, and AS4C4M4E1Q are high performance 16-megabit CMOS Quad CAS Dynamic Random Access Memories (DRAM)
organized as 4,194,304 words × 4 bits. The devices are fabricated using advanced CMOS technology and innovative design techniques
resulting in high speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family
is optimized for use as main memory in PC, workstation, router and switch applications.

These products feature a high speed page mode operation where read and write operations within a single row (or page) can be executed at
very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the
falling edge of RAS

and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of

column addresses prior to CAS

assertion.

Extended data out (EDO) read mode enables 50 MHz operation using 50 ns devices. Four individual CAS pins allow for separate I/O
operation which enables the device to operate in parity mode. In contrast to 'fast page mode' devices, data remains active on outputs after
CAS is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance and prevent bus
contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of RAS

and CAS

going high.

Refresh on the 4096 address combinations of A0 to A11 must be performed every 64 ms using:

•RAS

-only refresh: RAS is asserted while CAS is held high. Each of the 4096 rows must be strobed. Outputs remain high impedence.

• Hidden refresh: CAS

is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with

previous valid data.

•CAS

-before-RAS refresh (CBR): At least one CAS is asserted prior to RAS. Refresh address is generated internally.

Outputs are high-impedence (OE

and WE are don't care).

• Normal read or write cycles refresh the row being accessed.

• Self-refresh cycles

Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:

•RAS

-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.

• Hidden refresh: CAS

is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with

previous valid data.

•CAS

-before-RAS refresh (CBR): At least one CAS is asserted prior to RAS. Refresh address is generated internally.

Outputs are high-impedence (OE

and WE are don't care).

• Normal read or write cycles refresh the row being accessed.

• Self-refresh cycles

The 4C4M4EOQ and AS4C4M4E1Q are available in the standard 28-pin plastic SOJ and 28-pin plastic TSOP packages. The 4C4M4EOQ and
AS4C4M4E1Q operate with a single power supply of 5V ± 0.5V. All provide TTL compatible inputs and outputs.

®

AS4C4M4EOQ

AS4C4M4E1Q

3/22/01; v.1.0

Alliance Semiconductor

P. 3 of 16

Logic block diagram for 4K refresh

Logic block diagram for 2K refresh

Recommended operating conditions

†

VIL min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified.

Parameter Symbol Min Nominal Max Unit

Supply voltage

4C4M4EOQ
AS4C4M4E1Q

V

CC

4.5 5.0 5.5 V

GND 0.0 0.0 0.0 V

Input voltage

4C4M4EOQ
AS4C4M4E1Q

V

IH

2.4 – V

CC

V

V

IL

–0.5

†

–0.8V

Ambient operating temperature T

A

070°C

RAS clock
generator

Refresh

controller

4,194,304 × 4

Array

(16,777,216)

Sense amp

A0
A1
A2
A3
A4
A5
A6
A7

V

CC

GND

Address buffers

A8

Row decoder

Column decoder

Data

I/O

buffers

OE

RAS

CAS

WE clock
generator

WE

I/O0 to I/O3

CAS clock
generator

A9
A10
A11

RAS clock
generator

Refresh

controller

4,194,304 × 4

Array

(16,777,216)

Sense amp

A0

A1

A2

A3

A4

A5

A6

A7

V

CC

GND

Address buffers

A8

Row decoder

Column decoder

Substrate bias

generator

Data

I/O

buffers

OE

RAS

CAS

WE clock
generator

WE

I/O0 to I/O3

CAS clock
generator

A9
A10

AS4C4M4EOQ

AS4C4M4E1Q

®

3/22/01; v.1.0

Alliance Semiconductor

P. 4 of 16

Absolute maximum ratings

DC electrical characteristics (AS4C4M4E0/E1)

Parameter Symbol Min Max Unit

Input voltage V

in

-1.0 +7.0 V

Input voltage (DQs) V

DQ

-1.0 VCC + 0.5 V

Power supply voltage V

CC

-1.0 +7.0 V

Storage temperature (plastic) T

STG

-55 +150 °C

Soldering temperature × time T

SOLDER

–260 × 10

o

C × sec

Power dissipation P

D

–1W

Short circuit output current I

out

–50mA

Parameter Symbol Test conditions

-50 -60

Unit NotesMin Max Min Max

Input leakage current I

IL

0V ≤ Vin ≤ +5.5V,

Pins not under test = 0V

-5 +5 -5 +5 µA

Output leakage current I

OL

D

OUT

disabled, 0V ≤ V

out

≤ +5.5V -5 +5 -5 +5 µA

Operating power
supply current

I

CC1

RAS, UCAS, LCAS, Address cycling;
t

RC

=min

– 110 – 100 mA 1,2

TTL standby power
supply current

I

CC2

RAS = UCAS = LCAS ≥ V

IH

–2.0 – 2.0mA

Average power supply
current, RAS

refresh

mode or CBR

I

CC3

RAS cycling, UCAS = LCAS ≥ V

IH

,

t

RC

= min of RAS low after XCAS

low.

– 110 – 100 mA 1

EDO page mode
average power supply
current

I

CC4

RAS = VIL, UCAS or LCAS,
address cycling: t

HPC

= min

–90 – 80mA1, 2

CMOS standby power
supply current

I

CC5

RAS = UCAS = LCAS = VCC - 0.2V – 1.0 – 1.0 mA

Output voltage

V

OH

I

OUT

= -5.0 mA 2.4 – 2.4 – V

V

OL

I

OUT

= 4.2 mA – 0.4 – 0.4 V

CAS

before RAS refresh

current

I

CC6

RAS, UCAS or LCAS cycling, tRC =
min

– 110 – 100 mA

Self refresh current I

CC7

RAS = UCAS = LCAS ≤ 0.2V,

WE

= OE ≥ V

CC

- 0.2V,
all other inputs at 0.2V or
V

CC

- 0.2V

–0.6 – 0.6

mA

®

AS4C4M4EOQ

AS4C4M4E1Q

3/22/01; v.1.0

Alliance Semiconductor

P. 5 of 16

DC electrical characteristics (AS4LC4M4E0/E1)

Parameter Symbol Test conditions

-50 -60

Unit NotesMin Max Min Max

Input leakag

e c

urrent I

IL

0V ≤ Vin ≤ V

CC

(max)

Pins not under test = 0V

-5 +5 -5 +5

µ

A

Output leakage current I

OL

D

OUT

disabled, 0V ≤ V

out

≤ V

CC

(max)

-5 +5 -5 +5

µ

A

Operating power
supply current

I

CC1

RAS, UCAS, LCAS, Address cycling;
t

RC

=min

– 85 – 75 mA 4,5

TTL standby power
supply current

I

CC2

RAS = UCAS = LCAS ≥ V

IH

,

all other inputs at V

IH

or V

IL

–2.0–2.0mA

Average power supply
current, RAS

refresh

mode or CBR

I

CC3

RAS cycling, UCAS = LCAS ≥ V

IH

,

t

RC

= min of RAS low after XCAS low.

–80–70mA4

EDO page mode
average power supply
current

I

CC4

RAS = VIL, UCAS or LCAS,
address cycling: t

HPC

= min

– 85 – 75 mA 4, 5

CMOS standby power
supply current

I

CC5

RAS = UCAS = LCAS = VCC - 0.2V,
F = 0

–200–200µA

Output voltage

V

OH

I

OUT

= -2.0 mA 2.4 – 2.4 – V

V

OL

I

OUT

= 2 mA –0.4–0.4V

CAS

before RAS refresh

current

I

CC6

RAS, UCAS or LCAS cycling, tRC =
min

–80–70

mA

Self refresh current I

CC7

RAS = UCAS = LCAS ≤ 0.2V,

WE

= OE = VCC - 0.2V,

all other inputs at 0.2V or V

CC

-

0.2V

–0.3–0.3

mA