Alliance Semiconductor ASM5P23S04A Service Manual

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查询ASM5I23S04A-1H-08-SR供应商

September 2005 ASM5P23S04A

rev 1.3

3.3V ‘SpreadTrak’ Zero Delay Buffer

Features

 Zero input - output propagation delay, adjustable

by capacitive load on FBK input.

 Multiple configurations - Refer “ASM5P23S04A

Configurations Table”.

 Input frequency range: 15MHz to 133MHz

 Multiple low-skew outputs.

 Output-output skew less than 200pS.

 Device-device skew less than 500pS.

 Two banks of two outputs each.

 Less than 200pS Cycle-to-cycle jitter

(-1, -1H, -2, -2H).

 Available in space saving, 8 pin 150-mil SOIC

package.

 3.3V operation.

 Advanced 0.35µ CMOS technology.

 Industrial temperature available.

 ‘SpreadTrak’.

Functional Description

ASM5P23S04A is a versatile, 3.3V zero-delay buffer

designed to distribute high-speed clocks in PC,

workstation, datacom, telecom and other high-performance

applications. It is available in a 8 pin package. The part has

an on-chip PLL, which locks to an input clock, presented on

Block Diagram

the REF pin. The PLL feedback is required to be driven to

FBK pin, and can be obtained from one of the outputs. The

input-to-output propagation delay is guaranteed to be less

than 250pS, and the output-to-output skew is guaranteed to

be less than 200pS.

The ASM5P23S04A has two banks of two outputs each.

Multiple ASM5P23S04A devices can accept the same input

clock and distribute it. In this case the skew between the

outputs of the two devices is guaranteed to be less than

500pS.

The ASM5P23S04A is available in two different

configurations (Refer “ASM5P23S04A Configurations

Table). The ASM5P23S04A-1 is the base part, where the

output frequencies equal the reference if there is no

counter in the feedback path. The ASM5P23S04A-1H is

the high-drive version of the -1 and the rise and fall times

on this device are much faster.

The ASM5P23S04A-2 allows the user to obtain REF and

1/2X or 2X frequencies on each output bank. The exact

configuration and output frequencies depend on which

output drives the feedback pin.

FBK

CLKA1

REF

PLL

Alliance Semiconductor

2

Extra Divider

CLKA2

-2

CLKB1

CLKB2

2575 Augustine Drive • Santa Clara, CA • Tel: [phone] • Fax: [phone] • www.alsc.com

Notice: The information in this document is subject to change without notice.

September 2005

ASM5P23S04A

rev 1.3

ASM5P23S04A Configurations

Device Feedback From Bank A Frequency Bank B Frequency

ASM5P23S04A-1 Bank A or Bank B Reference Reference

ASM5P23S04A-1H Bank A or Bank B Reference Reference

ASM5P23S04A-2 Bank A Reference Reference /2

ASM5P23S04A-2 Bank B 2 X Reference Reference

ASM5P23S04A-2H Bank A Reference Reference/2

ASM5P23S04A-2H Bank B 2 X Reference Reference

‘SpreadTrak’

Many systems being designed now utilize a technology

called Spread Spectrum Frequency Timing Generation.

ASM5P23S04A is designed so as not to filter off the

Spread Spectrum feature of the Reference Input,

assuming it exists. When a zero delay buffer is not

designed to pass the Spread Spectrum feature through,

the result is a significant amount of tracking skew which

may cause problems in the systems requiring

synchronization.

1500

1000

500

0

-30

-25

-20 -15 -10 -5

-500

-1000

REF-Input to CLKA/CLKB Delay (ps)

-1500

REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins

Output Load Difference: FBK Load - CLKA/CLKB Load (pF)

0

5

10 15 20 25

30

3.3 Zero ‘SpreadTrak’ Delay Buffer 2 of 15

Notice: The information in this document is subject to change without notice.

September 2005

ASM5P23S04A

rev 1.3

Zero Delay and Skew Control

For applications requiring zero input-output delay, all

outputs must be equally loaded. To close the feedback loop

of ASM5P23S04A, the FBK pin can be driven from any of

the four available output pins. The output driving the FBK

pin will be driving a total load of 7pF plus any additional

load that it drives. The relative loading of this output (with

respect to the remaining outputs) can adjust the input

Pin Configuration

GND

1

2

ASM5P23S04A

3

4

Pin Description for ASM5P23S04A

REF

CLKA1

CLKA2

output delay. This is shown in the above graph. For

applications requiring zero input-output delay, all outputs

including the one providing feedback should be equally

loaded. If input-output delay adjustments are required, use

the above graph to calculate loading differences between

the feedback output and remaining outputs. For zero

output-output skew, be sure to load outputs equally.

8FBK

7

V

DD

CLKB2

6

5

CLKB1

Pin # Pin Name Description

1 REF1 Input reference frequency, 5V tolerant input

2 CLKA12 Buffered clock output, bank A

3 CLKA22 Buffered clock output, bank A

4 GND Ground

5 CLKB12 Buffered clock output, bank B

6 CLKB2

7 VDD 3.3V supply

8 FBK PLL feedback input

Notes:

1. Weak pull-down.

2. Weak pull-down on all outputs.

2

Buffered clock output, bank B

3.3 Zero ‘SpreadTrak’ Delay Buffer 3 of 15

Notice: The information in this document is subject to change without notice.

September 2005

ASM5P23S04A

rev 1.3

Absolute Maximum Ratings

Parameter Min Max Unit

Supply Voltage to Ground Potential -0.5 +7.0 V

DC Input Voltage (Except REF) -0.5 VDD + 0.5 V

DC Input Voltage (REF) -0.5 7 V

Storage Temperature -65 +150 °C

Max. Soldering Temperature (10 sec) 260 °C

Junction Temperature 150 °C

Static Discharge Voltage

(As per JEDEC STD22- A114-B)

>2000 V

Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device

reliability.

Operating Conditions for ASM5P23S04A Commercial Temperature Devices

Parameter Description Min Max Unit

VDD Supply Voltage 3.0 3.6 V

TA Operating Temperature (Ambient Temperature) 0 70 °C

CL Load Capacitance, below 100MHz 30 pF

CL Load Capacitance, from 100MHz to 133MHz 15 pF

CIN Input Capacitance3 7 pF

Note:

3. Applies to both Ref Clock and FBK.

3.3 Zero ‘SpreadTrak’ Delay Buffer 4 of 15

Notice: The information in this document is subject to change without notice.

September 2005

ASM5P23S04A

rev 1.3

Electrical Characteristics for ASM5P23S04A Commercial Temperature Devices

Parameter Description Test Conditions Min Max Unit

VIL Input LOW Voltage 0.8 V

VIH Input HIGH Voltage 2.0 V

IIL Input LOW Current VIN = 0V 50.0 µA

IIH Input HIGH Current VIN = VDD 100.0 µA

I

= 8mA (-1, -2)

VOL Output LOW Voltage 4

VOH Output HIGH Voltage 4

OL

I

= 12mA (-1H, -2H)

OH

I

= -8mA (-1, -2)

OL

IOH = -12mA (-1H, -2H)

0.4 V

2.4 V

Unloaded outputs 100MHz REF,

Select inputs at V

IDD Supply Current

Note:

4. Parameter is guaranteed by design and characterization. Not 100% tested in production.

Unloaded outputs, 66MHz REF

(-1, -2)

Unloaded outputs, 33MHz REF

(-1, -2)

or GND

DD

45.0

mA

32.0

18.0

3.3 Zero ‘SpreadTrak’ Delay Buffer 5 of 15

Notice: The information in this document is subject to change without notice.