Alliance Semiconductor AS7C4096, AS7C34096 Service Manual

查询AS7C34096-10供应商
January 2005
Features
• AS7C34096 (3.3V version)
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 1375 mW (AS7C4096) / max @ 12 ns
- 576 mW (AS7C34096) / max @ 10 ns
®
5V/3.3V 512K × 8 CMOS SRAM
• Low power consumption: STANDBY
- 110 mW (AS7C4096) / max CMOS
- 72 mW (AS7C34096) / max CMOS
• Equal access and cycle times
• Easy memory expansion with
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
• ESD protection 2000 volts
• Latch-up current 100 mA
CE, OE
AS7C4096
AS7C34096
inputs
Logic block diagram
V
CC
GND
Input buffer
A0 A1 A2 A3 A4 A5 A6 A7 A8
A9
524,288 × 8
(4,194,304)
Row decoder
Column decoder
A10
A11
A12
Array
A13
A14
A15
A16
A17
A18
Sense amp
Control
Circuit
I/O1
I/O8
WE OE CE
Pin arrangements
36-pin SOJ (400 mil) 44-pin TSOP 2
A0 A1 A2 A3 A4
CE I/O1 I/O2
V GND I/O3 I/O4
WE
A5 A6 A7 A8 A9
CC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
NC
36
A18
35
A17
34
A16
33
A15
32
OE
31 30
I/O8
29
I/O7
28
GND V
27 26 25 24 23 22 21 20 19
CC
I/O6 I/O5 A14 A13 A12 A11 A10 NC
NC
NC A0 A1 A2 A3 A4 CE
I/O1 I/O2
V
GND I/O3 I/O4
WE
A5 A6 A7 A8 A9
NC
NC
CC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
Selection guide
–10 –12 –15 –20 Unit
Maximum address access time 10 12 15 20 ns
Maximum outputenable access time 5 6 7 8 ns
Maximum operating current
Maximum CMOS standby current
AS7C4096 250 220 180 mA
AS7C34096 160 130 110 100 mA
AS7C4096 20 20 20 mA
AS7C34096 20 20 20 20 mA
NC NC NC
A18 A17
A16 A15 OE I/O8 I/O7 GND
V
CC
I/O6 I/O5 A14 A13 A12 A11 A10 NC NC NC
1/13/05; v.1.9 Alliance Semiconductor P. 1 of 9
Copyright © Alliance Semiconductor. All rights reserved.
AS7C4096
AS7C34096
®
Functional description
The AS7C4096 and AS7C34096 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices organized as 524,288 words × 8 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t ideal for high-performance applications. The chip enable input CE memory systems.
When CE
is high the device enters standby mode. The AS7C4096/AS7C34096 is guaranteed not to exceed 110/72 mW power
consumption in CMOS standby mode.
A write cycle is accomplished by asserting write enable (WE written on the rising edge of WE
(write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/
O pins only after outputs have been disabled with output enable (OE
A read cycle is accomplished by asserting output enable (OE drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from either a single 5V(AS7C4096) or 3.3V(AS7C34096) supply. Both devices are available in the JEDEC standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.
, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are
AA
permits easy memory expansion with multiple-bank
) and chip enable (CE). Data on the input pins I/O1–I/O8 is
) or write enable (WE).
) and chip enable (CE), with write enable (WE) high. The chip
Absolute maximum ratings
Parameter Device Symbol Min Max Unit
Voltage on V
relative to GND
CC
AS7C4096 V
AS7C34096 V
Voltage on any pin relative to GND V
Power dissipation P
Storage temperature T
Temperature with V
applied T
CC
DC current unto output (low) I
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func­tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
t1
t1
t2
D
stg
bias
OUT
–1 +7.0 V
–0.5 +5.0 V
–0.5 VCC +0.5 V
–1.0W
–65 +150 °C
–55 +125 °C
–20mA
Truth table
CE WE OE Data Mode
H X X High Z Standby (I
L H H High Z Output disable (I
LHL D
LLX D
Key: X = Don’t care, L = Low, H = High
OUT
IN
Read (ICC)
Write (ICC)
SB
, I
SB1
CC
)
)
1/13/05; v.1.9 Alliance Semiconductor P. 2 of 9
®
Recommended operating condition
Parameter Device Symbol Min Nominal Max Unit
(12/15/20) 4.5 5.0 5.5 V
CC
(10) 3.15 3.30 3.6 V
CC
(12/15/20) 3.0 3.3 3.6 V
CC
IH
IH
1
V
IL
A
A
Supply voltage
Input voltage
Ambient operating temperature
min = –1.0V for pulse width less than 5ns.
1 V
IL
commercial T
industrial T
AS7C4096 V
AS7C34096 V
AS7C34096 V
AS7C4096 V
AS7C34096 V
DC operating characteristics (over the operating range)1
Parameter Symbol Test c on d i ti o ns Device
Input leakage
current
Output
leakage
current
Operating
power supply
current
Standby
power supply
current
Output voltage
|I
|VCC = Max, VIN = GND to V
LI
= Max, CE = V
V
|I
|
LO
I
CC
I
SB
CC
V
= GND to V
OUT
VCC = Max, CE < V
f = f
Max
, I
OUT
= 0mA
VCC = Max, CE = V
f = f
Max
, I
OUT
= 0mA
VCC = Max,
CE
V
I
V
V
SB1
OL
OH
– 0.2V, VIN 0.2V or VIN
CC
V
– 0.2V, f = 0
CC
IOL = 8 mA, VCC = Min AS7C4096/
IOH = –4 mA, VCC = Min 2.4–2.4–2.4–2.4– V
IH
CC
IL
IH
AS7C4096/
CC
AS7C34096
AS7C4096/
AS7C34096
AS7C4096 250 220 180 mA
AS7C34096 160 130 110 100
AS7C4096– – –60–60–60
AS7C34096 60 60 60 60
AS7C4096– – –20–20–20
AS7C34096 20 20 20 20
AS7C34096
AS7C4096
AS7C34096
2.2 VCC + 0.5 V
2.0 VCC + 0.5 V
–0.5 0.8 V
0– 70°C
–40 85 °C
–10 –12 –15 –20
UnitMin Max Min Max Min Max Min Max
–1–1–1–1µA
–1–1–1–1µA
mA
mA
–0.4–0.4–0.4–0.4V
Capacitance (f = 1MHz, TA= 25° C, VCC = NOMINAL)
2
Parameter Symbol Signals Test conditions Max Unit
Input capacitance C
I/O capacitance C
1/13/05; v.1.9 Alliance Semiconductor P. 3 of 9
IN
I/O
A, CE, WE, OE VIN = 0V 5 pF
I/O VIN = V
= 0V 7 pF
OUT
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