Alliance Semiconductor AS7C3364PFD32B, AS7C3364PFD36B Service Manual

查询AS7C3364PFD32B供应商查询AS7C3364PFD32B供应商

February 2005

3.3V 64K X 32/36 pipeline burst synchronous SRAM

AS7C3364PFD32B
AS7C3364PFD36B

®

Features

• Organization: 65,536 words × 32 or 36 bits

• Fast clock speeds to 200 MHz

• Fast clock to data access: 3.0/3.5/4.0 ns

•Fast OE

access time: 3.0/3.5/4.0 ns

• Fully synchronous register-to-register operation

• Double-cycle deselect

• Asynchronous output enable control

• Available in 100-pin TQFP package

Logic block diagram

CLK

ADV
ADSC
ADSP

A[15:0]

GWE
BWE

BW

d

BW

c

BW

b

BW

a

CE0
CE1

CE2

Power

ZZ

down

OE

CLK

CE
CLR

16

DQ
CE
CLK

DQ

CLK

DQ

CLK

DQ

CLK

DQ

CLK

DQ

CE
CLK

DQ

CLK

Address
register

DQ

d

Byte write

registers

DQ

c

Byte write

registers

DQ

b

Byte write

registers

DQ

a

Byte write

registers

Enable

register

Enable

delay

register

• Linear or interleaved burst control

• Individual byte write and global write

• Snooze mode for reduced power-standby

• Common data inputs and data outputs

• Multiple chip enables for easy expansion

• 3.3V core power supply

• 2.5V or 3.3V I/O operation with separate V

LBO

Q0

Burst logic

Q1

64K × 32/36

Memory

161416

array

36/32

4

OE

Output

registers

CLK CLK

36/32

DQ [a:d]

36/32

registers

Input

DDQ

Selection guide

–200 –166 –133 Units

Minimum cycle time 5 6 7.5 ns
Maximum clock frequency 200 166 133 MHz
Maximum clock access time 3.0 3.5 4 ns
Maximum operating current 375 350 325 mA
Maximum standby current 130 100 90 mA
Maximum CMOS standby current (DC) 30 30 30 mA

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Copyright © Alliance Semiconductor. All rights reserved.

AS7C3364PFD32B
AS7C3364PFD36B

®

2 Mb Synchronous SRAM products list

Org Part Number Mode Speed

128KX18 AS7C33128PFS18B PL-SCD 200/166/133 MHz

64KX32
64KX36 AS7C3364PFS36B PL-SCD 200/166/133 MHz

128KX18 AS7C33128PFD18B PL-DCD 200/166/133 MHz

64KX32
64KX36 AS7C3364PFD36B PL-DCD 200/166/133 MHz

128KX18 AS7C33128FT18B FT 6.5/7.5/8.0/10 ns

64KX32
64KX36 AS7C3364FT36B FT 6.5/7.5/8.0/10 ns

AS7C3364PFS32B PL-SCD 200/166/133 MHz

AS7C3364PFD32B PL-DCD 200/166/133 MHz

AS7C3364FT32B FT 6.5/7.5/8.0/10 ns

1,2

1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V +

VDDQ = 2.5V +

0.165V for 3.3V I/O

0.125V for 2.5V I/O

PL-SCD : Pipelined Burst Synchronous SRAM - Single Cycle Deselect
PL-DCD : Pipelined Burst Synchronous SRAM - Double Cycle Deselect
FT : Flow-through Burst Synchronous SRAM

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Pin arrangement

DQPc/NC

DQPd/NC

DQ
DQ

V

V
DQ
DQ
DQ
DQ
V

V

DQ
DQ

DQ
DQ

V

V
DQ
DQ
DQ
DQ
V

V

DQ
DQ

DDQ

SSQ

SSQ

DDQ

NC

V

DD

NC

V

DDQ

SSQ

SSQ

DDQ

c0
c1

c2
c3
c4
c5

c6
c7

SS

d0
d1

d2
d3
d4
d5

d6
d7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

®

DD

AACE0

100

CE1

BWdBWcBWbBWaCE2

99989796959493929190898887868584838281

V

VSSCLK

GWE

BWEOEADSC

ADSP

ADVAA

TQFP 14 × 20 mm

AS7C3364PFD32B
AS7C3364PFD36B

/NC

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DQP

b

DQ

b7

DQ

b6

V

DDQ

V

SSQ

DQ

b5

DQ

b4

DQ

b3

DQ

b2

V

SSQ

V

DDQ

DQ

b1

DQ

b0

V

SS

NC
VDD
ZZ
DQ

a7

DQ

a6

V

DDQ

V

SSQ

DQ

a5

DQ

a4

DQ

a3

DQ

a2

V

SSQ

V

DDQ

DQ

a1

DQ

a0

DQPa/NC

31323334353637383940414243444546474849

AAA

LBO

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A

A1

A0

Note: Pins 1,30,51,80 are NC for X32

NC

NC

V

SS

DD

V

AAAAA

NC

NC

50

A

NC

AS7C3364PFD32B
AS7C3364PFD36B

®

Functional description

The AS7C3364PFD32B and AS7C3364PFD36B are high-performance CMOS 2-Mbit synchronous Static Random Access
Memory (SRAM) devices organized as 65,536 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for
highest frequency on any given technology.

Timing for these devices is compatible with existing Pentium
for ASIC, DSP and PowerPC

™1

-based systems in computing, datacom, instrumentation, and telecommunications systems.

®

synchronous cache specifications. This architecture is suited

Fast cycle times of 5.0/6.0/7.5 ns with clock access times (t
frequencies. Three chip enable (CE
controller address strobe (ADSC

) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the

), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent

) of 3.0/3.5/4.0 ns enable 200, 166 and 133 MHz bus

CD

internally generated burst addresses.
Read cycles are initiated with ADSP

address register when ADSP

is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In

(regardless of WE and ADSC) using the new external address clocked into the on-chip

a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are
carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV
edge that samples ADSP
access of the burst when ADV
input. With

LBO

unconnected or driven High, burst operations use a Pentium® count sequence. With

device uses a linear count sequence suitable for PowerPC
Write cycles are performed by disabling the output buffers with OE

GWE

writes all 32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more

bytes may be written by asserting BWE
BWn

is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are
disabled when BWn
Low. Address is incremented internally to the next burst address if BWn

asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next

is sampled Low, and both address strobes are High. Burst mode is selectable with the

™

and many other applications.

and asserting a write command. A global write enable

and the appropriate individual byte BWn signal(s).

is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled

and ADV are sampled Low. This device operates in

is ignored on the clock

LBO

LBO

driven LOW, the

double-cycle deselect feature during read cycles.
Read or write cycles may also be initiated with ADSC

instead of ADSP. The differences between cycles initiated with ADSC

and ADSP are as follows:

• ADSP

•WE

• Master chip enable CE0

must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.

signals are sampled on the clock edge that samples ADSC LOW (and ADSP High).

blocks ADSP, but not ADSC.

AS7C3364PFD32B and AS7C3364PFD36B family operates from a core 3.3V power supply. I/Os use a separate power supply
that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package.

TQFP capacitance

Parameter Symbol Test conditions Min Max Unit

Input capacitance C

I/O capacitance C

* Guaranteed not tested

IN

I/O

*

*

VIN = 0V - 5 pF

V

= 0V - 7 pF

OUT

TQFP thermal resistance

Description Conditions Symbol Typ ic al Units

Thermal resistance
(junction to ambient)

Thermal resistance
(junction to top of case)

1 This parameter is sampled

1PowerPC™ is a trademark International Business Machines Corporation.

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1

1

Test conditions follow standard test methods and

procedures for measuring thermal impedance,

per EIA/JESD51

1–layer θ

4–layer θ

JA

JA

θ

JC

40 °C/W

22 °C/W

8 °C/W

AS7C3364PFD32B
AS7C3364PFD36B

®

Signal descriptions

Signal I/O Properties Description

CLK I CLOCK Clock. All inputs except
A,A0,A1 I SYNC Address. Sampled when all chip enables are active and
DQ[a,b,c,d] I/O SYNC Data. Driven as output when the chip is enabled and

CE0

CE1,

ADSP

ADSC
ADV

GWE

BWE

CE2

I SYNC

I SYNC

I SYNC

I SYNC Address strobe controller. Asserted LOW to load a new address or to enter standby mode.
I SYNC Advance. Asserted LOW to continue burst read/write.

I SYNC

I SYNC Byte write enable. Asserted LOW with

Master chip enable. Sampled on clock edges when
is inactive,

ADSP

Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock
edges when

ADSC

Address strobe processor. Asserted LOW to load a new bus address or to enter standby
mode.

Global write enable. Asserted LOW to write all 32/36 bits. When High,
BW[a:d]

control write enable.

Write enables. Used to control write of individual bytes when

BW[a,b,c,d]

I SYNC

Low. If any of

BW[a:d]

write cycle. If all

OE

I ASYNC

Asynchronous output enable. I/O pins are driven when
mode.

Selects Burst mode. When tied to V

LBO

ISTATIC

order. When driven Low, device follows linear Burst order. This signal is internally

pulled High.

ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC - - No connect

OE

, ZZ,

LBO

are synchronous to this clock.

ADSC

or

ADSP

are asserted.

OE

is active.

ADSP

or

ADSC

is active. When

is blocked. Refer to the Synchronous Truth Table for more information.

is active or when

is active with

BW[a:d]

are inactive the cycle is a read cycle.

CE0

and

ADSP

are active.

BWE

and

GWE

= HIGH to enable effect of

GWE

GWE

= HIGH and

or left floating, device follows Interleaved Burst

DD

BWE

= LOW the cycle is a

OE

is active and the chip is in read

BW[a:d]

= HIGH and

inputs.

BWE

CE0

=

Snooze Mode

SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.

The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.

When the ZZ pin becomes a logic High, I
disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during t
MODE.

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, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE

PUS

is guaranteed after the time t

SB2

is met. After entering SNOOZE MODE, all inputs except ZZ is

ZZI

. The duration of

SB2

®

Write enable truth table (per byte)

Function GWE BWE BWa BWb BWc BWd

Write All Bytes

Write Byte a

Write Byte c and d

Read

Key: X = don’t care, L = low, H = high, n = a, b, c, d;

LXXXXX
HLLLLL
HLLHHH
HLHHLL
HHXXXX
HLHHHH

BWE, BWn

= internal write signal.

Asynchronous Truth Table

Operation ZZ OE I/O Status

Snooze mode H X High-Z

Read

Write L X Din, High-Z
Deselected L X High-Z

Notes:

1. X means “Don’t Care”

2. ZZ pin is pulled down internally

3. For write cycles that follows read cycles, the output buffers must be disabled with OE

4. Snooze mode means power down state of which stand-by current does not depend on cycle times

5. Deselected means power down state of which stand-by current depends on cycle times

L L Dout
L H High-Z

, otherwise data bus contention will occur.

AS7C3364PFD32B
AS7C3364PFD36B

Burst sequence table

Interleaved burst address (LBO = 1) Linear burst address (LBO = 0)

A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0

1st Address

nd

2

Address

rd

3

Address

th

4

Address

0 00 11 01 1
0 10 01 11 0
1 01 10 00 1
1 11 00 10 0

1st Address

nd

2

Address

rd

3

Address

th

4

Address

0 00 11 01 1
0 11 01 10 0
1 01 10 00 1
1 11 00 11 0

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