Alliance Semiconductor AS7C3364NTF32B, AS7C3364NTF36B Service Manual

April 2005

AS7C3364NTF32B
AS7C3364NTF36B

®

3.3V 64K × 32/36 Flowthrough Synchronous SRAM with NTD

Features

• Organization: 65,536 words × 32 or 36 bits

™

•NTD

• Fast clock to data access: 7.5/8.0/10.0 ns

•Fast OE

• Fully synchronous operation

• Flow-through mode

• Asynchronous output enable control

• Available in 100-pin TQFP package

• Byte write enables

• Clock enable for operation hold

Logic block diagram

architecture for efficient bus operation

access time: 3.5/4.0 ns

R/W

BWa

BWb
BWc

BWd

LBO

16

ZZ

A[15:0]

CE0
CE1

CE2

ADV / LD

D

Address

register

Burst logic

Control

logic

CLK

CLK

TM

• Multiple chip enables for easy expansion

• 3.3V core power supply

• 2.5V or 3.3V I/O operation with separate V

DDQ

• Self-timed write cycles

• Interleaved or linear burst modes

• Snooze mode for standby operation

Q

16

D

addr. registers

Write delay

CLK

Q

16

CLK

Write Buffer

64K x 32/36

SRAM

Array

DQ[a,b,c,d]

CLK

CEN

32/36

D

Data

Input

Register

CLK

Q

32/36

OE

32/36

OE

32/36

Output

32/36

Buffer

32/36

DQ[a,b,c,d]

Selection guide

-75 -80 -10 Units

Minimum cycle time 8.5 10 12 ns

Maximum clock access time 7.5 8.0 10 ns

Maximum operating current 260 230 200 mA

Maximum standby current 110 100 90 mA

Maximum CMOS standby current (DC) 30 30 30 mA

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Copyright © Alliance Semiconductor. All rights reserved.

AS7C3364NTF32B/36B

®

2 Mb Synchronous SRAM products list

Org Part Number Mode Speed

128KX18 AS7C33128PFS18B PL-SCD 200/166/133 MHz

64KX32

64KX36 AS7C3364PFS36B PL-SCD 200/166/133 MHz

128KX18 AS7C33128PFD18B PL-DCD 200/166/133 MHz

64KX32

64KX36 AS7C3364PFD36B PL-DCD 200/166/133 MHz

128KX18 AS7C33128FT18B FT 6.5/7.5/8.0/10 ns

64KX32

64KX36 AS7C3364FT36B FT 6.5/7.5/8.0/10 ns

128KX18 AS7C33128NTD18B NTD-PL 200/166/133 MHz

64KX32

64KX36 AS7C3364NTD36B NTD-PL 200/166/133 MHz

128KX18 AS7C33128NTF18B NTD-FT 7.5/8.0/10 ns

64KX32

64KX36 AS7C3364NTF36B NTD-FT 7.5/8.0/10 ns

AS7C3364PFS32B PL-SCD 200/166/133 MHz

AS7C3364PFD32B PL-DCD 200/166/133 MHz

AS7C3364FT32B FT 6.5/7.5/8.0/10 ns

AS7C3364NTD32B NTD-PL 200/166/133 MHz

AS7C3364NTF32B NTD-FT 7.5/8.0/10 ns

1,2

3

1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V +

VDDQ = 2.5V +

0.165V for 3.3V I/O

0.125V for 2.5V I/O

3 Refer corresponding product datasheets for the latest information on Clock Speed and Clock Access Time availability.

PL-SCD : Pipelined Burst Synchronous SRAM - Single Cycle Deselect
PL-DCD : Pipelined Burst Synchronous SRAM - Double Cycle Deselect
FT : Flow-through Burst Synchronous SRAM

1

NTD

-PL : Pipelined Burst Synchronous SRAM with NTD

NTD-FT : Flow-through Burst Synchronous SRAM with NTD

TM

TM

1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property
of their respective owners.

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100-pin TQFP - top view

NC/DQPc

DQc0
DQc1
V

DDQ

V

SSQ

DQc2
DQc3
DQc4
DQc5

V

SSQ

V

DDQ

DQc6
DQc7

NC

V

DD

NC

V

SS

DQd0
DQd1
V

DDQ

V

SSQ

DQd2
DQd3
DQd4
DQd5

V

SSQ

V

DDQ

DQd6
DQd7

NC/DQPd

®

DD

V

BWa

CE2

VSSCLK

TQFP 14 x 20mm

R/W

CENOEADV/LDNCNCAA

1
2
3
4
5
6
7
8

9
10

11
12

13
14
15
16
17
18
19
20
21
22
23

24
25
26
27
28
29
30

CE1

BWd

BWc

AACE0

99989796959493929190898887868584838281

100

BWb

31323334353637383940414243444546474849

AS7C3364NTF32B/36B

DQPb/NC

80
79

DQb7

78

DQb6

77

V
76
75
74
73
72
71
70
69

68
67

66
65
64
63
62

61
60
59
58
57

56
55

54
53

52
51

50

DDQ

V

SSQ

DQb5

DQb4

DQb3

DQb2

V

SSQ

V

DDQ

DQb1

DQb0

V

SS

NC

V

DD

ZZ

DQa7

DQa6

V

DDQ

V

SSQ

DQa5

DQa4

DQa3

DQa2

V

SSQ

V

DDQ

DQa1

DQa0

DQPa/NC

AAA

LBO

A

A1

A0

NC

NC

SS

DD

V

V

NC

NC

AAAAA

A

NC

Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration. DQPn applies to the x36 configuration.

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AS7C3364NTF32B/36B

®

Functional Description

The AS7C3364NTF32B/36B family is a high performance CMOS 2 Mbit synchronous Static Random Access Memory
(SRAM) organized as 65,536 words × 32 or 36 bits and incorporates a LATE Write.

This variation of the 2Mb+ synchronous SRAM uses the No Turnaround Delay (NTD
write operation that improves bandwidth over flowthrough burst devices. In a normal flowthrough burst device, the write data,
command, and address are all applied to the device on the same clock edge. If a read command follows this write command,
the system must wait for one dead cycle for valid data to become available. This dead cycle can significantly reduce overall
bandwidth for applications requiring random access or read-modify-write operations.

™

NTD

devices use the memory bus more efficiently by introducing a write latency which matches the one-cycle flow­through read latency. Write data is applied one cycle after the write command and address, allowing the read pipeline to clear.
With NTD

Assert R/W

™

, write and read operations can be used in any order without producing dead bus cycles.

low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 36
bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied
to the device one clock cycle later. Unlike some asynchronous SRAMs, output enable OE
operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-selected by
any of the three chip enable inputs.

Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip
select, R/W
device operations, including burst, can be stalled using the CEN

pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any

=1, the clock enable input.

™

) architecture, featuring an enhanced

does not need to be toggled for write

The AS7C3364NTF32B/36B operates with a 3.3V ± 5% power supply for the device core (V
power supply (V

) that operates across 2.5V or 3.3V ranges. These devices are available in a 100-pin TQFP package.

DDQ

TQFP Capacitance

Parameter Symbol Test conditions Min Max Unit

Input capacitance C

I/O capacitance C

*Guranteed not tested

IN

I/O

*

*

Vin = 0V - 5 pF

Vin = V

= 0V - 7 pF

out

TQFP thermal resistance

Description Conditions Symbol Typ ic al Units

Thermal resistance
(junction to ambient)

Thermal resistance
(junction to top of case)

1 This parameter is sampled

1

1

Test conditions follow standard test methods and

procedures for measuring thermal impedance,

per EIA/JESD51

1–layer θ

4–layer θ

θ

). DQ circuits use a separate

DD

JA

JA

JC

40 °C/W

22 °C/W

8 °C/W

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AS7C3364NTF32B/36B

®

Signal descriptions

Signal I/O Properties Description

CLK I CLOCK Clock. All inputs except OE

CEN

I SYNC Clock enable. When de-asserted high, the clock input signal is masked.

A, A0, A1 I SYNC Address. Sampled when all chip enables are active and ADV/LD

DQ[a,b,c,d] I/O SYNC Data. Driven as output when the chip is enabled and OE

CE0

, CE1,

CE2

ADV/LD

R/W

BW[a,b,c,d]

OE

LBO

I SYNC

I SYNC

I SYNC

I SYNC

I ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive.

ISTATIC

Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD
Are ignored when ADV/LD

Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO

A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD

Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.

Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order. This signal is internally pulled High.

ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.

NC - - No connect

, LBO, and ZZ are synchronous to this clock.

is asserted.

is active.

is asserted.

is high.

input value. When low, a new address is loaded.

is high.

Snooze Mode

SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.

The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.

When the ZZ pin becomes a logic High, I
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during t

, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.

PUS

is guaranteed after the time t

SB2

is met. After entering SNOOZE MODE, all inputs except ZZ

ZZI

. The duration of

SB2

Burst order

Interleaved burst order LBO = 1 Linear burst order LBO = 0

A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0

Starting address 0 0 0 1 1 0 1 1 Starting Address 0 0 0 1 1 0 1 1

First increment 0 1 0 0 1 1 1 0 First increment 0 1 1 0 1 1 0 0

Second increment 1 0 1 1 0 0 0 1 Second increment 1 0 1 1 0 0 0 1

Third increment 1 1 1 0 0 1 0 0 Third increment 1 1 0 0 0 1 1 0

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AS7C3364NTF32B/36B

®

Synchronous truth table

CE0 CE1 CE2 ADV/LD R/W BWn OE CEN

[5,6,7,8,9,11]

Address

source

CLK Operation DQ Notes

H X X L X X X L NA L to H DESELECT Cycle High-Z

X X H L X X X L NA L to H DESELECT Cycle High-Z

X L X L X X X L NA L to H DESELECT Cycle High-Z

X X X H X X X L NA L to H CONTINUE DESELECT Cycle High-Z 1

L H L L H X L L External L to H READ Cycle (Begin Burst) Q

X X X H X X L L Next L to H READ Cycle (Continue Burst) Q 1,10

L H L L H X H L External L to H NOP/DUMMY READ (Begin Burst) High-Z 2

X X X H X X H L Next L to H DUMMY READ (Continue Burst) High-Z 1,2,10

L H L L L L X L External L to H WRITE CYCLE (Begin Burst) D 3

X X X H X L X L Next L to H WRITE CYCLE (Continue Burst) D 1,3,10

L H L L L H X L External L to H NOP/WRITE ABORT (Begin Burst) High-Z 2,3

X X X H X H X L Next L to H WRITE ABORT (Continue Burst) High-Z

X X X X X X X H Current L to H INHIBIT CLOCK - 4

Key: X = Don’t Care, H = HIGH, L = LOW. BWn = H means all byte write signals (BWa, BWb, BWc, and BWd) are HIGH. BWn = L means one or more byte write signals are
LOW.
Notes:
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the initial BEGIN BURST

cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.

2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a WRITE command is given,

but no operation is performed.

may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE cycle. OE may be used

3 OE

when the bus turn-on and turn-off times do not meet an application’s requirements.

4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will remain in High-Z. No

WRITE operations will be performed during the INHIBIT CLOCK cycle.

a enables WRITEs to byte “a” (DQa pins); BWb enables WRITEs to byte “b” (DQb pins); BWc enables WRITEs to byte “c” (DQc pins); BWd enables WRITEs to byte “d”

5 BW

(DQd pins).
6 All inputs except OE
7 Wait states are inserted by setting CEN
8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
10 The address counter is incremented for all CONTINUE BURST cycles.
11 ZZ pin is always Low.

and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

HIGH.

1,2,3,

10

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