Alliance Semiconductor AS7C33256NTF32A, AS7C33256NTF36A Service Manual

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November 2004

AS7C33256NTF32A AS7C33256NTF36A

3.3V 256K×32/36 Flowthrough Synchronous SRAM with NTD

Features

• Organization: 262,144 words × 32 or 36 bits

™

•NTD

architecture for efficient bus operation

• Fast clock to data access: 7.5/8.5/10 ns

•Fast OE

access time: 3.5/4.0 ns

• Fully synchronous operation

• Flow-through mode

• Asynchronous output enable control

• Available in 100-pin TQFP

• Byte write enables

• Clock enable for operation hold

• Multiple chip enables for easy expansion

Logic Block Diagram

R/W BWa

BWb BWc

BWd

LBO

A[17:0]

CE0 CE1 CE2

ADV / LD

Address

Burst logic

Control

logic

CLK

• 3.3 core power supply

• 2.5V or 3.3V I/O operation with separate V

DDQ

• 30 mW typical standby power

• Self-timed write cycles

• Interleaved or linear burst modes

• Snooze mode for standby operation

Write delay

addr. registers

CLK

Wri te Buf fe r

256K x 32/36

SRAM

Array

DQ[a,b,c,d]

CLK

CEN

32/36

Data

Input

CLK

32/36

Output

32/36

Buffer

32/36

DQ[a,b,c,d]

Selection Guide

-75 -85 -10 Units

Minimum cycle time 8.5 10 12 ns

Maximum clock access time 7.5 8.5 10 ns

Maximum operating current 300 280 240 mA

Maximum standby current 120 110 100 mA

Maximum CMOS standby current (DC) 30 30 30 mA

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AS7C33256NTF32A AS7C33256NTF36A

8 Mb Synchronous SRAM products list

Org Part Number Mode Speed

512KX18 AS7C33512PFS18A PL-SCD 166/133 MHz

256KX32

256KX36 AS7C33256PFS36A PL-SCD 166/133 MHz

512KX18 AS7C33512PFD18A PL-DCD 166/133 MHz

256KX32

256KX36 AS7C33

512KX18 AS7C33512FT18A FT 7.5/8.5/10 ns

256KX32

256KX36 AS7C33

512KX18 AS7C33512NTD18A NTD-PL 166/133 MHz

256KX32

256KX36 AS7C33

512KX18 AS7C33512NTF18A NTD-FT 7.5/8.5/10 ns

256KX32

256KX36 AS7C33

AS7C33256PFS32A PL-SCD 166/133 MHz

AS7C33

256

1,2

PFD32A PL-DCD 166/133 MHz

PFD36A PL-DCD 166/133 MHz

FT32A FT 7.5/8.5/10 ns

FT36A FT 7.5/8.5/10 ns

NTD32A NTD-PL 166/133 MHz

NTD36A NTD-PL 166/133 MHz

NTF32A NTD-FT 7.5/8.5/10 ns

NTF36A NTD-FT 7.5/8.5/10 ns

1 Core Power Supply: VDD = 3.3V + 0.165V 2 I/O Supply Voltage: VDDQ = 3.3V +

VDDQ = 2.5V +

0.165V for 3.3V I/O

0.125V for 2.5V I/O

PL-SCD : Pipelined Burst Synchronous SRAM - Single Cycle Deselect PL-DCD : Pipelined Burst Synchronous SRAM - Double Cycle Deselect FT : Flow-through Burst Synchronous SRAM

NTD

-PL : Pipelined Burst Synchronous SRAM with NTD

NTD-FT : Flow-through Burst Synchronous SRAM with NTD

1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners.

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Pin arrangement for TQFP (top view)

AACE0

99989796959493929190898887868584838281

DQPc/NC

DQc0 DQc1

DDQ

SSQ

DQc2 DQc3 DQc4

DQc5

SSQ

DDQ

DQc6 DQc7

DQd0 DQd1

DDQ

SSQ

DQd2 DQd3 DQd4 DQd5

SSQ

DDQ

DQd6 DQd7

DQPd/NC

100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

31323334353637383940414243444546474849

CE1

BWd

BWc

BWb

BWa

CE2

TQFP 14x20mm

VSSCLK

R/W

CENOEADV/LD

NCAA

AS7C33256NTF32A AS7C33256NTF36A

DQPb/NC

DQb7

DQb6

V 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

DDQ

SSQ

DQb5

DQb4

DQb3

DQb2

SSQ

DDQ

DQb1

DQb0

DQa7

DQa6

DDQ

SSQ

DQa5

DQa4

DQa3

DQa2

SSQ

DDQ

DQa1

DQa0

DQP/NC

AAA

LBO

Note: Pins 1, 30, 51 , and 80 are NC for ×32

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AAAAA

AS7C33256NTF32A AS7C33256NTF36A

Functional description

The AS7C33256NTF32A/36A family is a high performance CMOS 8 Mbit Synchronous Static Random Access Memory (Flowthrough SRAM) organized as 262,144 words × 32 or 36 bits and incorporates a LATE Write.

This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTD™) architecture, featuring an enhanced write operation that improves bandwidth over pipelined burst devices. In a normal flowthrough burst device, the write data, command, and address are all applied to the device on the same clock edge. If a read command follows this write command, the system must wait for one 'dead' cycle for valid data to become available. This dead cycle can significantly reduce overall bandwidth for applications requiring random access or readmodify-write operations.

™

devices use the memory bus more efficiently by introducing a write latency which matches one-cycle flow-through read latency.

NTD Write data is applied one cycle after the write command and address, allowing the read pipeline to clear. With NTD operations can be used in any order without producing dead bus cycle.

Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 32/36 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device one clock cycle later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs.

Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select,

pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations,

R/W including burst, can be stalled using the CEN=1, the clock enable input.

The AS7C33256NTF32A and AS7C33256NTF36A operate with a 3.3V ± 5% power supply for the device core (VDD). DQ circuits use a separate power supply (V

) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP package

DDQ

Capacitance

Parameter Symbol Test conditions Min Max Unit

Input capacitance C

I/O capacitance C

Guaranteed not tested

I/O

Vin = 0V - 5 pF

Vin = V

= 0V - 7 pF

out

™

, write and read

TQFP thermal resistance

Description Conditions Symbol Typ ic al Units

Thermal resistance (junction to ambient)

Thermal resistance (junction to top of case)

1 This parameter is sampled

Test conditions follow standard test methods and procedures for measuring thermal

impedance, per EIA/JESD51

1–layer θ

4–layer θ

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40 °C/W

22 °C/W

8 °C/W

AS7C33256NTF32A AS7C33256NTF36A

Signal descriptions

Signal I/O Properties Description

CLK I CLOCK Clock. All inputs except OE

CEN

I SYNC Clock enable. When de-asserted high, the clock input signal is masked.

A, A0, A1 I SYNC Address. Sampled when all chip enables are active and ADV/LD

DQ[a,b,c,d] I/O SYNC Data. Driven as output when the chip is enabled and OE

CE0 CE2

, CE1,

I SYNC

Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD Are ignored when ADV/LD

Advance or Load. When sampled high, the internal burst address counter will increment in

ADV/LD

I SYNC

the order defined by the LBO input value. (refer to table on page 2) When low, a new address is loaded.

R/W

BW[a,b,c,d]

I SYNC

I ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive.

A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE operation. Is ignored when ADV/LD

Byte write enables. Used to control write on individual bytes. Sampled along with WRITE command and BURST WRITE.

Selects Burst mode. When tied to V

LBO

ISTATIC

order. When driven Low, device follows linear Burst order. This signal is internally pulled

High.

ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.

NC - - No connects. Note that pin 84 will be used for future address expansion to 16Mb density.

, LBO, and ZZ are synchronous to this clock.

is asserted.

is active.

is high.

or left floating, device follows Interleaved Burst

is asserted.

Snooze Mode

SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state.

The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.

When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time t become disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successful complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly, when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.

is met. After entering SNOOZE MODE, all inputs except ZZ

ZZI

Burst Order

Interleaved Burst Order LBO=1 Linear Burst Order LBO=0

A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0

Starting Address0 00 11 01 1 Starting Address0 00 11 01 1

First increment 0 1 0 0 1 1 1 0 First increment 0 1 1 0 1 1 0 0

Second increment 1 0 1 1 0 0 0 1 Second increment 1 0 1 1 0 0 0 1

Third increment 1 1 1 0 0 1 0 0 Third increment 1 1 0 0 0 1 1 0

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AS7C33256NTF32A AS7C33256NTF36A

Synchronous truth table

CE0 CE1 CE2 ADV/LD R/W BWn OE CEN

[5,6,7,8,9,11

]

Address

source CLK Operation DQ Notes

H X X L X X X L NA L to H DESELECT Cycle High-Z

X X H L X X X L NA L to H DESELECT Cycle High-Z

X L X L X X X L NA L to H DESELECT Cycle High-Z

X X X H X X X L NA L to H CONTINUE DESELECT Cycle High-Z 1

L H L L H X L L External L to H READ Cycle (Begin Burst) Q

X X X H X X L L Next L to H READ Cycle (Continue Burst) Q 1,10

L H L L H X H L External L to H NOP/DUMMY READ (Begin Burst) High-Z 2

X X X H X X H L Next L to H DUMMY READ (Continue Burst) High-Z 1,2,10

L H L L L L X L External L to H WRITE CYCLE (Begin Burst) D 3

X X X H X L X L Next L to H WRITE CYCLE (Continue Burst) D 1,3,10

L H L L L H X L External L to H NOP/WRITE ABORT (Begin Burst) High-Z 2,3

X X X H X H X L Next L to H WRITE ABORT (Continue Burst) High-Z

X X X X X X X H Current L to H INHIBIT CLOCK - 4

Key: X = Don’t Care, H = HIGH, L = LOW. BWn = H means all byte write signals (BWa, BWb, BWc, and BWd) are HIGH. BWn = L means one or more byte write signals are LOW.

Notes:

1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chose in the initial BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.

2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a WRITE command is given, but no operation is performed.

may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE

3 OE cycle. OE

4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.

5 balls);

6 All inputs except

7 Wait states are inserted by setting

8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.

9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE. 10 The address counter is incremented for all CONTINUE BURST cycles. 11 ZZ pin is always Low.

may be used when the bus turn-on and turn-off times do not meet an application’s requirements.

BWa enables WRITEs to byte “a” (DQa pins/balls); BWb enables WRITEs to byte “b” (DQb pins/balls); BWc enables WRITEs to byte “c” (DQc pins/

BWd enables WRITEs to byte “d” (DQd pins/balls).

OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

CEN HIGH.

1,2,3,

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+ 12 hidden pages

Alliance Semiconductor AS7C33256NTF32A, AS7C33256NTF36A Service Manual

Specifications and Main Features

Frequently Asked Questions

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