Alliance Semiconductor AS7C31026B Service Manual

March 2004

3.3 V 64K X 16 CMOS SRAM

Features

• Industrial and commercial versions

• Organization: 65,536 words × 16 bits

• Center power and ground pins for low noise

• High speed

- 10/12/15/20 ns address access time

- 5, 6, 7, 8 ns output enable access time

• Low power consumption: ACTIVE

- 288 mW / max @ 10 ns

• Low power consumption: STANDBY

- 18 mW / max CMOS I/O

• 6 T 0.18 u CMOS technology

®

• Easy memory expansion with

CE, OE inputs

• TTL-compatible, three-state I/O

• JEDEC standard packaging

- 44-pin 400 mil SOJ

- 44-pin TSOP 2-400

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

AS7C31026B

Logic block diagram

A0
A1
A2
A3
A4
A5

WE

UB

OE

LB

CE

I/O0–I/O7

I/O8–I/O15

A6
A7

Row decoder

I/O

buffer

Control circuit

Column decoder

A8

64 K × 16

Array

A9

A11

A10

V

CC

GND

A12

A13

A14

A15

Pin arrangement

44-Pin SOJ (400 mil), TSOP 2

A4
A3
A2
A1
A0

CE
I/O0
I/O1
I/O2
I/O3
V

CC

GND

I/O4
I/O5
I/O6
I/O7

WE
A15
A14
A13
A12

NC

1

44

AS7C31026B

A5

43

A6

42

A7

41

OE

UB

40

LB

39

I/O15

38

I/O14

37

I/O13

36

I/O12

35

GND

34

V

33

CC

I/O11

32

I/O10

31

I/O9

30

I/O8

29

NC

28

A8

27

A9

26

A10

25

A11

24

NC

23

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

Selection guide

-10 -12 -15 -20 Unit

Maximum address access time
Maximum output enable access time
Maximum operating current 80 75 70 65 mA
Maximum CMOS standby current 5555mA

10 12 15 20 ns

5678ns

3/26/04, v 1.3 Alliance Semiconductor P. 1 of 10

Copyright © Alliance Semiconductor. All rights reserved.

AS7C31026B

®

Functional description

The AS7C31026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words
× 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.

Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for
high-performance applications.

When CE is high, the device enters standby mode. A write cycle is accomplished by asserting wr ite ena ble (WE ) an d chi p enable (CE). Data
on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention,
external devices should drive I/O pins only after outputs have been disabled with output enable (OE

A read cycle is accomplished by asserting output enable (OE
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.

The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.

All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The device is packaged in common industry
standard packages.

) and chip enable (CE) with write enable (WE) high. The chips drive I/O pins

Absolute maximum ratings

Parameter Symbol Min Max Unit

Voltage on V
Voltage on any pin relative to GND V
Power dissipation P
Storage temperature (plastic) T
Ambient temperature with VCC applied T
DC current into outputs (low) I

Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func­tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.

relative to GND V

CC

t1
t2
D

stg

bias

OUT

–0.50 +5.0 V
–0.50 VCC +0.50 V

–1.0W
–65 +150 °C
–55 +125 °C

–20mA

) or write enable (WE).

Truth table

CE WE OE LB UB I/O0–I/O7 I/O8–I/O15 Mode

H X X X X High Z High Z Standby (I
LHLLHD

OUT

L H L H L High Z D
LHLLLD
LLXLLD
LLXLHD

OUT

IN
IN

L L X H L High Z D
L

L

H
X

H
X

X
H

X
H

High Z High Z O utput disable (I

High Z Read I/O0–I/O7 (ICC)

Read I/O8–I/O15 (I
Read I/O0–I/O15 (ICC)

Write I/O0–I/O15 (ICC)

D

OUT
OUT

D

IN

High Z Write I/O0–I/O7 (ICC)

IN

Write I/O8–I/O15 (ICC)

Key: H = high, L = low, X = don’ t care.

3/26/04, v 1.3 Alliance Semiconductor P. 2 of 10

SB

), I

SBI

CC

)

CC)

)

®

Recommended operating conditions

Parameter Symbol Min Nominal Max Unit

Supply voltage V
Input voltage V

commercial T

Ambient operating temperature

V

= -1.0V for pulse width less than 5ns

IL

V

+ 1.5V for pulse width less than 5ns

IH = VCC

industrial T

CC

IH

V

IL
A
A

3.0 3.3 3.6 V

2.0 – VCC + 0.5 V

–0.5 – 0.8 V

0– 70o C

–40 – 85

DC operating characteristics (over the operating range)1

-10 -12 -15 -20

Parameter Sym Test conditions

Input leakage
current

Output leakage
current

Operating power
supply current

Standby
power supply
current

Output
voltage

|

| I

LI

|

| I

LO

V

V

I

CC

I

SB

CE

VCC = Max, CE ≥ VCC–0.2 V,

I

SB1

VIN ≥ VCC–0.2 V, f = 0

V

OL

V

OH

IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 V

IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – 2.4 – V

= Max

V

CC

= GND to V

IN

VCC = Max

CE = VIH,

= GND to V

OUT

VCC = Max,

≤ VIL, I

f = f

OUT

Max

VCC = Max,

CE ≥ VIH, f = f

≤ 0.2 V or

V

IN

CC

CC

= 0mA

Max

–1–1–1–1µA

–1–1–1–1µA

–80–75– 70 – 65mA

–30–25–20–20

–5–5–5–5

AS7C31026B

o

C

UnitMin Max Min Max Min Max Min Max

mA

mA

Capacitance (f = 1MHz, Ta = 25 °C, VCC = NOMINAL)

2

Parameter Symbol Signals T est conditions Max Unit

Input capacitance C
I/O capacitance C

IN

I/O

3/26/04, v 1.3 Alliance Semiconductor P. 3 of 10

A, CE, WE, OE, LB, UB VIN = 0 V 5 pF

I/O VIN = V

= 0 V 7 pF

OUT