Alliance Semiconductor AS7C31025B Service Manual

March 2004

3.3V 128K X 8 CMOS SRAM (Center power and ground)

Features

• Industrial and commercial temperatures

• Organization: 131,072 x 8 bits

• High speed

- 10/12/15/20 ns address access time

- 5, 6, 7, 8 ns output enable access time

• Low power consumption: ACTIVE

- 252 mW / max @ 10 ns

• Low power consumption: STANDBY

- 18 mW / max CMOS

• 6 T 0.18 u CMOS technology

Logic block diagram

V

CC

GND

Input buffer

A0
A1
A2
A3
A4
A5
A6
A7
A8

512 x 256 x 8

Array

(1,048,576)

Row decoder

Column decoder

Sense amp

Control

circuit

WE

OE
CE

I/O7

I/O0

AS7C31025B

®

• Easy memory expansion with

• Center power and ground

• TTL/LVTTL-compatible, three-state I/O

• JEDEC-standard packages

- 32-pin, 300 mil SOJ

- 32-pin, 400 mil SOJ

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

Pin arrangement

32-pin SOJ (300 mil)
32-pin SOJ (400 mil)

1

A0

2

A1

3

A2

4

A3

5

CE

WE

6
7
8

CC

9
10
11
12
13

A4

14

A5

15

A6

16

A7

I/O0
I/O1
V

GND

I/O2
I/O3

CE, OE

A16

32

A15

31

A14

30

A13

29
28

OE
I/O7

27
26

I/O6

25

GND
V

24

CC

23

I/O5

AS7C31025B

22

I/O4

21

A12
A11

20
19

A10
A9

18
17

A8

inputs

A9

A1 1

A10

A12

A13

A14

A15

A16

Selection guide

-10 -12 -15 -20 Unit

Maximum address access time 10 12 15 20 ns
Maximum output enable access time 5678ns
Maximum operating current 70 65 60 55 mA
Maximum CMOS standby current 5555mA

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Copyright © Alliance Semiconductor. All rights reserved.

AS7C31025B

®

Functional description

The AS7C31025B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 x 8
bits. It is designed for memory applications where fast data access, low power, and simple interfa cing are desired.

Equal address access and cycle times (t
high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems.

When CE is high the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data
on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention,
external devices should drive I/O pins only after outputs have been disabled with output enable (

A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31025B is packaged in common
industry standard packages.

Absolute maximum ratings

Parameter Symbol Min Max Unit

Voltage on V
Voltage on any pin relative to GND V
Power dissipation P
Storage temperature (plastic) T
Ambient temperature with V
DC current into outputs (low) I

NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func­tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.

relative to GND V

CC

CC

, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for

AA

OE

applied T

t1
t2
D

stg

bias

OUT

) or write enable (

–0.50 +5.0 V
–0.50 VCC + 0.5 V

–1.0W
–65 +150
–55 +125

–20mA

WE

o
o

).

C
C

Truth table

CE WE OE

H X X High Z Standby (I
L H H High Z Output disable (I
LHL D
LLX D

Key: X = don’t care, L = low, H = high.

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Data Mode

SB

OUT

IN

Read (ICC)

Write (ICC)

, I

SB1

CC

)

)

Recommended operating conditions

Parameter Symbol Min Nominal Max Unit

Supply voltage V

Input voltage

Ambient operating temperature

V

= -1.0V for pulse width less than 5ns

IL

V

+ 1.5V for pulse width less than 5ns

IH = VCC

AS7C31025B

®

CC

V

IH

V

IL

T

A

T

A

3.0 3.3 3.6 V

2.0 – VCC + 0.5 V

–0.5 – 0.8 V

0–70o C

–40 – 85

o

C

DC operating characteristics (over the operating range)

-10 -12 -15 -20

Parameter Sym Test conditions

Input leakage
current

Output leakage
current

Operating power
supply current

Standby power
supply current

Output voltage

Capacitance (f = 1 MHz, T

Input capacitance C
I/O capacitance C

| I

|

VCC = Max, VIN = GND to V

LI

| I

|

LO

VCC = Max, CE = VIH,

V

= GND to V

out

CC

–1–1–1–1µA

CC

–1–1–1–1µA

VCC = Max

I

CC

CE

≤ VIL, f = f
I

OUT

= 0 mA

Max

,

–70–65–60–55

VCC = Max

I

SB

1

I

V

SB1

CE

≥ VIH, f = f

Max

VCC = Max, CE ≥ VCC–0.2 V,

≤ 0.2 V or VIN ≥ VCC –0.2 V,

IN

–30–25–20–20

– 5 – 5 – 5 – 5

f = 0

V

OL

V

OH

IOL = 8 mA, VCC = Min

IOH = –4 mA, VCC = Min

= 25o C, VCC = NOMINAL)

a

–0.4–0.4–0.4–0.4V

2.4–2.4–2.4–2.4– V

2

Parameter Symbol Signals Test conditions Max Unit

IN

I/O

A, CE, WE,

I/O VIN = V

1

OE

VIN = 0 V 5 pF

= 0 V 7 pF

OUT

UnitMin Max Min Max Min Max Min Max

mA

mA

mA

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