Alliance Semiconductor AS7C256A Service Manual
September 2004
5V 32K X 8 CMOS SRAM (Common I/O)
Features
• Pin compatible with AS7C256
• Industrial and commercial temperature options
• Organization: 32,768 words × 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
• Very low power consumption: ACTIVE
- 412.5 mW max @ 10 ns
• Very low power consumption: STANDBY
- 11 mW max CMOS I/O
• Easy memory expansion with
CE
and OE inputs
AS7C256A
®
• TTL-compatible, three-state I/O
• 28-pin JEDEC standard packages
- 300 mil SOJ
-8 × 13.4 mm TSOP 1
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• 2.0V Data retention
Logic block diagram
V
CC
GND
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
Row decoder
256 X 128 X 8
(262,144)
Column decoder
A9A
A10A11A12A13A
8
Array
Sense amp
Control
circuit
14
WE
OE
CE
Pin arrangement
28-pin TSOP 1 (8×13.4 mm)
OE
A11
A9
I/O7
I/O0
A8
A13
WE
V
CC
A14
A12
A7
A6
A5
A4
A3 A2
28-pin SOJ (300 mil)
A14
1
2
3
4
5
6
7
8
AS7C256A
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A12
I/O0
I/O1
I/O2
GND
1
2
3
A7
4
A6
5
A5
6
A4
7
A3
8
A2
A1
A0
AS7C256A
9
10
11
12
13
14
Selection guide
-10 -12 -15 -20 Unit
Maximum address access time 10 12 15 20 ns
Maximum output enable access time 5 6 7 8 ns
Maximum operating current 75 70 65 60 mA
Maximum CMOS standby current 2 2 2 2 mA
28
V
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
CC
27
26
25
24
23
22
21
20
19
18
17
16
15
9/24/04; v.1.2 Alliance Semiconductor P. 1 of 9
Copyright © Alliance Semiconductor. All rights reserved.
AS7C256A
®
Functional description
The AS7C256A is a 5.0V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized
as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including
Pentium
operation without sacrificing performance or operating margins.
The device enters standby mode when
power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode.
Equal address access and cycle times (t
are ideal for high-performance applications. The chip enable (
memory organizations.
A write cycle is accomplished by asserting chip enable (
is written on the rising edge of
drive I/O pins only after outputs have been disabled with output enable (
A read cycle is accomplished by asserting chip enable (
chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write
enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0 ±0.5V supply. The AS7C256A is packaged in high volume industry standard packages.
TM
, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 5.0V
CE
is high. CMOS standby mode consumes ≤11 mW. Normal operation offers 75%
, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns
AA
WE
(write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should
CE
) input permits easy memory expansion with multiple-bank
CE
) and write enable (WE) LOW. Data on the input pins I/O0-I/O7
OE
) or write enable (WE).
CE
) and output enable (OE) LOW, with write enable (WE) high. The
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on V
Voltage on any pin relative to GND V
Power dissipation P
Storage temperature (plastic) T
Ambient temperature with V
DC current into outputs (low) I
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
relative to GND V
CC
applied T
CC
t1
t2
D
stg
bias
OUT
–0.5 +7.0 V
–0.5 VCC + 0.5 V
–1.0W
–65 +150
–55 +125
o
C
o
C
–20mA
Truth table
CE WE OE
H X X High Z Standby (I
L H H High Z Output disable (I
LHLD
LLXD
Key: X = Don’t care, L = Low, H = High
OUT
IN
Data Mode
, I
SB
SB1
Read (ICC)
Write (ICC)
CC
)
)
9/24/04; v.1.2 Alliance Semiconductor P. 2 of 9
®
Recommended operating conditions
Parameter Symbol Min Typical Max Unit
Supply voltage V
Input voltage
commercial T
Ambient operating temperature
*
min = –1.0V for pulse width less than 5ns.
V
IL
**
max = VCC + 2.0V for pulse width less than 5ns.
V
IH
industrial T
CC
**
V
IH
*
V
IL
A
A
DC operating characteristics (over the operating range)1
-10 -12 -15 -20
Parameter Sym Test conditions
Input leakage
current
Output leakage
current
Operating
power supply
current
Standby power
supply current
Output voltage
|I
LI
|I
LO
I
CC
I
SB
I
SB1
V
OLIOL
V
OHIOH
= Max,
V
CC
|
V
= GND to V
in
= Max,
V
CC
|
V
= GND to V
OUT
VCC = Max, CE < V
f = f
Max
, I
OUT
VCC = Max, CE > V
f = f
Max
CC
CC
IL
= 0mA
IH
–1–1–1–1µA
–1–1–1–1µA
–75-70–65–60mA
–45–45–40–40mA
VCC = Max, CE > VCC–0.2V
V
< 0.2V or
IN
V
> VCC–0.2V, f = 0
IN
–2.0–2.0–2.0–2.0mA
= 8 mA, VCC = Min –0.4–0.4–0.4–0.4V 4
= –4 mA, VCC = Min 2.4–2.4–2.4–2.4– V 4
AS7C256A
4.5 5.0 5.5 V
2.2 – VCC+0.5 V
-0.5 – 0.8 V
0–70oC
–40 – 85
Unit NotesMin Max Min Max Min Max Min Max
o
C
Capacitance (f = 1MHz, T
= room temperature, VCC = NOMINAL)
a
4
Parameter Symbol Signals Test conditions Max Unit
Input capacitance C
I/O capacitance C
9/24/04; v.1.2 Alliance Semiconductor P. 3 of 9
IN
I/O
A, CE, WE,
OE
I/O Vin = V
Vin = 0V 5 pF
= 0V 7 pF
out
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