Alliance Semiconductor AS7C252MFT18A Service Manual

查询AS7C252MFT18A供应商

January 2005

2.5V 2M × 18 Flow-through synchronous SRAM

Features

• Organization: 2,097152 words × 18 bits

• Fast clock to data access: 7.5/8.5/10 ns

•Fast OE

• Fully synchronous flow-through operation

• Asynchronous output enable control

• Available in 100-pin TQFP package

• Individual byte write and global write

Logic block diagram

access time: 3.5/4.0 ns

CLK

ADV ADSC ADSP

A[20:0]

GWE

BWE

CE0 CE1

CE2

Power

down

• Multiple chip enables for easy expansion

• 2.5V core power supply

• Linear or interleaved burst control

• Snooze mode for reduced power-standby

• Common data inputs and data outputs

LBO

CLK CS

Burst logic

CLR

Address register

DQb

Byte Write

registers

CLK

DQa

Byte Write

registers

CLK

Enable

CE CLK

Enable

delay

CLK

AS7C252MFT18A

2M x 18

Output

registers

CLK

Memory

array

Input

registers

CLK

DQ[a,b]

Selection guide

-75 -85 -10 Units

Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC)

1/17/05, v 1.2 Alliance Semiconductor 1 of 19

8.5 10 12 ns

7.5 8.5 10 ns 325 300 275 mA 130 130 130 mA

90 90 90 mA

AS7C252MFT18A

2.5V 32 Mb Synchronous SRAM products list

Org Part Number Mode Speed

2MX18 AS7C252MPFS18A PL-SCD 200/166/133 MHz 1MX32 1MX36 AS7C251MPFS36A PL-SCD 200/166/133 MHz 2MX18 1MX32 1MX36 AS7C251MPFD36A PL-DCD 200/166/133 MHz 2MX18 AS7C252MFT18A FT 7.5/8.5/10 ns 1MX32 AS7C251MFT32A FT 7.5/8.5/10 ns 1MX36 2MX18 1MX32 1MX36 2MX18 1MX32 1MX36

AS7C251MPFS32A PL-SCD 200/166/133 MHz

AS7C252MPFD18A PL-DCD 200/166/133 MHz AS7C251MPFD32A PL-DCD 200/166/133 MHz

AS7C251MFT36A FT 7.5/8.5/10 ns AS7C252MNTD18A NTD-PL 200/166/133 MHz AS7C251MNTD32A NTD-PL 200/166/133 MHz AS7C251MNTD36A NTD-PL 200/166/133 MHz

AS7C252MNTF18A NTD-FT 7.5/8.5/10 ns AS7C251MNTF32A NTD-FT 7.5/8.5/10 ns AS7C251MNTF36A NTD-FT 7.5/8.5/10 ns

1,2

1 Core Power Supply: VDD = 2.5V + 0.125V 2 I/O Supply Voltage: VDDQ = 2.5V +

0.125V

PL-SCD : Pipelined Burst Synchronous SRAM - Single Cycle Deselect PL-DCD : Pipelined Burst Synchronous SRAM - Double Cycle Deselect FT : Flow-through Burst Synchronous SRAM

NTD

-PL : Pipelined Burst Synchronous SRAM with NTD

NTD-FT : Flow-through Burst Synchronous SRAM with NTD

1NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners.

1/17/05, v 1.2 Alliance Semiconductor 2 of 19

Pin assignment

100-pin TQFP - top view

NC NC

DDQ

SSQ

NC DQb0 DQb1

SSQ

DDQ

DQb2 DQb3

DQb4 DQb5

DDQ

SSQ

DQb6 DQb7

DQPb

SSQ

DDQ

1 2

3 4 5 6 7 8 9

10 11 12

13 14 15 16 17 18 19 20 21 22 23

24 25 26

27 28

29 30

AACE0

100

CE1NCNC

99989796959493929190898887868584838281

BWb

BWa

CE2

VSSCLK

GWE

BWEOEADSC

ADSP

ADVAA

TQFP 14 x 20mm

AS7C252MFT18A

80 79

78 77 76 75 74 73 72 71 70 69

68 67

66 65 64

63 62

61 60 59 58 57

56 55

54 53

52 51

A NC NC V

DDQ

SSQ

NC DQPa

DQa7 DQa6

SSQ

DDQ

DQa5 DQa4 V

NC V

ZZ DQa3

DQa2 V

DDQ

SSQ

DQa1 DQa0

NC NC V

SSQ

DDQ

NC NC NC

31323334353637383940414243444546474849

AAA

LBO

1/17/05, v 1.2 Alliance Semiconductor 3 of 19

AAAAAAA

AS7C252MFT18A

Functional description

The AS7C252MFT18A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM) device organized as 2,097152 words × 18 bits.

Fast cycle times of 8.5/10/12 ns with clock access times (t Burst operation is initiated in one of two ways: the controller address strobe (ADSC advance pin (ADV

Read cycles are initiated with ADSP when ADSP

) allows subsequent internally generated burst addresses.

(regardless of WE and ADSC) using the new external address clocked into the on-chip address register

is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV LBO

unconnected or driven high, burst operations use an interleaved count sequence. With

is sampled low and both address strobes are high. Burst mode is selectable with the

sequence.

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signals.

BWn

is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented

BWn internally to the next burst address if BWn and ADV are sampled low.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are as follows:

• ADSP

must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.

) of 7.5/8.5/10 ns. Three chip enable (CE) inputs permit easy memory expansion.

), or the processor address strobe (ADSP). The burst

LBO

input. With

LBO

driven low, the device uses a linear count

•WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).

• Master chip enable CE0 blocks ADSP, but not ADSC.

The AS7C252MFT18A family operates from a core 2.5V power supply. These devices are available in 100-pin TQFP package.

TQFP capacitance

Parameter Symbol Test conditions Min Max Unit

Input capacitance C

I/O capacitance C

*Guaranteed not tested

I/O

VIN = 0V - 5 pF

= 0V - 7 pF

OUT

TQFP thermal resistance

Description Conditions Symbol Typ ic al Units

Thermal resistance (junction to ambient)

Thermal resistance (junction to top of case)

1 This parameter is sampled

1–layer θ

Test conditions follow standard test methods and

procedures for measuring thermal impedance,

per EIA/JESD51

4–layer θ

40 °C/W

22 °C/W

8 °C/W

1/17/05, v 1.2 Alliance Semiconductor 4 of 19

Signal descriptions

AS7C252MFT18A

Pin I/O Properties

Description

CLK I CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.

A,A0,A1 I SYNC Address. Sampled when all chip enables are active and when ADSC

DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and when OE

CE0

ISYNC

CE1, CE2 ISYNC

ADSP

ADSC

ADV

GWE

BWE

I SYNC Address strobe processor. Asserted low to load a new address or to enter standby mode.

I SYNC Address strobe controller. Asserted low to load a new address or to enter standby mode.

I SYNC Advance. Asserted low to continue burst read/write.

ISYNC

I SYNC Byte write enable. Asserted low with GWE high to enable effect of BW[a,b] inputs.

Master chip enable. Sampled on clock edges when ADSP

is blocked. Refer to the “Synchronous truth table” for more information.

ADSP

Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when ADSC

is active or when CE0 and ADSP are active.

Global write enable. Asserted low to write all 18 bits. When high, BWE enable.

or ADSC is active. When CE0 is inactive,

Write enables. Used to control write of individual bytes when GWE

BW[a,b] ISYNC

BW[a,b]

is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a,b] are inactive,

or ADSP are asserted.

is active.

and BW[a,b] control write

is high and BWE is low. If any of

the cycle is a read cycle.

LBO ISTATIC

I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.

Selects Burst mode. When tied to V

or left floating, device follows interleaved Burst order. When

driven Low, device follows linear Burst order. This signal is internally pulled High.

ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.

NC - - No connect

Snooze Mode

SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I SNOOZE MODE is dictated by the length of time the ZZ is in a High state.

The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.

When the ZZ pin becomes a logic High, I

is guaranteed after the time t

SB2

is met. After entering SNOOZE MODE, all inputs except ZZ is

ZZI

disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during t

, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.

PUS

1/17/05, v 1.2 Alliance Semiconductor 5 of 19

. The duration of

SB2

Write enable truth table (per byte)

Function GWE BWE BWa BWb

Write All Bytes

Write Byte a

Write Byte b

Read

Key: X = don’t care, L = low, H = high, n = a, b;

LXXX HLLL HLLH HLHL HHXX HLHH

BWE, BWn

= internal write signal.

Asynchronous Truth Table

Operation ZZ OE I/O Status

Snooze mode H X High-Z

Read

Write L X Din, High-Z Deselected L X High-Z

Notes:

1. X means “Don’t Care”

2. ZZ pin is pulled down internally

3. For write cycles that follows read cycles, the output buffers must be disabled with OE

4. Snooze mode means power down state of which stand-by current does not depend on cycle times

5. Deselected means power down state of which stand-by current depends on cycle times

L L Dout L H High-Z

, otherwise data bus contention will occur.

AS7C252MFT18A

Burst sequence table

Interleaved burst address (LBO = 1) Linear burst address (LBO = 0)

A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0

1st Address

Address

0 00 11 01 1 0 10 01 11 0 1 01 10 00 1 1 11 00 10 0

1st Address

Address

0 00 11 01 1 0 11 01 10 0 1 01 10 00 1 1 11 00 11 0

1/17/05, v 1.2 Alliance Semiconductor 6 of 19

+ 13 hidden pages

Alliance Semiconductor AS7C252MFT18A Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual