Alliance Semiconductor AS7C1025B Service Manual

查询AS7C1025B供应商

March 2004

5V 128K X 8 CMOS SRAM (Center power and ground)

Features

• Industrial and commercial temperatures

• Organization: 131,072 x 8 bits

• High speed

- 10/12/15/20 ns address access time

- 5/6/7/8 ns output enable access time

• Low power consumption: ACTIVE

- 605mW / max @ 10 ns

• Low power consumption: STANDBY

- 55 mW / max CMOS

• 6 T 0.18 u CMOS technology

• Easy memory expansion with

• Center power and ground

• TTL/LVTTL-compatible, three-state I/O

Logic block diagram

V

CC

GND

Input buffer

A0
A1
A2
A3
A4
A5
A6
A7
A8

512 x 256 x 8

Array

(1,048,576)

Row decoder

CE, OE

inputs

Sense amp

I/O7

I/O0

®

• JEDEC-standard packages

- 32-pin, 300 mil SOJ

- 32-pin, 400 mil SOJ

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

Pin arrangement

32-pin SOJ (300 mil)
32-pin SOJ (400 mil)

A0
A1

A2
A3

CE
I/O0
I/O1
V

CC

GND

I/O2
I/O3

WE

A4
A5
A6
A7

AS7C1025B

1
2

3
4
5
6
7

8
9
10

AS7C1025B

11
12
13
14
15

16

A16

32

A15

31

A14

30

A13

29
28

OE
I/O7

27
26

I/O6

25

GND
V

24

CC

23

I/O5

22

I/O4

21

A12
A11

20
19

A10
A9

18
17

A8

WE

OE
CE

Column decoder

A9

A1 1

A10

A12

A13

A14

A15

Control

circuit

A16

Selection guide

-10 -12 -15 -20 Unit

Maximum address access time 10 12 15 20 ns
Maximum output enable access time 5 6 7 8 ns
Maximum operating current 110 100 90 80 mA
Maximum CMOS standby current 10 10 10 10 mA

3/26/04, v. 1.3 Alliance Semiconductor P. 1 of 9

Copyright © Alliance Semiconductor. All rights reserved.

AS7C1025B

®

Functional description

The AS7C1025B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 x 8
bits. They are designed for memory applications where fast data access, low power , and simple interfacing are desired.

Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are ideal for high­performance applications. The chip enable input CE

When CE
standby power is reached (I

A write cycle is accomplished by asserti ng write enable (
the rising edge of
outputs have been disabled with output enable (

A read cycle is accomplished by asserting output enable (
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1025B is packaged in common
industry standard packages.

is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full

). For example, the AS7C1026B is guaranteed not to exceed 55 mW under nominal full standby conditions.

SB1

WE

(write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after

permits easy memory and expansion with multiple-bank memory systems.

WE

) and chip enable (CE). Data on the input pins I/O0 through I/O7 is written on

OE

) or write enable (

WE

).

OE

) and chip enable (CE), with write enable (WE) high. The chips drive I/O pins

Absolute maximum ratings

Parameter Symbol Min Max Unit

Voltage on V
Voltage on any pin relative to GND V
Power dissipation P
Storage temperature (plastic) T
Ambient temperature with V
DC current into outputs (low) I

NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func­tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.

relative to GND V

CC

applied T

CC

t1
t2
D

stg

bias

OUT

–0.50 +7.0 V
–0.50 VCC + 0.5 V

–1.0W
–65 +150
–55 +125

o

C

o

C

–20mA

Truth table

CE WE OE

H X X High Z Standby (I
L H H High Z Output disable (I
LHL D
LLX D

Key: X = don’t care, L = low, H = high.

Data Mode

SB

OUT

IN

Read (ICC)

Write (ICC)

, I

SB1

CC

)

)

3/26/04, v. 1.3 Alliance Semiconductor P. 2 of 9

®

Recommended operating conditions

Parameter Symbol Min Nominal Max Unit

Supply voltage V

Input voltage

Ambient operating temperature

VIL min = -1.0V for pulse width less than 5ns
V

max = VCC+2.0V for pulse width less than 5ns.

IH

commercial T

industrial T

AS7C1025B

CC

V

IH

V

IL
A
A

4.5 5.0 5.5 V

2.2 – VCC + 0.5 V

–0.5 – 0.8 V

0–70o C

–40 – 85

o

C

DC operating characteristics (over the operating range)

Parameter Symbol Test co nditio ns

Input leakage current | ILI | VCC = Max, VIN = GND to V
Output leakage

current
Operating power

supply current
Standby power supply

1

current

Output voltage

|

| I

LO

I

CC

I

SB

I

SB1

V

OL

V

OHIOH

= Max, CE = VIH,

V

CC

= GND to V

V

out

VCC = Max

≤ VIL, f = f

CE
VCC = Max

≥ VIH, f = f

CE
VCC = Max

≥ VCC–0.2 V,

CE
VIN ≤ 0.2 V or VIN ≥ VCC –0.2 V,
f = 0

IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 V

= –4 mA, VCC = Min 2.4 2.4 – 2.4 – 2.4 – V

CC

Max, IOUT

Max

Capacitance (f = 1 MHz, T

Parameter Symbol Signals Test conditions Max Unit

Input capacitance C
I/O capacitance C

= 25o C, VCC = NOMINAL)

a

IN

I/O

= 0 mA

A, CE, WE,

–1–1–1–1µA

CC

–1–1–1–1µA

– 110 – 100 – 90 – 80 mA

–50–45–45–40mA

–

2

I/O VIN = V

1

-10 -12 -15 -20

10 10 10 10 mA

OE

VIN = 0 V 5 pF

= 0 V 7 pF

OUT

UnitMin Max Min Max Min Max Min Max

3/26/04, v. 1.3 Alliance Semiconductor P. 3 of 9