Alliance Semiconductor AS6WA25616 Service Manual
查询AS6WA25616供应商
September 2001
3.0V to 3.6V 256K×16 Intelliwatt™ low-power CMOS SRAM with one chip enable
AS6WA25616
Features
• AS6WA25616
• Intelliwatt™ active power circuitry
• Industrial and commercial temperature ranges available
• Organization: 262,144 words × 16 bits
• 3.0V to 3.6V at 55 ns
• Low power consumption: ACTIVE
- 144 mW at 3.6V and 55 ns
• Low power consumption: STANDBY
- 72 µW max at 3.6V
Logic block diagram
I/O1–I/O8
I/O9–I/O16
WE
UB
OE
LB
CS
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
Row Decoder
I/O
buffer
256K × 16
Array
(4,194,304)
Control circuit
Column decoder
A5
A9
A10
A11
A14
A15
A16
A17
V
CC
V
SS
• 1.5V data retention
• Equal access and cycle times
• Easy memory expansion with CS
, OE inputs
• Smallest footprint packages
- 48-ball FBGA
- 400-mil 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Pin arrangement (top view)
44-pin 400-mil TSOP 2
A4
A3
A0
CS
I/O1
I/O2
I/O3
I/O4
V
CC
V
SS
I/O5
I
/O6
I/O7
I/O8
WE
A17
A16
A15
A
14
A13
48-CSP Ball-Grid-Array Package
123456
ALB
OE A0 A1 A2 NC
BI/O9UB
C I/O10 I/O11 A5 A6 I/O2 I/O3
DV
I/O12 A17 A7 I/O4 V
SS
EVCCI/O13 NC A16 I/O5 V
F I/O15 I/O14 A14 A15 I/O6 I/O7
G I/O16 NC A12 A13 WE
H NC A8 A9 A10 A11 NC
44
1
43
2
3A2
42
4A1
41
5
40
6
39
7
38
8
37
9
36
10
35
11
3
33
32
31
30
29
28
27
26
25
24
23
4
12
13
14
15
16
17
18
19
20
21
22
A3 A4 CS I/O1
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O1
V
SS
V
CC
I/O12
I/O1
I/O10
I/O9
NC
A8
A9
A10
A11
A12
3
1
CC
SS
I/O8
Selection guide
Range
V
CC
Operating (I
Max (mA) Max (
Product
Min
(V)
Typ
(V)
2
Max
(V)
Speed
(ns)
AS6WA25616 3.0 3.3 3.6 55 2 20
7/9/02; v.1.3
Alliance Semiconductor
Power Dissipation
)Standby (I
CC
Copyright ©Alliance Semiconductor. All rights reserved.
P. 1 of 9
)
SB1
A)
µ
AS6WA25616
Functional description
The AS6WA25616 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words × 16 bits.
It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 55 ns are ideal for low-power applications. Active high and low chip selects (CS) permit
easy memory expansion with multiple-bank memory systems.
When CS is high, or UB and LB are high, the device enters standby mode: the AS6WA25616 is guaranteed not to exceed 72 µW power
consumption at 3.6V and 55 ns. The device also returns data when VCC is reduced to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and chip select (CS) low, and UB and/or LB low. Data on the input pins
I/O1–O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/
O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip select (CS), UB and LB low, with write enable (WE) high. The chip drives
I/O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write enable is active, or
) and (LB), output drivers stay in high-impedance mode.
(UB
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 3.0 to 3.6V supply. Device is available in the JEDEC standard
400-mm, TSOP 2, and 48-ball FBGA packages.
Absolute maximum ratings
Parameter Device Symbol Min Max Unit
Voltage on V
Voltage on any I/O pin relative to GND V
Power dissipation P
Storage temperature (plastic) T
Temperature with V
DC output current (low) I
Note: Stresses greater than those listed under
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
relative to V
CC
CC
SS
applied T
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional
V
tI/O
OUT
tIN
D
stg
bias
–0.5 VCC + 0.5 V
–0.5 V
–1.0W
–65 +150
–55 +125
C
°
C
°
–20mA
Truth table
Supply
CS
WE OE LB UB
HXXXX
LXXHH
LHHXXI
LH
LHL
LL D
LH
LLX
LL DIND
Key: X = Don’t care, L = Low, H = High.
Current I/O1–I/O8 I/O9–I/O16 Mode
I
SB
CC
I
CC
I
CC
High Z High Z Standby (ISB)
High Z High Z Output disable (ICC)
D
OUT
OUT
D
IN
High Z
OUT
D
OUT
High Z
IN
IN
Read (I
Write (I
CC
CC
)HL High ZD
)HL High ZD
7/9/02; v.1.3
Alliance Semiconductor
P. 2 of 9
AS6WA25616
Recommended operating condition (over the operating range)
Parameter Description Test Conditions Min Max Unit
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Output HIGH Voltage IOH = –2.1mA VCC = 3.0 - 3.6V 2.4 V
Output LOW Voltage IOL = 2.1mA VCC = 3.0 - 3.6V 0.4 V
Input HIGH Voltage VCC = 3.0 - 3.6V 2.2 VCC + 0.5 V
Input LOW Volt age VCC = 3.0 - 3.6V –0.5 0.8 V
Input Load Current GND < VIN < V
Output Load Current GND < VO < V
= VIL, VIN = VIL
VCC Operating Supply
Current
CS
or V
IH, IOUT
f = 0
= 0mA,
Outputs High Z –1 +1
CC;
CC
VCC = 3.6V 2 mA
–1 +1
A
µ
A
µ
I
@
CC1
1MHz
I
CC2
I
SB
I
SB1
Average VCC Operating
Supply Current at 1 MHz
Average VCC Operating
Supply Current
CS Power Dow n Current ;
TTL Inputs
CS Power Dow n Current ;
CMOS Inputs
< 0.2V, V
CS
or V
> VCC – 0.2V,
IN
f = 1 mS
CS ≠ VIL, VIN = VIL or
V
IH
> VIH or UB = LB
CS
>
VIH, other inputs =
V
or VIH, f = 0
IL
> VCC – 0.2V or
CS
UB
= LB > VCC – 0.2V,
other inputs = 0V – V
, f = f
< 0.2V
IN
Max
CC
VCC = 3.6V 5 mA
V
= 3.6V 40 mA
CC
= 3.6V 100
V
CC
V
= 3.6V 20
,
CC
f = 0
Capacitance (f = 1 MHz, Ta = Room temperature, VCC = NOMINAL)
Parameter Symbol Signals Test conditions Max Unit
Input capacitance C
I/O capacitance C
IN
I/O
A, CS, WE, OE, LB, UB VIN = 0V 5 pF
I/O VIN = V
= 0V 7 pF
OUT
A
µ
A
µ
7/9/02; v.1.3
Alliance Semiconductor
P. 3 of 9
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