Alliance MEMORY AS7C34098A Service Manual
August 2004
Features
• Pin compatible with AS7C34098
• Industrial and commercial temperature
• Organization: 262,144 words × 16 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
• Low power consumption: ACTIVE
- 650 mW /max @ 10 ns
• Low power consumption: STANDBY
-28.8 mW /max CMOS
• Individual byte read/write controls
®
3.3 V 256 K × 16 CMOS SRAM
• Easy memory expansion with CE
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
- 400-mil SOJ
- TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
AS7C34098A
, OE inputs
Logic block diagram
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O9–I/O16
WE
UB
OE
LB
CE
I/O1–I/O8
I/O
buffer
V
CC
1024 × 256 × 16
Array
Row Decoder
(4,194,304)
Control circuit
Column decoder
A5
A9
A10
A11
A14
A15
A16
GND
A17
Pin arrangement for SOJ and TSOP 2
44-pin (400 mil) SOJ
TSOP2
44
A4
CE
I/O1
I/O2
I/O3
I/O4
V
GND
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
CC
1A0
2A1
3A2
4A3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
GND
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
Selection guide
–10 –12 –15 –20 Unit
Maximum address access time 10 12 15 20 ns
Maximum output enable access time 4 5 6 7 ns
Maximum operating current
Maximum CMOS standby current 8 8 8 8 mA
Industrial 180 160 140 110 mA
Commercial 170 150 130 100 mA
8/17/04, v. 2.1 Alliance Memory Inc. P. 1 of 10
Copyright © Alliance Memory Inc. All rights reserved.
AS7C34098A
®
Functional description
The AS7C34098A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as
262,144 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (t
ideal for high-performance applications. The chip enable input CE
memory systems.
When CE
is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in
CMOS standby mode. A write cycle is accomplished by asserting write enable (WE
pins I/O1–I/O16 is written on the rising edge of WE
devices should drive I/O pins only after outputs have been disabled with output enable (OE
A read cycle is accomplished by asserting output enable (OE
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB
controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are TTL- and CMOS-compatible, and operation is for 3.3V (AS7C34098A) supply. The device is
available in the JEDEC standard 400-mL, 44-pin SOJ, TSOP 2.
, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 4/5/6/7 ns are
AA
permits easy memory expansion with multiple-bank
) and chip enable (CE). Data on the input
(write cycle 1) or CE (write cycle 2). To avoid bus contention, external
) or write enable (WE).
) and chip enable (CE), with write enable (WE) high. The chip
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on V
Voltage on any pin relative to GND V
Power dissipation P
Storage temperature (plastic) T
Ambient temperature with V
DC current into outputs (low) I
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE WE OE LB UB I/O1–I/O8 I/O9–I/O16 Mode
HXXXX High Z High Z Standby (I
LHHXX
LXXHH
LHL
LLX
Key: X = Don’t care, L = Low, H = High.
relative to GND V
CC
applied T
CC
LH D
LL D
LH D
H L High Z D
LL D
t1
t2
D
stg
bias
OUT
–0.50 +5.0 V
–0.50 VCC +0.50 V
–1.5W
–65 +150 °C
–55 +125 °C
–±20mA
, I
)
SB
SB1
High Z High Z Output disable (I
OUT
OUT
IN
IN
High Z
OUT
D
OUT
High Z
IN
D
IN
Read (I
Writ e (I
)
CC
)H L High Z D
CC
)
CC
8/17/04,v. 2.1 Alliance Memory Inc P. 2 of 10
Recommended operating conditions
Parameter Symbol Min Typical Max Unit
Supply voltage V
Input voltage
Ambient operating temperature
*
min = –1.0V for pulse width less than 5ns.
V
IL
**
V
max = VCC + 2.0V for pulse width less than 5ns.
IH
commercial T
industrial T
®
(10/12/15/20) 3.0 3.3 3.6 V
CC
**
V
IH
*
V
IL
A
A
2.0 – VCC + 0.5 V
–0.5 – 0.8 V
0– 70°C
–40 – 85 °C
AS7C34098A
DC operating characteristics (over the operating range)
Parameter Symbol Test conditions
Input leakage
current
Output leakage
current
Operating
power supply
current
Standby power
supply current
Output voltage
|I
|I
I
I
V
V
LI
LO
CC
I
SB
SB1
OL
OH
|
|
≤ VIL, f = f
CE
CE
V
CE
V
VCC = Max
max IOUT
CE
≥ VCC – 0.2V, VIN ≥ VCC – 0.2V or
IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 V
IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – 2.4 – V
= Max
V
CC
= GND to V
IN
V
CC
= Max
CC
= VIH or OE = VIH
= VIL
or WE
= GND to V
I/O
CC
= 0mA
VCC = Max
≥ VIH, f = Max
VCC = Max
≤ 0.2V, f = 0
V
IN
Industrial – 180 – 160 – 140 – 110 mA
Commercial - 170 - 150 - 130 - 100 mA
1
–10 –12 –15 –20
UnitMin Max Min Max Min Max Min Max
– 1– 1 –1–1µA
– 1– 1 –1–1µA
– 60 – 60 – 60 – 60 mA
– 8– 8 –8–8mA
Capacitance (f = 1MHz, Ta = 25° C, VCC = NOMINAL)2
Parameter Symbol Signals Test conditions Max Unit
Input capacitance C
I/O capacitance C
8/17/04,v. 2.1 Alliance Memory Inc P. 3 of 10
IN
I/O
A, CE, WE, OE, UB, LB VIN = 0V 6 pF
I/O VIN = V
= 0V 8 pF
OUT
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