Alliance MEMORY AS7C34098A Service Manual

August 2004

Features

• Pin compatible with AS7C34098

• Industrial and commercial temperature

• Organization: 262,144 words × 16 bits

• Center power and ground pins

• High speed

- 10/12/15/20 ns address access time

- 4/5/6/7 ns output enable access time

• Low power consumption: ACTIVE

- 650 mW /max @ 10 ns

• Low power consumption: STANDBY

-28.8 mW /max CMOS

• Individual byte read/write controls

®

3.3 V 256 K × 16 CMOS SRAM

• Easy memory expansion with CE

• TTL- and CMOS-compatible, three-state I/O

• 44-pin JEDEC standard packages

- 400-mil SOJ

- TSOP 2

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

AS7C34098A

, OE inputs

Logic block diagram

A0 A1 A2 A3 A4 A6 A7

A8 A12 A13

I/O9–I/O16

WE

UB OE

LB CE

I/O1–I/O8

I/O

buffer

V

CC

1024 × 256 × 16

Array

Row Decoder

(4,194,304)

Control circuit

Column decoder

A5

A9

A10

A11

A14

A15

A16

GND

A17

Pin arrangement for SOJ and TSOP 2

44-pin (400 mil) SOJ

TSOP2

44

A4

CE

I/O1 I/O2 I/O3 I/O4

V

GND I/O5 I/O6 I/O7

I/O8

WE

A5 A6 A7 A8 A9

CC

1A0 2A1 3A2 4A3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

25 24 23

A17 A16 A15 OE UB LB I/O16 I/O15 I/O14 I/O13 GND V

CC

I/O12 I/O11 I/O10

I/O9 NC

A14 A13 A12 A11 A10

Selection guide

–10 –12 –15 –20 Unit

Maximum address access time 10 12 15 20 ns

Maximum output enable access time 4 5 6 7 ns

Maximum operating current

Maximum CMOS standby current 8 8 8 8 mA

Industrial 180 160 140 110 mA

Commercial 170 150 130 100 mA

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AS7C34098A

®

Functional description

The AS7C34098A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.

Equal address access and cycle times (t ideal for high-performance applications. The chip enable input CE memory systems.

When CE

is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE pins I/O1–I/O16 is written on the rising edge of WE devices should drive I/O pins only after outputs have been disabled with output enable (OE

A read cycle is accomplished by asserting output enable (OE drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.

The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB

controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.

All chip inputs and outputs are TTL- and CMOS-compatible, and operation is for 3.3V (AS7C34098A) supply. The device is available in the JEDEC standard 400-mL, 44-pin SOJ, TSOP 2.

, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 4/5/6/7 ns are

AA

permits easy memory expansion with multiple-bank

) and chip enable (CE). Data on the input

(write cycle 1) or CE (write cycle 2). To avoid bus contention, external

) or write enable (WE).

) and chip enable (CE), with write enable (WE) high. The chip

Absolute maximum ratings

Parameter Symbol Min Max Unit

Voltage on V

Voltage on any pin relative to GND V

Power dissipation P

Storage temperature (plastic) T

Ambient temperature with V

DC current into outputs (low) I

Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Truth table

CE WE OE LB UB I/O1–I/O8 I/O9–I/O16 Mode

HXXXX High Z High Z Standby (I

LHHXX

LXXHH

LHL

LLX

Key: X = Don’t care, L = Low, H = High.

relative to GND V

CC

applied T

CC

LH D

LL D

LH D

H L High Z D

LL D

t1

t2

D

stg

bias

OUT

–0.50 +5.0 V

–0.50 VCC +0.50 V

–1.5W

–65 +150 °C

–55 +125 °C

–±20mA

, I

)

SB

SB1

High Z High Z Output disable (I

OUT

IN

High Z

OUT

D

OUT

High Z

IN

D

IN

Read (I

Writ e (I

)

CC

)H L High Z D

CC

)

CC

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Recommended operating conditions

Parameter Symbol Min Typical Max Unit

Supply voltage V

Input voltage

Ambient operating temperature

*

min = –1.0V for pulse width less than 5ns.

V

IL

**

V

max = VCC + 2.0V for pulse width less than 5ns.

IH

commercial T

industrial T

®

(10/12/15/20) 3.0 3.3 3.6 V

CC

**

V

IH

*

V

IL

A

2.0 – VCC + 0.5 V

–0.5 – 0.8 V

0– 70°C

–40 – 85 °C

AS7C34098A

DC operating characteristics (over the operating range)

Parameter Symbol Test conditions

Input leakage current

Output leakage current

Operating power supply current

Standby power supply current

Output voltage

|I

I

V

LI

LO

CC

I

SB

SB1

OL

OH

|

≤ VIL, f = f

CE

V

CE

V

VCC = Max

max IOUT

CE

≥ VCC – 0.2V, VIN ≥ VCC – 0.2V or

IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 V

IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – 2.4 – V

= Max

V

CC

= GND to V

IN

V

CC

= Max

CC

= VIH or OE = VIH

= VIL

or WE

= GND to V

I/O

CC

= 0mA

VCC = Max

≥ VIH, f = Max

VCC = Max

≤ 0.2V, f = 0

V

IN

Industrial – 180 – 160 – 140 – 110 mA

Commercial - 170 - 150 - 130 - 100 mA

1

–10 –12 –15 –20

UnitMin Max Min Max Min Max Min Max

– 1– 1 –1–1µA

– 60 – 60 – 60 – 60 mA

– 8– 8 –8–8mA

Capacitance (f = 1MHz, Ta = 25° C, VCC = NOMINAL)2

Parameter Symbol Signals Test conditions Max Unit

Input capacitance C

I/O capacitance C

8/17/04,v. 2.1 Alliance Memory Inc P. 3 of 10

IN

I/O

A, CE, WE, OE, UB, LB VIN = 0V 6 pF

I/O VIN = V

= 0V 8 pF

OUT

AS7C34098A

®

Read cycle (over the operating range)

Parameter Symbol

Read cycle time

Address access time

Chip enable (CE

Output enable (OE

) access time

Output hold from address change

CE

Low to output in low Z

CE

High to output in high Z

OE

Low to output in low Z

OE

High to output in high Z

LB

, UB access time

LB

, UB Low to output in low Z

LB

, UB High to output in high Z

Power up time

Power down time

t

AA

t

ACE

t

OH

t

CLZ

t

CHZ

t

OLZ

t

OHZ

t

BLZ

t

BHZ

t

RC

OE

BA

PU

PD

3,9

–10 –12 –15 –20

Unit NotesMin Max Min Max Min Max Min Max

10 – 12 – 15 – 20 – ns

– 10 – 12 – 15 – 20 ns

– 4 –5–6–7ns

3 – 3–3–3–ns5

3 – 3–3–3–ns4, 5

– 5 –6–7–9ns4, 5

0 – 0–0–0–ns4, 5

– 5 –6–7–9ns4, 5

– 5 –6–7–8ns

0 – 0–0–0–ns

– 5 –6–7–9ns

0 – 0–0–0–ns5

– 10 – 12 – 15 – 20 ns 5

Key to switching waveforms

Read waveform 1 (address controlled)

Address

t

OH

Data

OUT

6,7,9

Undefined/don’t careFalling inputRising input

t

RC

t

AA

Data validPrevious data valid

t

OH

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AS7C34098A

®

Read waveform 2 (CE, OE, UB, LB controlled)

Address

t

AA

OE

t

OLZ

CE

LB, UB

t

BLZ

Data

OUT

Write cycle (over the operating range)

Parameter Symbol

t

CLZ

10

OE

t

ACE

t

BA

–10 –12 –15 –20

6,8,9

t

RC

t

OHZ

t

OH

t

CHZ

t

BHZ

Data valid

Unit NoteMin Max Min Max Min Max Min Max

Write cycle time

Chip enable (CE)

to write end

Address setup to write end

Address setup time

Write pulse width (OE

= High)

= Low)

Write recovery time

Address hold from end of write

Data valid to write end

Data hold time

Write enable to output in High-Z

Output active from write end

Byte enable Low to write end

t

WC

t

CW

t

AW

t

WP1

t

WP2

t

WR

t

AH

t

DW

t

DH

t

WZ

t

OW

t

BW

AS

10–12–15–20– ns

7–8–10–12–ns

0–0–0–0–ns

7–8–10–12–ns

10–12–15–20– ns

0–0–0–0–ns

5–6 7–9–ns

0–0–0–0–ns4, 5

05060709ns4, 5

3–3–3–3–ns4, 5

7–8–10–12–ns4, 5

8/17/04,v. 2.1 Alliance Memory Inc P. 5 of 10

Write waveform 1(WE controlled)10

Address

CE

LB, UB

t

AS

WE

Data

IN

Data

OUT

Data undefined

t

AW

t

WZ

WC

CW

BW

AS7C34098A

®

t

AH

t

WR

t

WP

t

DW

Data valid

t

DH

t

High Z

OW

Write waveform 2 (CE controlled)10

Address

t

AS

CE

LB, UB

WE

Data

IN

OUT

t

CLZ

High Z High Z

t

AW

Data undefined

WC

t

WZ

t

CW

BW

t

WP

t

DW

t t

Data valid

AH WR

t

DH

t

OW

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AS7C34098A

®

Write waveform 3

Address

CE

LB, UB

WE

Data

IN

Data

OUT

10

t

WC

t

AS

High Z High Z

t

CW

t

AW

t

BW

t

WP

t

DW

t

WZ

Data undefined

Data valid

t

AH

WR

t

DH

AC test conditions

- Output load: see Figure B.

- Input pulse level: GND to 3.0V. See Figure A.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

+3.0V

GND

90%

10%

2 ns

Figure A: Input pulse

90%

10%

D

OUT

350

Ω

Figure B: 3.3V Output load

Notes

1During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. 2 This parameter is sampled, but not 100% tested. 3 For test conditions, see AC Test Conditions, Figures A and B.

and t

4t

CLZ

5 This parameter is guaranteed, but not tested.

is High for read cycle.

6WE

and OE are Low for read cycle.

7CE 8 Address valid prior to or coincident with CE 9 All read cycle timings are referenced from the last valid address to the first transitioning address. 10 All write cycle timings are referenced from the last valid address to the first transitioning address.

11 C=30pF, except on High Z and Low Z parameters, where C=5pF.

are specified with CL = 5pF as in Figure B. Transition is measured ±500mV from steady-state voltage.

CHZ

transition Low.

+3.3V

320

Ω

11

C

GND

Thevenin equivalent:

D

OUT

168

Ω

+1.728V

8/17/04,v. 2.1 Alliance Memory Inc P. 7 of 10

Package dimensions

AS7C34098A

®

44 43424140393837363534333231

44-pin TSOP 2

1234567891011121314

d

A

Pin 1

A1

1

b

e

44-pin SOJ

B

b

E

D

3029

1516

1718 1920

Seating

Plane

272625

28

E1

A

212422

E2

23

c

44-pin TSOP 2

Min (mm) Max (mm)

A 1.2

H

e

A A

0.05 0.15

1

0.95 1.05

2

b 0.3 0.45

c 0.12

0.21

d 18.31 18.52

e 10.06 10.26

A

2

0–5

°

l

H

E 0.80 (typical)

11.68 11.94

e

l 0.40 0.60

44-pin SOJ 400 mils

Min(mils) Max(mils)

A 0.128 0.148

c

A2

E

A1 0.025 - A2 0.105 0.115

B 0.026 0.032 b 0.015 0.020

c 0.007 0.013 D 1.120 1.130 E 0.370 NOM

E1 0.395 0.405 E2 0.435 0.445

e 0.050 NOM

8/17/04,v. 2.1 Alliance Memory Inc P. 8 of 10

AS7C34098A

®

Ordering Codes

Package Temperature 10 ns 12 ns 15 ns 20 ns

SOJ Commercial AS7C34098A-10JC AS7C34098A-12JC AS7C34098A-15JC AS7C34098A-20JC

Industrial AS7C34098A-10JI AS7C34098A-12JI AS7C34098A-15JI AS7C34098A-20JI

TSOP 2

Note: Add suffix ‘N’ to the above part numbers for Lead Free Parts. (EX: AS7C34098A - 10TCN)

Part numbering system

AS7C X 4098A –XX J or T X X

SRAM prefix

Commercial AS7C34098A-10TC AS7C34098A-12TC AS7C34098A-15TC AS7C34098A-20TC

Industrial AS7C34098A-10TI AS7C34098A-12TI AS7C34098A-15TI AS7C34098A-20TI

Voltage:

3 - 3.3V CMOS

Device

number

Access

time

Packages:

J: SOJ 400 mil

T: TSOP 2

Temperature ranges:

C: Commercial, 0°C to 70°C

I: Industrial, –40°C to 85°C

N = Lead Free Parts

8/17/04,v. 2.1 Alliance Memory Inc P. 9 of 10

®

AS7C34098A

Alliance Memory, Inc.

511 Taylor Way,

San

Carlos, CA 94070 Tel: 650Fax: 650-

610-6800

620-9211

Part Number: AS7C34098A

Document Version: v. 2.1

www.alliancememory.com

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